View detail for Implementation of DDR2 and LP-DDR2 on SAMA5D3x Devices

APPLICATION NOTE
Implementation of DDR2 and LPDDR2 on SAMA5D3x
Devices
Atmel | SMART SAMA5D3 Series
Scope
The Atmel® | SMART SAMA5D3 series is a high-performance, power-efficient
embedded MPU based on the ARM® Cortex®-A5 processor.
The SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 and SAMA5D36 eMPUs
feature one multi-port DDR2 controller that supports 32-bit DDR2-SDRAM, 32-bit
LPDDR1-SDRAM, and 32-bit LPDDR2-SDRAM memories. These memories are
called SDRAM in this document.
SAMA5D3x embeds a pad calibration feature that performs bus impedance
adaptation, improving signal integrity. This leads to a reduction of overshoots, of
Electromagnetic Interference (EMI), of power consumption on I/Os and eliminates
the need of serial resistor on data lines.
This application note is intended to help the developer in the design of a system
using external memory.
Reference Documents
1.
Type
Title
Literature No.
Datasheet
SAMA5D3 Series
11121 (1)
SAMA5D3 Series datasheet available on www.atmel.com
SMART
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
Table of Contents
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.
Multi-port DDR Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.
Multi-Port DDR Controller Signals Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.
SDRAM Connection on SAMA5D3x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
3.4
4.
Layout and Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
5.
Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibration Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
6.2
7.
General Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DDR2/LPDDR Bus Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1
Signals Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.2
Signals Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.3
Signals Group 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EBI Trace Routing Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1
Topology About the EBI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.2
Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.3
Bypassing Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.4
Trace Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.5
Trace Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.6
Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.7
Ground Plane(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.8
Power Plane(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.9
General Considerations for High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . 12
LPDDR2-SDRAM Power-up and Power-off Considerations . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
6.
32-bit Using 2x16-bit DDR2-SDRAM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1
Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2
Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDR2 VREF Signal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
32-bit Using 2x16-bit LPDDR2-SDRAM Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.1
Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.2
Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LPDDR2 VREF Signal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDR2-SDRAM or LPDDR1-SDRAM Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.2
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LPDDR2-SDRAM Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.2
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDR2 Electromagnetic Compatibility (EMC) Improvement . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
Simultaneous Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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7.2
8.
Overshoots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multi-port DDR Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1
8.2
8.3
DDR2-SDRAM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LPDDR2-SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Micron® MT47H128M16 DDR2 SDRAM (MPDDRC Configuration Example). . . . . . . . . . . . . . . . . 18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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1.
Multi-port DDR Controller Overview
The Multi-port DDR Controller (MPDDRC) extends the memory capabilities of a chip by providing the interface to
an external 32-bit SDRAM device. The page size supports ranges from 2048 to 16384, and a number of columns
from 256 to 4096. It supports word (32-bit), half-word (16-bit), byte (8-bit) accesses on a 32-bit data path.
The MPDDRC supports a read or write burst length of four locations thanks to the 4-port architecture. It keeps
track of the active row in each bank, thus maximizing the SDRAM performance, e.g., the application may be
placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing
different rows in the same bank (Open Bank Policy).
The MPDDRC supports a CAS latency of 2 and 3 and optimizes the read access depending on the frequency.
Self-refresh, power down and deep power down mode features allow to minimize the consumption of SDRAM
device.
The MPDDRC I/Os are powered by VDDIODDR. For DDR2-SDRAM and LPDDR1-SDRAM, VDDIODDR is set to
1.8V nominal, for LPDDR2-SDRAM, VDDIODDR is set to 1.2V nominal.
The DDR Chip Select allows to have 512 Mbytes of SDRAM, from address 0x2000 0000 to address 0x4000 0000.
4
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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2.
Multi-Port DDR Controller Signals Definition
The MPDDRC manages 4-bank and 8-bank SDRAM devices. The signals generated by the controller are defined
in Table 2-1.
Table 2-1.
SDRAM Controller Signals
Signal Name
Function
Type
DDR_VREF
Reference Voltage
Input
DDR_CALP
LPDDR2 Calibration Positive
Reference
Input
DDR_CALN
LPDDR2 Calibration Negative
Reference
Input
DDR_CK, DDR_CKN
DDR2 Differential Clock
Active
Level
Description
Used by the input buffers of the DDR2 memories as
well as the DDR2 controller to determine logic
levels. VREF is specified to be ½ the power supply
voltage and is created using a voltage divider
constructed from two 1.5 KΩ, 1% tolerance resistors.
Used to calibrate I/O. See calibration section for
more details.
Output
Differential clock signals that feed the SDRAM
device. All other signals take those two signals as a
reference.
DDR_CKE
DDR2 Clock Enable
Output
High
Acts as an inhibit signal to the DDR device.
DDR_CKE remains high during valid DDR2 access
(Read, Write, Prech). This signal goes low when the
device is in power down mode or in self-refresh
mode; a self-refresh command can be issued by the
controller (refer to the DDR2 controller self-refresh
mode).
DDR_CS
DDR2 Controller Chip Select
Output
Low
When the Chip Select (DDR_CS) is low, the
command input is valid. When it is high, the
commands are ignored but the operation continues.
DDR_BA[2..0]
Bank Select
Output
Low
Select the bank to address when a command is
input. Read/write or precharge is applied to the bank
selected by DDR_BA0, DDR_BA1, or DDR_BA2.
DDR_WE
DDR2 Write Enable
Output
Low
DDR_RAS - DDR_CAS
Row and Column Signal
Output
Low
DDR_A[13..0]
DDR2 Address Bus
Output
SDRAM controller address lines, respectively
bounded to [A0:A13] on the microcontroller.
DDR_D[31..0]
DDR2 Data Bus
I/O/-PD
SDRAM controller data lines, respectively bounded
to [DDR_D31:DDR_D0] on the microcontroller.
I/O/-PD
DDR_DQS[0..3]: Data Strobe. The data is sampled
on DDR_DQS edges.
DDR_DQSN[0..3]: Negative Data Strobe, for
LPDDR2-SDRAM. DQSN must be connected to
DDR_VREF for DDR2 memories.
DDR_DQS[3..0],
DDR_DQSN[3..0]
Differential Data Strobe
The Row Address Strobe (DDR_RAS) and the
Column Address Strobe (DDR_CAS) will assert to
indicate that the corresponding address is present
on the bus. The conjunction with Write Enable
(DDR_WE) and chip select (SDCS), at the rising
edge of the clock (DDR_CK) or the falling edge of
the #clock (#DDR_CK), determines the DDR2
operation.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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Table 2-1.
SDRAM Controller Signals (Continued)
Signal Name
Function
DDR_DQM[3..0]
Write Data Mask
6
Type
Output
Active
Level
Description
Data is accessed in 32 bits by means of
DDR_DQM[3..0], which are respectively the highest
to lowest mask bit for the DDR2 data on the bus.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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3.
SDRAM Connection on SAMA5D3x
The SAMA5D3x microprocessor supports 32-bit DDR2 devices on DDR Chip Select area (0x2000 0000 memory
zone). This memory area has a length of 512 Mbyte.
The user interface to configure the MPDDR controller is mapped at address 0xFFFF EA00.
Each memory device must use sufficient decoupling to provide an efficient filtering on the power supply rails.
3.1
32-bit Using 2x16-bit DDR2-SDRAM Implementation
3.1.1
Hardware Configuration
{3} DDR_D[0..31]
{3} DDR_A[0..13]
MN8
{3}
{3}
{3}
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CKE
{3}
{3}
DDR_CLK
DDR_CLKN
{3}
DDR_CS
{3}
{3}
DDR_CAS
DDR_RAS
{3}
{3}
DDR_WE
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
VDDIODDR
R93 DNP
R94
{3}
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
K9
0R
DDR_CKE
K2
DDR_CLK
DDR_CLKN
J8
K8
DDR_CS
L8
DDR_CAS
DDR_RAS
L7
K7
DDR_WE
K3
B7
A8
DDR_DQS1
R98
{3}
DDR_DQS0
{3}
{3}
DDR_DQM1
DDR_DQM0
R99
VREF
UDQS
UDQS
4.7K
F7
E8
MN9
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H128M16RT DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
A12
DQ12
DQ13
DQ14
BA0
DQ15
BA1
BA2
VDD
ODT
VDD
VDD
VDD
VDD
CKE
VDDL
CK
CK
VDDQ
VDDQ
VDDQ
CS
VDDQ
VDDQ
VDDQ
CAS
VDDQ
RAS
VDDQ
VDDQ
WE
VDDQ
LDQS
LDQS
VSS
VSS
VSS
VSS
VSS
4.7K
B3
F3
DDR_A13
A2
E2
R3
R7
R8
UDM
LDM
RFU1
RFU2
RFU3
RFU4
RFU5
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
VDDIODDR
A1
E1
J9
M9
R1
C53
C55
C57
C59
C61
J1
100nF
100nF
100nF
100nF
100nF
C63 100nF
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
VDDIODDR
C65
C67
C69
C71
C73
C75
C77
C79
C81
C83
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
R91
DNP
R92
0R
K9
DDR_CKE
K2
DDR_CLK
DDR_CLKN
J8
K8
DDR_CS
L8
DDR_CAS
DDR_RAS
L7
K7
K3
DDR_WE
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H128M16RT DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
A12
DQ12
DQ13
DQ14
BA0
DQ15
BA1
BA2
VDD
ODT
VDD
VDD
VDD
VDD
CKE
VDDL
CK
CK
VDDQ
VDDQ
VDDQ
CS
VDDQ
VDDQ
VDDQ
CAS
VDDQ
RAS
VDDQ
VDDQ
WE
VDDQ
DDR_VREF
A3
E3
J3
N1
P9
{3}
B7
A8
DDR_DQS3
C85
100nF
R100 4.7K
{3}
DDR_DQS2
{3}
{3}
DDR_DQM3
DDR_DQM2
F7
E8
VREF
UDQS
UDQS
LDQS
LDQS
VSS
VSS
VSS
VSS
VSS
R101 4.7K
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
B3
F3
DDR_A13
A2
E2
R3
R7
R8
UDM
LDM
RFU1
RFU2
RFU3
RFU4
RFU5
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
VDDIODDR
A1
E1
J9
M9
R1
C54
C56
C58
C60
C62
J1
C64 100nF
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
100nF
100nF
100nF
100nF
100nF
C66
C68
C70
C72
C74
C76
C78
C80
C82
C84
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
DDR_VREF
A3
E3
J3
N1
P9
C86
100nF
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
DDR2 SDRAM
VDDIODDR
L8
10uH/150mA
C87
4.7uF
R64
1R
C88
100nF
R65
1.5K 1%
DDR_VREF
C89
4.7uF
3.1.2
C90
100nF
TP22
SMD
DDR_VREF
{3}
R66
1.5K 1%
Software Configuration
Refer to Section 8.1 “DDR2-SDRAM Initialization” on page 18 for information on the DDR2 initialization sequence.
3.2
DDR2 VREF Signal Considerations
DDR_VREF which is half the interface voltage, or 0.9 V, is provided by a voltage divider of 1.8 V using two 1.5 KΩ,
1% tolerance resistors.
DDR_VREF is not a high current supply, but it is important to keep it as quiet as possible with minimal inductance.
DQSN[3:0] must be connected to DDR_VREF for DDR2 memories.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
7
3.3
32-bit Using 2x16-bit LPDDR2-SDRAM Implementation
3.3.1
Hardware Configuration
DDR_D[0..31]
LPDDR2 SDRAM
LPDDR2 SDRAM
U1A
C1
R1
49.9
DDR_CLK
R2
49.9
DDR_CLKN
100nF
DDR_RAS
DDR_CAS
DDR_WE
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
AC6
AB6
AC7
AB8
AB9
W1
V2
U1
T2
T1
DDR_CKE
AC3
AC4
DDR_CLK
DDR_CLKN
VDDIODDR
1V2_VDD2
R3
0R
R4
0R
R5
0R
1V2_VDDCA
Y2
Y1
DDR_CS
AB3
AB4
DDR_DQS0
DDR_DQSN0
R23
P22
DDR_DQS1
DDR_DQSN1
J22
K23
1V2_VDDQ
AB18
AC19
B18
A19
DDR_DQM0
DDR_DQM1
N23
L23
AB20
B20
1V8_VDD1
1V2_VDD2
1V2_VDDCA
1V2_VDDQ
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C2
C8
C12
C13
C9
C16
C18
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C20
C21
C23
C24
C26
C28
C6
C7
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
B11
B21
C2
L22
R2
AA2
AB10
AB21
U2
W2
AC8
B13
B16
B19
D22
G22
K22
R22
V22
AA22
AB13
AB16
AB19
C38
C40
C42
C44
C46
C48
C50
C52
C54
C56
C58
C60
VREFCA
VREFDQ
CKE0
CKE1
CK
CK#
CS0#
CS1#
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
U2A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
AA23
Y22
W22
W23
V23
U22
T22
T23
H22
H23
G23
F22
E22
E23
D23
C22
AB12
AC13
AB14
AC14
AB15
AC16
AB17
AC17
B17
A17
A16
B15
B14
A14
A13
B12
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
P2
M22
A3
A4
A5
A7
A8
A10
B4
B6
B7
B9
D1
D2
E1
E2
G1
G2
H1
H2
K1
K2
L1
L2
DDR_CS
AC6
AB6
AC7
AB8
AB9
W1
V2
U1
T2
T1
DDR_CKE
AC3
AC4
R20
0R
ZQ
R23
P22
DDR_DQS3
DDR_DQSN3
J22
K23
B18
A19
P1
R6
DDR_DQM2
DDR_DQM3
240R 1%
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDDCA
VDDCA
VDDCA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFCA
VREFDQ
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
N23
L23
AB20
B20
1V8_VDD1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
AB3
AB4
DDR_DQS2
DDR_DQSN2
DQS3
DQS3#
DM0
DM1
DM2
DM3
Y2
Y1
AB18
AC19
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DNU13
DNU14
DNU15
DNU16
(NC)1
(NC)2
(NC)3
(NC)4
(NC)5
NC23
NC24
NC25
B5
B10
C1
F2
J2
M2
M23
AA1
AC5
AC9
A21
B8
R1
AB11
AC21
1V2_VDD2
1V2_VDDCA
V1
AB7
1V2_VDDQ
A12
A15
A18
C23
F23
J23
P23
U23
Y23
AC12
AC15
AC18
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C10
C11
C3
C14
C15
C17
C19
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C4
C22
C5
C25
C27
C29
C30
C31
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
B11
B21
C2
L22
R2
AA2
AB10
AB21
U2
W2
AC8
A1
A2
A22
A23
B1
B2
B22
B23
AB1
AB2
AB22
AB23
AC1
AC2
AC22
AC23
A6
A9
F1
J1
AC10
M1
N1
AC11
B13
B16
B19
D22
G22
K22
R22
V22
AA22
AB13
AB16
AB19
C39
C41
C43
C45
C47
C49
C51
C53
C55
C57
C59
C61
VREFCA
VREFDQ
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CKE0
CKE1
CK
CK#
CS0#
CS1#
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
AA23
Y22
W22
W23
V23
U22
T22
T23
H22
H23
G23
F22
E22
E23
D23
C22
AB12
AC13
AB14
AC14
AB15
AC16
AB17
AC17
B17
A17
A16
B15
B14
A14
A13
B12
P2
M22
A3
A4
A5
A7
A8
A10
B4
B6
B7
B9
D1
D2
E1
E2
G1
G2
H1
H2
K1
K2
L1
L2
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DQS3
DQS3#
DM0
DM1
DM2
DM3
ZQ
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDDCA
VDDCA
VDDCA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFCA
VREFDQ
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DNU13
DNU14
DNU15
DNU16
(NC)1
(NC)2
(NC)3
(NC)4
(NC)5
NC23
NC24
NC25
MT42L128M16D1KL-25
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
P1
MT42L128M16D1KL-25
U2B
A11
A20
B3
N2
N22
AC20
AB5
100nF C33
100nF C35
100nF C37
MT42L128M16D1KL-25
8
DDR_RAS
DDR_CAS
DDR_WE
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_CLK
DDR_CLKN
MT42L128M16D1KL-25
U1B
A11
A20
B3
N2
N22
AC20
AB5
100nF C32
100nF C34
100nF C36
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
B5
B10
C1
F2
J2
M2
M23
AA1
AC5
AC9
A21
B8
R1
AB11
AC21
V1
AB7
A12
A15
A18
C23
F23
J23
P23
U23
Y23
AC12
AC15
AC18
A1
A2
A22
A23
B1
B2
B22
B23
AB1
AB2
AB22
AB23
AC1
AC2
AC22
AC23
A6
A9
F1
J1
AC10
M1
N1
AC11
R7
240R 1%
3.3.2
Software Configuration
Refer to Section 8.2 “LPDDR2-SDRAM Initialization” on page 18 for information on the LPDDR2 initialization
sequence.
3.4
LPDDR2 VREF Signal Considerations
DDR_VREF which is half the interface voltage, or 0.6 V, is provided by a voltage divider of 1.2 V using two 1.5 KΩ,
1% tolerance resistors.
DDR_VREF is not a high current supply, but it is important to keep it as quiet as possible with minimal inductance.
To reduce noise two VREF pins are needed for LPDDR2-SDRAM: VREFCA and VREFDQ.
1V2_VDDCA
L1
10uH/150mA
VREFCA
R8
1R
C62
100nF
R9
1.5K 1%
R10
C63
4.7uF
C64
100nF
0R
C65
100nF
R11
1.5K 1%
C74
100nF
1V2_VDDQ
L2
10uH/150mA
VREFDQ
R14
1R
C66
100nF
R15
1.5K 1%
R16
C71
4.7uF
C72
100nF
R18
1.5K 1%
0R
C73
100nF
C75
100nF
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
9
4.
Layout and Design Constraints
4.1
General Considerations
This section provides routing guidelines for layout and design of a printed circuit board using high-speed
memories. The signal integrity rules for high-speed interfaces need to be considered. In fact, it is highly
recommended that the board design be simulated to determine optimum layout for signal integrity and quality.
Keep in mind that this document can only highlight the most important issues that should be considered when
designing a board with high-speed memories. The designer has to take into account the corresponding information
(specification, design guidelines, etc.) contained in the documentation for each interface that is to be implemented
on board.
4.2
DDR2/LPDDR Bus Interface Controller
Bus signals can be split in three groups:
1.
Differential Clock source, VREF middle voltage point for DDR2 reference voltage
̶
2.
3.
4.2.1
This first and most critical signal group is set up by only the CK, NCK signals and the VREF reference
voltage.
Bus, strobe and Mask signals
̶
Data bus signals
̶
DQS Signals
̶
DQM Signals
Address, Control signals
̶
Address bus signals (DDR_Ax)
̶
DDR_BAx signals (Bank select signals)
̶
CKE signal, RAS, CAS, NWE and NCS control signals
Signals Group 1
All Group 1 signals are the most critical and shall be routed at first. The Clock is driven in differential mode. Two
traces shall be planned to drive this signal to DDR2 packages. The clock traces shall have the same impedance
therefore:

Both traces shall route on outer layer,

Both traces shall make parallel,

Clock traces shall use only 2 via/trace.
About VREF, this voltage reference must be considered like a potential victim. This voltage reference traces versus
other traces must be stood back from noisy digital traces (in tree dimension: above and below layers and on both
sides): Maintain a 15–20 mil clearance from other nets.
This net shall be larger other traces (like a small local voltage plane) and shall be on layer immediately on facing
ground layer.
4.2.2
Signals Group 2
All Group 2 signals shall be routed by keeping propagation delay equal as first constraint:
10

Route each data group (DQ + DQS + DM) on same layer to match propagation delays and minimize skew
between these signals,

Between DQ and DQM signals, 3 widths minimum space must be set up, but, between DQS (potential
victim) and DQ/DQM, 4 widths shall be set up.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
4.2.3
Signals Group 3
All Group 3 signals shall be routed by minimizing crosstalk with [DQ, DQS, DQM] ↔ [Addresses, CTRL Bus]:
Maintain a gap between the two groups and do not interlace them.
Table 4-1.
Example of PCB Stackup
Layer
Type
Description
Layer 1 (Top)
Signal
Differential and critical signals: oscillators, quartz, clock, DDR_VREF,
DDR_CLK / DDR_NCLK, CLK_EBI / NCLK_EBI
Layer 2
GND
GND
Layer 3
Signal
Addresses and data buses
Layer 4
Plane Power and Signal
Non-critical signal
Layer 5
Signal
Free
Layer 6
Signal
Free
Layer 7
Plane Power and Signal
Non-critical signal
Layer 8
Signal
Addresses and data buses
Layer 9
GND
GND
Layer 10 (Bottom)
Signal
Differential and critical signals: Same as Layer 1 (Top)
4.3
EBI Trace Routing Guidelines
4.3.1
Topology About the EBI Bus
Bus impedance: Maintain an impedance of 50 ohms to ±10%.
4.3.2
Placement
Place the highest-speed/highest-current components as far from the I/O connections as possible.
4.3.3
Bypassing Capacitors
Keep all surface traces that run between the pads of the decoupling capacitors and their vias as short and wide as
possible. Use as small a body size for a decoupling capacitor as you can afford and minimize the length of all
connections from the capacitor pads to the power and ground planes.
4.3.4
Trace Length
Keep the time delay of stubs less than 20% of the rise time of the fastest signals.
Route the shorter path between MPU and resistor networks dedicated to the memories.
4.3.5
Trace Spacing
For microstrip or stripline transmission lines, keep the spacing between adjacent signal paths at least twice the line
width.
Keep all traces at least five line widths from the edge of the board.
4.3.6
Via
Use vias as large in diameter as practical when routing to power or ground planes.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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11
4.3.7
Ground Plane(s)
Follow the return path of each signal and keep the width of the return path under each signal path at least as wide,
and preferably at least three times as wide, as the signal trace.
Route signal traces around rather than across return-path discontinuities.
4.3.8
4.3.9
Power Plane(s)

Minimize the loop inductance between the power and ground paths.

Allocate power and ground planes on adjacent layers with as thin a dielectric as you can afford.

Route the power and ground planes as close as possible to the surface where the decoupling capacitors are
mounted.

Supply voltages must be composed of planes only, not traces. Short connections (≈ 8 mil) are commonly
used to attach vias to planes. Any connections required from supply voltages to vias for device pins or
decoupling capacitors should be as short and as wide as possible to minimize trace impedance (20 mil trace
width).
General Considerations for High-Speed Differential Interfaces
The following is a list of suggestions for designing with high-speed differential signals.
12

Use controlled impedance PCB traces that match the specified differential impedance.

Keep the trace lengths of the differential signal pairs as short as possible.

The differential signal pair traces should be trace-length matched and the maximum trace-length mismatch
should not exceed the specified values. Match each differential pair per segment.

Maintain parallelism and symmetry between differential signals with the trace spacing needed to achieve the
specified differential impedance.

Maintain maximum possible separation between the differential pairs and any high-speed clocks/periodic
signals (CMOS/TTL) and any connector leaving the PCB (such as, I/O connectors, control and signal
headers, or power connectors).

Route differential signals on the signal layer nearest to the ground plane using a minimum of vias and
corners. This will reduce signal reflections and impedance changes. Use GND stitching vias when changing
layers.

Route CMOS/TTL and differential signals on a different layer(s), which should be isolated by the power and
ground planes.

Avoid tight bends. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a
single 90° turn.

Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that use,
and/or generate, clocks.

Stubs on differential signals should be avoided due to the fact that stubs will cause signal reflections and
affect signal quality.

Keep the length of high-speed clock and periodic signal traces that run parallel to high-speed signal lines at
a minimum to avoid crosstalk. Based on EMI testing experience, the minimum suggested spacing to clock
signals is 50 mil.

Use a minimum of 20 mil spacing between the differential signal pairs and other signal traces for optimal
signal quality. This helps to prevent crosstalk.

Route all traces over continuous planes (VCC or GND) with no interruptions.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
DDR_D3
DDR_D4
G17
G16
H15
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_VREF
C18
D16
C17
A18
C16
C14
D15
B14
A15
A14
E12
A11
B11
F12
A10
E11
G12
E15
B15
D12
E18
G18
B17
B13
D18
F18
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
GND
C63
5
5
5
5
DDR_VREF
group 1AB
DDR_BA0
DDR_BA1
DDR_BA2
5
5
5
5
0402
GND
0402
0402
top/bot
top/bot
R13
200R
200R
R10
VDDIODDR
5
0402
100n/10V
C13
E13
C12
F9
TP12
TP13
DDR_WE#
DDR_CAS#
A5
B5
E9
B6
DDR_CKE
DDR_RAS#
B7
G11
A12
A17
A13
C8
B12
5
5
5
5
5
5
5
5
5
GND
R51
VDDIODDR
R50
DDR_D[0-31]
DDR_DATA
DDR_CS#
DDR_D12
D17
DDR_D24
DDR_D10
DDR_D11
G14
E16
B16
B18
C15
DDR_D8
DDR_D9
F16
E17
F17
G15
DDR_D1
DDR_D2
H17
H13
DDR_D5
DDR_D6
DDR_D7
DDR_D0
D9 DDR_A12
A6 DDR_A13
H12
B8 DDR_A9
F11 DDR_A10
A7 DDR_A11
DNP
DDR_CKE
5
5
5
5
5
5
5
5
5
group 1AB
DDR_CK#
DDR_CK
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
DDR_BA0
DDR_BA1
DDR_BA2
DDR_A13
DDR_A10
DDR_A11
DDR_A12
DDR_A8
DDR_A9
DDR_A6
DDR_A7
DDR_A5
DDR_A4
DDR_A3
DDR_A2
DDR_A1
DDR_A0
4u7/6V3/X5R
C64
1R
0402
GND
R11
BLM15AG121SN1D
L7
5 Differential
5 100 ohms
VDDIODDR
DDR_CK#
DDR_CK
group 1AB
0R
0R
5
DDR_ADDR
DDR_A[0-13]
GND
H8
J7
F2
F8
H2
E7
D2
D8
A7
B2
B8
P9
N1
E3
J3
A3
J8
K8
K2
K9
L7
K7
L8
K3
R8
R3
R7
L2
L3
L1
R2
P7
M2
P8
P3
M3
M7
N2
N8
N3
N7
P2
M8
group 3AB
0402
SAMA5D3x
DDR_VREF
DDR_CALN
DDR_CALP
DDR_BA2
DDR_BA0
DDR_BA1
DDR_WE
DDR_CAS
DDR_CLKN
DDR_CKE
DDR_RAS
DDR_CLK
DDR_DQS3
DDR_DQSN0
DDR_DQSN1
DDR_DQSN2
DDR_DQSN3
DDR_CS
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQM3
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_D28
DDR_D29
DDR_D30
DDR_D25
DDR_D26
DDR_D27
DDR_D22
DDR_D23
DDR_D24
DDR_D21
DDR_D18
DDR_D19
DDR_D20
DDR_D15
DDR_D16
DDR_D17
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_A13
DDR_D0
DDR_D1
DDR_A11
DDR_A12
DDR_A9
DDR_A10
DDR_A8
DDR_A7
C10 DDR_A8
A8
D10 DDR_A6
B9 DDR_A4
E10 DDR_A5
A9 DDR_A2
D11 DDR_A3
0402
GND
VDD
VDDQ
VDDQ
VSSQ
VSSQ
VREF
1k5/1%
R14
R12
1k5/1%
GND
100n/10V
C65
100n/10V
C62
MT47H128M16RT-3:C
VSSQ
VSSDL
VDDQ
VDDQ
VDDL
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VSS
VSSQ
VSSQ
VDDQ
VDDQ
VSS
VSS
VDD
VDD
NC
NC
UDM
LDM
UDQS#/NU
LDQS
LDQS#/NU
UDQS
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ0
DQ1
VDD
VDD
A
DDR_D6
DDR_D7
F1
F9
DDR_D10
D7
D3
D1
C109
5
5
GND
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
DDR_VREF
group 1AB
5
5
100n/10V
C112 100n/10V
C111 100n/10V
100n/10V
100n/10V
C76
C108
100n/10V
C77
100n/10V
C79
C110
100n/10V
100n/10V
100n/10V
C60
5
5
group 2A
L3 & L8
VDDIODDR
100n/10V
DDR_VREF
group 1AB
C57
C56
C53
GND
top/bot
J2
G7
G9
J1
C9
E9
G1
G3
C52
C49
C48
M9
R1
A9
C1
C3
C7
C45
C44
DDR_DQM0
DDR_DQM1
A1
E1
J9
A2
E2
B3
F3
A8
B7
E8
DDR_DQS0
R72 0402
4k7
DDR_DQS1
R73 0402
4k7
DDR_D15
B9
F7
DDR_D13
DDR_D14
D9
B1
DDR_D11
DDR_D12
DDR_D8
DDR_D9
C8
C2
H9
H1
DDR_D0
DDR_D1
DDR_D2
DDR_D[0-15]
DDR_DATA
minimizing crosstalk with [DQ, DQS, DQM]
DDR_D3
DDR_D4
DDR_D5
H7
H3
G2
G8
Zo=50 ohms
VSS
VSS
CK
CK#
CKE
WE#
CAS#
RAS#
CS#
ODT
RFU
RFU
BA0
BA1
BA2
RFU(A13)
A9
A10
A11
A12
A8
A2
A3
A4
A5
A6
A7
A0
A1
U4
L3 & L8
Zo=50 ohms
C11 DDR_A1
Address and control traces may not exceed 1.3 inches (33.0 mm).
Address and control traces must be length-matched to within 0.1 inch (2.54 mm).
Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm).
DQS-4w-DQ-3w-DQM-4w-DQS
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A[0-13]
GND
keeping propagation delay equal
(between 2A & 2B too)
DDR_ADDR
0402
0402
0R
0R
5
DNP
DDR_CKE
5
5
5
5
5
5
5
5
5
group 1AB
DDR_CK#
DDR_CK
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
DDR_BA0
DDR_BA1
DDR_BA2
DDR_A13
DDR_A10
DDR_A11
DDR_A12
DDR_A8
DDR_A9
DDR_A6
DDR_A7
DDR_A5
DDR_A4
DDR_A3
GND
H8
J7
F2
F8
H2
E7
D2
D8
A7
B2
B8
P9
N1
E3
J3
A3
J8
K8
K2
K9
L7
K7
L8
K3
R8
R3
R7
L2
L3
L1
R2
P7
M2
P8
P3
M3
M7
N2
N8
N3
N7
P2
DDR_A1
DDR_A2
M8
B
DQ0
DQ1
VREF
VDDQ
VDDQ
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
NC
NC
UDM
LDM
UDQS#/NU
LDQS
LDQS#/NU
UDQS
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
MT47H128M16RT-3:C
VSSQ
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSSQ
VSSQ
VSS
VSS
VSS
VSS
CK
CK#
CKE
WE#
CAS#
RAS#
CS#
ODT
RFU
RFU
BA0
BA1
BA2
RFU(A13)
A9
A10
A11
A12
A8
A2
A3
A4
A5
A6
A7
A0
A1
G8
J2
G7
G9
J1
C9
E9
G1
G3
A9
C1
C3
C7
M9
R1
A1
E1
J9
A2
E2
B3
F3
A8
B7
E8
F7
B9
D9
B1
D7
D3
D1
R70
GND
100n/10V
5
100n/10V
C120 100n/10V
C119 100n/10V
100n/10V
100n/10V
C113 100n/10V
group 1AB
C61
100n/10V
GND
GND
100n/10V
5
5
5
5
L3 & L8
group 2B
C116
100n/10V
100n/10V
C114 100n/10V
100n/10V
C115 100n/10V
C118
100n/10V
100n/10V
C117
100n/10V
DDR_DQM3
DDR_DQM2
DDR_VREF
C59
C58
C55
C54
C51
C50
C47
C46
VDDIODDR
R71
DDR_DQS2
4k7
0402
DDR_DQS3
4k7
0402
DDR_D31
DDR_D29
DDR_D30
DDR_D28
DDR_D27
DDR_D26
DDR_D24
DDR_D25
DDR_D22
DDR_D23
C8
C2
DDR_D21
F1
F9
DDR_D20
DDR_D19
DDR_D18
DDR_D17
H9
H1
H7
H3
G2
DDR_D16
DDR_D[16-31]
DDR_A0
DDR_DATA
U5
DDR_ADDR
DDR_A[0-13]
Keep nets as short as possible, therefore, DDR2/LPDDR2 devices have to be placed as close as possible to the MPU.
The layout EBI DDR2/LPDDR2 should use controlled impedance traces of Zo = 50 ohm characteristic impedance.
Trace width = 0.13mm (4 mil minimum, 6 mil nominal)
Trace space = 0.30 to 0.38 mm.
GND
R53
VDDIODDR
R52
Data traces may not exceed 1.3 inches (33.0 mm).
Data traces must be length-matched to within 0.1 inch (2.54 mm).
Data traces must match the data group trace lengths to within
0.25 inches (6.35 mm).
B10 DDR_A0
Zo=50 ohms
DDR_A0
GND
DQS-4w-DQ-3w-DQM-4w-DQS
U3-H
keeping propagation delay equal
(between 2A & 2B too)
Figure 4-1.
Schematic SAMA5D3x-CM Memory
13
5.
LPDDR2-SDRAM Power-up and Power-off Considerations
5.1
Power-up Sequence
A specific sequence must be used to power up the LPDDR2-SDRAM device, this procedure is mandatory. Powerup and initialization by means other than those specified will result in undefined operation.
Refer to the LPDDR2-SDRAM datasheet for full details and timings.
5.2
Power-off Sequence
A specific sequence must be used to power off the LPDDR2-SDRAM device, this procedure is mandatory. Poweroff by means other than those specified will result in uncontrolled power-off.
The VDDIODDR power fail must be handled at system level (IRQ or FIQ). When this event occurs the LPDDR2
power-off sequence is to be applied using the LPDDR2_PWOFF bit (bit 3 in MPDDRC_LPR) before the
VDDIODDR power-off.
Uncontrolled power-off sequence can be applied only up to 400 times in the life of a LPDDR2-SDRAM device.
Refer to the LPDDR2-SDRAM datasheet for full details and timings.
14
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
6.
Calibration Considerations
SAMA5D3x embeds a pad calibration feature that performs bus impedance adaptation, improving signal integrity.
This leads to

reduction of overshoots

reduction of Electromagnetic Interference (EMI)

reduction of power consumption on I/Os

eliminating the need of serial resistor on data lines
6.1
DDR2-SDRAM or LPDDR1-SDRAM Calibration
6.1.1
Hardware
DDR2 or LPDDR1 calibration requires connecting a 200Ω resistor on DDR_CALP to GND and on DDR_CALN to
VDDIODDR.
6.1.2
Software
DDR2 or LPDDR1 software calibration is to be done only once and requires following steps:
1.
Set RDIV field in MPDDRC_IO_CALIBR register, according to the board impedance
2.
Calculate TZQIO value using the formula TZQIO = (DDRCLK × 20 ns) + 1
3.
Set TZQIO time in MPDDRC_IO_CALIBR
4.
Activate calibration by setting the 5th bit in High Speed Register (0xFFFFEA24)
6.2
LPDDR2-SDRAM Calibration
6.2.1
Hardware
LPDDR2 calibration requires to connect 240Ω resistor on DDR_CALP to GND and DDR_CALN to VDDIODDR.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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15
6.2.2
Software
LPDDR2 software calibration is to be done only once and requires following steps:
1.
Set RDIV field in MPDDRC_IO_CALIBR register, according to the board impedance
2.
Calculate TZQIO value using the formula TZQIO = (DDRCLK × 20 ns) + 1
3.
Set TZQIO time in MPDDRC_IO_CALIBR
4.
Program Short Calibration Time with ZQCS field in LPDDR2_TIM_CAL, according to the LPDDR2-SDRAM
datasheet
5.
Calculate the calibration pulse over Process Voltage Temperature (PVT) according to the refresh rate, the
temperature and voltage expected change, the temperature and voltage sensitivities defined in LPDDR2SDRAM datasheet, using the formula ZQCorrection / ((TSens × Tdriftrate) + (VSens × Vdriftrate))
6.
Set the value in field COUNT_CAL in LPDDR2_CAL_MR4 register
For example, if TSens = 0.75%/°C, VSens = 0.2%/mV, Tdriftrate = 1°C/sec and driftrate = 15mV/sec, then the
interval between ZQCS commands is calculated as 1.5 / ((0.75 × 1) + (0.2 × 15)) = 0.4 sec.
This LPDDR2-SDRAM devices require a calibration every 0.4s.
The value to be loaded depends on average time between REFRESH commands, tREF.
For an LPDDR2-SDRAM with a time between refresh of 7.8 µs, the value of the Calibration Timer Count bit is
programmed (0.4/7.8 × 10-6) = 0xC852.
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Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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7.
DDR2 Electromagnetic Compatibility (EMC) Improvement
7.1
Simultaneous Switching
Simultaneous switching is the worst enemy of EMC at device operation level. SAMA5D3x embeds pad calibration
feature that performs bus impedance adaptation improving signal integrity, reducing current driven and so power
consumption.
7.2
Overshoots
Overshoots occur when the current driven is too high. SAMA5D3x embeds pad calibration feature that performs
bus impedance adaptation improving signal integrity, reducing overshoots.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
17
8.
Multi-port DDR Controller Configuration
8.1
DDR2-SDRAM Initialization
The DDR2-SDRAM initialization sequence is described in the section “DDR2-SDRAM Initialization” of the
SAMA5D3 Series datasheet. For an example of initialization, see the “DDR2 Initialization Code Example” on page
20.
8.2
LPDDR2-SDRAM Initialization
The LPDDR2-SDRAM initialization sequence is described in the section “Low-power DDR2-SDRAM Initialization”
of the SAMA5D3 Series datasheet.
8.3
Micron® MT47H128M16 DDR2 SDRAM (MPDDRC Configuration Example)
The Micron MT47H128M16 are 256 MB DDR2 SDRAM devices arranged as 16 Mbit × 16 × 8 banks with a CAS
latency of 3 at 134 MHz. These devices are featured on the SAMA5D3x-CM.
Table 8-1 gives the delay in ns extracted from the DDR2 SDRAM datasheet, the corresponding number of cycles
at 134 MHz, and the field to program these values accordingly in a system running at 536 MHz for Processor Clock
and 134 MHz for System Clock.
Table 8-1.
MPDDRC Configuration Example with Micron MT47H128M16
System
Configuration
Description
Value in Number of Value in
Micron
Cycles at SAMA5D3
Datasheet 134 MHz Datasheet
Register
Bit or
Field
Register or
Field Value
System
PLL Frequency
Processor / Bus Clock
System Clock
1072 MHz
CKGR_PLLAR
0x215C3F01
536 / 134 MHz
PMC_MCKR
0x00001202
DDR clock
enable
PMC_SCER
0x00000005
MPDDRC_CR
0x13D
DDR2 Device
(2)
MPDDRC Configuration Register
Number of Columns
10
10
MPDDRC_CR
NC
0x1
Number of Rows
14
14
MPDDRC_CR
NR
0x3
CAS Latency
3
3 cycles
MPDDRC_CR
CAS
0x3
Disable
MPDDRC_CR
DLL
0x0
Weak
MPDDRC_CR
DIC_DS
0x1
Normal
MPDDRC_CR
DIC/DS
0x0
No
MPDDRC_CR
DIS_DLL
0x0
(1)
MPDDRC_CR
OCD
0x0
Not shared
MPDDRC_CR
DMQS
0x0
Disabled
MPDDRC_CR
ENRDM
0x0
Reset DLL
Drive Strength (DDR2 only)
Output Driver Impedance control
Disable DLL
Off-Chip Driver
Mask Data is shared
Enable Read Measure
Weak
MPDDRC_IO_
CALIBR
MPDDRC I/O Calibration Register(2)
Resistor Divider
50Ω
IO Calibration
18
MPDDRC_IO_
CALIBR
RDIV
0x4
MPDDRC_IO_
CALIBR
TZQIO
0x4
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
0x404
Table 8-1.
MPDDRC Configuration Example with Micron MT47H128M16 (Continued)
System
Configuration
Description
Value in Number of Value in
Micron
Cycles at SAMA5D3
Datasheet 134 MHz Datasheet
MPDDRC Timing Parameter 0 Register(2)
Register
Bit or
Field
MPDDRC_TPR0
Register or
Field Value
0x21228226
ACTIVATE to PRECHARGE Time (delay)
45 ns
6
MPDDRC_TPR0
TRAS
0x6
ACTIVATE to READ/WRITE Time (delay)
15 ns
2
MPDDRC_TPR0
TRCD
0x2
Last DATA-IN to PRECHARGE Time (delay)
15 ns
2
MPDDRC_TPR0
TWR
0x2
REFRESH to ACTIVATE Time (delay)
55 ns
8
MPDDRC_TPR0
TRC
0x8
PRECHARGE to ACTIVATE Time (delay)
15 ns
2
MPDDRC_TPR0
TRP
0x2
ACTIVE bankA to ACTIVE BankB (delay)
10 ns
2
MPDDRC_TPR0
TRRD
0x2
Internal Write to Read Delay
7.5 ns
1
MPDDRC_TPR0
TWTR
0x1
2 cycles
2
MPDDRC_TPR0
TMRD
0x2
Load Mode Register Command to ACTIVE or
REFRESH Command (delay)
MPDDRC Timing Parameter 1 Register
MPDDRC_TPR1
0x02C81C1B
Row Cycle Delay
197.5 ns
27
MPDDRC_TPR1
TRFC
0x1B
Exit Self Refresh Delay to Non-Read Command
TRFC +
10 ns
28
MPDDRC_TPR1
TXSNR
0x1C
Exit Self Refresh Delay to Read Command
200 cycles
200
MPDDRC_TPR1
TXSRD
0xC8
Exit Power-down Delay to First Command
2 cycles
2
MPDDRC_TPR1
TXP
0x2
(2)
MPDDRC_TPR2
MPDDRC Timing Parameter 2 Register
Exit Active Power Down Delay to Read
Command (Fast Exit)
2 cycles
2
MPDDRC_TPR2
TXARD
0x2
Exit Active Power Down Delay to Read
Command (Slow Exit)
7
MPDDRC_TPR2
TXARDS
0x7
Row Precharge All Delay
2
MPDDRC_TPR2
TRPA
0x2
2
MPDDRC_TPR2
TRTP
0x2
Read to Precharge
15 ns
MPDDRC Memory Device Register
MPDDRC_MD
0x00000006
Memory Device DDR2-SDRAM
MPDDRC_MD
MD
0x6
Data Bus Width
MPDDRC_MD
DBW
0x0
MPDDRC Refresh Timer Register - Timer
Count
Notes:
0x000002272
32 bits
7.8 µs
MPDDRC_RTR
0x410
1. OCD is not supported, but it is a mandatory step in the DDR2 initialization phase.
2. Any bits or fields of this register not listed in the table must remain unchanged.
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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19
Appendix A. DDR2 Initialization Code Example
This appendix provides the following example of the DDR2 initialization code, associated to the different steps of
the DDR2-SDRAM initialization sequence:
//*---------------------------------------------------------------------------//* \fn
ddram_init
//* \brief Initialization of the DDR Controller
//*---------------------------------------------------------------------------int ddram_init(unsigned int ddram_controller_address, unsigned int ddram_address, struct
SDdramConfig *ddram_config)
{
volatile unsigned int i;
unsigned int cr = 0;
// Initialization Step 1: Program the memory device type
// Configure the DDR controller
write_ddramc(ddram_controller_address, HMPDDRC_MDR, ddram_config->ddramc_mdr);
// Program the DDR Controller
write_ddramc(ddram_controller_address, HMPDDRC_CR, ddram_config->ddramc_cr);
// Initialization Step 2: assume timings for 7.5 ns min clock period
write_ddramc(ddram_controller_address, HMPDDRC_T0PR, ddram_config->ddramc_t0pr);
// pSDDRC->HMPDDRC_T1PR
write_ddramc(ddram_controller_address, HMPDDRC_T1PR, ddram_config->ddramc_t1pr);
// pSDDRC->HMPDDRC_T2PR
write_ddramc(ddram_controller_address, HMPDDRC_T2PR, ddram_config->ddramc_t2pr);
// Initialization Step 3: NOP command -> allow to enable clk
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// Initialization Step 3 (must wait 200 µs) (6 core cycles per iteration, core is at 536 MHz:
// min 17,733 loops)
for (i = 0; i < 17800; i++) {
asm("
nop");
}
// Initialization Step 4: A NOP command is issued to the DDR2-SDRAM
// NOP command -> allow to enable cke
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// wait 400 ns min
for (i = 0; i < 250; i++) {
asm("
nop");
}
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Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
Atmel-11172B-ATARM-Implementation-of-DDR2-and-LPDDR2-on-SAMA5D3x-Devices-ApplicationNote_26-Feb-15
// Initialization Step 5: Set All Bank Precharge
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// wait 400 ns min
for (i = 0; i < 250; i++) {
asm("
nop");
}
// Initialization Step 6: Set EMR operation (EMRS2)
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x4000000)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 7: Set EMR operation (EMRS3)
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x6000000)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 8: Set EMR operation (EMRS1)
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x2000000)) = 0;
// wait 200 cycles min
for (i = 0; i < 10000; i++) {
asm("
nop");
}
// Initialization Step 9: enable DLL reset
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
// Initialization Step 10: reset DLL
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
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21
// Initialization Step 11: Set All Bank Precharge
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 400 ns min
for (i = 0; i < 250; i++) {
asm("
nop");
}
// Initialization Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh
// command (CBR) into the Mode Register.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Set 2nd CBR
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 13: Program DLL field into the Configuration Register to low (Disable
// DLL reset).
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED));
// Initialization Step 14: A Mode Register set (MRS) cycle is issued to program the parameters
// of the DDR2-SDRAM devices.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_LMR_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// Initialization Step 15: Program OCD field into the Configuration Register to high (OCD
// calibration default).
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr | AT91C_DDRC2_OCD_DEFAULT);
// Initialization Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default
// value.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned int*) (ddram_address + 0x2000000))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
22
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// Initialization Step 17: Program OCD field into the Configuration Register to low (OCD
// calibration mode exit). Write a 1 to DIC_DS field to use DDR2 weak drive strength.
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr & (~AT91C_DDRC2_OCD_EXIT));
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr |(AT91C_DDRC2_WEAKSTRENGTH));
// Initialization Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD
// exit.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned int*) (ddram_address + 0x6000000))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 19, 20: A mode Normal command is provided. Program the Normal mode into
// Mode Register.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// Initialization Step 21: Write the refresh rate into the count field in the Refresh Timer
// Register.
// Set Refresh timer
write_ddramc(ddram_controller_address, HMPDDRC_RTR, ddram_config->ddramc_rtr);
// OK, now we are ready to work on the DDRSDR
// wait for the end of calibration
for (i = 0; i < 500; i++) {
asm("
nop");
}
return 0;
}
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23
Appendix B. LPDDR2 Initialization Code Example
This appendix provides the following example of the LPDDR2 initialization code, associated to the different steps
of the LPDDR2-SDRAM initialization sequence:
void LPDDR2_MT42L128M16D1_Initialise( LPDDR2 psst_ddr2 )
{
/****************************************************************************************/
/****************************************************************************************/
// Initialization Step 1
// Program the memory device type into the Memory Device Register
/****************************************************************************************/
/****************************************************************************************/
// Memory device = LPDDR2 => MPDDRC_MD_MD_LPDDR2_SDRAM
// Data bus width = 32 bits => 0x0 (The system is in 64 bits, thus memory data bus width should
be 32 bits)
MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_LPDDR2_SDRAM ;// LPDDR2
/****************************************************************************************/
/****************************************************************************************/
// Initialization Step 2
// Program the features of Low-power DDR2-SDRAM device into the Timing Register
// (asynchronous timing, trc, tras, etc.) and into the Configuration Register (number of
// columns, rows, banks, CAS latency and output drive strength) (see Section 8.3 on
// page 35, Section 8.4 on page 39 and Section 80.5 on page 41).
/****************************************************************************************/
/****************************************************************************************/
//////////////////////////MPDDRC Configuration Register//////////////////////////
// NC = 0x0. Number of collumn to address is 9 (extract from memory data sheet)
// NR = 0x2. Number of row to address is 13 (extract from memory data sheet)
// CAS latency = 3. FPGA platform runs at 30 MHz (depends on the frequency, check memory data
sheet)
// No DLL in LPDDR2 devices => DLL, DIS_DLL and DIC_DS = 0
// ZQ = 0. ZQ_INIT calibration will be performed later
// OCD = 0
// DQMS = 0. Bus isnt shared
// NB = 0.5 8 banks (extract from memory data sheet)
// NDQS = 0. LPDDR2 uses DQS and NDQS
// DECOD = 0. Sequential decoding is choosen (may changed after the initialization)
// UNAL = 1; Unaligned accesses will be performed
MPDDRC->MPDDRC_CR = (psst_ddr2.n_col|
psst_ddr2.n_row
// 9 col + 8 COl supported or not
|
MPDDRC_CR_CAS_3_LPDDR2
// 14 row
|
// CAS 3
MPDDRC_CR_NB_8) |
// 8 banks
MPDDRC_CR_UNAL_SUPPORTED|
// Unaligned accesses
MPDDRC_CR_ENRDM_ON;
24
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// Write the LPDDR2 drive strength according to the PCB. It should be set according to RDIV field
in MPDDRC I/O Calibration Register
// DS Write-only OP<3:0>
// 0000B: reserved
// 0001B: 34.3-ohm typical
// 0010B: 40-ohm typical (default)
// 0011B: 48-ohm typical
// 0100B: 60-ohm typical
// 0101B: reserved for 68.6-ohm typical
// 0110B: 80-ohm typical
// 0111B: 120-ohm typical (optional)
// All others: reserved
MPDDRC->MPDDRC_LPDDR2_LPR|=MPDDRC_LPDDR2_LPR_DS(0x3);
//////////////////////////MPDDRC Timing Parameter
MPDDRC->MPDDRC_TPR0
//////////////////////////
= \
MPDDRC_TPR0_TRAS(psst_ddr2.t_tras)
| /*03-TRAS tRAS Row active time*/
MPDDRC_TPR0_TRCD(psst_ddr2.t_trcd)
| /*04 -TRC tRCD RAS-to-CAS delay*/
MPDDRC_TPR0_TWR(psst_ddr2.t_twr)
| /*05 -TWR tWR WRITE recovery time */
MPDDRC_TPR0_TRC(psst_ddr2.t_trc)
\
\
\
|/*06 -TRC tRC ACTI-to-ACTIVT command period*/
MPDDRC_TPR0_TRP(psst_ddr2.t_trp) |/*07 -TRP tRPpb
Row precharge time
*/
\
\
MPDDRC_TPR0_TRRD(psst_ddr2.t_trrd) |/*08 -TRRD tRRD Active bank a to active bank b*/
\
MPDDRC_TPR0_TWTR(psst_ddr2.t_twtr) | /*09 -TWTR-tWTR Internal WRITE-to-READcommand delay*/
MPDDRC_TPR0_TMRD(psst_ddr2.t_tmrd)/*10 -TMRD-tMRD
MPDDRC->MPDDRC_TPR1
=
\
MPDDRC_TPR1_TRFC(psst_ddr2.t_trfc)
|/*11 -TRFC tRFCab Refresh cycle time
MPDDRC_TPR1_TXSNR(psst_ddr2.t_txsnr) | /*12 -TXSNR
MPDDRC_TPR1_TXSRD(psst_ddr2.t_txsrd)
=
*/ \
SELF REFRESH exit to next valid delay */\
| /*13-TXSRD Exit Self Refresh*/\
MPDDRC_TPR1_TXP(psst_ddr2.t_txp) /*14 -TXP-tXP Exit power-down */
MPDDRC->MPDDRC_TPR2
\
*/;
;
\
MPDDRC_TPR2_TXARD(psst_ddr2.t_txard) |/*15 TXARD-txARD
*/ \
MPDDRC_TPR2_TXARDS(psst_ddr2.t_tards) |/*16 TXARDS-txARDs */ \
MPDDRC_TPR2_TRPA(psst_ddr2.t_trpa)
|/*17 TRPA-tRPpab Row precharge time (all banks)
MPDDRC_TPR2_TRTP(psst_ddr2.t_trtp) |/*18 TRTP-tRTP */
*/
\
\
MPDDRC_TPR2_TFAW(psst_ddr2.t_tfaw) /*19TFAW--tFAW */;
MPDDRC->MPDDRC_LPR= 0x00000000; // Set low power register to normal mode
/****************************************************************************************/
/****************************************************************************************
// Initialization Step 3
// An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP
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25
// command into the Mode Register, the application must set the MODE (MDDRC Command
// Mode) field to 1 in the Mode Register (see Section 8.1 on page 32). Perform a
// write access to any Low-power DDR2-SDRAM address to acknowledge this command.
// Now, clocks which drive Low-power DDR2-SDRAM devices are enabled.
// A minimum pause of 100 ns must be observed to precede any signal toggle.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_NOP_CMD;// NOP to ENABLE CLOCK output
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 100 ns)
/****************************************************************************************
***************************************************************************************
// Initialization Step 4
// An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP
// command into the Mode Register, the application must set MODE to 1 in the Mode
// Register (see Section 8.1 on page 32). Perform a write access to any Low-power
// DDR2-SDRAM address to acknowledge this command. Now, CKE is driven high.
// A minimum pause of 200 ìs must be satisfied before Reset Command.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_NOP_CMD;// NOP to drive CKE high
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 200 us)
/****************************************************************************************
****************************************************************************************
// Initialization Step 5
// A reset command is issued to the Low-power DDR2-SDRAM. Program
// LPDDR2_CMD in the MODE (MDDRC Command Mode) and MRS (Mode Register
// Select LPDDR2) field of the Mode Register, the application must set MODE to 7 and
// MRS to 63. (see Section 8.1 on page 32). Perform a write access to any Low-power
// DDR2-SDRAM address to acknowledge this command. Now, the reset command is issued.
// A minimum pause of 1 ìs must be satisfied before any commands.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_MR=MPDDRC_MR_MRS( 0x3F)| MPDDRC_MR_MODE_LPDDR2_CMD;/// Reset command. MODE =
0x7 and MRS = 0x3F
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 1 us)
/***************************************************************************************
***************************************************************************************
// Initialization Step 6
// A Mode Register Read command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
// application must set MODE to 7 and must set MRS field to 0. (see Section 8.1 on
26
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// page 32). Perform a write access to any Low-power DDR2-SDRAM address to
// acknowledge this command. Now, the Mode Register Read command is issued.
// A minimum pause of 10 ìs must be satisfied before any commands.
****************************************************************************************
****************************************************************************************/
// Mode Register Read
command. MODE = 0x7 and MRS = 0x00
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x00);
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 1 us)
/****************************************************************************************
****************************************************************************************
// Initialization Step 7
A calibration command is issued to the Low-power DDR2-SDRAM. Program the type
of calibration into the Configuration Register, ZQ field, RESET value (see Section 8.3
”MPDDRC Configuration Register” on page 37). In the Mode Register, program the
MODE field to LPDDR2_CMD value, and the MRS field; the application must set
MODE to 7 and MRS to 10 (see Section 8.1 ”MPDDRC Mode Register” on page 34).
Perform a write access to any Low-power DDR2-SDRAM address to acknowledge
this command. Now, the ZQ Calibration command is issued. Program the type of calibration
into the Configuration Register, ZQ field,
****************************************************************************************
***************************************************************************************/
MPDDRC->MPDDRC_CR&=~MPDDRC_CR_ZQ_Msk;
MPDDRC->MPDDRC_CR|=
// Mode Register Read
MPDDRC->MPDDRC_MR=
MPDDRC_CR_ZQ_RESET;
command. MODE = 0x7 and MRS = 0x0A
MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x0A);
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 1 us)
MPDDRC->MPDDRC_CR&=~MPDDRC_CR_ZQ_Msk;
MPDDRC->MPDDRC_CR|=
MPDDRC_CR_ZQ_SHORT;
/****************************************************************************************
****************************************************************************************
// Initialization Step 8
// A Mode Register Write command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field in the Mode Register, the
// application must set MODE to 7 and must set MRS field to 0.5 (see Section 8.1 on
// page 32). The Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular burst length. Perform a
// write access to any Low-power DDR2-SDRAM address to acknowledge this command.
// Now, the Mode Register Write command is issued.
****************************************************************************************
****************************************************************************************/
// Programm LPDDR2 parameters MODE = 0x7 and MRS = 0x01
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x01);
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27
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 9
// Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field in the Mode Register, the
// application must set MODE to 7 and must set MRS field to 2. (see Section 8.1 on
// page 32). The Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular CAS latency. Perform a
// write access to any Low-power DDR2-SDRAM address to acknowledge this command.
// Now, the Mode Register Write command is issued.
****************************************************************************************
***************************************************************************************/
// Programm LPDDR2 CAS MODE = 0x7 and MRS = 0x02
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x02);
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 10
// A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
// application must set MODE to 7 and must set MRS field to 3. (see Section 8.1 on
// page 32). The Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular Drive Strength and Slew
// Rate. Perform a write access to any Low-power DDR2-SDRAM address to acknowledge
// this command. Now, the Mode Register Write command is issued.
****************************************************************************************
****************************************************************************************/
// Programm LPDDR2 DS MODE = 0x7 and MRS = 0x03
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x03);//0x00000307;
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 11
// A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
// application must set MODE to 7 and must set MRS field to 16. (see Section 8.1 on
// page 32). Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular Partial Array Self Refresh
// (PASR). Perform a write access to any Low-power DDR2-SDRAM address to
// acknowledge this command. Now, the Mode Register Write command is issued.
28
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****************************************************************************************
****************************************************************************************/
// Programm LPDDR2 PASR MODE = 0x7 and MRS = 0x10
MPDDRC->MPDDRC_MR=MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x10);// 0x00001007;
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 12
// Write the refresh rate into the COUNT field in the Refresh Timer register (see page
// 33). (Refresh rate = delay between refresh cycles). The Low-power DDR2-SDRAM
// device requires a refresh every 7.81 ìs. With a 100 MHz frequency, the refresh timer
// count register must to be set with (7.81/100 MHz) = 781 i.e. 0x030d.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_RTR&=~MPDDRC_RTR_COUNT_Msk;
MPDDRC->MPDDRC_RTR |=MPDDRC_RTR_COUNT(psst_ddr2.t_refresh);
//MPDDRC->MPDDRC_RTR|= MPDDRC_RTR_ADJ_REF ;// MR4 READ enabled
MPDDRC->MPDDRC_MR= 0x00000000;// Set Normal mode
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Perform
Wait (0xFFFF);
// Launch short ZQ calibration
MPDDRC->MPDDRC_CR&= ~
(MPDDRC_CR_ZQ_Msk);// Enable short calibration in the CR
MPDDRC->MPDDRC_CR |= (MPDDRC_CR_ZQ_SHORT);
MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Perform
// Calculate ZQS: search for tZQCS in the memory datasheet => tZQCS = 180 ns
MPDDRC->MPDDRC_LPDDR2_TIM_CAL =
MPDDRC_LPDDR2_TIM_CAL_ZQCS(psst_ddr2.t_tZQCS);
}
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29
Revision History
Table 8-2.
Doc. Rev.
Revision History
Date
Changes
Reformatted document
General editorial changes throughout
Revised content of “Scope” (now includes mention of SAMA5D36 device)
Added “Reference Documents”
Section 1. “Multi-port DDR Controller Overview”: replaced “The MPDDRC supports a CAS
latency of 2, 3, 4, 5 or 6” with “The MPDDRC supports a CAS latency of 2 and 3”
Table 2-1 "SDRAM Controller Signals": reorganized content; removed “Frequency” column
Renamed Section 4. “Layout and Design Constraints” (was “SDRAM Signal Routing
Considerations”) and revised content
Revised Section 8.1 “DDR2-SDRAM Initialization”
Revised Section 8.2 “LPDDR2-SDRAM Initialization”
Section 8.3 “Micron® MT47H128M16 DDR2 SDRAM (MPDDRC Configuration Example)”:
11172B
26-Feb-15
- in first sentence, corrected “32 Mbit × 16 × 8 banks” to “16 Mbit × 16 × 8 banks”
- replaced all instances of “132 MHz” or “133 MHz” with “134 MHz”
- changed processor clock speed from “528 MHz” to “536 MHz”
- changed PLL frequency from “1056 MHz” to “1072 MHz”
Table 8-1 "MPDDRC Configuration Example with Micron MT47H128M16":
- reformatted table and reorganized content
- updated register names
- deleted “EBI Chip Select Assignment” rows
- added “Drive Strength (DDR2 only)” to MPDDRC_CR parameters
- changed “7 µs” to “7.8 µs” as timer count period for MPDDRC_RTR
Appendix A. “DDR2 Initialization Code Example”: added title and updated introductory
sentence; in Initialization Step 3, changed instance of “528 MHz” to “536 MHz”; updated
Initialization Step 17 to include DDR2 weak drive strength
Added Appendix B. “LPDDR2 Initialization Code Example”
11172A
30
19-Oct-2012
First issue
Implementation of DDR2 and LPDDR2 on SAMA5D3x Devices [APPLICATION NOTE]
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