AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS ISSUE 1.2 APPLICATION NOTE PECL Driver Application Note Overview This application note explains why the output levels of PECL drivers in a CMOS process do not comply with the original bipolar specifications, and proposes some possible workarounds to allow interfacing to standard PECL input stages. Revision 2.0/August 2001 © Semtech Corp. Page 1 www.semtech.com AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS APPLICATION NOTE Table of Contents List of Sections Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 3 4 5 The PECL Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Semtech CMOS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Possible Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Interface Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 List of Figures Figure 4.1 Voltage/Time plot at 155MHz (worst case), 100ohm termination on VDD-1.4V . . . . . . . . . . . . . . . . . . . . .4 Figure 5.1 Voltage/Time plot at 155MHz, 100ohm to VDD-1.65V termination, typical conditions. . . . . . . . . . . . . . . .6 List of Tables Table 2.1 Table 3.1 Table 5.1 Table 5.2 PECL Input and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Semtech CMOS Driver Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Input Levels for Specific devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Output Level Range for Proposed Termination Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Revision 2.0/August 2001 © Semtech Corp. Page 2 www.semtech.com AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS APPLICATION NOTE 1 Introduction This application note is intended to clarify some of the issues surrounding PECL drivers in a CMOS process. There has been some concern because the output levels do not comply with the original bipolar specifications. This note will explain the reasons for this and will propose some possible workarounds to allow interfacing to standard PECL input stages. 2 The PECL Standard The following are the standard PECL input and output levels. Table 2.1 PECL Input and Output Levels Parameter Symbol Min Max Units Driver High Voh VDD-1.02 VDD-0.88 V Driver Low Vol VDD-1.81 VDD-1.62 V Receiver High Vih VDD-1.16 VDD-0.88 V Receiver Low Vil VDD-1.81 VDD-1.48 V 3 Semtech CMOS Driver These are the quoted drive levels for the PECL output stages used on the SETS chips. The max levels are set to the same figures as for the PECL standard but it should be noted that in practice the actual max levels will be lower than these figures. The assumed termination is 50ohm to VDD-2V at a nominal VDD=3.3V. However this means that for VDD=3.6V the termination voltage will be VDD-2.2V hence it is possible to get a min Vol level of VDD-2.1V Table 3.1 Semtech CMOS Driver Levels Parameter Symbol Min Max Units Driver High Voh VDD-1.25 VDD-0.88 V Driver Low Vol VDD-2.1 VDD-1.62 V As can be seen, the output levels are generally lower than the PECL standard as formulated for the original PECL driver designs implemented in BiPolar processes. The reason for this is that the High level is achieved by switching the gate of an NMOS source follower to VDD. The output High level is then determined by the threshold drop of the NMOS transistor. Since these are generally higher in value than the threshold drop of a bipolar transistor this means that the resultant High level for a CMOS driver will be lower than that of a Bipolar driver. Since the drive levels standards were originally set to accommodate the variation range seen in Bipolar transistors this is the reason why the standard does not easily accommodate CMOS processes. Since the Low levels are set by switching the NMOS driver gate to a level less than VDD, it would be possible to make these comply with the Vol standard but since this would result in the signal amplitude being reduced, it was decided to keep the amplitude at the same level and hence the output Low levels are also lower than the original standard. Revision 2.0/August 2001 © Semtech Corp. Page 3 www.semtech.com AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS APPLICATION NOTE 4 Possible Solutions Since the PECL outputs on the SETS chips are differential, the implications of this level shift should be minor as long as the receiving stage can accommodate a slightly lower than standard common mode input voltage. For example the SETS PECL receivers can have an input common mode range anywhere between 0V and VDD and as long as the differential input swing is greater than 200mV the signal will be correctly received. However, if it is essential that the receiving stage sees a higher common mode switching point then this can be achieved albeit at the expense either of reduced signal amplitude or reduced bandwidth The normal PECL termination is 50ohm to VDD-2V. If the impedance is increased then the Voh levels will increase since there is less pull down current on the NMOS output transistor. However to achieve a significantly higher Voh would require a load impedance of around 500ohm which would drastically reduce bandwidth although the signal swing would be essentially unchanged. A possible compromise is to increase the load impedance by a smaller factor but also increase the effective termination voltage to a value higher than VDD-2V. The following plot shows operation at 155MHz with a 100ohm termination to VDD-1.4V. For VDD=3.3V this can be achieved by a 180ohm resistor from VDD to the output and a 240ohm resistor from the output to Ground. Figure 4.1 Voltage/Time plot at 155MHz (worst case), 100ohm termination on VDD-1.4V As can be seen, the Voh level has now improved from VDD-1.25V to VDD-1.05V and the bandwidth has been maintained, however the signal amplitude has now decreased from around 600mV to 250mV. For different receivers and operating speeds there will be different optimum terminations and these can be determined on a case by case basis. Revision 2.0/August 2001 © Semtech Corp. Page 4 www.semtech.com AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS APPLICATION NOTE 5 Interface Recommendations The following table gives the input level specifications for some interface chips which may need to be driven by the CMOS PECL output stages. Table 5.1 Input Levels for Specific devices Device Symbol SK1500 SK1900 SK100LVE111 ACS8941 Min Max Units Vih VDD-1.25 (1) VDD V Vil 0 VDD-0.2 V Vih VDD-1.25 (1) VDD V Vil 0 VDD-0.2 V Vih VDD-1.165 VDD-0.88 V Vil VDD-1.81 VDD-1.475 V Vih 1.6 VDD V Vil 0 VDD V Notes: (i) This is a specification relaxation from an original figure of VDD-1V. Using a standard termination of 50ohm to VDD-2V the CMOS PECL drivers will just comply with the input specifications of all the above chips apart from the SK100E111. In order to have a general solution that will satisfy all four chips, the following termination scheme is proposed: 100ohm to VDD-1.65V (at VDD=3.3V). This can be achieved with a 200ohm resistor from the output to VDD plus 200ohm from the output to Ground. This will give the following output level range over the whole process and temperature range and for supply voltages between 3V and 3.6V Table 5.2 Output Level Range for Proposed Termination Scheme Parameter Symbol Min Typ Max Units Driver High Voh VDD-1.15 VDD-1.1 VDD-0.85 V Driver Low Vol VDD-1.8 VDD-1.65 VDD-1.5 V Note that since the termination resistance is now 100ohm that any long connection runs should be implemented with 100ohm stripline on the PCB instead of the usual 50ohm. The following plot shows operation at 155MHz with the above termination under typical conditions. Revision 2.0/August 2001 © Semtech Corp. Page 5 www.semtech.com AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS Figure 5.1 APPLICATION NOTE Voltage/Time plot at 155MHz, 100ohm to VDD-1.65V termination, typical conditions. Revision 2.0/August 2001 © Semtech Corp. Page 6 www.semtech.com AN-SETS-5 PECL Driver ADVANCED COMMUNICATIONS APPLICATION NOTE Revision History Revision Date Reference Description of changes 1.0 13/Dec/2000 All Pages First draft 1.1 15/Dec/2000 New pages 4and 5 Interface recommendations added. 2.0 01/Aug/2001 All pages Reformatted throughout Contacts For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: [email protected] [email protected] Internet: http://www.semtech.com USA: 652 Mitchell Road, Newbury Park, CA 91320-2289 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE Semtech Ltd.,Units 2-3 Park Court, Premier Way, Romsey, Hampshire, SO51 9AQ. Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601 ISO9001 CERTIFIED Revision 2.0/August 2001 © Semtech Corp. Page 7 www.semtech.com