SUM110N06-3m9H-DS

SPICE Device Model SUM110N06-3m9H
Vishay Siliconix
N-Channel 60-V (D-S) 175°C MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Model Subcircuit)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70737
S-62012Rev. B, 09-Oct-06
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SPICE Device Model SUM110N06-3m9H
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = 250 µA
3.7
ID(on)
VDS = 5 V, VGS = 10 V
1380
VGS = 10 V, ID = 30 A
0.0033
VGS = 10 V, ID = 30 A, TJ = 125°C
0.0053
VGS = 10 V, ID = 30 A, TJ = 175°C
0.0064
IF = 85 A, VGS = 0 V
0.92
1.1
11860
15800
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistance a
Forward Voltage a
Dynamic
rDS(on)
VSD
V
A
0.0033
Ω
S
b
Input Capacitance
Ciss
Output Capacitance
Coss
1050
1050
Reverse Transfer Capacitance
Crss
610
600
Total Gate Charge c
Qg
230
200
Gate-Source Charge
Gate-Drain Charge c
c
Qgs
Qgd
VGS = 0 V, VDS = 25 V, f = 1 MHz
VDS = 30 V, VGS = 10 V, ID = 110 A
80
80
45
45
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
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Document Number: 70737
S-62012Rev. B, 09-Oct-06
SPICE Device Model SUM110N06-3m9H
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 70737
S-62012Rev. B, 09-Oct-06
www.vishay.com
3
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Document Number: 91000
Revision: 18-Jul-08
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