PDF Data Sheet Rev. B

a
High Speed, Low Power
Wide Supply Range Amplifier
AD817
CONNECTION DIAGRAM
FEATURES
Low Cost
High Speed
50 MHz Unity Gain Bandwidth
350 V/ms Slew Rate
45 ns Settling Time to 0.1% (10 V Step)
Flexible Power Supply
Specified for Single (+5 V) and
Dual (65 V to 615 V) Power Supplies
Low Power: 7.5 mA max Supply Current
High Output Drive Capability
Drives Unlimited Capacitive Load
50 mA Minimum Output Current
Excellent Video Performance
70 MHz 0.1 dB Bandwidth (Gain = +1)
0.04% & 0.088 Differential Gain & Phase Errors
@ 3.58 MHz
Available in 8-Pin SOIC and 8-Pin Plastic Mini-DIP
8-Pin Plastic Mini-DIP (N) and
SOIC (R) Packages
8
NULL
2
7
+VS
+IN
3
6
OUTPUT
–VS
4
5
NC
NULL
1
–IN
AD817
TOP VIEW
NC = NO CONNECT
The AD817 is fully specified for operation with a single +5 V
power supply and with dual supplies from ± 5 V to ± 15 V. This
power supply flexibility, coupled with a very low supply current
of 7.5 mA and excellent ac characteristics under all power supply conditions, make the AD817 the ideal choice for many demanding yet power sensitive applications.
PRODUCT DESCRIPTION
The AD817 is a low cost, low power, single/dual supply, high
speed op amp which is ideally suited for a broad spectrum of
signal conditioning and data acquisition applications. This
breakthrough product also features high output current drive
capability and the ability to drive an unlimited capacitive load
while still maintaining excellent signal integrity.
The 50 MHz unity gain bandwidth, 350 V/µs slew rate and settling time of 45 ns (0.1%) make possible the processing of high
speed signals common to video and imaging systems. Furthermore, professional video performance is attained by offering differential gain & phase errors of 0.04% & 0.08° @ 3.58 MHz
and 0.1 dB flatness to 70 MHz (gain = +1).
In applications such as ADC buffers and line drivers the AD817
simplifies the design task with its unique combination of a
50 mA minimum output current and the ability to drive
unlimited capacitive loads.
The AD817 is available in 8-pin plastic mini-DIP and SOIC
packages.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD817AN
AD817AR
–40°C to +85°C
–40°C to +85°C
8-Pin Plastic DIP
N-8
8-Pin Plastic SOIC R-8
1kΩ
+VS
5V
3.3µF
500ns
100
90
0.01µF
HP
PULSE
GENERATOR
VIN
1kΩ
2
AD817
50Ω
3
100pF
LOAD
7
4
VOUT
6
0.01µF
CL
1000pF
TEKTRONIX
P6201 FET
PROBE
10
0%
3.3µF
1000pF
LOAD
–VS
AD817 Driving a Large Capacitive Load
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD817–SPECIFICATIONS (@ T = +258C, unless otherwise noted)
A
Parameter
Conditions
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Bandwidth for 0.1 dB Flatness
Gain = +1
Full Power Bandwidth1
VOUT = 5 V p-p
RLOAD = 500 Ω
VOUT = 20 V p-p
RLOAD = 1 kΩ
RLOAD = 1 kΩ
Gain = 1
Slew Rate
Settling Time to 0.1%
Total Harmonic Distortion
Differential Gain Error
(RLOAD = 150 Ω)
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
FC = 1 MHz
NTSC
Gain = +2
Differential Phase Error
(RLOAD = 150 Ω)
NTSC
Gain = +2
Settling Time to 0.01%
VS
Min
AD817A
Typ
Max
Units
±5 V
± 15 V
0, +5 V
±5 V
± 15 V
0, +5 V
30
45
25
18
40
10
35
50
29
30
70
20
MHz
MHz
MHz
MHz
MHz
MHz
15.9
MHz
5.6
250
350
200
45
45
70
70
63
0.04
0.05
0.11
0.08
0.06
0.14
MHz
V/µs
V/µs
V/µs
ns
ns
ns
ns
dB
%
%
%
Degrees
Degrees
Degrees
±5 V
± 15 V
±5 V
± 15 V
0, +5 V
±5 V
± 15 V
±5 V
± 15 V
± 15 V
± 15 V
±5 V
0, +5 V
± 15 V
±5 V
0, +5 V
200
300
150
± 5 V to ± 15 V
INPUT OFFSET VOLTAGE
0.5
TMIN to TMAX
Offset Drift
0.1
0.1
2
3
mV
mV
µV/°C
10
INPUT BIAS CURRENT
± 5 V, ± 15 V
3.3
6.6
10
4.4
µA
µA
µA
± 5 V, ± 15 V
25
200
500
nA
nA
nA/°C
TMIN
TMAX
INPUT OFFSET CURRENT
TMIN to TMAX
Offset Current Drift
OPEN LOOP GAIN
0.08
0.1
0.3
VOUT = ± 2.5 V
RLOAD = 500 Ω
TMIN to TMAX
RLOAD = 150 Ω
VOUT = ± 10 V
RLOAD = 1 kΩ
TMIN to TMAX
VOUT = ± 7.5 V
RLOAD = 150 Ω
(50 mA Output)
±5 V
± 15 V
± 15 V
±5
± 15 V
± 15 V
2
1.5
1.5
4
3
V/mV
V/mV
V/mV
4
2.5
6
5
V/mV
V/mV
2
4
V/mV
78
86
80
100
120
100
dB
dB
dB
75
72
86
dB
dB
COMMON-MODE REJECTION
VCM = ± 2.5 V
VCM = ± 12 V
POWER SUPPLY REJECTION
VS = ± 5 V to ± 15 V
TMIN to TMAX
INPUT VOLTAGE NOISE
f = 10 kHz
± 5 V, ± 15 V
15
nV/√Hz
INPUT CURRENT NOISE
f = 10 kHz
± 5 V, ± 15 V
1.5
pA/√Hz
–2–
REV. B
AD817
VS
Min
AD817A
Typ
Max
Units
±5 V
+3.8
–2.7
+13
–12
+3.8
+1.2
+4.3
–3.4
+14.3
–13.4
+4.3
+0.9
V
V
V
V
V
V
3.3
3.2
13.3
12.8
+1.5,
+3.5
50
50
30
3.8
3.6
13.7
13.4
±V
±V
±V
±V
90
V
mA
mA
mA
mA
INPUT RESISTANCE
300
kΩ
INPUT CAPACITANCE
1.5
pF
8
Ω
Parameter
Conditions
INPUT COMMON-MODE
VOLTAGE RANGE
± 15 V
0, +5 V
OUTPUT VOLTAGE SWING
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 1 kΩ
RLOAD = 500 Ω
RLOAD = 500 Ω
±5 V
±5 V
± 15 V
± 15 V
0, +5 V
± 15 V
±5 V
0, +5 V
± 15 V
Output Current
Short-Circuit Current
OUTPUT RESISTANCE
POWER SUPPLY
Operating Range
Open Loop
Dual Supply
Single Supply
± 2.5
+5
±5 V
±5 V
± 15 V
± 15 V
Quiescent Current
TMIN to TMAX
TMIN to TMAX
7.0
7.0
± 18
+36
7.5
7.5
7.5
7.5
V
V
mA
mA
mA
mA
NOTES
1
Full power bandwidth = slew rate/2 π VPEAK.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
2.0
MAXIMUM POWER DISSIPATION – Watts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Small Outline (R) . . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Output Short Circuit Duration . . . . . . . . See Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 8-pin plastic package: θJA = 100°C/watt;
8-pin SOIC package: θJA = 160°C/watt.
8-PIN MINI-DIP PACKAGE
1.5
1.0
8-PIN SOIC PACKAGE
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE – °C
70
80 90
Maximum Power Dissipation vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD817 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
TJ = +150°C
–3–
WARNING!
ESD SENSITIVE DEVICE
AD817–Typical Characteristics
8.0
QUIESCENT SUPPLY CURRENT – mA
INPUT COMMON-MODE RANGE – ± Volts
20
15
+VCM
10
–VCM
5
0
0
5
10
15
SUPPLY VOLTAGE – ± Volts
+85°C
-40°C
6.5
0
15
350
SLEW RATE – V/µs
400
RL = 500Ω
10
10
15
SUPPLY VOLTAGE – ±Volts
20
RL = 150Ω
300
250
5
200
0
5
10
15
SUPPLY VOLTAGE – ±Volts
20
0
5
10
15
SUPPLY VOLTAGE – ±Volts
20
Figure 5. Slew Rate vs. Supply Voltage
Figure 2. Output Voltage Swing vs. Supply
100
CLOSED-LOOP OUTPUT IMPEDANCE – Ohms
30
OUTPUT VOLTAGE SWING – Volts p-p
5
Figure 4. Quiescent Supply Current vs. Supply Voltage
for Various Temperatures
20
0
+25°C
7.0
6.0
20
Figure 1. Common-Mode Voltage Range vs. Supply
OUTPUT VOLTAGE SWING – ±Volts
7.5
25
VS = ±15V
20
15
10
VS = ±5V
5
100
1k
LOAD RESISTANCE – Ω
1
0.1
0.01
1k
0
10
10
10k
Figure 3. Output Voltage Swing vs. Load Resistance
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 6. Closed-Loop Output Impedance vs. Frequency
–4–
REV. B
AD817
100
5
4
3
2
+100
+80
80
OPEN-LOOP GAIN – dB
INPUT BIAS CURRENT – µA
6
PHASE ±5V OR
±15V SUPPLIES
GAIN ±15V SUPPLIES
+60
60
+40
40
GAIN ±5V SUPPLIES
+20
20
PHASE MARGIN – Degrees
7
0
0
RL = 1kΩ
1
–60
–40
–20
0
20
40
60
80
100
120
–20
1k
140
TEMPERATURE – °C
Figure 7. Input Bias Current vs. Temperature
10k
100k
1M
10M
FREQUENCY – Hz
100M
1G
Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
130
7
110
OPEN-LOOP GAIN – V/mV
SHORT CIRCUIT CURRENT – mA
±15V
6
SOURCE CURRENT
90
SINK CURRENT
70
50
30
–60
5
±5V
4
3
2
–40
–20
0
20
40
60
80
TEMPERATURE – °C
100
120
1
100
140
Figure 8. Short Circuit Current vs. Temperature
1k
LOAD RESISTANCE – Ohms
10k
Figure 11. Open Loop Gain vs. Load Resistance
100
100
80
60
GAIN BANDWIDTH
40
40
–40
–20
0
20
40
60
80
TEMPERATURE – °C
100
120
60
NEGATIVE
SUPPLY
50
40
30
20
20
140
10
100
Figure 9. Unity Gain Bandwidth and Phase Margin
vs. Temperature
REV. B
POSITIVE
SUPPLY
70
PSR – dB
60
20
–60
80
80
PHASE MARGIN
UNITY GAIN BANDWIDTH – MHz
PHASE MARGIN – Degrees
90
1k
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 12. Power Supply Rejection vs. Frequency
–5–
AD817–Typical Characteristics
120
–40
VIN = 1V p-p
GAIN = +2
HARMONIC DISTORTION – dB
–50
CMR – dB
100
80
60
–60
–70
2nd HARMONIC
–80
3rd HARMONIC
–90
40
1k
10k
100k
FREQUENCY – Hz
1M
–100
100
10M
Figure 13. Common-Mode Rejection vs. Frequency
10k
100k
FREQUENCY – Hz
1M
10M
Figure 16. Harmonic Distortion vs. Frequency
30
Hz
50
RL = 1kΩ
INPUT VOLTAGE NOISE – nV/
OUTPUT VOLTAGE – Volts p-p
1k
20
RL = 150Ω
10
0
100k
1M
10M
FREQUENCY – Hz
40
30
20
10
0
100M
3
Figure 14. Large Signal Frequency Response
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 17. Input Voltage Noise Spectral Density
10
380
0.1%
6
360
4
SLEW RATE – V/µs
OUTPUT SWING FROM 0 TO ±V
8
0.01%
1%
2
0
–2
1%
0.01%
–4
340
320
–6
0.1%
–8
–10
0
20
40
60
80
100
SETTLING TIME – ns
120
140
300
–60
160
Figure 15. Output Swing and Error vs. Settling Time
–40
–20
0
20
40
60
80
TEMPERATURE – °C
100
120
140
Figure 18. Slew Rate vs. Temperature
–6–
REV. B
0.05
DIFF GAIN
DIFFERENTIAL PHASE – Degrees
0.04
0.03
0.1
0.08
DIFFERENTIAL GAIN – Percent
AD817
1kΩ
3.3µF
+V S
0.01µF
HP
PULSE (LS)
OR FUNCTION
(SS)
GENERATOR
DIFF PHASE
2
VIN 100Ω
3
7
VOUT
AD817
6
4
0.01µF
50Ω
0.06
3.3µF
TEKTRONIX
P6201 FET
PROBE
TEKTRONIX
7A24
PREAMP
RL
–VS
0.04
±5
±10
SUPPLY VOLTAGE – Volts
±15
Figure 19. Differential Gain and Phase vs.
Supply Voltage
Figure 22. Noninverting Amplifier Connection
5
4
3
1kΩ
1kΩ
V OUT
VIN
CC
GAIN – dB
2
VS
±15V
±5V
+5V
CC
3pF
4pF
6pF
1
5V
0.1dB
FLATNESS
50ns
100
16MHz
14MHz
12MHz
90
VS = ±15V
0
–1
V S = ±5V
–2
10
0%
–3
VS = +5V
–4
–5
100k
1M
5V
10M
FREQUENCY – Hz
100M
Figure 20. Closed-Loop Gain vs. Frequency,
Gain = –1
Figure 23. Noninverting Large Signal Pulse
Response, RL = 1 kΩ
5
4
1kΩ
3
GAIN – dB
2
V OUT
V IN
150Ω
VS
±15V
±5V
+5V
200mV
0.1dB
FLATNESS
70MHz
26MHz
17MHz
1
100
90
V S = ±15V
0
–1
V S = ±5V
–2
10
0%
V S = +5V
–3
200mV
–4
–5
100k
1M
10M
FREQUENCY – Hz
100M
Figure 21. Closed-Loop Gain vs. Frequency,
Gain = +1
REV. B
20ns
Figure 24. Noninverting Small Signal Pulse
Response, RL = 1 kΩ
–7–
AD817–Typical Characteristics
5V
5V
50ns
100
100
90
90
10
10
0%
0%
5V
50ns
5V
Figure 28. Inverting Large Signal Pulse
Response, RL = 1 kΩ
Figure 25. Noninverting Large Signal Pulse
Response, RL = 150 Ω
200mV
20ns
200mV
100
100
90
90
10
10
0%
0%
200mV
50ns
200mV
Figure 29. Inverting Small Signal Pulse
Response, RL = 1 kΩ
Figure 26. Noninverting Small Signal Pulse
Response, RL = 150 Ω
1kΩ
3.3µF
+V S
0.01µF
HP
RIN
PULSE (LSIG) V
IN 1kΩ
OR FUNCTION
(SSIG)
GENERATOR
50Ω
2
3
7
VOUT
AD817
6
4
0.01µF
3.3µF
TEKTRONIX
P6201 FET
PROBE
TEKTRONIX
7A24
PREAMP
RL
–VS
Figure 27. Inverting Amplifier Connection
–8–
REV. B
AD817
DRIVING CAPACITIVE LOADS
+VS
The internal compensation of the AD817, together with its high
output current drive, permit excellent large signal performance
while driving extremely high capacitive loads.
1kΩ
OUTPUT
3.3µ F
+V S
CF
–IN
0.01µF
HP
PULSE
GENERATOR
VIN
RIN
1kΩ
2
50Ω
3
7
VOUT
AD817
6
4
0.01µF
TEKTRONIX
P6201 FET
PROBE
TEKTRONIX
7A24
PREAMP
+IN
CL
1000pF
–VS
3.3µF
NULL 1
NULL 8
–VS
Figure 31. Simplified Schematic
Figure 30a. Inverting Amplifier Driving a 1000 pF
Capacitive Load
5V
INPUT CONSIDERATIONS
An input protection resistor (RIN in Figure 22) is required in circuits where the input to the AD817 will be subjected to transient or continuous overload voltages exceeding the +6 V
maximum differential limit. This resistor provides protection for
the input transistors by limiting their maximum base current.
500ns
100
100pF
90
For high performance circuits, it is recommended that a “balancing” resistor be used to reduce the offset errors caused by
bias current flowing through the input and feedback resistors.
The balancing resistor equals the parallel combination of RIN
and RF and thus provides a matched impedance at each input
terminal. The offset voltage error will then be reduced by more
than an order of magnitude.
1000pF
10
0%
5V
GROUNDING & BYPASSING
When designing high frequency circuits, some special precautions are in order. Circuits must be built with short interconnect
leads. When wiring components, care should be taken to provide a low resistance, low inductance path to ground. Sockets
should be avoided, since their increased interlead capacitance
can degrade circuit bandwidth.
Figure 30b. Inverting Amplifier Pulse Response While
Driving Capacitive Loads
THEORY OF OPERATION
The AD817 is a low cost, wide band, high performance operational amplifier which effectively drives heavy capacitive or resistive loads. It also provides a constant slew rate, bandwidth and
settling time over its entire specified temperature range.
Feedback resistors should be of low enough value (<1 kΩ) to
assure that the time constant formed with the inherent stray
capacitance at the amplifier’s summing junction will not limit
performance. This parasitic capacitance, along with the parallel
resistance of RF/RIN, form a pole in the loop transmission which
may result in peaking. A small capacitance (1 pF–5 pF) may be
used in parallel with the feedback resistor to neutralize this effect.
The AD817 (Figure 31) consists of a degenerated NPN differential pair driving matched PNPs in a folded-cascode gain stage.
The output buffer stage employs emitter followers in a class AB
amplifier which delivers the necessary current to the load while
maintaining low levels of distortion.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of 0.1 µF
are recommended.
The capacitor, CF, in the output stage mitigates the effect of
capacitive loads. At low frequencies, and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case, CF is bootstrapped and does not
contribute to the overall compensation capacitance of the device.
As the capacitive load is increased, a pole is formed with the
output impedance of the output stage. This reduces the gain,
and therefore, CF is incompletely bootstrapped. Effectively,
some fraction of CF contributes to the overall compensation
capacitance, reducing the unity gain bandwidth. As the load
capacitance is further increased, the bandwidth continues to fall,
maintaining the stability of the amplifier.
+VS
2
7
AD817
3
6
8
1
4
10kΩ
VOS ADJUST
–VS
Figure 32. Offset Null Configuration
REV. B
–9–
AD817
OFFSET NULLING
AD817 SETTLING TIME
Settling time is comprised primarily of two regions. The first is
the slew time in which the amplifier is overdriven, where the
output voltage rate of change is at its maximum. The second is
the linear time period required for the amplifier to settle to
within a specified percent of the final value.
0
–2
6
4
2
SETTLING TIME TO %
OF FINAL VALUE
0
–6
–8
–10
SETTLING TIME TO %
OF FINAL VALUE
8
OUTPUT SWING – Volts
–4
10
0.05
0
0.05
OUTPUT SWING – Volts
Measuring the rapid settling time of AD817 (45 ns to 0.1% and
70 ns to 0.01%–10 V step) requires applying an input pulse with
a very fast edge and an extremely flat top. With the AD817 configured in a gain of –1, a clamped false summing junction responds when the output error is within the sum of two diode
voltages (ª1 volt). The signal is then amplified 20 times by a
clamped amplifier whose output is connected directly to a sampling oscilloscope. Figures 33 and 34 show the settling time of
the AD817, with a 10 volt step applied.
The input offset voltage of the AD817 is inherently very low.
However, if additional nulling is required, the circuit shown in
Figure 32 can be used. The null range of the AD817 in this configuration is ± 15 mV.
0.20
0.15
0.10
0.05
0
0.05
0.10
0
50
100
150
200
250
300
350
400
0.15
0.20
Figure 34. Settling Time in ns 0 V to –10 V
0
50
100
150
200
250
300
350
400
Figure 33. Settling Time in ns 0 V to +10 V
2×
HP2835
5
3
100Ω
2×
HP2835
AD829
6
0.47µF
4
2
0.01µF
0.01µF
0.47µF
–V S +V S
100Ω
0 TO ±10V
POWER
SUPPLY
1.9kΩ
EI&S
DL1A05GM
MERCURY RELAY
7, 8
13
1, 14
50Ω
COAX
CABLE
NOTE:
USE CIRCUIT BOARD
WITH GROUND PLANE
FALSE
SUMMING
NODE
NULL
ADJUST
1kΩ
2
TTL LEVEL
SIGNAL
GENERATOR
50Hz
OUTPUT
100Ω
1kΩ
500Ω
DEVICE
UNDER
TEST
5–18pF
500Ω
2
AD817
50Ω
6
10pF
SCOPE PROBE
CAPACITANCE
7
3
4
2.2µF
DIGITAL
GROUND
2.2µF
ANALOG
GROUND
SETTLING
OUTPUT
SHORT, DIRECT
CONNECTION TO
TEKTRONIX TYPE 11402
OSCILLOSCOPE PREAMP
INPUT SECTION
7
ERROR
SIGNAL
OUTPUT
15pF
1MΩ
ERROR AMPLIFIER
VERROR OUTPUT × 10
0.01µF
TEKTRONIX P6201
FET PROBE TO
TEKTRONIX TYPE
11402
OSCILLOSCOPE
PREAMP INPUT
SECTION
0.01µF
+V S
–V S
Figure 35. Settling Time Test Circuit
–10–
REV. B
AD817
A HIGH PERFORMANCE ADC INPUT BUFFER
+V S
High performance analog to digital converters (ADCs) require
input buffers with correspondingly high bandwidths and very
low levels of distortion. Typical requirements include distortion
levels of –60 dB to –70 dB for a 1 volt p-p signal and bandwidths of 10 MHz or more. In addition, an ADC buffer may
need to drive very large capacitive loads.
R3
1kΩ
C2
0.1µ F
The circuit of Figure 36 is useful for driving high speed converters such as the differential input of the AD733, 10-bit ADC.
This circuit may be used with other converters with only minor
modifications. Using the AD817 provides the user with the option of either operating the buffer in differential mode or from a
single +5 volt supply. Operating from a +5 volt power supply
helps to avoid overdriving the ADC—a common problem with
buffers operating at higher supply voltages.
3.3µF
0.01µF
R1
9kΩ
2
C1
0.1µF
7
COUT
AD817
VIN
3
6
4
C3
0.1µF
Figure 37. Single Supply Amplifier Configuration
Referring to Figure 37, careful consideration should be given to
the proper selection of component values. The choices for this
particular circuit are: R1+ R3//R2 combine with C1 to form a
low frequency corner of approximately 300 Hz.
1kΩ
+V S
1kΩ
AD817
3
4
MAX
6
+V S
AD773
10-BIT
18MHz
ADC
0.1µF
7
3
AD817
1kΩ
26 VINA
0.1µF
–VS
52.5Ω
2
+V S
4
6
27 VINB
0.1µF
–VS
100µF
25V
ADREF43
COMMON
1kΩ
100µF
25V
–5V
0.1µF
7
2
+5V
VOLTAGE
REFERENCE
+2.5V
–VS
Figure 36. A Differential Input Buffer for High Bandwidth ADCs
REV. B
CL
200pF
Combining R3 with C2 forms a low-pass filter with a corner
frequency of 1.5 kHz. This is needed to maintain amplifier
PSRR, since the supply is connected to VIN through the input
divider. The values for RL and CL were chosen to demonstrate
the AD817’s exceptional output drive capability. In this configuration, the output is centered around 2.5 V. In order to
eliminate the static dc current associated with this level, C3 was
inserted in series with RL.
Another exciting feature of the AD817 is its ability to perform
well in a single supply configuration. The AD817 is ideally
suited for applications that require low power dissipation and
high output current and those which need to drive large capacitive loads, such as high speed buffering and instrumentation.
VIN
500mVp-p
VOUT
RL
150Ω
R2
10kΩ
SINGLE SUPPLY OPERATION
50Ω
COAX
CABLE
SELECT C1, R1, R2 & R3
FOR DESIRED LOW
FREQUENCY CORNER.
(R2 = R1 + R3)
–11–
AD817
(10.24 V for a 1 kΩ resistor). Note that since the DAC generates a positive current to ground, the voltage at the amplifier
output will be negative. A 100 Ω series resistor between the
noninverting amplifier input and ground minimizes the offset
effects of op amp input bias currents.
HIGH SPEED DAC BUFFER
The wide bandwidth and fast settling time of the AD817 make
it a very good output buffer for high speed current output D/A
converters like the AD668. As shown in Figure 38, the op amp
establishes a summing node at ground for the DAC output. The
output voltage is determined by the amplifier’s feedback resistor
C1707b–5–6/95
+15V
10µF
TO ANALOG
GROUND PLANE
0.1µF
1
VCC 24
MSB
2
REFCOM 23
3
REFIN1 22
4
REFIN2 21
1V NOMINAL
REFERENCE INPUT
10kΩ
1kΩ
5
DIGITAL
INPUTS
I OUT 20
AD668
6
R LOAD 19
7
ACOM 18
8
LCOM 17
100Ω
AD817
ANALOG GROUND PLANE
ANALOG
SUPPLY
GROUND
10µF
9
IBPO 16
10
VEE 15
11
THCOM 14
12 LSB
ANALOG
OUTPUT
0.1µF
–15V
100pF
1kΩ
+5V
VTH 13
Figure 38. High Speed DAC Buffer
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic Mini-DIP
(N-8)
5
0.25
(6.35)
PIN 1
1
0.018±0.003
(0.46±0.08)
0.1968 (5.00)
0.1890 (4.80)
0.035±0.01
(0.89±0.25)
0.18±0.03
(4.57±0.76)
0.10
(2.54)
BSC
0.033
(0.84)
NOM
0.2440 (6.20)
0.2284 (5.80)
4
1
0.30 (7.62)
REF
0.39 (9.91) MAX
0.125
(3.18)
MIN
0.1574 (4.00)
0.1497 (3.80)
PIN 1
4
0.165±0.01
(4.19±0.25)
5
8
0.31
(7.87)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.011±0.003
(0.28±0.08)
0.0500
(1.27)
BSC
15 °
0°
0.0196 (0.50)
x 45 °
0.0099 (0.25)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
SEATING
PLANE
–12–
REV. B
PRINTED IN U.S.A.
8
8-Pin SOIC
(SO-8)