Precision Micropower, OVP, RRIO Operational Amplifier ADA4091-2/ADA4091-4 Data Sheet PIN CONFIGURATIONS Single-supply operation: 3.0 V to 30 V Wide input voltage range Rail-to-rail output swing Low supply current: 200 μA/amplifier Wide bandwidth: 1.2 MHz Slew rate: 0.46 V/μs Low offset voltage: 250 μV maximum No phase reversal Overvoltage protection (OVP) 25 V above/below supply rails at ±5 V 12 V above/below supply rails at ±15 V OUTA 1 8 +V –INA 2 ADA4091-2 7 OUTB +INA 3 TOP VIEW (Not to Scale) 6 –INB 5 +INB –V 4 07671-001 FEATURES Figure 1. 8-Lead, Narrow-Body SOIC (R-8) OUTA 1 8 +V –INA 2 ADA4091-2 TOP VIEW (Not to Scale) +INA 3 7 OUTB 6 –INB NOTES 1. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–. APPLICATIONS 07571-102 5 +INB –V 4 14 OUTD –INA 2 13 –IND +INA 3 ADA4091-4 12 +IND TOP VIEW (Not to Scale) 11 –V +INB 5 10 +INC –INB 6 9 –INC OUTB 7 8 OUTC OUTA 1 +V 4 GENERAL DESCRIPTION 07671-101 Figure 2. 8-Lead LFCSP (CP-8-21) Industrial process control Battery-powered instrumentation Power supply control and protection Telecommunications Remote sensors Low voltage strain gage amplifiers DAC output amplifiers 13 NC 14 OUTD 16 NC 15 OUTA Figure 3. 14-Lead TSSOP (RU-14) The ADA4091-2 dual and ADA4091-4 quad are micropower, single-supply, 1.2 MHz bandwidth amplifiers featuring rail-torail inputs and outputs. They are guaranteed to operate from a +3.0 V to +30 V single supply as well as from ±1.5 V to ±15 V dual supplies. –INA 1 +INA 2 12 –IND ADA4091-4 11 +IND The ADA4091-2/ADA4091-4 features a unique input stage that allows the input voltage to exceed either supply safely without any phase reversal or latch-up; this is called overvoltage protection (OVP). +INB 4 Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezoelectric, and resistive transducers. NOTES 1. NC = NO CONNECT. 2. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–. The ability to swing rail-to-rail at both the input and output enables designers, for example, to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios (SNR). The ADA4091-2 is available in 8-lead, plastic SOIC and 8-lead LFCSP packages. The ADA4091-4 is available in 14–lead TSSOP and 16-lead LFCSP surface-mount packages. The ADA4091-2/ADA4091-4 is specified over the extended industrial temperature range of −40°C to +125°C. The ADA4091-2/ ADA4091-4 is part of the growing selection of 36 V, low power operational amplifiers from Analog Devices, Inc., (see Table 1). Table 1. Low Power, 36 V Operational Amplifiers Rev. H TOP VIEW 10 V– +INC –INC 8 OUTC 7 –INB 5 OUTB 6 9 07671-103 V+ 3 Figure 4. 16-Lead LFCSP (CP-16-17) Family Single Dual Quad Rail-to-Rail I/O PJFET ADA4091-2 ADA4091-4 AD8682 AD8684 Low Noise OP1177 OP2177 OP4177 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADA4091-2/ADA4091-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Theory of Operation ...................................................................... 14 Pin Configurations ........................................................................... 1 Input Stage ................................................................................... 14 Revision History ............................................................................... 2 Output Stage................................................................................ 14 Specifications..................................................................................... 3 Input Overvoltage Protection ................................................... 15 Electrical Specifications ............................................................... 3 Outline Dimensions ....................................................................... 16 Absolute Maximum Ratings ............................................................ 6 Ordering Guide .......................................................................... 18 Thermal Resistance ...................................................................... 6 REVISION HISTORY 5/2016—Rev. G. to Rev. H Changed CP-8-9 to CP-8-21 ........................................ Throughout Changes to Figure 2 .......................................................................... 1 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 18 10/2013—Rev. F. to Rev. G Changed Open-Loop Impedance to Closed-Loop Impedance (Throughout) .................................................................................... 3 Updated Outline Dimensions ....................................................... 17 10/2010—Rev. E. to Rev. F Changes to Features Section and General Description Section . 1 Changes to Outline Dimensions................................................... 17 5/2010—Rev. D. to Rev. E Changes to Data Sheet Title ............................................................ 1 Changes to Table 2, Input Characteristics, Offset Voltage .......... 3 Changes to Table 3, Input Characteristics, Offset Voltage .......... 4 Changes to Table 4, Input Characteristics, Offset Voltage .......... 5 4/2010—Rev. C to Rev. D Changes to Table 2, Added LFCSP to Input Characteristics ...... 3 Changes to Table 3, Added LFCSP to Input Characteristics ...... 4 Changes to Table 4, Added LFCSP to Input Characteristics ...... 5 10/2009—Rev. B to Rev. C Added 8-Lead LFCSP and 16-Lead LFCSP ..................... Universal Change to Features Section ............................................................. 1 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 18 7/2009—Rev. A to Rev. B Added New Part ADA4091-4 ........................................... Universal Changes to Features Section, General Description Section, and Figure 4 ...............................................................................................1 Added Figure 2, Renumbered Sequentially ...................................1 Changes to Table 1.............................................................................1 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................4 Changes to Table 4.............................................................................5 Changes to Table 5.............................................................................6 Changes to Table 6.............................................................................6 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 7/2009—Rev. 0 to Rev. A Changes to Data Sheet Title .............................................................1 Changes to Features ..........................................................................1 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................4 Changes to Table 4.............................................................................5 Added Input Current Parameter, Table 5 .......................................6 Added New Figure 12 and Figure 13, Renumbered Sequentially ........................................................................................8 Added New Figure 24 and Figure 25 ........................................... 10 Added New Figure 36 and Figure 37 ........................................... 12 Added New Figure 43 .................................................................... 13 Changes to Input Overvoltage Protection Section..................... 15 Changes to Ordering Guide .......................................................... 16 10/2008—Revision 0: Initial Version Rev. H | Page 2 of 20 Data Sheet ADA4091-2/ADA4091-4 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VSY = ±1.5 V, VCM = 0.0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Symbol Test Conditions/Comments Min Typ Max Unit ADA4091-4 LFCSP package −40°C ≤ TA ≤ +125°C −250 −400 −600 −40 −40 +250 +400 +600 µV µV µV µV/°C nA nA nA nA nA nA V dB dB dB dB dB dB VOS ∆VOS/∆T IB −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Offset Current IOS −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Closed-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density VOH VOL ISC ZOUT PSRR ISY VCM = −1.35 V to +1.35 V −40°C ≤ TA ≤ +125°C RL = 100 kΩ, VO = −1.2 V to +1.2 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = −1.2 V to +1.2 V −40°C ≤ TA ≤ +125°C −55 −55 −275 −3 −5 −75 −1.5 84 78 106 101 92 85 RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C to +125°C RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C Source/sink f = 1 MHz, AV = 1 1.490 1.490 1.475 1.455 VSY = 2.7 V to 36 V −40°C ≤ TA ≤ +125°C IO = 0 mA −40°C ≤ TA ≤ +125°C 108 100 2.5 −44 0.5 +55 +275 +3 +5 +75 +1.5 100 113 94 1.495 1.485 −1.499 −1.495 −1.495 −1.495 −1.490 −1.490 ±31 102 126 165 200 300 V V V V V V V V mA Ω dB dB µA µA SR tS GBP ΦM RL = 100 kΩ, CL = 30 pF To 0.01% 0.46 22 1.22 69 V/µs µs MHz Degrees en p-p en 0.1 Hz to 10 Hz f = 1 kHz 0.8 24 µV p-p nV/√Hz Rev. H | Page 3 of 20 ADA4091-2/ADA4091-4 Data Sheet VSY = ±5.0 V, VCM = 0.0 V, TA = 25°C, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Symbol Test Conditions/Comments Min Typ Max Unit ADA4091-4 LFCSP package −40°C ≤ TA ≤ +125°C −250 −400 −600 −45 −40 +250 +400 +600 µV µV µV µV/°C nA nA nA nA nA nA V dB dB dB dB dB dB VOS ∆VOS/∆T IB −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Offset Current IOS −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Closed-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density VOH VOL ISC ZOUT PSRR ISY VCM = −4.85 V to +4.85 V −40°C ≤ TA ≤ +125°C RL = 100 kΩ, VO = ±4.7 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = ±4.7 V −40°C ≤ TA ≤ +125°C −60 −80 −350 −3 −7 −100 −5 95 88 113 106 98 90 RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C Source/sink f = 1 MHz, AV = 1 4.980 4.980 4.950 4.900 VSY = 2.7 V to 36 V −40°C ≤ TA ≤ +125°C IO = 0 mA −40°C ≤ TA ≤ +125°C 108 100 2.5 −50 0.5 +80 +350 +3 +7 +100 +5 113 117 100 4.990 4.960 −4.998 −4.990 −4.990 −4.980 −4.980 −4.975 ±20 77 126 180 225 300 V V V V V V V V mA Ω dB dB µA µA SR tS GBP ΦM RL = 100 kΩ, CL = 30 pF To 0.01% 0.46 22 1.22 70 V/µs µs MHz Degrees en p-p en 0.1 Hz to 10 Hz f = 1 kHz 0.8 24 µV p-p nV/√Hz Rev. H | Page 4 of 20 Data Sheet ADA4091-2/ADA4091-4 VSY = ±15.0 V, VCM = 0.0 V, VO = 0.0 V, TA = 25°C, unless otherwise noted. Table 4. Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Symbol Test Conditions/Comments Min Typ Max Unit ADA4091-4 LFCSP package −40°C ≤ TA ≤ +125°C −250 −400 −600 −35 −40 +250 +400 +600 µV µV µV µV/°C nA nA nA nA nA nA V dB dB dB dB dB dB VOS ∆VOS/∆T IB −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Offset Current IOS −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Closed-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density VOH VOL ISC ZOUT PSRR ISY VCM = −14.85 V to +14.85 V −40°C ≤ TA ≤ +125°C RL = 100 kΩ, VO = ±14.7 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = ±14.7 V −40°C ≤ TA ≤ +125°C −60 −80 −510 −3 −10 −140 −15 104 95 116 108 102 93 RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C Source/sink f = 1 MHz, AV = 1 14.975 14.950 14.900 14.800 VSY = 2.7 V to 36 V −40°C ≤ TA ≤ +125°C IO = 0 mA −40°C ≤ TA ≤ +125°C 108 100 SR tS GBP ΦM CS RL = 100 kΩ, CL = 30 pF To 0.01% en p-p en 3.0 −50 0.5 +80 +510 +3 +10 +140 +15 121 119 104 14.980 14.920 −14.996 −14.975 −14.990 −14.985 −14.950 −14.940 ±20 71 126 200 250 350 V V V V V V V V mA Ω dB dB µA µA f = 1 kHz 0.46 22 1.27 72 100 V/µs µs MHz Degrees dB 0.1 Hz to 10 Hz f = 1 kHz 0.8 25 µV p-p nV/√Hz Rev. H | Page 5 of 20 ADA4091-2/ADA4091-4 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Supply Voltage Input Voltage Differential Input Voltage Input Current Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) 1 1 Rating 36 V Refer to the Input Overvoltage Protection section ±VSY ±5 mA Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C θJA is specified for the device soldered on a 4-layer JEDEC standard PCB with zero airflow. The exposed pad is soldered to the application board. Table 6. Thermal Resistance Package Type 8-Lead SOIC (R-8) 14-Lead TSSOP (RU-14) 8-Lead LFCSP (CP-8-21) 16-Lead LFCSP (CP-16-17) ESD CAUTION Input current must be limited to ±5 mA. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. H | Page 6 of 20 θJA 155 112 75 55 θJC 45 35 12 14 Unit °C/W °C/W °C/W °C/W Data Sheet ADA4091-2/ADA4091-4 TYPICAL PERFORMANCE CHARACTERISTICS 200 10,000 ADA4091-2 TA = 25°C VSY = ±1.5V 180 1000 140 VOUT TO RAIL (mV) 120 100 80 60 100 VDD – VOH 10 VOL – VSS 40 1 20 50 100 150 200 250 1 10 100 ADA4091-2 –40°C ≤ TA ≤ +125°C VSY = ±1.5V 200 150 100 80 80 60 60 GAIN 50 40 40 20 20 –1 0 1 2 3 4 5 6 7 8 TCVOS (µV/°C) 07671-035 0 0 100 PHASE OPEN-LOOP GAIN (dB) 250 100 Figure 8. Dropout Voltage vs. Load Current 300 NUMBER OF AMPLIFIERS 0.1 LOAD CURRENT (mA) Figure 5. Input Offset Voltage Distribution ADA4091-2 VSY = ±1.5V RL = 1MΩ CL = 35pF –20 1k 0 10k 100k –20 10M 1M FREQUENCY (Hz) Figure 6. TCVOS Distribution Figure 9. Open-Loop Gain and Phase vs. Frequency 350 300 0.01 PHASE (Degrees) 0 VOS (µV) 07671-034 –250 –200 –150 –100 –50 0.1 0.001 07671-017 ADA4091-2 VSY = ±1.5V 0 07671-007 NUMBER OF AMPLIFIERS 160 50 ADA4091-2 VSY = ±1.5V AV = 100 40 250 100 50 +85°C 0 –50 –100 –40°C –150 –1.5 –1.0 –0.5 0 0.5 1.0 VCM (V) 1.5 AV = 10 20 10 AV = 1 0 ADA4091-2 –10 V = ±1.5V SY RL = 1MΩ CL = 35pF –20 10 100 +25°C 07671-033 IB (nA) 150 30 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. Input Bias Current vs. Common-Mode Voltage Figure 10. Closed-Loop Gain vs. Frequency Rev. H | Page 7 of 20 10M 07671-010 CLOSED-LOOP GAIN (dB) +125°C 200 ADA4091-2/ADA4091-4 Data Sheet 3.0 1k 2.5 VOUT SWING (V) 100 10 AV = 10 2.0 1.5 1.0 AV = 1 100 10 1k 10k 100k 1M 10M FREQUENCY (Hz) 0 100 07671-013 0.1 ADA4091-2 VSY = ±1.5V VIN = 2.8V p-p RL = 100kΩ 0.5 ADA4091-2 TA = 25°C VSY = ±1.5V 1k 2.0 1.6 1.5 1.4 OUTPUT VOLTAGE (V) VOUT (V) 0.5 0 ADA4091-2 VSY = ±1.5V TA = 25°C RL = 100kΩ CL = 100pF AV = +1 –0.5 –1.0 1.0 0.8 0.6 0.4 0.2 –1.5 ADA4091-2 TA = 25°C VSY = ±1.5V 0 0 5 10 15 20 25 30 35 40 45 50 TIME (µs) –0.2 07671-025 –2.0 0 10 Figure 12. Large Signal Transient Response 20 30 40 50 TIME (µs) 60 70 80 90 Figure 15. Positive Overload Recovery 0.06 0 0.04 –0.2 –0.4 OUTPUT VOLTAGE (V) 0.02 0 ADA4091-2 VSY = ±1.5V TA = 25°C RL = 100kΩ CL = 100pF AV = +1 –0.6 –0.8 –1.0 –1.2 ADA4091-2 TA = 25°C VSY = ±1.5V –1.4 –0.08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (µs) –1.6 0 10 20 30 40 50 TIME (µs) 60 70 Figure 16. Negative Overload Recovery Figure 13. Small Signal Transient Response Rev. H | Page 8 of 20 80 90 07671-045 –0.06 07671-028 VOUT (V) 1M 1.2 1.0 –0.04 100k Figure 14. Output Swing vs. Frequency Figure 11. Output Impedance vs. Frequency –0.02 10k FREQUENCY (Hz) 07671-036 1 07671-051 ZOUT (Ω) AV = 100 Data Sheet ADA4091-2/ADA4091-4 0.06 225 ADA4091-2 TA = 25°C VSY = ±5V 0.04 175 0.02 150 VOUT (V) 125 100 ADA4091-2 VSY = ±5V TA = 25°C RL = 100kΩ CL = 100pF AV = +1 0 –0.02 75 –0.04 50 –250 –200 –150 –100 –50 0 50 100 150 200 250 VOS (µV) –0.08 07671-037 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (µs) Figure 20. Small Signal Transient Response Figure 17. Input Offset Voltage Distribution 500 400 ADA4091-2 –40°C ≤ TA ≤ +125°C VSY = ±5V ADA4091-2 VSY = ±5V 400 300 300 250 IB (nA) NUMBER OF AMPLIFIERS 350 07671-029 –0.06 25 200 200 +125°C 100 150 +85°C +25°C 0 100 –100 50 –40°C –1 0 1 2 3 4 5 6 7 8 TCVOS (µV/°C) –200 –5 07671-038 0 –4 –3 –2 –1 0 1 2 3 4 5 VCM (V) Figure 18. TCVOS Distribution 07671-032 NUMBER OF AMPLIFIERS 200 Figure 21. Input Bias Current vs. Common-Mode Voltage 100 6 100 0 ADA4091-2 VSY = ±5V TA = 25°C RL = 100kΩ CL = 100pF AV = +1 –2 –6 0 5 10 15 20 25 30 35 40 TIME (µs) 45 50 80 60 60 GAIN 40 40 20 20 0 ADA4091-2 VSY = ±5V RL = 1MΩ CL = 35pF –20 1k 10k –4 07671-026 VOUT (V) 2 80 0 100k 1M FREQUENCY (Hz) Figure 19. Large Signal Transient Response Figure 22. Open-Loop Gain and Phase vs. Frequency Rev. H | Page 9 of 20 –20 10M 07671-005 OPEN-LOOP GAIN (dB) 4 PHASE (Degrees) PHASE ADA4091-2/ADA4091-4 Data Sheet 50 AV = 100 40 CLOSED-LOOP GAIN (dB) ZOUT (Ω) 100 AV = 100 10 AV = 10 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 07671-012 0.1 AV = 10 20 10 AV = 1 0 ADA4091-2 –10 VSY = ±5V RL = 1MΩ CL = 35pF –20 10 100 ADA4091-2 TA = 25°C VSY = ±5V AV = 1 30 1k 10k 100k 1M 10M FREQUENCY (Hz) 07671-009 1k Figure 26. Closed-Loop Gain vs. Frequency Figure 23. Output Impedance vs. Frequency 6 10 9 5 VOUT SWING (V) 7 6 5 4 3 1 ADA4091-2 VSY = ±5V VIN = 9.8V p-p RL = 100kΩ 0 100 1k 10k 100k 1M FREQUENCY (Hz) 3 2 1 ADA4091-2 TA = 25°C VSY = ±5V 0 0 10 20 07671-015 2 4 30 40 50 TIME (µs) 60 70 80 90 07671-046 OUTPUT VOLTAGE (V) 8 Figure 27. Positive Overload Recovery Figure 24. Output Voltage Swing vs. Frequency 1 10,000 0 100 VOL – VSS 10 –1 –2 –3 –4 1 ADA4091-2 TA = 25°C VSY = ±5V –5 0.1 0.001 ADA4091-2 VSY = ±5V 0.01 0.1 1 10 LOAD CURRENT (mA) 100 –6 0 10 20 30 40 50 TIME (µs) 60 Figure 28. Negative Overload Recovery Figure 25. Dropout Voltage vs. Load Current Rev. H | Page 10 of 20 70 80 07671-047 OUTPUT VOLTAGE (V) VDD – VOH 07671-018 VOUT TO RAIL (mV) 1000 Data Sheet ADA4091-2/ADA4091-4 250 100 0 50 100 150 200 250 VOS (µV) 60 GAIN 20 0 ADA4091-2 VSY = ±15V RL = 1MΩ CL = 35pF –20 10k 1k 0 –20 10M 1M 100k FREQUENCY (Hz) Figure 32. Open-Loop Gain and Phase vs. Frequency Figure 29. Input Offset Voltage Distribution 20 350 ADA4091-2 –40°C ≤ TA ≤ +125°C VSY = ±15V 300 15 10 250 5 200 VOUT (V) 150 ADA4091-2 VSY = ±15V TA = 25°C RL = 100kΩ CL = 100pF AV = +1 0 –5 100 –10 50 –15 –1 0 1 2 3 4 6 5 7 8 TCVOS (µV/°C) –20 –25 07671-042 0 25 50 75 100 125 150 175 200 TIME (µs) Figure 33. Large Signal Transient Response Figure 30. TCVOS Distribution 0.06 700 600 0 07671-027 NUMBER OF AMPLIFIERS 40 20 07671-041 –250 –200 –150 –100 –50 60 40 50 0 80 07671-006 OPEN-LOOP GAIN (dB) 150 80 PHASE (Degrees) PHASE 200 NUMBER OF AMPLIFIERS 100 100 ADA4091-2 TA = 25°C VSY = ±15V ADA4091-2 VSY = ±15V 0.04 500 0.02 400 +125°C VOUT (V) 200 +85°C 100 0 –0.02 +25°C 0 ADA4091-2 VSY = ±15V TA = 25°C RL = 100kΩ CL = 100pF AV = +1 –0.04 –100 –0.06 –40°C –300 –15 –10 –5 0 5 10 VCM (V) 15 –0.08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (µs) Figure 34. Small Signal Transient Response Figure 31. Input Bias Current vs. Common-Mode Voltage Rev. H | Page 11 of 20 07671-030 –200 07671-031 IB (nA) 300 ADA4091-2/ADA4091-4 Data Sheet 50 30 40 VOUT SWING (V) 25 20 15 10 0 100 1k 10k 100k 1M FREQUENCY (Hz) 30 AV = 10 20 10 AV = 1 0 –10 ADA4091-2 –20 VSY = ±15V RL = 1MΩ CL = 35pF –30 10 100 07671-016 5 ADA4091-2 VSY = ±15V VIN = 29.8V p-p RL = 100kΩ AV = 100 1k 10k 10M 1M 100k FREQUENCY (Hz) Figure 35. Output Voltage Swing vs. Frequency 07671-008 CLOSED-LOOP GAIN (dB) 35 Figure 38. Closed-Loop Gain vs. Frequency 10,000 16 14 12 OUTPUT VOLTAGE (V) VDD – VOH 100 VOL – VSS 10 8 6 4 2 1 0.1 1 10 100 LOAD CURRENT (mA) 07671-019 0.01 ADA4091-2 TA = 25°C VSY = ±15V 0 ADA4091-2 VSY = ±15V 0.1 0.001 10 –2 0 10 20 Figure 36. Dropout Voltage vs. Load Current 30 40 50 TIME (µs) 60 70 80 90 07671-048 VOUT TO RAIL (mV) 1000 Figure 39. Positive Overload Recovery 1k 2 0 –2 1 OUTPUT VOLTAGE (V) 10 AV = 100 AV = 10 –4 –6 –8 –10 –12 0.1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M ADA4091-2 TA = 25°C VSY = ±15V –14 Figure 37. Output Impedance vs. Frequency –16 0 10 20 30 40 50 TIME (µs) 60 Figure 40. Negative Overload Recovery Rev. H | Page 12 of 20 70 80 07671-049 ADA4091-2 TA = 25°C VSY = ±15V AV = 1 07671-011 ZOUT (Ω) 100 Data Sheet ADA4091-2/ADA4091-4 100 0.5 ADA4091-2 VSY = ±1.5V, ±5V, ±15V 0.4 80 0.3 60 0.1 PSRR (dB) NOISE (µV p-p) 0.2 0 –0.1 PSRR+ PSRR– 40 20 –0.2 –0.3 ADA4091-2 VSY = ±15V 1 0 3 2 5 4 6 8 7 10 9 TIME (Seconds) –20 100 07671-043 –0.5 1k 10k 100k 1M 10M FREQUENCY (Hz) 07671-003 0 –0.4 Figure 44. PSRR vs. Frequency Figure 41.Peak-to-Peak Voltage Noise 500 –60 ADA4091-2 450 TA = 25°C ADA4091-2 VSY = ±15V 400 –80 350 300 –90 ISY (µA) CHANNEL SEPARATION (dB) –70 –100 250 200 150 –110 100 –120 50 1k 10k 100k FREQUENCY (Hz) 0 0 5 10 15 20 25 30 07671-004 100 10 07671-044 –130 35 VSY (V) Figure 45. Supply Current vs. Supply Voltage Figure 42. Channel Separation vs. Frequency 1k 110 ADA4091-2 VSY = ±5V, ±15V 100 VOLTAGE NOISE (nV/ Hz) 90 80 VSY = ±1.5V 60 50 40 30 20 1k 10k 100k FREQUENCY (Hz) 1M 10M 10 0.01 0.1 1 10 FREQUENCY (Hz) Figure 46. Voltage Noise Density Figure 43. CMRR vs. Frequency Rev. H | Page 13 of 20 100 1k 07671-050 0 100 100 ADA4091-2 TA = 25°C VSY = ±5V 10 07671-002 CMRR (dB) 70 ADA4091-2/ADA4091-4 Data Sheet THEORY OF OPERATION The ADA4091-2/ADA4091-4 is a single-supply, micropower amplifier featuring rail-to-rail inputs and outputs. To achieve wide input and output ranges, these amplifiers employ unique input and output stages. Eventually, the emitters of Q1 and Q2 are high enough to turn on Q3, which diverts the tail current away from the PNP input stage, turning it off. The tail current of the PNP pair is diverted to the Q4/Q7 current mirror to activate the NPN input stage. INPUT STAGE A common practice in bipolar amplifiers to protect the input transistors from large differential voltages is to include series resistors and differential diodes. See Figure 48 for the full input protection circuitry. These diodes turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current flows between the input pins, limited only by the two 5 kΩ resistors. Evaluate each application carefully to make sure that the increase in current does not affect performance. In Figure 47, the input stage comprises two differential pairs, a PNP pair (PNP input stage) and an NPN pair (NPN input stage). These input stages do not work in parallel. Instead, only one stage is on for any given input common-mode signal level. The PNP stage (Transistor Q1 and Transistor Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. Alternatively, the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to, and including, the positive rail. OUTPUT STAGE The output stage in the ADA4091-2/ADA4091-4 device uses a PNP and an NPN transistor, as do most output stages. However, Q32 and Q33, the output transistors, connect with their collectors to the output pin to achieve the rail-to-rail output swing. For the majority of the input common-mode range, the PNP stage is active, as shown in Figure 7, Figure 21, and Figure 31. Notice that the bias current switches direction at approximately 1.5 V below the positive rail. At voltages below this level, the bias current flows out of the ADA4091-2/ADA4091-4 input, from the PNP input stage. Above this voltage, however, the bias current enters the device, due to the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises Transistor Q3, Transistor Q4, and Transistor Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage has inherent gain arising from the transistor output impedance, as well as any external load impedance; consequently, the open-loop gain of the operational amplifier is dependent on the load resistance and decreases when the output voltage is close to either rail. –IN Q32 Q3 Q16 Q5 Q6 Q1 Q2 Q8 Q10 Q12 Q17 Q14 OUT Q9 Q11 Q13 Q15 Q18 Q4 Q19 Q33 07671-024 +IN Q7 Figure 47. Simplified Schematic Without Input Protection (see Figure 48) Rev. H | Page 14 of 20 Data Sheet ADA4091-2/ADA4091-4 INPUT OVERVOLTAGE PROTECTION The ADA4091-2/ADA4091-4 has two different ESD circuits for enhanced protection, as shown in Figure 48. For a worst-case design analysis, consider two cases. The ADA4091-2/ADA4091-4 has a normal ESD structure from the internal operational amplifier inputs to the supply rails. In addition, it has 42 V DIACs from the external inputs to the rails, as shown in Figure 47. Therefore, two conditions need to be considered to determine which case is the limiting factor. • Condition 1. Consider, for example, that when operating on ±15 V, the inputs can go +42 V above the negative supply rail. With the −V pin equal to −15 V, +42 V above this supply (the negative supply) is +27 V. • Condition 2. There is a restriction on the input current of 5 mA through a 5 kΩ resistor to the ESD structure to the positive rail. In Condition 1, +27 V through the 5 kΩ resistor to +15 V gives a current of 2.4 mA. Thus, the DIAC is the limiting factor. If the ADA4091-2/ADA4091-4 supply voltages are changed to ±5 V, then −5 V + 42 V = +37 V. However, +5 V + (5 kΩ × 5 mA) = 30 V. Thus, the normal resistor diode structure is the limitation when running on lower supply voltages. +V D3 R1 D7 R2 D8 D6 D1 D2 D5 D4 07671-023 –V Figure 48. Complete Input Protection Network One circuit is a series resistor of 5 kΩ to the internal inputs and diodes (D1 and D2 or D5 and D6) from the internal inputs to the supply rails. The other protection circuit is a circuit with two DIACs (D3 and D4 or D7 and D8) to the supply rails. A DIAC can be considered a bidirectional Zener diode with a transfer characteristic, as shown in Figure 49. 5 The flatband voltage noise of the ADA4091-2/ADA4091-4 is approximately 24 nV/√Hz, and a 5 kΩ resistor has a noise of 9 nV/√Hz. Adding an additional 5 kΩ resistor increases the total noise by less than 15% root sum square (rss). Therefore, maintain resistor values below this value (5 kΩ) when overall noise performance is critical. Note that this represents input protection under abnormal conditions only. The correct amplifier operation input voltage range (IVR) is specified in Table 2, Table 3, and Table 4. 4 3 2 1 0 –1 –2 –3 –50 –40 –30 –20 –10 0 10 20 VOLTAGE (V) 30 40 50 07671-100 CURRENT (mA) Additional resistance can be added externally in series with each input to protect against higher peak voltages; however, the additional thermal noise of the resistors must be considered. Figure 49. DIAC Transfer Characteristic Rev. H | Page 15 of 20 ADA4091-2/ADA4091-4 Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 2.54 2.44 2.34 3.10 3.00 SQ 2.90 0.50 BSC 8 PIN 1 INDEX AREA 1.70 1.60 1.50 EXPOSED PAD 0.50 0.40 0.30 4 TOP VIEW PKG-004371 0.80 0.75 0.70 SEATING PLANE 0.05 MAX 0.02 NOM 0.30 0.25 0.20 1 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.203 REF Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-21) Dimensions shown in millimeters Rev. H | Page 16 of 20 0.20 MIN PIN 1 INDICATOR (R 0.20) 12-03-2013-A 5 Data Sheet ADA4091-2/ADA4091-4 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP] Narrow Body (RU-14) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 SEATING PLANE 0.45 0.40 0.35 8 5 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-16-17) Dimensions are millimeters Rev. H | Page 17 of 20 08-16-2010-C TOP VIEW ADA4091-2/ADA4091-4 Data Sheet ORDERING GUIDE Model 1 ADA4091-2ARZ ADA4091-2ARZ-R7 ADA4091-2ARZ-RL ADA4091-2ACPZ-R2 ADA4091-2ACPZ-R7 ADA4091-2ACPZ-RL ADA4091-4ARUZ ADA4091-4ARUZ-RL ADA4091-4ACPZ-R2 ADA4091-4ACPZ-R7 ADA4091-4ACPZ-RL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Z = RoHS Compliant Part. Rev. H | Page 18 of 20 Package Option R-8 R-8 R-8 CP-8-21 CP-8-21 CP-8-21 RU-14 RU-14 CP-16-17 CP-16-17 CP-16-17 Branding A1Z A1Z A1Z Data Sheet ADA4091-2/ADA4091-4 NOTES Rev. H | Page 19 of 20 ADA4091-2/ADA4091-4 Data Sheet NOTES ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07671-0-5/16(H) Rev. H | Page 20 of 20