Low Power JFET-Input Op Amps ADA4062-2/ADA4062-4 PIN CONFIGURATIONS Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity-gain stable ±5 V to ±15 V dual-supply operation Packaging 8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and 16-lead LFCSP packages OUT A 1 –IN A 2 ADA4062-2 +IN A 3 TOP VIEW (Not to Scale) V– 4 OUT B 6 –IN B 5 +IN B 9 V+ 1 OUT A 10 NC 8 OUT B –IN A 2 ADA4062-2 07670-065 +IN B 6 NC 5 NC = NO CONNECT V– 4 7 –IN B TOP VIEW (Not to Scale) +IN A 3 GENERAL DESCRIPTION OUT A 1 14 OUT D –IN A 2 13 –IN D +IN A 3 ADA4062-4 12 +IN D V+ 4 TOP VIEW (Not to Scale) 11 V– +IN B 5 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C 07670-064 Figure 2. 10-Lead LFCSP Power controls and monitoring Active filters Industrial/process controls Body probe electronics Data acquisition Integrators Input buffering 13 NC 14 OUT D 16 NC 15 OUT A Figure 3. 14-Lead TSSOP –IN A 1 +IN A 2 V+ 3 12 –IN D ADA4062-4 TOP VIEW (Not to Scale) +IN B 4 11 +IN D 10 V– +IN C –IN C 8 OUT C 7 –IN B 5 OUT B 6 9 NOTES 1. NC = NO CONNECT. 2. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–. 07670-068 The ADA4062-2 and ADA4062-4 are dual and quad JFET-input amplifiers with industry-leading performance. They offer lower power, offset voltage, drift, and ultralow bias current. The ADA4062-2 B grade (SOIC package) features a typical low offset voltage of 0.5 mV, an offset drift of 5 μV/°C, and a bias current of 2 pA. The ADA4062 family is also specified for the extended industrial temperature range of −40°C to +125°C. The ADA4062-2 is available in lead-free, 8-lead SOIC, 8-lead MSOP, and 10-lead LFCSP (1.6 mm × 1.3 mm × 0.55 mm) packages, while the ADA4062-4 is available in lead-free, 14-lead TSSOP and 16-lead LFCSP packages. V+ 7 Figure 1. 8-Lead Narrow-Body SOIC and 8-Lead MSOP APPLICATIONS The ADA4062 family is ideal for various applications, including process controls, industrial and instrumentation equipment, active filtering, data conversion, buffering, and power control and monitoring. With a low supply current of 165 μA per amplifier, they are well suited for lower power applications. 8 07670-001 FEATURES Figure 4. 16-Lead LFCSP Table 1. Low Power Op Amps Single Dual Quad Precision CMOS AD8663 AD8667 AD8669 Precision High Bandwidth AD8641 AD8642 AD8643 High Bandwidth AD8682 AD8684 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. ADA4062-2/ADA4062-4 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Applications Information .............................................................. 15 Pin Configurations ........................................................................... 1 Notch Filter ................................................................................. 15 Revision History ............................................................................... 2 High-Side Signal Conditioning ................................................ 15 Specifications..................................................................................... 3 Micropower Instrumentation Amplifier ................................. 15 Electrical Characteristics ............................................................. 3 Phase Reversal ............................................................................ 16 Absolute Maximum Ratings............................................................ 5 Schematic ......................................................................................... 17 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 18 Power Sequencing ........................................................................ 5 Ordering Guide .......................................................................... 20 REVISION HISTORY 2/10—Rev. A to Rev. B Added 16-Lead LFCSP Package........................................ Universal Changes to Features Section, General Description Section, and Table 1 ................................................................................................ 1 Changes to Offset Voltage Drift Parameter, Table 2 .................... 3 Changes to Table 4 ............................................................................ 5 Changes to Typical Performance Characteristics Layout ............ 6 Added Figure 6 and Figure 9; Renumbered Sequentially ........... 6 Changes to Figure 7, Figure 8, and Figure 10 ............................... 6 Changes to Figure 25 and Figure 28 ............................................... 9 Changes to Figure 37 and Figure 40 ............................................. 11 Changes to Figure 41 to Figure 46 ................................................ 12 Changes to Figure 47 and Figure 50 ............................................. 13 Changes to Figure 53 to Figure 58 ................................................ 14 Changes to Notch Filter Section and Micropower Instrumentation Amplifier Section ............................................................................ 15 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 20 7/09—Rev. 0 to Rev. A Added ADA4062-4 ............................................................. Universal Added 14-Lead TSSOP Package ....................................... Universal Added 10-Lead LFCSP Package ....................................... Universal Changes to Features Section and Table 1 .......................................1 Changes to Table 2.............................................................................3 Changes to Thermal Resistance Section ........................................5 Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ..................6 Changes to Figure 37 and Figure 40............................................. 11 Changes to Figure 41 and Figure 44............................................. 12 Changes to Figure 47, Figure 48, Figure 50, and Figure 51....... 13 Added Figure 49 and Figure 52; Renumbered Sequentially ..... 13 Changes to Figure 57 and Figure 59............................................. 15 Changes to Phase Reversal Section and Figure 61 ..................... 16 Changes to Figure 63...................................................................... 17 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 10/08—Revision 0: Initial Version Rev. B | Page 2 of 20 ADA4062-2/ADA4062-4 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage B Grade (ADA4062-2, 8-Lead SOIC Only) Symbol Conditions Min Typ Max Unit 0.5 1.5 3 2.5 5 mV mV mV mV μV/°C pA nA pA nA V VOS −40°C ≤ TA ≤ +125°C A Grade Offset Voltage Drift Input Bias Current 0.75 ∆VOS/∆T IB −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 5 2 −40°C ≤ TA ≤ +125°C Input Offset Current Input Voltage Range Common-Mode Rejection Ratio B Grade (ADA4062-2, 8-Lead SOIC Only) IOS Input Resistance Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio B Grade (ADA4062-2, 8-Lead SOIC Only) AVO DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation (ADA4062-2 Only) Channel Separation (ADA4062-4 Only) VCM = −11.5 V to +11.5 V −40°C ≤ TA ≤ +125°C VCM = −11.5 V to +11.5 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = −10 V to +10 V −40°C ≤ TA ≤ +125°C 80 80 73 70 76 72 RIN CINDM CINCM VOH VOL ISC ZOUT 90 dB dB dB dB dB dB TΩ pF pF 90 83 10 1.5 4.8 RL = 10 kΩ to VCM −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VCM −40°C ≤ TA ≤ +125°C 13 12.5 13.5 −13.8 −13 −12.5 20 1 f = 1 kHz, AV = 1 V V V V mA Ω PSRR A Grade Supply Current per Amplifier −11.5 CMRR A Grade Large-Signal Voltage Gain 0.5 −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 50 5 25 2.5 +15 ISY SR tS GBP ΦM CS CS VSY = ±4 V to ±18 V −40°C ≤ TA ≤ +125°C VSY = ±4 V to ±18 V −40°C ≤ TA ≤ +125°C IO = 0 mA −40°C ≤ TA ≤ +125°C RL = 10 kΩ, CL = 100 pF, AV = 1 To 0.1%, VIN = 10 V step, CL = 100 pF, RL = 10 kΩ, AV = 1 RL = 10 kΩ, AV = 1 RL = 10 kΩ, AV = 1 f = 1 kHz f = 1 kHz Rev. B | Page 3 of 20 80 80 74 70 90 90 165 220 260 dB dB dB dB μA μA 3.3 3.5 V/μs μs 1.4 78 135 130 MHz Degrees dB dB ADA4062-2/ADA4062-4 Parameter NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Symbol Conditions en p-p en in f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz Rev. B | Page 4 of 20 Min Typ 1.5 36 5 Max Unit μV p-p nV/√Hz fA/√Hz ADA4062-2/ADA4062-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage Input Current Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. It was measured using a standard 4-layer board. Rating ±18 V ±VSY ±VSY ±10 mA Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C Table 4. Thermal Resistance Package Type 8-Lead SOIC 8-Lead MSOP 10-Lead LFCSP 14-Lead TSSOP 16-Lead LFCSP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA 120 142 132 112 75 θJC 45 45 46 35 12 Unit °C/W °C/W °C/W °C/W °C/W POWER SEQUENCING The supply voltages of the op amps must be established simultaneously with, or before, any input signals are applied. If this is not possible, the input current must be limited to 10 mA. ESD CAUTION Rev. B | Page 5 of 20 ADA4062-2/ADA4062-4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 70 50 40 30 20 200 160 120 80 40 –2 –1 0 1 2 3 4 VOS (mV) 0 –4 NUMBER OF AMPLIFERS 10 2 4 6 8 10 TCVOS (µV/°C) 4 20 10 –2 0 2 4 6 8 10 Figure 9. Input Offset Voltage Drift Distribution 25 ADA4062-4 ONLY VSY = ±5V –40°C ≤ T ≤ 125°C BASED ON 200 OP AMPS ADA4062-4 ONLY VSY = ±15V –40°C ≤ T ≤ 125°C BASED ON 200 OP AMPS NUMBER OF AMPLIFIERS 20 15 10 15 10 0 2 4 6 8 10 12 14 16 TCVOS (µV/°C) 18 0 0 2 4 6 8 10 12 14 16 TCVOS (µV/°C) Figure 10. Input Offset Voltage Drift Distribution Figure 7. Input Offset Voltage Drift Distribution Rev. B | Page 6 of 20 18 07670-069 5 5 07670-070 NUMBER OF AMPLIFIERS 3 TCVOS (µV/°C) 25 20 2 ADA4062-2 ONLY VSY = ±15V –40°C ≤ TA ≤ +125°C BASED ON 200 OP AMPS Figure 6. Input Offset Voltage Drift Distribution 0 1 30 0 07670-055 NUMBER OF AMPLIFERS 20 0 0 40 ADA4062-2 ONLY VSY = ±5V –40°C ≤ TA ≤ +125°C BASED ON 200 OP AMPS –2 –1 Figure 8. Input Offset Voltage Distribution 30 0 –2 VOS (mV) Figure 5. Input Offset Voltage Distribution 40 –3 07670-005 –3 07670-054 –4 07670-003 10 0 VSY = ±15V VCM = 0V BASED ON 600 OP AMPS 240 NUMBER OF AMPLIFERS 60 NUMBER OF AMPLIFERS 280 VSY = ±5V VCM = 0V BASED ON 600 OP AMPS ADA4062-2/ADA4062-4 4 3 2 2 1 1 VOS (mV) 3 0 –1 –1 –2 –3 –3 –4 –4 –5 –4 –3 –2 –1 0 1 2 3 4 5 VCM (V) –5 –15 –12 –9 –6 –3 0 3 6 9 12 15 VCM (V) Figure 11. Input Offset Voltage vs. Common-Mode Voltage 10000 VSY = ±15V 0 –2 07670-056 Figure 14. Input Offset Voltage vs. Common-Mode Voltage 10000 VSY = ±5V 1000 100 100 10 10 1 1 –25 0 25 50 75 100 125 TEMPERATURE (°C) 0.1 –50 07670-012 0.1 –50 0 25 50 75 100 125 TEMPERATURE (°C) Figure 12. Input Bias Current vs. Temperature 3 –25 07670-009 IB (pA) IB (pA) 1000 VSY = ±15V Figure 15. Input Bias Current vs. Temperature 5 VSY = ±5V 4 1 3 IB (pA) IB (pA) 2 VSY = ±15V 0 2 –1 1 –2 –1 0 1 2 3 4 VCM (V) 5 0 –12 –10 07670-013 –2 –3 –8 –6 –4 –2 0 2 4 6 8 10 12 14 VCM (V) Figure 16. Input Bias Current vs. Common-Mode Voltage Figure 13. Input Bias Current vs. Common-Mode Voltage Rev. B | Page 7 of 20 16 07670-010 VOS (mV) 4 5 VSY = ±5V 07670-006 5 ADA4062-2/ADA4062-4 10 V+ – VOH 1 VOL – V– 0.1 0.01 0.1 1 10 100 LOAD CURRENT (mA) 1 0.1 1 10 100 Figure 20. Output Voltage to Supply Rail vs. Load Current 200 +125°C 190 SUPPLY CURRENT/AMP (µA) 160 140 +25°C 120 –40°C 100 80 60 180 170 150 130 120 20 110 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±V) 100 –50 07670-146 2 OUTPUT VOTLAGE TO SUPPLY RAIL (V) 1.5 V+ – VOH VOL – V– 25 50 75 100 TEMPERATURE (°C) 125 50 75 100 125 150 VSY = ±15V RL = 10kΩ V+ – VOH 1.5 VOL – V– 1.0 0.5 0 –50 07670-018 0.5 0 25 2.0 VSY = ±5V RL = 10kΩ –25 0 Figure 21. Supply Current/Amp vs. Temperature 2.0 0 –50 –25 TEMPERATURE (°C) Figure 18. Supply Current/Amp vs. Supply Voltage 1.0 VSY = ±5V 140 40 0 VSY = ±15V 160 07670-149 +85°C 180 –25 0 25 50 75 100 TEMPERATURE (°C) Figure 19. Output Voltage to Supply Rail vs. Temperature Figure 22. Output Voltage to Supply Rail vs. Temperature Rev. B | Page 8 of 20 125 07670-015 200 OUTPUT VOTLAGE TO SUPPLY RAIL (V) VOL – V– LOAD CURRENT (mA) 220 SUPPLY CURRENT/AMP (µA) V+ – VOH 0.1 0.01 Figure 17. Output Voltage to Supply Rail vs. Load Current 0 VSY = ±15V 07670-011 OUTPUT VOLTAGE TO SUPPLY RAIL (V) VSY = ±5V 07670-014 OUTPUT VOLTAGE TO SUPPLY RAIL (V) 10 ADA4062-2/ADA4062-4 120 100 100 80 80 80 80 60 60 60 60 20 20 0 0 40 40 GAIN 20 20 0 0 –20 –20 –20 –20 –40 –40 –40 –40 10k 100k 1M –60 100M 10M –60 1k 07670-019 –60 1k FREQUENCY (Hz) 10k 50 40 30 30 AV = +10 20 GAIN (dB) 10 AV = +1 20 10 0 –10 AV = +1 –10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –20 10 07670-020 –20 10 100 1000 VSY = ±5V 100 ZOUT (Ω) AV = +10 10 1 AV = +1 1k 10k 100k 1M FREQUENCY (Hz) 10M 1M 10M 100M VSY = ±15V AV = +100 AV = +10 AV = +1 0.1 100 07670-021 ZOUT (Ω) AV = +100 0.1 100 100k Figure 27. Closed-Loop Gain vs. Frequency 100 1 10k FREQUENCY (Hz) Figure 24. Closed-Loop Gain vs. Frequency 10 1k 07670-017 GAIN (dB) AV = +10 1000 VSY = ±15V AV = +100 40 0 –60 100M 10M Figure 26. Open-Loop Gain and Phase vs. Frequency VSY = ±5V AV = +100 1M FREQUENCY (Hz) Figure 23. Open-Loop Gain and Phase vs. Frequency 50 100k PHASE (Degrees) 40 GAIN 100 PHASE 1k 10k 100k 1M FREQUENCY (Hz) Figure 25. Output Impedance vs. Frequency Figure 28. Output Impedance vs. Frequency Rev. B | Page 9 of 20 10M 07670-018 GAIN (dB) 40 120 VSY = ±15V 07670-016 PHASE 100 GAIN (dB) VSY = ±5V PHASE (Degrees) 120 120 ADA4062-2/ADA4062-4 100 90 80 80 70 70 60 60 CMRR (dB) 90 50 40 50 40 30 30 20 20 10 10 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) VSY = ±15V 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 29. CMRR vs. Frequency 07670-022 VSY = ±5V 07670-025 CMRR (dB) 100 Figure 32. CMRR vs. Frequency 120 140 VSY = ±5V VSY = ±15V 120 100 100 80 PSRR (dB) PSRR+ 40 PSRR+ 40 PSRR– 20 PSRR– 20 0 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –20 10 100 60 1M 10M VSY = ±15V AV = +1 RL = 10kΩ 50 OVERSHOOT (%) 40 30 20 10 40 30 20 10 0 10 100 1000 10000 CL (pF) 07670-030 OVERSHOOT (%) 100k Figure 33. PSRR vs. Frequency VSY = ±5V AV = +1 RL = 10kΩ 50 10k FREQUENCY (Hz) Figure 30. PSRR vs. Frequency 60 1k 07670-023 0 07670-026 –20 60 Figure 31. Small-Signal Overshoot vs. Load Capacitance 0 10 100 1000 10000 CL (pF) Figure 34. Small-Signal Overshoot vs. Load Capacitance Rev. B | Page 10 of 20 07670-027 PSRR (dB) 80 60 ADA4062-2/ADA4062-4 TIME (10µs/DIV) Figure 38. Large-Signal Transient Response VOLTAGE (20mV/DIV) TIME (10µs/DIV) TIME (10µs/DIV) Figure 36. Small-Signal Transient Response Figure 39. Small-Signal Transient Response 4 4 VSY = ±5V AV = –10 VSY = ±15V AV = –10 2 INPUT 0 INPUT OUTPUT –5 –10 –4 –6 –15 07670-036 TIME (2µs/DIV) 0 TIME (2µs/DIV) Figure 40. Negative Overload Recovery Figure 37. Negative Overload Recovery Rev. B | Page 11 of 20 –20 07670-033 –2 INPUT VOLTAGE (V) 0 OUTPUT VOLTAGE (V) 0 OUTPUT 07670-029 VSY = ±15V VIN = 100mV p-p AV = +1 RL = 10kΩ CL = 100pF 07670-032 VSY = ±5V VIN = 100mV p-p AV = +1 RL = 10kΩ CL = 100pF OUTPUT VOLTAGE (V) VOLTAGE (20mV/DIV) Figure 35. Large-Signal Transient Response 2 07670-028 VOLTAGE (5V/DIV) TIME (4µs/DIV) INPUT VOLTAGE (V) VSY = ±15V VIN = 20V p-p AV = +1 RL = 10kΩ CL = 100pF 07670-031 VOLTAGE (1V/DIV) VSY = ±5V VIN = 4V p-p AV = +1 RL = 10kΩ CL = 100pF ADA4062-2/ADA4062-4 OUTPUT –2 15 10 5 OUTPUT 0 –2 TIME (2µs/DIV) 0 –5 TIME (2µs/DIV) Figure 41. Positive Overload Recovery OUTPUT VOLTAGE (V) 2 INPUT VOLTAGE (V) 4 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) –2 VSY = ±15V AV = –10 INPUT 0 07670-037 INPUT 0 2 VSY = ±5V AV = –10 07670-034 2 Figure 44. Positive Overload Recovery INPUT VOLTAGE (5V/DIV) +20mV OUTPUT 0V +100mV OUTPUT 0V –20mV –100mV ERROR BAND ERROR BAND TIME (2µs/DIV) TIME (2µs/DIV) Figure 42. Positive Settling Time to 0.1% VOLTAGE (5V/DIV) +20mV OUTPUT VSY = ±15V CL = 100pF RL = 10kΩ INPUT 0V +100mV OUTPUT 0V –20mV –100mV ERROR BAND TIME (2µs/DIV) ERROR BAND 07670-076 VOLTAGE (1V/DIV) Figure 45. Positive Settling Time to 0.1% VSY = ±5V CL = 100pF RL = 10kΩ INPUT 07670-077 VSY = ±15V CL = 100pF RL = 10kΩ 07670-075 VSY = ±5V CL = 100pF RL = 10kΩ Figure 43. Negative Settling Time to 0.1% TIME (2µs/DIV) Figure 46. Negative Settling Time to 0.1% Rev. B | Page 12 of 20 07670-078 VOLTAGE (1V/DIV) INPUT ADA4062-2/ADA4062-4 1000 100 10 1 10 100 1k FREQUENCY (Hz) VSY = ±15V 100 10 1 10 Figure 47. Voltage Noise Density 1k Figure 50. Voltage Noise Density VSY = ±5V TIME (1s/DIV) Figure 48. 0.1 Hz to 10 Hz Noise 0 100kΩ 1kΩ –40 –20 RL –60 –80 –100 –120 –140 100kΩ 1kΩ –40 RL –60 –80 –100 –120 –140 100 1k 10k 100k FREQUENCY (Hz) 07670-049 –160 VSY = ±15V VIN = 10V p-p RL = 10kΩ ADA4062-2 ONLY –160 100 1k 10k 100k FREQUENCY (Hz) Figure 52. Channel Separation vs. Frequency (ADA4062-2 Only) Figure 49. Channel Separation vs. Frequency (ADA4062-2 Only) Rev. B | Page 13 of 20 07670-046 –20 VSY = ±5V VIN = 5V p-p RL = 10kΩ ADA4062-2 ONLY Figure 51. 0.1 Hz to 10 Hz Noise CHANNEL SEPARATION (dB) 0 07670-041 07670-044 INPUT NOISE VOLTAGE (0.5µV/DIV) INPUT NOISE VOLTAGE (0.5µV/DIV) VSY = ±15V TIME (1s/DIV) CHANNEL SEPARATION (dB) 100 FREQUENCY (Hz) 07670-040 VOLTAGE NOISE DENSITY (nV/√Hz) VSY = ±5V 07670-043 VOLTAGE NOISE DENSITY (nV/√Hz) 1000 ADA4062-2/ADA4062-4 –20 100kΩ –20 1kΩ –40 RL –60 –80 –100 –120 1k 10k 100k 1kΩ –40 RL –60 –80 –100 –120 –160 100 07670-067 100 FREQUENCY (Hz) 100 10 1k 10k 100k FREQUENCY (Hz) Figure 56. Channel Separation vs. Frequency (ADA4062-4 Only) Figure 53. Channel Separation vs. Frequency (ADA4062-4 Only) 10 VS = ±5V f = 1kHz RL = 10kΩ 1 1 THD + N (%) THD + N (%) 100kΩ –140 –140 –160 VSY = ±15V VIN = 10V p-p RL = 10kΩ ADA4062-4 ONLY 07670-066 CHANNEL SEPARATION (dB) 0 VSY = ±5V VIN = 5V p-p RL = 10kΩ ADA4062-4 ONLY CHANNEL SEPARATION (dB) 0 0.1 0.1 0.01 0.01 0.1 1 10 AMPLITUDE (V rms) 0.001 0.001 0.1 1 10 AMPLITUDE (V rms) Figure 57 THD + N vs. Amplitude Figure 54. THD + N vs. Amplitude 1 0.01 07670-072 0.01 07670-071 0.001 0.001 VS = ±15V f = 1kHz RL = 10kΩ 1 VSY = ±5V VIN = 0.5V rms RL = 10kΩ VS = ±15V VIN = 2V rms RL = 10kΩ 0.1 THD + N (%) THD + N (%) 0.1 10 100 1k 10k FREQUENCY (Hz) 100k 07670-073 0.001 0.001 100 1k 10k 100k FREQUENCY (Hz) Figure 58. THD + N vs. Frequency Figure 55. THD + N vs. Frequency Rev. B | Page 14 of 20 1M 07670-074 0.01 0.01 ADA4062-2/ADA4062-4 APPLICATIONS INFORMATION NOTCH FILTER HIGH-SIDE SIGNAL CONDITIONING A notch filter rejects a specific interfering frequency and can be implemented using a single op amp. Figure 59 shows a 60 Hz notch filter that uses the twin-T network with the ADA4062-x configured as a voltage follower. The ADA4062-x works as a buffer that provides high input resistance and low output impedance. The low bias current (2 pA typical) and high input resistance (10 TΩ typical) of the ADA4062-x enable large resistors and small capacitors to be used. Many applications require the sensing of signals near the positive rail. The ADA4062-x can be used in high-side current sensing applications. Figure 61 shows a high-side signal conditioning circuit using the ADA4062-x. The ADA4062-x has an input common-mode range that includes the positive supply (−11.5 V ≤ VCM ≤ +15 V). In the circuit, the voltage drop across a low value resistor, such as the 0.1 Ω shown in Figure 61, is amplified by a factor of 5 using the ADA4062-x. Therefore, to achieve the desired performance, 1% or better component tolerances are usually required. In addition, a notch filter requires an op amp with a bandwidth of at least 100× to 200× the center frequency. Hence, using the ADA4062-x with a bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter. Figure 60 shows the frequency response of the notch filter. At 60 Hz, the notch filter has about 50 dB attenuation of signal. +VSY R1 804kΩ R2 804kΩ C1 3.3nF VO –VSY C2 3.3nF 1 fO = 2π R C 1 1 C1 = C2 = 07670-060 R1 = R2 = 2R3 C3 2 100kΩ 500kΩ –15V Figure 61. High-Side Signal Conditioning MICROPOWER INSTRUMENTATION AMPLIFIER The ADA4062-2 is a dual amplifier and is perfectly suited for applications that require lower supply currents. For supply voltages of ±15 V, the supply current per amplifier is 165 μA typical. The ADA4062-2 also offers a typical low offset voltage drift of 5 μV/°C and a very low bias current of 2 pA, which make it well suited for instrumentation amplifiers. R3 10.1kΩ 20 R4 1MΩ 10 R2 1MΩ +15V R1 10.1kΩ 1/2 0 ADA4062-2 –10 V1 –20 V2 –30 +15V 1/2 VO ADA4062-2 –15V –15V VO = 100(V2 – V1) TYPICAL: 0.5mV < │V2 – V1│< 135mV TYPICAL: –13.8V < VO < +13.5V USE MATCHED RESISTORS –40 –50 Figure 62. Micropower Instrumentation Amplifier –60 –70 100 FREQUENCY (Hz) 1k 07670-057 GAIN (dB) VO ADA4062-x Figure 59. Notch Filter Circuit –80 10 RL +15V Figure 62 shows the classic 2-op-amp instrumentation amplifier with four resistors using the ADA4062-2. The key to high CMRR for this instrumentation amplifier are resistors that are well matched to both the resistive ratio and relative drift. For true difference amplification, matching of the resistor ratio is very important, where R3/R4 = R1/R2. Assuming perfectly matched resistors, the gain of the circuit is 1 + R2/R1, which is approximately 100. Tighter matching of two op amps in one package, as is the case with the ADA4062-2, offers a significant boost in performance over the classical 3-op-amp configuration. Overall, the circuit only requires about 330 μA of supply current. ADA4062-x C3 6.6nF R3 402kΩ 500kΩ 100kΩ Figure 60. Frequency Response of the Notch Filter Rev. B | Page 15 of 20 07670-059 IN 0.1Ω +15V 07670-058 Alternatively, different combinations of resistor and capacitor values can be used to achieve the desired notch frequency. However, the major drawback to this circuit topology is the need to ensure that all the resistors and capacitors be closely matched. If they are not closely matched, the notch frequency offset and drift cause the circuit to attenuate at a frequency other than the ideal notch frequency. ADA4062-2/ADA4062-4 PHASE REVERSAL VIN +VSY R D1 10kΩ IN5711 –VSY 07670-053 VO ADA4062-x Figure 63. Phase Reversal Solution Circuit Rev. B | Page 16 of 20 TIME (40µs/DIV) Figure 64. No Phase Reversal 07670-063 For the ADA4062-x, the output does not phase reverse if one or both of the inputs exceeds the input voltage range but remains within the positive supply rail and 0.5 V above the negative supply rail. In other words, for an application with a supply voltage of ±15 V, the input voltage can be as high as +15 V without any output phase reversal. However, when the voltage of the inputs is driven beyond −14.5 V, phase reversal occurs due to saturation of the input stage leading to forward biasing of the gate-drain diode. Phase reversal in ADA4062-x can be prevented by using a Schottky diode to clamp the input terminals to each other. In the simple buffer circuit in Figure 63, D1 protects the op amp against phase reversal, and R limits the input current that flows into the op amp. VOUT VOLTAGE (5V/DIV) Phase reversal occurs in some amplifiers when the input commonmode voltage range is exceeded. When the voltage driving the input to these amplifiers exceeds the maximum input commonmode voltage range, the output of the amplifiers changes polarity. Most JFET input amplifiers have phase reversal if either input exceeds the input common-mode range. VSY = ±15V ADA4062-2/ADA4062-4 SCHEMATIC V+ OUT V– Figure 65. Simplified Schematic of the ADA4062-x Rev. B | Page 17 of 20 07670-062 +IN –IN ADA4062-2/ADA4062-4 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.80 0.55 0.40 0.23 0.09 6° 0° 0.40 0.25 100709-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 66. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 67. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.20 DIA TYP 0.55 0.40 0.30 1.30 1 1.60 0.40 BSC 4 0.05 MAX 0.02 NOM 0.20 BSC 033007-A SEATING PLANE 6 0.35 0.30 0.25 BOTTOM VIEW TOP VIEW 0.60 0.55 0.50 PIN 1 IDENTIFIER 9 Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ] 1.30 mm × 1.60 mm, Body, Ultra Thin Quad (CP-10-10) Dimensions shown in millimeters Rev. B | Page 18 of 20 ADA4062-2/ADA4062-4 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 69. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 1.75 1.60 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 4 8 5 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters Rev. B | Page 19 of 20 01-13-2010-D PIN 1 INDICATOR 3.10 3.00 SQ 2.90 ADA4062-2/ADA4062-4 ORDERING GUIDE Model 1 ADA4062-2ARMZ ADA4062-2ARMZ-RL ADA4062-2ARMZ-RL7 ADA4062-2ARZ ADA4062-2ARZ-R7 ADA4062-2ARZ-RL ADA4062-2BRZ ADA4062-2BRZ-R7 ADA4062-2BRZ-RL ADA4062-2ACPZ-R2 ADA4062-2ACPZ-RL ADA4062-2ACPZ-R7 ADA4062-4ARUZ ADA4062-4ARUZ-RL ADA4062-4ACPZ-R2 ADA4062-4ACPZ-R7 ADA4062-4ACPZ-RL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 10-Lead LFCSP_UQ 10-Lead LFCSP_UQ 10-Lead LFCSP_UQ 14-Lead TSSOP 14-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ Z = RoHS Compliant Part. ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07670-0-2/10(B) Rev. B | Page 20 of 20 Package Option RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 CP-10-10 CP-10-10 CP-10-10 RU-14 RU-14 CP-16-22 CP-16-22 CP-16-22 Branding A25 A25 A25 J J J A2K A2K A2K