Design Solutions 43 June 2004 High Performance Switch Mode Power Solutions for Altera Low Voltage FPGAs by Mike Shriver INTRODUCTION The core voltages for FPGAs are moving lower as a result of advances in the fabrication process. The newest FPGA family from Altera, the Stratix® II, now requires a core voltage of 1.2V and the Stratix, Stratix GX, HardCopy® Stratix and CycloneTM families require a core voltage of 1.5V. This article discusses how to power the core and I/O of low voltage FPGAs using the latest step-down switch mode controllers from Linear Technology Corporation. To ensure correct selection of power management circuitry, it is recommended to use Altera’s PowerPlay Power Estimation Tools to obtain accurate results. Tools are available to help determine power consumption before and during the design process. More information on these tools is available from Altera’s website: http://www.altera.com/ support/devices/estimator/pow-powerplay.html. Overview The load and input voltage requirements for FPGA systems vary considerably. A single FPGA typically requires less than 2A, but for systems using multiple FPGAs, the load requirements can go to 10A or higher. Since power must be applied to the core and I/O, more than one rail is often required. Combinations of 1.2V and higher voltages such as 1.5V, 1.8V, 2.5V and 3.3V might be encountered. The input voltage requirements vary as well. The system designer may be inclined to step down from an input voltage such as 12V for high output current systems to reduce the I2R losses in the PCB traces, connector and cabling. For low output current levels, an input voltage of 5V or lower may be used. The regulators shown in Table 1 cover a wide variety of output current and input voltage levels often encountered in low voltage FPGA systems. The special features shown in Table 1 along with more general ones are covered below. Table 1. Switch Mode Regulators for 1.2V and 1.5V FPGA Systems LTC CONTROLLER PART NUMBER REFERENCE DESIGN VIN VOUT AT IOUT LTC®3407 Dual Output, Monolithic, 100% Duty Cycle 3.3V, 5V 2.5V at 0.6A 1.5V at 0.6A LTC3413 DDR Memory, Monolithic 2.5V, 3.3V, 5V 1.25V at ±3A LTC3414 Single Output, Monolithic, 100% Duty Cycle 3.3V, 5V 1.5V at 4A LTC3736 Dual Output/Dual Phase, Rail Tracking, No RSENSETM, 100% Duty Cycle 3.3V, 5V 2.5V at 5A 1.2V at 5A (VIN = 5V) LTC3728L Dual Output/Dual Phase, 3.3V and 5V LDO 5V, 12V 2.5V at 5A 1.5V at 5A LTC1778 Single Output, Fixed On-Time, No RSENSE, 5V LDO 5V, 12V 1.2V at 12A LTC3717 DDR Memory, Fixed On-Time, No RSENSE 5V, 12V 1.25V at ±10A LTC3708* Dual Output/Dual Phase, Rail Tracking, Fixed On-Time, No RSENSE 5V, 12V 2.5V at 15A 1.2V at 15A SPECIAL FEATURES *5V bias supply required. Synchronous Operation All of the regulators shown in Table 1 are synchronous step-down regulators. This means that a MOSFET switch is used in place of the free-wheeling Schottky diode of nonsynchronous switch mode step-down regulators (see Figure 1). The advantage of using a synchronous stepdown regulator as opposed to a nonsynchronous step-down regulator or linear mode regulator is efficiency. A small Schottky placed in parallel with the bottom switch provides further yet modest efficiency gains. The full load efficiency of all the regulators in Table 1 is greater than 78%, with most efficiencies in the mid 80% range. See Table 2 for efficiency data. , LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. Stratix and HardCopy are registered trademarks of Altera Corporation. Cyclone is a trademark of Altera Corporation. dsol43fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 Design Solutions 43 the user with a minimum parts count, reduced footprint solution. For higher output current levels, controllers driving external switches are required. VIN TOP GATE DRIVE L VOUT CIN No RSENSE Operation D COUT The No RSENSE parts (LTC1778, LTC3717, LTC3708, LTC3736) sense the voltage drop across the RDS(ON) of the external FETs, eliminating the need for a sense resistor. This reduces circuit size and cost and improves efficiency. Of the parts listed in Table 1, only the LTC3728L uses external sense resistors, and the advantage of this is tighter peak current measurement accuracy. DSOL43 F01a (1a) Conventional Step-Down Converter VIN TOP GATE DRIVE L 100% Duty Cycle VOUT CIN BOTTOM GATE DRIVE D OPTIONAL The LTC3407 dual monolithic, LTC3414 monolithic and LTC3736 controller are examples of synchronous devices that can operate at duty cycles up to and including 100%, which is beneficial in battery-powered applications. At 100% duty cycle, the top switch turns on continuously and reduces the dropout voltage to the voltage drop across the RDS(ON) of the top switch and the output inductor. Battery run-time is extended as a result, for small step-down ratio applications. COUT DSOL43 F01b (1b) Synchronous Step-Down Converter Figure 1. Conventional Step-Down Regulator vs Synchronous Step-Down Regulator Table 2. Full Load Regulator Efficiency PART NUMBER INPUT VOLTAGE VOUT at IOUT 2.5V 3.3V 5V 88% 81% 87% 80% 81% 81% Light Load Efficiency 12V LTC3407 2.5V at 0.6A 1.5V at 0.6A LTC3413 1.25V at ±3A 78% LTC3414 1.5V at 4A 78% LTC3736 2.5V at 5A/3A 1.2V at 5A/3A (VIN = 5V/3.3V) LTC3728L 2.5V at 5A 1.5V at 5A 90% 85% 91% 87% LTC1778 1.2V at 12A 85% 83% LTC3717 1.25V at ±10A 83% 82% LTC3708 2.5V at 15A 1.2V at 15A 92% 88% 92% 88% 80% 80% 92% 86% 90% 83% Monolithic Converters The LTC3407, LTC3413 and LTC3414 devices are monolithic, which means that the switches and current sensing elements are built-in. These monolithic devices provide The devices listed in Table 1 feature a variety of light load operating modes such as Burst Mode® operation or Pulse Skip designed to improve efficiency by preventing reverse currents from flowing through the inductor. However, these operating modes may affect the output voltage ripple. Refer to the individual data sheets for more details on these operating modes. Switching Frequency A high switching frequency is desired because as the switching frequency increases, smaller output capacitors and inductors can be used. The lowest output current/ lowest input voltage regulators are able to operate with the highest switching frequency, which further reduces the solution size. The highest output current/high input voltage regulators operate at lower frequencies. The switching frequency range for all of the reference design shown varies from 200kHz to over 1MHz. Burst Mode is a registered trademark of Linear Technology. dsol43fa 2 Design Solutions 43 Fixed On-Time The fixed on-time parts (LTC1778, LTC3708, LTC3717) are ideal for applications that require a very fast response time with a minimal amount of output capacitance and/or for applications that operate with a very narrow duty cycle (i.e., large input to output voltage differentials) and a relatively high switching frequency. IRMS = IOUT(MAX) • √(D • (1 – D)), where D = VOUT/VIN. Dual Output/Dual Phase Operation The dual phase controllers (LTC3736, LTC3728L, LTC3708) drive their two outputs 180 degrees out of phase. This interleaves the current pulses flowing into the top switch of each phase which reduces the RMS ripple current through the input capacitors and eases input filter design requirements (see Figure 2). For a 2.5V/10A and 1.5V/10A Single Phase Dual Controller converter operating with an input voltage of 4.5V to 14V, dual phase operation reduces the input capacitor ripple current by a least 30%. As a rule of thumb, the input capacitors only need to be sized for the phase with the highest output current operating at 50% duty cycle. The RMS ripple current for one phase is given as: 2-Phase Dual Controller SW1 (V) At 50% duty cycle, the equation reduces to: IRMS = IOUT(MAX)/2 Power Supply Tracking The most recent dual phase/dual output regulator controllers (LTC3736, LTC3708) offer rail tracking. This feature allows either coincidental or ratiometric tracking to be implemented. The LTC3736 offers ramp-up tracking. The LTC3708 offers both ramp-up and ramp-down tracking, and multiple LTC3708s can be daisy-chained for applications where tracking of more than two rails is required. See Figures 3 and 4 for examples. SW2 (V) IL1 0.5V/DIV IL2 0.5V/DIV IIN 2ms/DIV DSOL43 F02 INPUT CAPACITOR RIPPLE CURRENT (ARMS) Figure 2a. Dual-Phase vs Single Phase Operation DSOL43 F03 Figure 3. Up/Down Coincident Rail Tracking of the LTC3708 10 9 8 SINGLE PHASE/ DUAL OUTPUT 7 6 5 0.5V/DIV DUAL PHASE/ DUAL OUTPUT 4 3 0.5V/DIV 2 1 VOUT1 = 2.5V/10A VOUT2 = 1.5V/10A 0 4 5 6 7 8 9 10 11 12 13 14 15 INPUT VOLTAGE (V) DSOL45 F02b Figure 2b. Input Capacitor Ripple Current vs Input Voltage (LTC3708) 2ms/DIV DSOL43 F04 Figure 4. Up/Down Ratiometric Rail Tracking of the LTC3708 dsol43fa 3 Design Solutions 43 DDR Memory Termination The Stratix II, Stratix, Stratix GX and Cyclone FPGAs can interface with DDR memory. A DDR memory interface requires a termination supply set to half the driver voltage that can both sink and source current. A synchronous buck regulator is well suited for the latter because current can flow both ways through the switches. A synchronous buck regulator is also more efficient than a linear mode DDR regulator. Two products targeted for DDR memory termination are the LTC3413 and the LTC3717. LTC3407 Figure 5 shows a 2.5V/600mA and 1.5V/600mA LTC3407 regulator that can be powered from a local 3.3V or 5V rail. It operates at a frequency of 1.5MHz, allowing the use of tiny output capacitors and inductors with less than a 2mm profile, and its integrated switches conserve board space. This dual regulator provides a very compact design for low power FPGA systems. LTC3414 REFERENCE DESIGNS Figure 6 shows a 1.5V/4A LTC3414 regulator that can be powered from a local 3.3V or 5V rail. This regulator is programmed for a switching frequency of 1MHz, allowing the use of a small, low DC resistance (DCR), 6.5mm × 6.9mm 0.47µH output inductor, and its internal switches conserve board space. This is a compact solution for medium power single voltage FPGA systems. The reference designs in Table 1 are all optimized for specific output current and input voltage ranges found in FPGA systems, with an emphasis on 1.2V and 1.5V core voltages. A brief description of each follows. VIN 2.5V TO 5.5V + C1 47µF 10V CIN 10µF 6.3V 3 L1 2.2µH VOUT1 1.5V 600mA COUT1 10µF 6.3V 10pF 604k VIN LTC3407EMS 8 2 RUN1 POR 9 4 SW1 RUN2 7 SW2 10 1 VFB2 VFB1 R2 100k L2 2.2µH C2 10pF COUT2 10µF 6.3V R6 887k GND MODE/SYNC 402k 5 VOUT2 2.5V 600mA R7 280k 6 CIN, COUT1, COUT2: TAIYO YUDEN JMK212BJ106MG C1: AVX TAJW476M010R L1, L2: TAIYO YUDEN LQLBC2518R2M DSOL43 F05 Figure 5. LTC3407: Monolithic 1.5V/600mA and 2.5V/600mA Regulator VIN 2.5V TO 5.5V 7 CIN 100µF 6.3V ×2 6 14 15 2.2M 16 100k PGOOD 17 RUN/SS 4 1000pF X7R 3 PVIN SW NC SW PVIN SW NC SW SVIN L 0.47µH COUT 100µF 6.3V ×2 9 12 13 LTC3414EFE VFB RUN/SS ITH SYNC/MODE RT SGND PGND PGND PGND PGND 1 10 VOUT 1.5V 4A 33pF PGOOD 5 8 11 19 18 200k 2 178k 12.1k 294k 20 470pF 100pF CIN, COUT: TDK C4532X5R0J107M L: VISHAY IHLP-2525CZ-01 0.47µH DSOL43 F06 Figure 6. LTC3414: Monolithic 1.5V/4A Regulator dsol43fa 4 Design Solutions 43 LTC3736 LTC3728L Figure 7 shows a 2.5V/1.2V dual output LTC3736 regulator that is powered from a local 3.3V or 5V rail. At an input voltage of 5V, both rails can provide 5A of output current. This regulator is an efficient solution for mid-power FPGA systems that require ramp-up power supply tracking. Figure 8 shows a 2.5V/1.5V dual output LTC3728L regulator which can be powered from either a 5V or 12V rail. Both outputs can provide 5A. This is another efficient solution for mid-power FPGA systems with a higher input voltage range. CIN1 10µF 6.3V 1µF 10V 10Ω Q1B 5 20 Q1A 21 VOUT1 2.5V IOUT1 RUN/SS VIN 17 L1 1.5µH + COUT1 150µF 4V 22 19 10µF 6.3V 18 14 59k 6 23 187k 24 1 VIN Q2B 25 PGND PGND PGND 12 Q2A 11 SENSE1+ SENSE2+ 15 TG1 TG2 10 SW1 SW2 LTC3736EUF 13 BG1 BG2 16 SYNC/FCB PGND 9 RUN/SS PGOOD 3 TRACK PLLLPF 2 IPRG1 IPRG2 7 VFB1 VFB2 8 ITH1 ITH2 SGND L2 1µH + VIN * 470pF 470pF 59k 15k 100pF 100pF COUT2 150µF 4V 10µF 6.3V VIN IOUT1, IOUT2 3.3V 5V 3A 5A VOUT2 1.2V IOUT2 0.01µF 59k 4 59k VIN 2.7V TO 5V CIN2 10µF 6.3V 15k 10k 59k DSOL43 F07 CIN1, CIN2: TAIYO YUDEN JMK316BJ106ML COUT1, COUT2: SANYO 4TPB150MC L1, L2: VISHAY IHLP-2525CZ-01 1µH Q1, Q2: SILICONIX Si7540DP *INSERT THE PLLLPF PIN COMPONENTS ONLY WHEN A CLOCK SIGNAL IS APPLIED TO THE SYNC/FCB Figure 7. LTC3736: 2.5V/5A and 1.2V/5A Regulator with Rail Tracking dsol43fa 5 Design Solutions 43 1M 1M 10Ω 10Ω 32 NC ON/OFF 28 ON/OFF 100pF 0.1µF 0.1µF 29 L1 3.2µH NC RUN/SS1 PGOOD SENSE1+ TG1 27 + 1000pF 30 RSENSE1 6mΩ 26 Q1B COUT1 220µF 4V Q1A 0.1µF 43.2k 5V 31 SENSE1– SW1 VOSENSE1 BOOST1 PLLFLTR VIN VOUT1 2.5V 5A 10µF 6.3V 25 CMDSH-3 20k 1 24 10k 2 3.16k 3 PLLIN BG1 1Ω 23 22 5V 4 680pF 15k 5 100pF 6 FCB EXTVCC LTC3728LEUH ITH1 INTVCC SGND PGND 21 20 1µF + 19 10µF 16V 1µF + 4.7µF 10V VIN 4.5V TO 14V CIN 100µF 16V 680pF 15k 7 100pF 3.3VOUT BG2 18 CMDSH-3 8 BOOST2 ITH2 17 0.1µF 20k 9 330pF 17.5k VOSENSE2 SW2 11 SENSE2– TG2 12 SENSE2+ RUN/SS2 NC NC 15 14 Q2B 10Ω 10Ω 10 Q2A L2 3.2µH 1000pF 13 RSENSE2 6mΩ + 16 COUT2 220µF 4V VOUT2 1.5V 5A 10µF 6.3V DSOL43 F08 5V LDO 3.3V LDO C24 0.01µF CIN: SANYO 16SVP100M (100µF, 16V) COUT1, COUT2: PANASONIC EEFUE0G221R L1, L2: SUMIDA CDEP105-3R2MC-50 Q1, Q2: FAIRCHILD FDS6982S RSENSE1, RSENSE2: IRC LRF1206-01-R006-J NOTE: FOR VIN = 5V, TIE PINS 20, 21 AND 23 TOGETHER Figure 8. LTC3728L: High VIN 2.5V/5A and 1.5V/5A Regulator dsol43fa 6 Design Solutions 43 LTC1778 Figure 9 shows a 1.2V/12A single output LTC1778 regulator. Its input can be tapped from either a 5V or 12V rail. This is an efficient solution for high power FPGA systems. LTC3708 Figure 10 shows a 2.5V/15A and 1.2V/15A LTC3708 regulator, which can use either 5V or 12V as its input. The PGOOD strong gate drivers of the LTC3708 allow high output current to be delivered efficiently. For an input voltage of either 5V or 12V, its 1.2V output can deliver 15A with an efficiency of 88%. This is a very efficient solution for highpower FPGA systems that require up/down power supply tracking and has the highest efficiency of all the regulators shown. VIN 1M INTVCC 0.1µF 1 10k 43.2k 100k 2 3 4 680pF 10k 5 6 100pF 0.1µF 7 8 20k 10k 10µF 16V RUN/SS CMDSH-3 LTC1778CGN RUN/SS BOOST PGOOD TG VRNG SW PGND FCB BG ITH INTVCC SGND ION VIN VFB EXTVCC + 16 15 Q1 0.22µF 14 CIN 330µF 16V L 0.8µH 13 + 12 Q2 11 10 VIN 4.5V TO 14V D COUT 220µF 2.5V ×2 22µF 6.3V VOUT 1.2V 12A 4.7µF 6.3V 1µF 9 1Ω 549k DSOL43 F09 CIN: SANYO 16SVP330M COUT: PANASONIC EEFUE0E221R D: DIODES B340A L: SUMIDA CDEP105-0R8MC-88 Q1: SILICONIX Si4860DY Q2: SILICONIX Si4842DY NOTE: FOR VIN = 5V, TIE PINS 9, 10 AND 11 TOGETHER Figure 9. LTC1778: High VIN 1.2V/12A Regulator dsol43fa 7 Design Solutions 43 VIN 4.5V TO 14V + 10µF 16V ×2 BAT54A CIN 330µF 16V ×2 EXT 5V VCC 5V 2.2µF 6.3V X5R 10Ω 1µF 17 27 Q1 VOUT1 2.5V 15A 47µF 6.3V 0Ω COUT1 330µF 4V ×2 0.22µF 26 0Ω + D1 28 25 100pF Q2 0Ω 22 24 23 6.04k 1% 56pF 19.1k 1% 1.5M 130k 1% VCC 32 VIN 29 10nF 3 6 9 2 1nF 6.04k 1% 6.04k 1% 24.9k 1% 475Ω NOTE 1: EXTERNAL 5V BIAS REQUIRED NOTE 2: COINCIDENT RAIL TRACKING IMPLEMENTED 4 31 TG2 TG1 BOOST2 BOOST1 SW2 SW1 150pF 2.2µF 14 13 Q3 0Ω 15k 1% 15 0.22µF SGND 680pF 5 15k 1% 0.1µF L2 0.8µH BOOST2 16 SENSE2+ SENSE1+ 20 100pF BG1 LTC3708EUH BG2 18 – – SENSE1 SENSE2 19 PGND1 PGND2 11 715k 1% VRNG1 VRNG2 VIN 12 ION1 ION2 10nF 7 VFB1 VFB2 30 TRACK2 PGOOD 10 EXTLPF INTLPF 8 ITH1 ITH2 1 47nF 21 VCC TRACK1 FCB DRVCC RUN/SS 470pF 2.2µF VCC BOOST2 L1 1.4µH 5V 100pF 0Ω + Q4 0Ω 130k 1% VCC D2 COUT2 470µF 2.5V ×2 6.04k 1% VOUT2 1.2V 15A 47µF 6.3V 5V 100pF 100k PGOOD 470pF 3.32k 1% 150pF 0.01µF 6.04k 1% 24.9k 1% DSOL43 F10 * RUN/SS BAT54W VIN 1M CIN: SANYO 16SVP330M COUT1: SANYO 4TPD330M COUT2: SANYO 2R5TPD470M D1, D2: DIODES B340LA L1: PANASONIC ETQP3H0R8BF L2: PANASONIC ETQP2H1R2BF Q1, Q3: RENESAS HAT2168H Q2, Q4: RENESAS HAT2165H *INSERT THE EXTLPF PIN COMPONENTS ONLY IF A CLOCK SIGNAL IS APPLIED TO THE FCB PIN Figure 10. LTC3708: 2.5V/15A and 1.2V/15A Regulator with Up/Down Rail Tracking dsol43fa 8 Design Solutions 43 LTC3413 LTC3717 Figure 11 shows a monolithic 1.25V ±3A DDR termination regulator featuring the LTC3413. It can use either a local 2.5V, 3.3V or 5V rail as its input voltage. It operates at a switching frequency of 1MHz, which allows a small 6.5mm × 6.9mm 0.47µH output inductor to be used. It is a compact and efficient solution for typical DDR applications. Figure 12 shows a 1.25V ±10A DDR regulator that uses the LTC3717 controller. It can be powered from either a 5V or 12V rail. This is an efficient solution for high power DDR applications. 16 VIN 2.25V TO 5.5V CIN 100µF 6.3V ×2 4.7M 9 PVIN SW PVIN SW SW 1 2 7 RUN/SS 6 330pF VOUT 1.25V ±3A VOUT = VREF/2 COUT 100µF 6.3V ×2 14 11 10 LTC3413EFE 100k PGOOD SW SVIN L 0.47µH 15 PGOOD VFB RUN/SS ITH VREF RT 4 3 5 5.11k 1% SGND PGND PGND EXTREF 2.5V 8 12 309k 13 100pF 220pF DSOL43 F11 SGND CIN, COUT: TDK C4532X5R0J107M L: VISHAY IHLP-2525CZ-01 0.47 PGND Figure 11. LTC3413: Monolithic 1.25V ±3A DDR Termination Regulator VIN 0.1µF 1M 1 2 PGOOD INTVCC INTVCC 3 10k 4 CMDSH-3 RUN/SS TG VRNG SW PGND ITH 16 6 VIN 7 VREF 2.5V 8 SGND Q1 14 BG INTVCC VFB VCC EXTVCC L1 1.5µH 13 D2 4.7µF ION VREF D1 0.33µF 15 LTC3717EGN 5 499k 1% BOOST PGOOD 330pF 1000pF 10µF 16V + ×2 12 Q2 11 0.1µF COUT 180µF 4V ×2 CIN 330µF 16V VOUT 1.25V VOUT = VREF/2 10µF 6.3V INTVCC 10 9 + VIN 4.5V TO 14V VIN 1µF 1Ω 1µF DSOL43 F12 CIN: SANYO 16SVP330M COUT: PANASONIC EEFUE0G181R D1, D2: DOIDES B340A L1: SUMIDA CEP125-1R5MC Q1: SILICONIX Si7840DP Q2: SILICONIX Si7440DP NOTE: FOR VIN = 5V, TIE PINS 9, 10 AND 11 TOGETHER Figure 12. LTC3717: 1.25V ±10A DDR Termination Regulator dsol43fa 9 Design Solutions 43 An equation for output ripple is as follows: OUTPUT VOLTAGE REGULATION Output voltage regulation is an important consideration when designing a power supply. Important factors to consider are set point accuracy, load regulation and output ripple. Set Point Accuracy The output voltage set point accuracy is determined by the tolerance of the reference and the feedback resistor divider used. The equation for the output voltage is given as: ⎛ RTOP ⎞ VOUT = VREF • ⎜ 1 + ⎟ ⎝ RBOTTOM ⎠ ⎛ ⎞ 1 Ripple = IP-P • ⎜ ESR + ⎟ mVP-P ⎝ 8 • fSW • C OUT ⎠ where the peak-to-peak ripple current (IP-P) is defined as: IP-P = VIN – VOUT VOUT • L • fSW VIN The dominant term in the above equation is ESR. When selecting output capacitors, choose components with low ESR values to minimize the output ripple. CURRENT LIMIT See Figure 13 for a simplified schematic. The reference voltage tolerance for the parts discussed in this article is from 1% to 2%. Use 1% feedback resistors for the specified performance. VOUT CONTROLLER VFB RTOP – RBOTTOM VREF + DSOL43 F13 Figure 13. Feedback Voltage Divider DC Load Regulation The DC load regulation is affected by layout and open-loop gain. Layout is the dominant factor since the open-loop gain is always sufficiently high. To achieve good regulation, make sure the voltage feedback divider is connected directly across the (+) and (–) terminals of COUT . Output Ripple Ripple is measured in terms of mV peak-peak. This is the instantaneous variation of the output voltage and is determined by the switching frequency of the regulator as well as the input voltage, output voltage, inductor value, effective series resistance of the output capacitors and the amount of output capacitance. When designing a regulator, determine the maximum surge current that must be supplied. For FPGAs, the maximum surge current typically occurs during turn-on when the device is being programmed. The regulator’s maximum output current (IOUT(MAX)) must be greater than the maximum expected surge current. The data sheets for all of the parts shown contain the formulas for calculating IOUT(MAX). Refer to the data sheets and/or contact Linear Technology for assistance. COMPONENT SELECTION The four major components to be selected are the inductor(s), output capacitors, input capacitors and external MOSFETs. Use the demo board bill of materials and data sheet to help determine which parts to use, and consult with the parts vendor. An overview of the selection criteria follows. Output Inductor Select the inductor value such that inductor peak-to-peak ripple current (IP-P) is 40% of IOUT(MAX). This is a good starting point. Smaller values can be chosen, but the trade-off is higher ripple current and higher output voltage ripple. A larger value can be chosen, but the trade-off is larger package size, increased DCR and reduced signal strength for the current sense signal. Make sure the inductor’s rated saturation current is greater than IOUT(MAX) + IP-P/2. A partial list of vendors includes Sumida, Vishay, Toko, Pulse, Panasonic, Coilcraft, Coiltronics and Murata. dsol43fa 10 Design Solutions 43 Output Capacitance MOSFETs Select capacitors with low ESR to minimize the output voltage ripple. Low ESR capacitors include the Sanyo Poscap, Panasonic Specialty Polymer, Kemet AO-Cap, Kemet polymer tantalums (T520), as well as a variety of low ESR solid tantalums. Pay careful attention to the voltage derating. Multilayer ceramic capacitors can also be used, but they have very low ESR which makes loop compensation more challenging. Refer to Linear Technology Application Note 76 for more details. For the controllers, external MOSFETs are required. The bottom FET needs to have a low RDS(ON) to minimize conduction losses. The top FET needs to have a low gate charge (QG) to minimize transition losses, and if the duty cycle is high, a low value of RDS(ON) as well. Make sure the current rating of the MOSFET is not exceeded. Contact the MOSFET vendor for more details. MOSFET vendors include Vishay Siliconix, Renesas, International Rectifier, and Fairchild. Input Capacitance The input capacitance must supply the pulsed current that flows through the top FET. Select CIN with a ripple current rating that meets or exceeds the maximum expected ripple current. The capacitance value must also be high enough for adequate circuit stability. Sanyo OS-CONs or similar parts are a good choice due to their high RMS current ratings and their high capacitance. However, they have high series inductance (ESL). To minimize the ESL, a ceramic capacitor should be paralleled with the OS-CON and placed next to the top and bottom FETs. Aluminum electrolytics are inexpensive, but their RMS current ratings are low relative to OS-CONs and their ESL is also high. Sometimes, a carefully selected parallel combination of aluminum electrolytics and high grade ceramics can be used where the ceramics handle the ripple current and the aluminum electrolytics provide the bulk capacitance for stability. SWITCHING FREQUENCY The controllers shown in Table 1 operate at various frequencies. The LTC3407 operates at a fixed frequency of 1.5MHz. The switching frequency on the other parts can be set within a range by a voltage or a resistor. For the fixed on-time parts, the switching frequency is determined by the output voltage and programmed on-time. Refer to the individual data sheets for more details. LOOP COMPENSATION All of the controllers shown in Table 1 use current mode control. In the simplest model of a current mode buck regulator, the output inductor is considered to be a current source controlled by the output voltage of the error amplifier. This reduces the output power stage to a first order system with the output capacitance forming the dominant pole. Both the value of COUT and its ESR are critical in designing a stable loop in addition to the compensation components and the feedback divider. Refer to Linear Technology’s Application Note 76 for more details. dsol43fa 11 Design Solutions 43 LAYOUT Board layout is a very critical step in designing a switch mode step-down regulator. A poor layout can affect stability, regulation and reliability. Refer to the individual data sheets for specific guidelines as well as the demo board gerber files. Here are several points to keep in mind when addressing layout issues for controllers: • Keep the signal ground (SGND) and power grounds (PGND) separate, and tie SGND to PGND at one location. • The loop area formed by the top FET, bottom FET and ceramic input capacitor should be as small as possible. • Keep the high dV/dt traces away from the control signals. • Devote entire layers or planes for the ground, all output voltages and the input voltage. Liberally spread the copper for these signals. • If necessary, shield the high dV/dt traces on one layer from the control signals on another with the GND plane, VIN plane or VOUT plane. • Make all of the high current connections as wide and short as possible. • Use Kelvin current sensing for the current sense lines (if applicable). • Place a ground plane underneath the controller. • Allow sufficient copper for heat-spreading. dsol43fa 12 Linear Technology Corporation LT/TP 0505 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004