LINER LTC3717

LTC3717
Wide Operating Range,
No RSENSETM Step-Down Controller
for DDR/QDR Memory Termination
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DESCRIPTIO
FEATURES
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VOUT = 1/2 VIN (Supply Splitter)
Adjustable and Symmetrical Sink/Source
Current Limit up to 20A
±0.65% Output Voltage Accuracy
Up to 97% Efficiency
No Sense Resistor Required
Ultrafast Transient Response
True Current Mode Control
2% to 90% Duty Cycle at 200kHz
tON(MIN) ≤ 100ns
Stable with Ceramic COUT
Dual N-Channel MOSFET Synchronous Drive
Power Good Output Voltage Monitor
Wide VCC Range: 4V to 36V
Adjustable Switching Frequency up to 1.5MHz
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Available in a 16-Pin Narrow SSOP Package
The LTC®3717 is a synchronous step-down switching
regulator controller for double data rate (DDR) and Quad
Data RateTM (QDRTM) memory termination. The controller
uses a valley current control architecture to deliver very
low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is
compensated for variations in VIN.
Forced continuous operation reduces noise and RF interference. Output voltage is internally set to half of VREF,
which is user programmable.
Fault protection is provided by an output overvoltage
comparator and optional short-circuit shutdown timer.
Soft-start capability for supply sequencing is accomplished using an external timing capacitor. The regulator
current limit level is symmetrical and user programmable.
Wide supply range allows operation from 4V to 36V at the
VCC input.
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APPLICATIO S
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Bus Termination: DDR and QDR Memory, SSTL,
HSTL, ...
Notebook Computers, Desktop Servers
Tracking Power Supply
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, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
TYPICAL APPLICATIO
1µF
RUN/SS
RC
20k
+
VDD = 2.5V
M1
Si7840DP
TG
CSS
0.1µF
D2
B320A
SW
ITH
CB 0.22µF
BOOST
INTVCC
BG
PGOOD
PGND
L1
0.68µH
DB
CMDSH-3
LTC3717
SGND
VIN
2.5V TO 5.5V
ION
VREF
CC
470pF
Efficiency vs Load Current
RON
715k
VCC
+
M2
Si7840DP
CVCC
4.7µF
+
100
VOUT
1.25V
COUT ±10A
180µF
4V
×2
D1
B320A
VIN = 5V
80
70
VIN = 2.5V
60
50
40
30
20
10
0
VFB
VOUT = 1.25V
90
CIN
150µF
6.3V
×2
EFFICIENCY (%)
VCC
5V TO 28V
3717 F01a
0
2
4
6
8
10
LOAD CURRENT (A)
12
14
3717 F01b
Figure 1. High Efficiency DDR Memory Termination Supply
sn3717 3717fs
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LTC3717
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AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage (VCC, ION) .................36V to – 0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ................................................... 42V to – 0.3V
SW Voltage .................................................. 36V to – 5V
EXTVCC, (BOOST – SW), RUN/SS,
PGOOD Voltages ....................................... 7V to – 0.3V
VREF, VRNG Voltages ...............(INTVCC + 0.3V) to – 0.3V
ITH, VFB Voltages...................................... 2.7V to – 0.3V
TG, BG, INTVCC, EXTVCC Peak Currents .................... 2A
TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA
Operating Ambient Temperature
Range (Note 4) ................................... – 40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
RUN/SS 1
16 BOOST
PGOOD 2
15 TG
VRNG 3
14 SW
ITH 4
SGND 5
13 PGND
12 BG
ION 6
11 INTVCC
VFB 7
10 VCC
VREF 8
LTC3717EGN
9
GN PART
MARKING
EXTVCC
3717
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1000
15
2000
30
µA
µA
0.65
%
Main Control Loop
IQ
Input DC Supply Current
Normal
Shutdown Supply Current
VRUN/SS = 0V
VFB
Feedback Voltage Accuracy
ITH = 1.2V (Note 3), VREF = 2.4V
∆VFB(LINEREG)
Feedback Voltage Line Regulation
VCC= 4V to 36V, ITH = 1.2V (Note 3)
∆VFB(LOADREG)
Feedback Voltage Load Regulation
ITH = 0.5V to 1.9V (Note 3)
– 0.05
– 0.3
%
gm(EA)
Error Amplifier Transconductance
ITH = 1.2V (Note 3)
0.93
1.13
1.33
mS
tON
On-Time
ION = 30µA
ION = 60µA
186
95
233
115
280
135
ns
ns
tON(MIN)
Minimum On-Time
ION = 180µA
50
100
ns
tOFF(MIN)
Minimum Off-Time
ION = 30µA
300
400
ns
VSENSE(MAX)
Maximum Current Sense Threshold (Source)
VPGND – VSW
VRNG = 1V, VFB = VREF/2 – 50mV
VRNG = 0V, VFB = VREF/2 – 50mV
VRNG = INTVCC, VFB = VREF/2 – 50mV
●
●
●
108
76
148
135
95
185
162
114
222
mV
mV
mV
VSENSE(MIN)
Minimum Current Sense Threshold (Sink)
VPGND – VSW
VRNG = 1V, VFB = VREF/2 + 50mV
VRNG = 0V, VFB = VREF/2 + 50mV
VRNG = INTVCC, VFB = VREF/2 + 50mV
●
●
●
– 140
– 97
– 200
– 165
– 115
– 235
– 190
– 133
– 270
mV
mV
mV
∆VFB(OV)
Output Overvoltage Fault Threshold
8
10
12
%
∆VFB(UV)
Output Undervoltage Fault Threshold
VRUN/SS(ON)
RUN Pin Start Threshold
VRUN/SS(LE)
RUN Pin Latchoff Enable Threshold
RUN/SS Pin Rising
VRUN/SS(LT)
RUN Pin Latchoff Threshold
RUN/SS Pin Falling
IRUN/SS(C)
Soft-Start Charge Current
– 0.5
IRUN/SS(D)
Soft-Start Discharge Current
0.8
1.8
3
– 0.65
0.002
●
%/V
– 25
●
0.8
%
1.5
2
V
4
4.5
V
3.5
4.2
V
– 1.2
–3
µA
µA
sn3717 3717fs
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LTC3717
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VCC(UVLO)
Undervoltage Lockout Threshold
VCC Falling
VCC(UVLOR)
Undervoltage Lockout Threshold
VCC Rising
TG RUP
TG Driver Pull-Up On Resistance
TG High
TG RDOWN
TG Driver Pull-Down On Resistance
BG RUP
BG RDOWN
MIN
TYP
MAX
UNITS
●
3.4
3.9
●
3.5
4
V
2
3
Ω
TG Low
2
3
Ω
BG Driver Pull-Up On Resistance
BG High
3
4
Ω
BG Driver Pull-Down On Resistance
BG Low
1
2
Ω
TG tr
TG Rise Time
CLOAD = 3300pF
20
ns
TG tf
TG Fall Time
CLOAD = 3300pF
20
ns
BG tr
BG Rise Time
CLOAD = 3300pF
20
ns
BG tf
BG Fall Time
CLOAD = 3300pF
20
ns
V
Internal VCC Regulator
VINTVCC
Internal VCC Voltage
6V < VCC < 30V, VEXTVCC = 4V
∆VLDO(LOADREG)
Internal VCC Load Regulation
ICC = 0mA to 20mA, VEXTVCC = 4V
VEXTVCC
EXTVCC Switchover Voltage
ICC = 20mA, VEXTVCC Rising
∆VEXTVCC
EXTVCC Switch Drop Voltage
ICC = 20mA, VEXTVCC = 5V
∆VEXTVCC(HYS)
EXTVCC Switchover Hysteresis
●
●
4.7
4.5
5
5.3
V
– 0.1
±2
%
300
mV
4.7
150
V
200
mV
PGOOD Output
∆VFBH
PGOOD Upper Threshold
VFB Rising (0% = 1/3 VREF)
8
10
12
%
∆VFBL
PGOOD Lower Threshold
VFB Falling (0% = 1/3 VREF)
–8
– 10
– 12
%
∆VFB(HYS)
PGOOD Hysteresis
VFB Returning (0% = 1/3 VREF)
1
2
%
VPGL
PGOOD Low Voltage
IPGOOD = 5mA
0.15
0.4
V
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD as follows:
LTC3717EGN: TJ = TA + (PD • 130°C/W)
Note 3: The LTC3717 is tested in a feedback loop that adjusts VFB to achieve
a specified error amplifier output voltage (ITH).
Note 4: The LTC3717E is guaranteed to meet performance specifications from
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.
sn3717 3717fs
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LTC3717
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TYPICAL PERFOR A CE CHARACTERISTICS
VOUT/VIN Tracking Ratio vs Input
Voltage
Efficiency vs Load Current
100
VIN = 2.5V
VOUT = 1.25V
90
400
LOAD = 0A
49.95
80
LOAD = 10A
350
70
60
50
40
30
FREQUENCY (kHz)
49.90
VOUT/VIN (%)
EFFICIENCY (%)
Frequency vs Input Voltage
450
50.00
LOAD = 1A
49.85
LOAD = 10A
49.80
49.75
20
300
250
LOAD = 0A
200
150
100
10
49.70
FIGURE 1 CIRCUIT
0
0.01
0.1
1
10
LOAD CURRENT (A)
49.65
1.5
100
VOUT = 1.25V
FIGURE 1 CIRCUIT
50
FIGURE 1 CIRCUIT
0
1.7
1.9 2.1 2.3 2.5
INPUT VOLTAGE (V)
2.7
1.5
2.9
1.7
1.9 2.1 2.3 2.5
INPUT VOLTAGE (V)
2.7
2.9
3717 G06
3717 G08
3717 G07
Load Regulation
Start-Up Response
Load-Step Transient
0
VIN = 2.5V
VOUT = 1.25V
–0.1
VOUT
1V/DIV
VOUT
200mV/DIV
IL
2A/DIV
IL
5A/DIV
∆VOUT/VOUT (%)
–0.2
–0.3
–0.4
–0.5
VIN = 2.5V
4ms/DIV
VOUT = 1.25V
LOAD = 0.2Ω
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
–0.6
0
1
2
3 4 5 6 7
LOAD CURRENT (A)
8
9
10
VIN = 2.5V
20µs/DIV
VOUT = 1.25V
LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT
3718 G09.eps
3718 G10.eps
3717 G09
On-Time vs VON Voltage
1000
On-Time vs Temperature
300
IION = 30µA
IION = 30µA
250
600
400
200
ON-TIME (ns)
ON-TIME (ns)
800
ON-TIME (ns)
On-Time vs ION Current
10k
150
100
200
0
1k
100
50
0
2
1
VON VOLTAGE (V)
3
3717 G11
0
–50 –25
10
50
25
75
0
TEMPERATURE (°C)
100
125
3717 G12
1
10
ION CURRENT (µA)
100
3717 G13
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LTC3717
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TYPICAL PERFOR A CE CHARACTERISTICS
–0.1
2
–0.2
–0.3
5.0
RUN/SS THRESHOLD (V)
3
FCB PIN CURRENT (µA)
∆INTVCC (%)
0
PULL-DOWN CURRENT
1
0
PULL-UP CURRENT
LATCHOFF ENABLE
4.0
3.5
0
10
30
40
20
INTVCC LOAD CURRENT (mA)
LATCHOFF THRESHOLD
–2
–50 –25
50
50
25
0
75
TEMPERATURE (°C)
100
Undervoltage Lockout Threshold
vs Temperature
3.0
2.5
75
0
25
50
TEMPERATURE (C)
100
125
300
250
200
150
100
50
0
0.50
0.75
1.00
1.25 1.50
VRNG (V)
1.75
3717 G17
100
1.50
160
1.40
140
1.30
120
60
40
20
0
–50 –30 –10 10 30 50 70 90 110 130
3717 G20
TEMPERATURE (°C)
120
100
80
60
40
20
0
2.0
2.2
2.4
2.6 2.8 3.0
RUN/SS (V)
3.2
3.4 3.6
3717 G19
1.20
gm (ms)
80
140
Error Amplifier gm
vs Temperature
180
100
2.00
125
160
3717 G18
Maximum Current Sense Threshold
vs Temperature, VRNG = 1V
MAXIMUM CURRENT SENSE THRESHOLD (mV)
75
0
25
50
TEMPERATURE (°C)
Maximum Current Sense Threshold
vs RUN/SS Voltage, VRNG = 1V
MAXIMUM CURRENT SENSE THRESHOLD (mV)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
3.5
–25
3717 G16
Maximum Current Sense Threshold
vs VRNG Voltage
4.0
2.0
–50 –25
3.0
–50
125
3717 G15
3717 G14
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
4.5
–1
–0.4
–0.5
RUN/SS Latchoff Thresholds
vs Temperature
RUN/SS Latchoff Thresholds
vs Temperature
INTVCC Load Regulation
1.10
1.00
0.90
0.80
0.70
–50 –30 –10 10 30 50 70 90 110 130
3717 G21
TEMPERATURE (°C)
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LTC3717
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PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
PGOOD (Pin 2): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.
VRNG (Pin 3): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
ITH (Pin 4): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
SGND (Pin 5): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 6): On-Time Current Input. Tie a resistor from VIN
to this pin to set the one-shot timer current and thereby set
the switching frequency.
VFB (Pin 7): Error Amplifier Feedback Input. This pin
connects to VOUT and divides its voltage to 2/3 • VFB
through precision internal resistors before it is applied to
the input of the error amplifier. Do not apply more than
1.5V on VFB. For higher output voltages, attach an external
resistor R2 (1/2 • R1 at VREF) from VOUT to VFB.
VREF (Pin 8): Positive Input of Internal Error Amplifier.
This pin connects to an external reference and divides its
voltage to 1/3 VREF through precision internal resisters
before it is applied to the positive input of the error
amplifier. Reference voltage for output voltage, power
good threshold, and short-circuit shutdown threshold. Do
not apply more than 3V on VREF. If higher voltages are
used, connect an external resistor (R1 ≥ 160k) from
voltage reference to VREF.
EXTVCC (Pin 9): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC
and shuts down the internal regulator so that controller
and gate drive power is drawn from EXTVCC. Do not exceed
7V at this pin and ensure that EXTVCC < VCC.
VCC (Pin 10): Bias Input Supply. 4V to 36V operating
range. Decouple this pin to PGND with an RC filter (1Ω,
0.1µF).
INTVCC (Pin 11): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7µF
low ESR tantalum or ceramic capacitor.
BG (Pin 12): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
PGND (Pin 13): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of CVCC and the (–) terminal of CIN.
SW (Pin 14): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to a diode voltage
drop above VIN.
TG (Pin 15): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW.
BOOST (Pin 16): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
sn3717 3717fs
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LTC3717
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FU CTIO AL DIAGRA
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RON
VIN
6 ION
10 VCC
9 EXTVCC
+
4.7V
CIN
+
–
1.192V
BNGP
5V
REG
BOOST
tON =
0.7V
(10pF)
IION
R
S
TG
Q
FCNT
14
L1
SWITCH
LOGIC
IREV
VOUT
DB
–
–
M1
SW
+
ICMP
CB
15
ON
20k
+
16
INTVCC
INTVCC
11
SHDN
1.4V
BG
OV
12
+
COUT
CVCC
M2
VRNG
PGND
3
×
13
PGOOD
0.7V
2
5.7µA
1
240k
+
Q2
3
V
10 REF
ITHB
Q1
Q5
–
20k
+
40k
OV
–
–
SS
+
–
–
+
8
40k
5 SGND
1.2µA
6V
0.6V
80k
11
V
30 REF
RUN
SHDN
+
EA
VREF
7 VFB
UV
4 ITH
RC
CC1
VREF
4
1 RUN/SS CSS
3717 FD
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LTC3717
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OPERATIO
Main Control Loop
The LTC3717 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by
sensing the voltage between the PGND and SW pins using
the bottom MOSFET on-resistance . The voltage on the ITH
pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this
ITH voltage by comparing 2/3 of the feedback signal VFB
from the output voltage with a reference equal to 1/3 of the
VREF voltage. If the load current increases, it causes a drop
in the feedback voltage relative to the reference. The ITH
voltage then rises until the average inductor current again
matches the load current. As a result in normal DDR
operation VOUT is equal to 1/2 of the VREF voltage.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VCC. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
a high efficiency source connected to EXTVCC, such as an
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the VCC voltage is low and INTVCC drops below 3.4V,
undervoltage lockout circuitry prevents the power
switches from turning on.
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APPLICATIO S I FOR ATIO
The basic LTC3717 application circuit is shown in
Figure 1. External component selection is primarily determined by the maximum load current and begins with the
selection of the sense resistance and power MOSFET
switches. The LTC3717 uses the on-resistance of the synchronous power MOSFET for determining the inductor
current. The desired amount of ripple current and operating
frequency largely determines the inductor value. Finally, CIN
is selected for its ability to handle the large RMS current into
the converter and COUT is chosen with low enough ESR to
meet the output voltage ripple and transient specification.
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the PGND
and SW pins. The maximum sense voltage is set by the
voltage applied to the VRNG pin and is equal to approximately (0.13)VRNG for sourcing current and (0.17)VRNG for
sinking current. The current mode control loop will not
allow the inductor current valleys to exceed (0.13)VRNG/
RSENSE for sourcing and (0.17)VRNG/RSENSE for sinking. In
practice, one should allow some margin for variations in
sn3717 3717fs
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LTC3717
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APPLICATIO S I FOR ATIO
RSENSE =
VRNG
10 • IOUT (MAX)
An external resistive divider from INTVCC can be used to set
the voltage of the VRNG pin between 0.5V and 2V resulting
in nominal sense voltages of 50mV to 200mV. Additionally,
the VRNG pin can be tied to SGND or INTVCC in which case
the nominal sense voltage defaults to 70mV or 140mV,
respectively. The maximum allowed sense voltage is about
1.3 times this nominal value for positive output current and
1.7 times the nominal value for negative output current.
Power MOSFET Selection
The LTC3717 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom
(synchronous) switch. Important parameters for the power
MOSFETs are the breakdown voltage V(BR)DSS, threshold
voltage V(GS)TH, on-resistance RDS(ON), reverse transfer
capacitance CRSS and maximum current IDS(MAX).
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3717 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
the load current. During LTC3717’s normal operation, the
duty cycles for the MOSFETs are:
VOUT
VIN
V –V
= IN OUT
VIN
D TOP =
DBOT
The resulting power dissipation in the MOSFETs at maximum output current are:
PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX)
+ k VIN2 IOUT(MAX) CRSS f
PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
2.0
ρT NORMALIZED ON-RESISTANCE
the LTC3717 and external component values and a good
guide for selecting the sense resistance is:
1.5
1.0
0.5
0
– 50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3717 F02
RDS(ON)(MAX)
R
= SENSE
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
Figure 2. RDS(ON) vs. Temperature
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3717 applications is determined implicitly by the one-shot timer that controls the
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on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin according to:
tON =
(0.7V)
(10pF )
IION
Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency
operation as the input supply varies:
f=
VOUT
[HZ ]
(0.7V) RON (10pF )
Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
A more exact equation taking in account the 0.7V drop on
the ION pin is:
f=
VOUT (VIN – 0.7V)
[HZ ]
(0.7V) RON (10pF )VIN
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
RON2 =
5V
RON
0.7V
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
 V  V 
∆IL =  OUT   1 − OUT 
VIN 
 f L 
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
 VOUT  

V
L=
1 − OUT 


 f ∆IL(MAX)   VIN(MAX) 
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. A variety of inductors designed for high
current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft
and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to
be effective, the inductance between it and the bottom
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can be
omitted if the efficiency loss is tolerable.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
IRMS ≅ IOUT (MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX) / 2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
Kool Mµ is a registered trademark of Magnetics, Inc.
sn3717 3717fs
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current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
∆VOUT

1 
≤ ∆IL  ESR +


8fC OUT 
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1µF to 0.47µF, X5R or
X7R dielectric capacitor is adequate.
Fault Condition: Current Limit
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3717, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limits are:
ILIMIT POSITIVE =
VSNS(MAX) 1
+ ∆IL
RDS(ON) ρT 2
ILIMIT NEGATIVE =
VSNS(MIN) 1
– ∆IL
RDS(ON) ρT 2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
Minimum Off-time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
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time that the LTC3717 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 300ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
VIN(MIN) = VOUT
tON + tOFF(MIN)
tON
1. EXTVCC grounded. INTVCC is always powered from the
internal 5V regulator.
2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3717. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and
high frequency of operation may cause the LTC3717 to
exceed its maximum junction temperature rating or RMS
current rating. Most of the supply current drives the
MOSFET gates unless an external EXTVCC source is used.
In continuous mode operation, this current is IGATECHG =
f(Qg(TOP) + Qg(BOT)). The junction temperature can be
estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3717CGN
is limited to less than 14mA from a 30V supply:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
For larger currents, consider using an external supply with
the EXTVCC pin.
EXTVCC Connection
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTVCC
pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTVCC
pin to INTVCC. INTVCC power is supplied from EXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
the EXTVCC pin and ensure that EXTVCC ≤ VCC. The following list summarizes the possible connections for EXTVCC:
12
External Gate Drive Buffers
The LTC3717 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 4
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate, and benefit from an
increased EXTVCC voltage of about 6V.
INTVCC
BOOST
10Ω
TG
Q1
FMMT619
GATE
OF M1
Q2
FMMT720
SW
Q3
FMMT619
GATE
OF M2
Q4
FMMT720
10Ω
BG
PGND
3717 F04
Figure 4. Optional External Gate Driver
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3717 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3717 into a low quiescent current shutdown (IQ <
30µA). Releasing the pin allows an internal 1.2µA current
source to charge up the external timing capacitor CSS. If
RUN/SS has been pulled all the way to ground, there is a
delay before starting of about:
tDELAY =
1.5V
C SS = (1.3s/µF)C SS
1.2µA
sn3717 3717fs
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When the voltage on RUN/SS reaches 1.5V, the LTC3717
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF. The pin can be driven from logic as
shown in Figure 5. Diode D1 reduces the start delay while
allowing CSS to charge up slowly for the soft-start function.
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA current then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:
CSS > COUT VOUT RSENSE (10 – 4 [F/V s])
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. The feature can be overridden by adding a pullup current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of C SS during a
fault and also shortens the soft-start period. Using a
resistor to VIN as shown in Figure 5a is simple, but slightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 5b eliminates the additional
shutdown current, but requires a diode to isolate CSS . Any
pull-up network must be able to pull RUN/SS above the
4.5V maximum threshold that arms the latchoff circuit
and overcome the 4µA maximum discharge current.
INTVCC
RSS*
VIN
3.3V OR 5V
D1
RUN/SS
RSS*
D2*
RUN/SS
2N7002
CSS
CSS
3717 F06
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(5a)
(5b)
Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3717 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the
loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high
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efficiency source, such as an output derived boost network or alternate supply if available.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 6
will provide adequate compensation for most applications. For a detailed explanation of switching control loop
theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = VREF = 2.5V, VEXTVCC = 5V, VOUT =
1.25V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate
the timing resistor with VON = VOUT:
RON =
1.25V(2.5V – 0.7V)
= 514kΩ
(0.7V)(250kHz)(10pF )2.5V
and choose the inductor for about 40% ripple current at
the maximum VIN:
L=
 1.25V 
1.25V
 1−
 = 0.63µH
(250kHz)(0.4)(10A) 
2.5V 
Selecting a standard value of 0.68µH results in a maximum
ripple current of:
∆IL =
 1.25V 
1.25V
1–
 = 3.7A
(250kHz)(0.68µH) 
2.5V 
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
Tying VRNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ110°C = 1.4:
ILIMIT ≥
143mV
1
+ (3.7A) = 12.1A
(1.4)(0.010Ω) 2
and double check the assumed TJ in the MOSFET:
PBOT =
2.5V – 1.25V
(12.1A)2 (1.4)(0.010Ω) = 1.02 W
2.5V
TJ = 70°C + (1.02W)(40°C/W) = 111°C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to inductor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.
sn3717 3717fs
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(This is typically the case, since VIN is derived from
another DC/DC converter.) The ripple voltage will be only:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4A) (0.013Ω) = 52mV
However, a 0A to 10A load step will cause an output
change of up to:
∆VOUT(STEP) = ∆ILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.
PC Board Layout Checklist
When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
1
R3
11k
R4
39k
CC1
470pF
RPG
100k 2
3
RC
20k
4
CC2
100pF
5
CON 0.01µF
6
7
8
RON
511k
(OPT)
0.1µF
LTC3717
RUN/SS BOOST
PGOOD
TG
VRNG
SW
PGND
ITH
BG
SGND
ION
INTVCC
VFB
VCC
VREF
EXTVCC
16
15
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components on
the bottom side of the board.
• Place LTC3717 chip with pins 9 to 16 facing the power
components. Keep the components connected to pins
1 to 8 close to LTC3717 (noise sensitive components).
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3717.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
DB
CMDSH-3
CB
0.22µF
M1
Si4874
14
13
M2
Si4874
CIN
22µF
6.3V
X7R
D2
B320A
L1
0.68µH
D1
B320A
+
COUT1-2
270µF
2V
×2
+
VIN = 2.5V
CIN
180µF
4V
×2
VOUT
1.25V
±10A
COUT3
22µF
6.3V
X7R
12
11
+
CSS
0.1µF
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
CVCC
4.7µF
10
RF
1Ω
9
CF
0.1µF
VEXT 5V
10Ω
3717 F06a
CIN, COUT1-2: CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-0R68MC-H
Figure 6. Design Example: 1.25V/±10A at 250kHz
sn3717 3717fs
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• Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (VIN, VOUT, GND or to any other DC rail in
your system).
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC current.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in
Figure 7.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VCC pin decoupling capacitor CF closely to
the VCC and PGND pins.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
CSS
2
3
CC1
CB
LTC3717
1
RC
4
CC2
5
RUN/SS
BOOST
PGOOD
TG
VRNG
SW
ITH
PGND
SGND
BG
L
16
15
DB
14
+
M1
13
12
CION
M2
D2
D1
VIN
CIN
CVCC
ION
INTVCC
VFB
VCC
CFB
7
8
VREF
EXTVCC
–
11
+
6
10
9
–
VOUT
COUT
CF
+
RF
RON
BOLD LINES INDICATE HIGH CURRENT PATHS
3717F07
Figure 7. LTC3717 Layout Diagram
sn3717 3717fs
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TYPICAL APPLICATIO S
1.5V/±10A at 300kHz from 5V to 28V Input
CSS
0.1µF
1
RR1
11k
RR2
39k
CC1
680pF
RPG
100k 2
3
RC
20k
4
CC2
100pF
5
CON 0.01µF
6
7
8
VREF 3V
10µF
6.3V
X7R
LTC3717
RUN/SS BOOST
PGOOD
TG
VRNG
SW
ITH
SGND
PGND
BG
ION
INTVCC
VFB
VCC
VREF
EXTVCC
16
15
DB
CMDSH-3
CB
0.22µF
M1
IRF7811W
14
B320A
L1
1.2µH
13
M2
IRF7822
D1
B320A
+
VIN
CIN 5V TO 28V
10µF
35V
VOUT
×3
1.5V
±10A
COUT
270µF
2V
×2
12
11
CVCC
4.7µF
10
9
RON
510k
COUT: CORNELL DUBILIER ESRE271M02B
3717 TA01
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TYPICAL APPLICATIO S
High Voltage Half (VIN) Power Supply
CSS
0.1µF
LTC3717
1
RUN/SS BOOST
RPG
100k 2
CC1
470pF
3
RC
20k
4
CC2
100pF
5
CON 0.01µF
6
7
8
RON
510k
R2
1M
TG
PGOOD
SW
VRNG
PGND
ITH
BG
SGND
ION
INTVCC
VFB
VCC
VREF
EXTVCC
16
15
DB
CMDSH-3
CB
0.22µF
14
CIN
10µF
25V
×2
M1
FDS6680S
L1
1.8µH
13
M2
FDS6680S
+
COUT1
270µF
16V
VIN
5V TO 25V
VOUT
VIN/2
±6A
COUT2
10µF
15V
12
11
CVCC
4.7µF
10
RF
1Ω
9
CF
0.1µF
R1 2M
C2
2200pF
3717 TA02
CIN: TAIYO YUDEN TMK432BJ106MM
COUT1: SANYO, OS-CON 16SP270
COUT2: TAIYO YUDEN JMK316BJ106ML
L1: TOKO 919AS-1R8N
sn3717 3717fs
18
LTC3717
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
sn3717 3717fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3717
U
TYPICAL APPLICATIO
Typical Application 1.25V/±3A at 1.4MHz
CSS
0.1µF
1
RPG
100k 2
3
CC1
470pF
RC
33k
4
CC2
100pF
CON, 0.01µF
5
6
7
8
LTC3717
RUN/SS BOOST
PGOOD
VRNG
ITH
SGND
TG
SW
15
CB
0.22µF
+
M1
1/2 Si9802
L1
0.7µH
BG
INTVCC
VFB
VCC
EXTVCC
CIN
120µF
4V
14
+
PGND
ION
VREF
16
DB
CMDSH-3
13
M2
1/2 Si9802
VIN
2.5V
VOUT
1.25V
±3A
COUT
120µF
4V
12
11
10
CVCC
4.7µF
5V
9
1µF
RON
92k
3717 TA03
CIN, COUT: CORNELL DUBILIER ESRD121M04B
L1: TOKO A921CY-0R7M
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Burst Mode is a registered trademark of Linear Technology Corporation.
sn3717 3717fs
20 Linear Technology Corporation
LT/TP 0103 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2001