GV7704 Quad HD-VLC™ Receiver Key Features • Low power operation, typically 810mW • Quad channel serial digital video receiver for HD and 3G video surveillance and HDcctv applications • Wide operating temperature range: -20°C to + 85°C • Pb-free and RoHS compliant • Quad rate operation: 270Mb/s, 540Mb/s, 1.485Gb/s, and 2.97Gb/s • Supports HDcctv 1.0, HD-SDI (ST 292), 3G-SDI (ST 424), and SD-SDI (ST 259)* • Four independent receiver channels with high performance cable equalization, with support for 50/75Ω coaxial and twisted pair cable transmission • Integrated High Definition Visually Lossless CODEC (HD-VLC™) for extended cable reach: HD over 550m of Belden 543945 CCTV coax at Applications • • • • • Digital video recorders (DVR) Video servers Video multiplexers Video PC capture cards HDcctv peripherals Coaxial Cable Application HD-VLC™ Camera HD Sensor Image Signal Processor 270Mb/s • Serial digital loop-though output per channel • Integrated audio de-embedder for the extraction of up GV7700 Transmitter Supports both 720p and 1080p HD formats: HD Video CODEC HDD Storage HDMI Output 150m Cat-5e/6 Cable HD at 270Mb/s Power Source HD-VLC™ DVR IN1 IN2 RS422 RS422 IN3 GV7704 Quad Receiver IN4 Description Full HD: 1080p50/59.94/60fps HD: 1080p25/29.97/30fps HD: 720p25/29.97/30/50/59.94/60fps • Four 8/10-bit BT.1120 compliant output video interfaces, with embedded TRS and external HVF timing outputs • Automatic independent detection of HD-SDI and HD-VLC video input data streams per channel • Downstream ancillary data detection and extraction • Automatic HDcctv Stream ID detection • 4-wire Gennum Serial Peripheral Interface (GSPI 2.0) for external host command and control • JTAG test interface • 1.2V core voltage power supplies • 1.8V digital I/O power supply • Small footprint 169-BGA (11mm x 11mm) The GV7704 is a quad channel serial digital video receiver for High Definition component video. With integrated high performance cable equalizer technology, the GV7704 is capable of receiving compressed video at 270Mb/s or 540Mb/s, or uncompressed at 1.485Gb/s or 2.97Gb/s, over 75Ω coaxial cable, or differentially over a 100Ω twisted pair cable. The GV7704 integrates the High Definition Visually Lossless CODEC (HD-VLC™) technology, which has been developed specifically to reduce the transmission data rate of HD video over both coaxial and unshielded twisted pair (UTP) cable. This is achieved by encoding the HD video, normally transmitted at a serial data rate of 1.485Gb/s, to the same rate as Standard Definition (SD) video, at 270Mb/s serial data rate. At 270Mb/s, the effect of cable loss is greatly reduced, resulting in much longer cable transmission. For 75Ω www.semtech.com Rev.4 March 2016 Power Sink HD-VLC™ Camera to 4 channels of I2S serial digital audio at 32kHz, 44.1kHz and 48kHz sample rates, per video channel GV7704 Final Data Sheet PDS-060376 GV7704 Quad Receiver UTP Cable Application HD over 150m of Cat-5e/6 UTP cable at 270Mb/s • HD-VLC™ DVR HD at 270Mb/s HD-SDI or HD-VLC Cameras Full HD over 300m of Belden 543945 CCTV coax at 540Mb/s 550m Belden 543945 Coaxial Cable GV7700 Transmitter 1 of 56 Semtech The GV7704 supports the extraction of ancillary data from the horizontal blanking of the input video data stream. Ancillary data packets can be accessed via the GSPI, allowing downstream communication from the video source to sink device. The GV7704 recognizes data packets formatted in compliance with the HDcctv 2.0 communications protocol. coaxial cable, cable reach can be extended up to 3x the normal reach when transmitting encoded HD at 270Mb/s. In typical video over coaxial installations, cable distances of up to 550m are possible. Similarly, a 2.97Gb/s 3G signal can be transmitted at 540Mb/s using HD-VLC. The GV7704 can also be configured to receive HD and 3G video over UTP cable, such as Cat-5e and Cat-6 cable, when HD-VLC encoded at 270Mb/s and 540Mb/s, respectively. The GV7704 features an audio de-embedding core, which provides the extraction of up to 4 channels of I2S serial digital audio from the ancillary data space of the input video data stream. The audio de-embedding core supports 32kHz, 44.1kHz, and 48kHz sample rates. The device supports the reception of both 8-bit and 10-bit per pixel YCbCr 4:2:2 BT.1120 component digital video. A single 10-bit wide parallel digital video output bus per channel is provided, with associated pixel clock and timing signal outputs. The GV7704 supports direct interfacing of HD video formats conforming to ITU-R BT.709 and BT.1120-6 for 1125-line formats, and SMPTE ST 296 for 750-line formats. Packaged in a space saving 169 ball 11 x 11mm BGA, the GV7704 is ideal for high density, multi-channel video recorder architectures. Typically requiring only 810mW of power, the device does not require any special heat sinking or air flow, reducing the over cost of HD DVR designs. *Frame structure with encoded HD only. Does not support SD/D1 video. Functional Block Diagram TDO TCK TMS TDI TRST RESET SDOUT SCLK CS SDIN RBIAS Common GSPI JTAG Digital Control CH3_SDO CH3_SDO Channel 3 CH3_SDI CH3_SDI EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format Channel 2 CH2_SDI CH2_SDI EQ CH3_PCLK CH3_DOUT[9:0] CH3_AOUT_1_2 CH3_AOUT_3_4 CH3_ACLK CH3_WCLK CH2_SDO CH2_SDO CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format CH2_PCLK CH2_DOUT[9:0] CH2_AOUT_1_2 CH2_AOUT_3_4 CH2_ACLK CH2_WCLK CH1_SDO Channel 1 CH1_SDO CH1_SDI CH1_SDI EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format CH0_SDO CH0_SDO Channel 0 CH0_SDI CH0_SDI GV7704 Final Data Sheet PDS-060376 EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder www.semtech.com Rev.4 March 2016 CH1_PCLK CH1_DOUT[9:0] CH1_AOUT_1_2 CH1_AOUT_3_4 CH1_ACLK CH1_WCLK Output Format CH0_PCLK CH0_DOUT[9:0] CH0_AOUT_1_2 CH0_AOUT_3_4 CH0_ACLK CH0_WCLK 2 of 56 Semtech Revision History Version 4 ECO PCN 029083 — Date Description March 2016 Updated to Final Data Sheet. Updated Table 2-3 with added Input Jitter Tolerance and changes to values in Rise/Fall Time, Rise/Fall Time Matching, and Output Total Jitter. Updated to Preliminary Data Sheet. Updated Section 2.1, Section 2.2, Section 2.3, Section 4., and Figure 6-2. Added Figure 6-3. Various updates throughout document. 3 027518 — September 2015 2 027065 — July 2015 Updated cable reach values. Updated Table 2-2 and Table 2-3. Updated Section 2.2, Section 2.3, Section 5., and Figure 6-1. Added Section 3., Section 4.11 and Section 4.12. Various updates throughout document. 1 024435 — March 2015 0 021239 — October 2014 New Document Contents 1. Pin Out.................................................................................................................................................................5 1.1 GV7704 Pin Assignment ...................................................................................................................5 1.2 Pin Descriptions ..................................................................................................................................6 2. Electrical Characteristics............................................................................................................................. 13 2.1 Absolute Maximum Ratings ........................................................................................................ 13 2.2 DC Electrical Characteristics ........................................................................................................ 14 2.3 AC Electrical Characteristics ......................................................................................................... 15 3. Input/Output Circuits.................................................................................................................................. 17 4. Detailed Description.................................................................................................................................... 18 4.1 Functional Overview ...................................................................................................................... 18 4.2 Serial Digital Inputs ......................................................................................................................... 18 4.2.1 Input Termination Selection............................................................................................ 19 4.2.2 Automatic Signal Rate Detection .................................................................................. 19 4.3 Serial Digital Outputs ..................................................................................................................... 20 4.3.1 Output Signal Interface Levels ....................................................................................... 20 4.3.2 Serial Data Output Signal ................................................................................................. 20 4.4 Video Functionality ......................................................................................................................... 21 4.4.1 Descrambling and Word Alignment ............................................................................ 21 4.4.2 HD-VLC Decoding ............................................................................................................... 21 4.4.3 High Definition Output Video Format ......................................................................... 23 4.5 Parallel Video Data Outputs CHn_DOUT_[9:0] ..................................................................... 28 4.6 PCLK Control ..................................................................................................................................... 29 4.7 Stream ID Packet Extraction ........................................................................................................ 29 4.8 Ancillary Data Extraction ............................................................................................................... 31 GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 3 of 56 Semtech 4.9 Audio Extraction .............................................................................................................................. 32 4.9.1 Serial I2S Audio Data Format .......................................................................................... 33 4.9.2 Audio Mute............................................................................................................................ 34 4.10 GSPI Host Interface ....................................................................................................................... 34 4.10.1 CS Pin..................................................................................................................................... 34 4.10.2 SDIN Pin................................................................................................................................ 34 4.10.3 SDOUT Pin ........................................................................................................................... 35 4.10.4 SCLK Pin................................................................................................................................ 35 4.10.5 Command Word Description........................................................................................ 35 4.10.6 Data Word Description ................................................................................................... 36 4.10.7 GSPI Transaction Timing ................................................................................................ 37 4.10.8 Single Read/Write Access............................................................................................... 38 4.10.9 Auto-increment Read/Write Access ........................................................................... 38 4.11 JTAG ................................................................................................................................................... 39 4.12 Power Supply and Reset Timing .............................................................................................. 40 5. Register Map................................................................................................................................................... 41 6. Application Information............................................................................................................................. 51 6.1 Typical Application Circuit ........................................................................................................... 51 7. Packaging Information ............................................................................................................................... 53 7.1 Package Dimensions ...................................................................................................................... 53 7.2 Recommended PCB Footprint .................................................................................................... 54 7.3 Marking Diagram ............................................................................................................................. 54 7.4 Solder Reflow Profile ...................................................................................................................... 55 7.5 Packaging Data ................................................................................................................................ 55 7.6 Ordering Information ..................................................................................................................... 55 GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 4 of 56 Semtech 1. Pin Out 1.1 GV7704 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 A CH3_SDI CH3_SDI GND CH3_SDO TCK CH3_WCLK CH2_WCLK CH3_HOUT CH3_PCLK CH3_DOUT_5 CH3_DOUT_3 CH3_DOUT_1 CH3_DOUT_0 B GND GND VDD18_A CH3_SDO TMS CH3_ACLK CH2_ACLK CH3_VOUT CH3_DOUT_8 CH3_DOUT_6 CH3_DOUT_4 CH3_DOUT_2 CH2_VOUT C N/C N/C VDD18_A TDI TDO CH3_AOUT_1_2 CH2_AOUT_1_2 CH3_FOUT CH3_DOUT_9 CH3_DOUT_7 CH2_HOUT CH2_FOUT CH2_PCLK D CH2_SDI CH2_SDI GND TRST EXT_FW GND GND GND CH2_DOUT_9 CH2_DOUT_8 CH2_DOUT_7 E GND GND VDD18_A VDD12_A RSVD GND VDD18_D VDD18_D GND GND CH2_DOUT_6 CH2_DOUT_5 CH2_DOUT_4 F CH2_SDO CH2_SDO VDD18_A VDD12_A GND VDD12_D VDD12_D VDD12_D VDD18_D GND CH2_DOUT_3 CH2_DOUT_2 CH2_DOUT_1 G GND GND VDD18_A VDD12_A GND VDD12_D VDD12_D VDD12_D VDD18_D GND GND CH1_HOUT CH2_DOUT_0 H CH1_SDO CH1_SDO VDD18_A VDD12_A GND VDD12_D VDD12_D VDD12_D VDD18_D GND CH1_VOUT CH1_FOUT CH1_PCLK J GND GND VDD18_A VDD12_A GND GND VDD18_D VDD18_D GND GND CH1_DOUT_9 CH1_DOUT_8 CH1_DOUT_7 K CH1_SDI CH1_SDI GND RESET RSVD CH0_WCLK CH1_WCLK GND GND GND CH1_DOUT_6 CH1_DOUT_5 CH1_DOUT_4 L RBIAS VDD18_A GND SDIN SDOUT CH0_ACLK CH1_ACLK CH0_DOUT_2 CH0_DOUT_5 CH0_DOUT_8 CH1_DOUT_3 CH1_DOUT_2 CH1_DOUT_1 M GND GND VDD18_A CH0_SDO CS CH0_AOUT_1_2 CH1_AOUT_1_2 CH0_DOUT_1 CH0_DOUT_4 CH0_DOUT_7 CH0_DOUT_9 CH0_VOUT CH1_DOUT_0 N CH0_SDI CH0_SDI GND CH0_SDO SCLK CH0_AOUT_3_4 CH1_AOUT_3_4 CH0_DOUT_0 CH0_DOUT_3 CH0_DOUT_6 CH0_PCLK CH0_HOUT CH0_FOUT CH3_AOUT_3_4 CH2_AOUT_3_4 Figure 1-1: GV7704 Pin Out GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 5 of 56 Semtech 1.2 Pin Descriptions Table 1-1: GV7704 Pin Descriptions Pin Number Name Type Description Analog High-Speed Inputs N1, N2 CH0_SDI, CH0_SDI Analog High-Speed Input Differential high-speed data input 0. (75Ω nominal input impedance) K1, K2 CH1_SDI, CH1_SDI Analog High-Speed Input Differential high-speed data input 1. (75Ω nominal input impedance) D1, D2 CH2_SDI, CH2_SDI Analog High-Speed Input Differential high-speed data input 2. (75Ω nominal input impedance) A1, A2 CH3_SDI, CH3_SDI Analog High-Speed Input Differential high-speed data input 3. (75Ω nominal input impedance) Analog High-Speed Outputs N4, M4 CH0_SDO, CH0_SDO Analog High-Speed Output Differential high-speed test output 0. (75Ω nominal output impedance) H1, H2 CH1_SDO, CH1_SDO Analog High-Speed Output Differential high-speed test output 1. (75Ω nominal output impedance) F1, F2 CH2_SDO, CH2_SDO Analog High-Speed Output Differential high-speed test output 2. (75Ω nominal output impedance) A4, B4 CH3_SDO, CH3_SDO Analog High-Speed Output Differential high-speed test output 3. (75Ω nominal output impedance) RBIAS Input/Output External 10kΩ resistor for bias reference. Connect the resistor to ground. Analog Bias L1 Digital Video Outputs Parallel digital video output. L8, L9, L10, M8, M9, M10, M11, N8, N9, N10 GV7704 Final Data Sheet PDS-060376 CH0_DOUT_[9:0] Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. www.semtech.com Rev.4 March 2016 6 of 56 Semtech Table 1-1: GV7704 Pin Descriptions (Continued) Pin Number Name Type Description Horizontal blanking output. N12 CH0_HOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Vertical blanking output. M12 CH0_VOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. N13 CH0_FOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Pixel clock output (148.5MHz or 148.5/1.001 MHz). N11 CH0_PCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Parallel digital video output. J[11:13], K[11:13], L[11:13], M13 CH1_DOUT_[9:0] Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Horizontal blanking output. G12 CH1_HOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Vertical blanking output. H11 CH1_VOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. H12 CH1_FOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 7 of 56 Semtech Table 1-1: GV7704 Pin Descriptions (Continued) Pin Number Name Type Description Pixel clock output (148.5MHz or 148.5/1.001 MHz). H13 CH1_PCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Parallel digital video output. D[11:13], E[11:13], F[11:13], G13 CH2_DOUT_[9:0] Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Horizontal blanking output. C11 CH2_HOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Vertical blanking output. B13 CH2_VOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. C12 CH2_FOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Pixel clock output (148.5MHz or 148.5/1.001 MHz). C13 CH2_PCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Parallel digital video output. A[10:13], B[9:12], C9, C10 CH3_DOUT_[9:0] Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Horizontal blanking output. A8 CH3_HOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 8 of 56 Semtech Table 1-1: GV7704 Pin Descriptions (Continued) Pin Number Name Type Description Vertical blanking output. B8 CH3_VOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. C8 CH3_FOUT Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Pixel clock output (148.5MHz or 148.5/1.001 MHz). A9 CH3_PCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Digital Audio Outputs Channel 0 word clock (32kHz, 44.1kHz, or 48kHz). K6 CH0_WCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 0 I2S Audio clock (64 x word clock). L6 CH0_ACLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 0 I2S Audio output 1 & 2. M6 CH0_AOUT_1_2 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 0 I2S Audio output 3 & 4. N6 CH0_AOUT_3_4 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 1 word clock (32kHz, 44.1kHz, or 48kHz). K7 CH1_WCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 1 I2S Audio clock (64 x word clock). L7 GV7704 Final Data Sheet PDS-060376 CH1_ACLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). www.semtech.com Rev.4 March 2016 9 of 56 Semtech Table 1-1: GV7704 Pin Descriptions (Continued) Pin Number Name Type Description Channel 1 I2S Audio output 1 & 2. M7 CH1_AOUT_1_2 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 1 I2S Audio output 3 & 4. N7 CH1_AOUT_3_4 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 word clock (32kHz, 44.1kHz, or 48kHz). A7 CH2_WCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 I2S Audio clock (64 x word clock). B7 CH2_ACLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 I2S Audio output 1 & 2. C7 CH2_AOUT_1_2 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 I2S Audio output 3 & 4. D7 CH2_AOUT_3_4 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 word clock (32kHz, 44.1kHz, or 48kHz). A6 CH3_WCLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 I2S Audio clock (64 x word clock). B6 CH3_ACLK Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 I2S Audio output 1 & 2. C6 CH3_AOUT_1_2 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 I2S Audio output 3 & 4. D6 GV7704 Final Data Sheet PDS-060376 CH3_AOUT_3_4 Output High impedance when signal is not present or user disables the lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). www.semtech.com Rev.4 March 2016 10 of 56 Semtech Table 1-1: GV7704 Pin Descriptions (Continued) Pin Number Name Type Description JTAG Interface Dedicated JTAG pin – Test Mode Select. B5 TMS Input This pin is used to control the operation of the JTAG test. Schmitt Trigger Input with Pull-Up. If JTAG is not used this pin may be left floating. Dedicated JTAG pin – Test data input. C4 TDI Input This pin is used to shift JTAG test data into the device. Schmitt Trigger Input with Pull-Up. If JTAG is not used this pin may be left floating. C5 TDO Output Dedicated JTAG pin – Test data output. This pin is used to shift results from the device. Dedicated JTAG pin – Serial data clock signal. A5 TCK Input This pin is the JTAG clock. Schmitt Trigger Input. If JTAG is not used this pin must be pulled LOW. Dedicated JTAG pin – Test Reset. D4 TRST Input When set LOW, the JTAG logic will be reset. Schmitt Trigger Input with Pull-Up. If JTAG is not used this pin must be pulled LOW. General I/O and Host Interface K4 RESET Input Digital active–low reset input. Used to reset the internal. operating conditions to default settings. Schmitt Trigger Input. M5 CS Input Used to initiate and terminate GSPI commands. Active-low. L4 SDIN Input Serial input data, clocked in on the rising edge of SCLK. L5 SDOUT Output N5 SCLK Input Serial data output. Only used in GSPI mode. Clocked out on the falling edge of SCLK. Drive strength may be adjusted using register GSPI_SDOUT_DRV_STRENGTH_SEL_REG. Serial clock. The rising edge is used to latch the SDIN bits and the falling edge to drive SDOUT bits. External firmware loading control: D5 EXT_FW Input When HIGH, indicates to the GV7704 that the host will download firmware to the GV7704. When LOW, indicates to the GV7704 to boot with internal firmware. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 11 of 56 Semtech Table 1-1: GV7704 Pin Descriptions (Continued) Pin Number Name Type Description B3, C3, E3, F3, G3, H3, J3, L2, M3 VDD18_A Power Analog 1.8V Power Supply. Connect to 1.8V. E7, E8, F9, G9, H9, J7, J8 VDD18_D Power Digital 1.8V Power Supply. Connect to 1.8V. E4, F4, G4, H4, J4 VDD12_A Power Analog 1.2V Power Supply. Connect to 1.2V. F6, F7, F8, G6, G7, G8, H6, H7, H8 VDD12_D Power Digital 1.2V Power Supply. Connect to 1.2V. A3, B1, B2, D3, D8, D9, D10, E1, E2, E6, E9, E10, F5, F10, G1, G2, G5, G10, G11, H5, H10, J1, J2, J5, J6, J9, J10, K3, K8, K9, K10, L3, M1, M2, N3 GND Power Connect to GND. C1, C2 N/C — Do not Connect. E5, K5 RSVD — Connect to GND. Supply Pins GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 12 of 56 Semtech 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Value 1.8V I/O and Analog Supply Voltage –0.5V to +2.5V DC 1.2V Analog and Core Supply Voltage –0.3V to +1.5V DC DC Input Voltage, VIN (Not to exceed 2.5V) –0.5V to (VDD18 + 0.5V) DC Output Voltage, VOUT (Not to exceed 2.5V) –0.5V to (VDD18 + 0.5V) Input ESD Voltage (HBM) 2kV Input ESD Voltage (CDM) 500V Storage Temperature Range (TS) -50°C to 125°C Operating Temperature Range (TA) -20°C to 85°C Solder Reflow Temperature (4s) 260°C Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation outside of the ranges shown in the AC and DC Electrical Characteristics is not guaranteed. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 13 of 56 Semtech 2.2 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics TA = -20°C to +85°C unless otherwise stated Parameter Symbol Conditions Min Typ Max Units 270Mb/s — 172 — mA 1.485Gb/s — 250 — mA 270Mb/s — 440 — mA 1.485Gb/s — 456 — mA Notes I1V2 +1.2V Supply Current I1V8 +1.8V Supply Current +1.8V Power Supply Range VDD18 At the device pin (nominal ±5%) 1.71 1.8 1.89 V +1.2V Power Supply Range VDD12 At the device pin (nominal ±5%) 1.14 1.2 1.26 V 9.9 10 10.1 kΩ External RBIAS Resistor Power Supply Noise Mask +1.2V Power Supply Noise Mask +1.8V Total Power Consumption — — 0-200kHz — — 100 mVpp 1 — 200kHz to 1MHz — — 100 mVpp 1 — >1MHz — — 100 mVpp 1 — 0 to 200kHz — — 10 mVpp 1 — 200kHz to 1MHz — — 30 mVpp 1 — >1MHz — — 100 mVpp 1 270Mb/s, All Cable Drivers Enabled — 950 1030 mW 270Mb/s, All Cable Drivers Disabled — 810 890 mW 540Mb/s All Cable Drivers Enabled — 1065 1180 mW 540Mb/s All Cable Drivers Disabled — 925 1040 mW 1.485Gb/s, All Cable Drivers Enabled — 1070 1160 mW 1.485Gb/s, All Cable Drivers Disabled — 900 990 mW 2.97Gb/s, All Cable Drivers Enabled — 1200 1370 mW 2.97Gb/s, All Cable Drivers Disabled — 1030 1200 mW VIL Input LOW -0.3 — 0.63 V VIH Input HIGH 1.17 — 1.89 V Ptotal Digital Logic Input GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 14 of 56 Semtech Table 2-2: DC Electrical Characteristics (Continued) TA = -20°C to +85°C unless otherwise stated Parameter Symbol Conditions Min Typ Max Units Notes VOL Output LOW — — 0.45 V 2 VOH Output HIGH 1.35 — — V 2 — — 12 pF Min Typ Max Units — — 50 — Ω — — 75 — Ω Digital Logic Output CLOAD 148.5MHz Notes: 1. Using recommended supply decoupling. See Figure 6-1: Typical Application Circuit (Part 1). 2. All digital outputs. 2.3 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics VDD18_A, VDD18_D = 1.8V±5% and TA = -20°C to +85°C unless otherwise stated Parameter Symbol Conditions Notes Input Conditions SDI Input Termination (On Chip) Input Return Loss — 1MHz to 5MHz 23 — — dB — 5MHz to 1.485GHz 12 — — dB — 1.485GHz to 2.25GHz 10 — — dB — Data rate = 270Mb/s 0.29 — — UI — Data rate = 540Mb/s 0.29 — — UI — Data rate = 1.485Gb/s 0.20 — — UI — Data rate = 2.97Gb/s 0.20 — — UI — 148.5 or 148.5/ 1.001 — MHz Input Jitter Tolerance Clock and Data Output Conditions Output PCLK Clock Frequency fPCLK — 75Ω single-ended 66 75 84 Ω — 100Ω differential 88 100 112 Ω — 1MHz to 5MHz 25 — — dB — 5MHz to 1.485GHz 6 — — dB — 1.485GHz to 2.25GHz 6 — — dB SDO Output Impedance Output Return loss GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 15 of 56 Semtech Table 2-3: AC Electrical Characteristics (Continued) VDD18_A, VDD18_D = 1.8V±5% and TA = -20°C to +85°C unless otherwise stated Parameter Symbol Conditions Min Typ Max Units — 75Ω single-ended 0.36 0.8 0.9 Vpp — 100Ω differential 0.36 0.8 0.9 Vppd — 100Ω differential 20% - 80% — 85 95 ps — 75Ω single-ended 20% - 80% — 102 150 ps Rise/Fall Time Mismatch — 20% - 80% — — 50 ps Overshoot — — — 10 % Notes Amplitude Rise/Fall Time — Data rate = 270Mb/s — 0.08 — UIpp — Data rate = 540Mb/s — 0.1 — UIpp — Data rate = 1.485Gb/s — 0.12 — UIpp — Data rate = 2.97Gb/s — 0.17 — UIpp Output Total Jitter GSPI Digital Control GSPI Read/Write Clock Frequency — — — 55 MHz Reset Time — 10 — — ms Register Access Time — — — 300 ns GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 16 of 56 Semtech 3. Input/Output Circuits To Clamp RBIAS Figure 3-1: RBIAS ESD CLAMP 1.8V VDDA18_DRV 50/75Ω Output drive impedance CH[0:3]_SDO_P CH[0:3]_SDO_N Level & de-emphasis control Level & de-emphasis control GND Figure 3-2: Serial Output Driver ESD CLAMP 50/75Ω Receiver Termination CH[0:3]_SDI_P CH[0:3]_SDI_N Figure 3-3: Serial Input Receiver GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 17 of 56 Semtech 4. Detailed Description 4.1 Functional Overview The GV7704 is a low cost, quad channel HD-VLC receiver of compressed or uncompressed high-definition video. With integrated cable equalizer technology, the GV7704 is capable of receiving compressed video at 270Mb/s or 540Mb/s, or uncompressed video at 1.485Gb/s or 2.97Gb/s over 75Ω coaxial cable. Compressed signals can also be received differentially over 100Ω twisted pair cable. The High Definition Visually Lossless CODEC (HD-VLC™) technology is integrated in order to reduce the transmission data rate of HD video over both coaxial and unshielded twisted pair (UTP) cable. This is achieved by encoding the HD-SDI video, normally transmitted at a serial data rate of 1.485Gb/s, to the same rate as Standard Definition (SD-SDI) video, at 270Mb/s serial data rate. This provides extended cable reach for HD video up to 550m over Belden 543945 CCTV coax or 150m over Cat-5e/6 UTP cable. Similarly, 3G-SDI normally transmitted at 2.97Gb/s can be encoded down to 540Mb/s. The GV7704 features an audio de-embedding core, which provides the extraction of up to 4 channels of I2S serial digital audio from the ancillary data space of the input video data stream. The audio de-embedding core supports 32kHz, 44.1kHz and 48kHz sample rates. The device supports the reception of both 8-bit and 10-bit per pixel YCbCr 4:2:2 BT.1120 component digital video. A single 10-bit wide parallel digital video output bus per channel is provided, with associated pixel clock and H/V/F timing signal inputs. The GV7704 supports the extraction of ancillary data from the horizontal blanking of the input video data stream. Ancillary data packets can be accessed via the GSPI, allowing downstream communication from the video source to sink device. The GV7704 recognizes data packets formatted in compliance with the HDcctv 2.0 communications protocol. The device includes a 4-wire Gennum Serial Peripheral Interface (GSPI 2.0) for external host command and control. All read or write access to the GV7704 is initiated and terminated by the application host processor. The host interface is provided to allow optional configuration of some of the functions and operating modes of the GV7704. 4.2 Serial Digital Inputs The GV7704 can accept up to four separate channels of serial digital input signals compliant with ITU-R BT.709, and ITU-R BT.1120-6. The four differential input channels are CH0_SDI/CH0_SDI, CH1_SDI/CH1_SDI, CH2_SDI/CH2_SDI and CH3_SDI/CH3_SDI. The GV7704 integrates adaptive 75Ω coaxial cable equalizer technology which is capable of >50dB for HD-VLC encoded input signals and >35dB for HD uncompressed signals. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 18 of 56 Semtech Table 4-1: Typical Cable Length Performance Data Rate Belden 543945 CCTV Coaxial Cat-5e/6 UTP HD data @ 1.485Gb/s 150m N/A HD-VLC encoded data @ 270Mb/s 550m 150m 3G data @ 2.97Gb/s 50m N/A 300m 75m* HD-VLC encoded data @ 540Mb/s *Theoretical The Serial Data Signal may be connected to the input pins of any of the four channels in either a differential or single ended configuration. Only AC coupling of the inputs is supported, as the SDI and SDI inputs are internally biased at approximately 1.8V. Note: The serial data output should be disabled to achieve maximum SDI cable reach. 4.2.1 Input Termination Selection Each of the four channels can be individually configured to work in either 50Ω or 75Ω input termination. Please refer to Register Map for details. 4.2.2 Automatic Signal Rate Detection The device is able to automatically detect the rate of the incoming video signal. There are four data rates which are supported: • HD-VLC encoded 270Mb/s (including 270x1.001Mb/s) • HD-VLC encoded 540Mb/s (including 540x1.001Mb/s) • HD-SDI 1.485Gb/s (including 1.485/1.001Gb/s) • 3G-SDI 2.97Gb/s (including 2.97/1.001Gb/s) The detected rate is indicated by bits SD_HDB, THREEG_HDB, and OUT_THREEG_HDB in register GEN_VIDEO_CFG_0_REG which specify whether the incoming signal is HD-VLC encoded (270Mb/s), HD-VLC encoded (540Mb/s), HD (1.485Gb/s), or 3G (2.97Gb/s). Table 4-2 describes how these three bits are used in combination to indicate the input signal rate. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 19 of 56 Semtech Table 4-2: Input Rate Detection GEN_VIDEO_CFG_0_REG Rate SD_HDB THREEG_HDB OUT_THREEG_HDB HD 1.485Gb/s 0 0 0 HD-VLC 270Mb/s 1 0 0 3G 2.97Gb/s 0 1 1 HD-VLC 540MB/s 1 0 1 4.3 Serial Digital Outputs The GV7704’s serial data output pins, SDO and SDO, provide complementary outputs, each capable of driving at least 800mV into a 75Ω single-ended load. Compliance with all requirements defined in Section 4.3.1 through Section 4.3.2 is guaranteed when measured across a 75Ω terminated load at the output of 1m of Belden 543945 cable, including the effects of the BNC and coaxial cable connection, except where otherwise stated. Figure 4-1 illustrates this requirement. 1m Belden 543945 75Ω coaxial cable GV7704 Coupling Capacitor BNC Measuring Device BNC 75Ω resistive load Figure 4-1: BNC and Coaxial Cable Connection 4.3.1 Output Signal Interface Levels The Serial Data Output signals (SDO and SDO pins), of the device meet the amplitude requirements as defined in ITU-R BT.656 and BT.1120 for an unbalanced generator (single-ended). These requirements are met across all ambient temperature and power supply operating conditions described in 2. Electrical Characteristics. 4.3.2 Serial Data Output Signal The device supports two output termination modes (75Ω and 50Ω). The user can program the SDO_50_EN_REG to make that selection, on a per channel basis. Please refer to Register Map for details. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 20 of 56 Semtech 4.3.2.1 Serial Data Output Signal Procedure To enable the serial data output, the user must do a series of GSPI write transactions. The order is very important and must be followed exactly. The sequence is as shown below: 1. Write 03 to the POWER_UP_DRIVER_REG 2. Write 01 to the P2S_CLK_EN_REG 3. Write 01 to the TX_WORD_CLK_ENABLE_REG 4. Write 01 to the CDR_TX_CLK_EN_REG 5. Write 01 to the P2S_RSTB_REG 6. Write 09 to the DATALANE_FIFO_CTRL_REG 7. Write 08 to the DATALANE_FIFO_CTRL_REG Please refer to Section 5. Register Map for detailed register information. Refer to Section 4.10 for GSPI timing requirements. Note: The serial data output should be disabled to achieve maximum SDI cable reach. 4.4 Video Functionality 4.4.1 Descrambling and Word Alignment The GV7704 performs NRZI to NRZ decoding and data descrambling according to ITU-R BT.1120, and word aligns the data to TRS sync words. The GV7704 carries out descrambling and word alignment to enable the detection of TRS sync words. When two consecutive valid TRS words (SAV and EAV), with the same bit alignment have been detected, the device word-aligns the data to the TRS ID words. Note: Both 8-bit and 10-bit TRS headers are identified by the device. 4.4.2 HD-VLC Decoding The GV7704 integrates the High Definition Visually Lossless CODEC (HD-VLC) decoder for extended reach video reception. When used in conjunction with the GV7700 HD-VLC transmitter, HD video transmission can be extended significantly over existing HD serial digital video systems. HD-VLC is based on a simple visually lossless implementation of the Dirac compression tool kit (http://diracvideo.org/) The visually lossless decoder is used to reduce the video bandwidth, using a very low latency mode, from a transmission rate of 1.485Gb/s (HD-SDI) to 270Mb/s (SD-SDI). At a data rate of 270Mb/s, the serial digital encoded HD video can be transmitted over longer runs of coaxial cable. Table 4-3 below shows a comparison of cable distances between HD video transmission at 1.485Gb/s and HD-VLC encoded at 270Mb/s for various common coaxial cable types. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 21 of 56 Semtech Table 4-3: Cable Reach for Various Cable Types (In Metres) HD-VLC: 270Mb/s (m) HD-VLC: 540Mb/s (m) HD-SDI: 1.485Gb/s (m) 3G-SDI: 2.97Gb/s (m) Belden 1694A / Canare L-4.5CHD 710 400 230 80 Belden 543945 550 300 150 50 KW-Link SYV 75-5 500 275 140 50 Canare L-3C2V 300 160 95 30 KW-Link SYV 75-3 300 160 85 30 Cable Type Note: These values apply for new, properly terminated cables. Actual performance may vary. Note 1: Longer cable reach performance at both 3G and 540M is possible; up to 100m at 3G and 400m at 540M can be achieved using Belden 543945. However, GV7704 lock times can increase significantly at these cable ranges, and may exceed the lock time requirements of the intended application. Note 2: The serial data output should be disabled to achieve maximum SDI cable reach. After transmission over the coaxial cable, the 270Mb/s or 540Mb/s serial data is recovered using the GV7704 and the data is decoded back into the native HD or 3G format. The encoding and decoding process has a total latency of 12-14 HD/3G lines which makes the CODEC ideal for low latency real-time applications. Table 4-4 below shows the total encode/decode latency through the GV7704 and the GV7700. Table 4-4: Encode and Decode Total Latency (GV7704 + GV7700) Video Format Delay (μs) Delay (HD/3G Lines) 1080p25 422.2 11.9 1080p29.97 368.8 12.4 1080p30 368.4 12.4 1080p50 211.1 11.9 1080p59.94 184.4 12.4 1080p60 184.2 12.4 720p25 635.1 11.9 720p29.97 546.6 12.2 720p30 546.6 12.2 720p50 368.6 13.8 720p59.94 324.2 14.5 720p60 324.2 14.5 The 270Mb/s data stream uses the same timing and frame structure as Standard Definition SDI (SD-SDI), and can be monitored using standard SD-SDI test equipment to check signal integrity. However, the data contained within the active picture area of the GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 22 of 56 Semtech SD-SDI stream contains only encoded HD packets. The HD video content can only be viewed after the HD-VLC decoding process. When the GV7704 is HD-VLC encoding video formats at “true” 30 or 60 frames per second, the 270Mb/s (540Mb/s) serial data input will actually be incoming at a rate of 270x1.001Mb/s (540x1.001Mb/s). This multiplication factor is to account for the fractional increase in the original HD video frame rate. For all other HD frame rates, the incoming serial data will be exactly 270Mb/s. 4.4.3 High Definition Output Video Format ITU-R BT.1120 describes the serial and parallel format for 1080-line interlaced and progressive digital video. The field/frame blanking period (V), the line blanking period (H), and the field identification (F), are embedded as digital timing codes (TRS) within the video. After deserialization, a single 10-bit bus carrying the C'B, Y', C'R, Y', etc. data pattern is output on the 10-bit parallel data interface, operating at a pixel clock rate of 148.5MHz or 148.5/1.001MHz. For 3G formats the parallel interface uses a DDR pixel clock at 148.5MHz or 148.5/1.001MHz. The following figures show horizontal and vertical timing for 1080-line interlaced systems. LINE 1 V=1 BLANKING 20 21 V=0 FIELD 1 (F=0) ODD FIELD 1 ACTIVE VIDEO 560 561 V=1 BLANKING 563 564 BLANKING 583 584 V=0 FIELD 2 (F=1) EVEN FIELD 2 ACTIVE VIDEO V=1 BLANKING 1123 1124 1125 H=1 EAV H=0 SAV Figure 4-2: Field Timing Relationship for 1080-line Interlaced Systems GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 23 of 56 Semtech START OF DIGITAL LINE BLANKING NEXT LINE H1 3FF 3FF CBD959 YD1918 CRD959 YD1919 3FF 3FF 000 000 000 000 XYZ XYZ CBD0 YD0 CRD0 YD1 CBD1 YD2 CA(n-1) YA(n-1) SAV CODE 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CCR0 YCR0 CCR1 YCR1 CA0 YA0 CA1 YA1 CA2 YA2 EAV CODE START OF DIGITAL ACTIVE LINE MULTIPLEXED STREAM 1920 H2 Figure 4-3: Multiplexed Luma and Chroma Over One Video Line - 1080i Table 4-5: 1080-line Interlaced Horizontal Timing Interlaced 60 or 60/1.001 Hz 50Hz H1 560 1440 H2 4400 5280 4.4.3.1 High Definition 1080p Output Formats ITU-R BT.1120 also includes progressive scan formats with 1080 active lines, with Y'C'BC'R 4:2:2 sampling at pixel rates of 74.25MHz or 74.25/1.001 MHz. The following diagrams show horizontal and vertical timing for 1080-line progressive systems. The GV7704 provides a 10-bit multiplexed output interface, doubling the pixel clock output rate to 148.5MHz or 148.5/1.001 MHz. LINE 1 V=1 BLANKING 41 V=0 42 ACTIVE VIDEO (F=0) 1121 V=1 1122 BLANKING 1125 H=1 EAV H=0 SAV Figure 4-4: Frame Timing Relationship For 1080-line Progressive Systems START OF DIGITAL LINE BLANKING NEXT LINE H1 3FF 3FF CBD959 YD1918 CRD959 YD1919 3FF 3FF 000 000 000 000 XYZ XYZ CBD0 YD0 CRD0 YD1 CBD1 YD2 SAV CODE CA(n-1) YA(n-1) 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CCR0 YCR0 CCR1 YCR1 CA0 YA0 CA1 YA1 CA2 YA2 EAV CODE START OF DIGITAL ACTIVE LINE MULTIPLEXED STREAM 1920 H2 GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 24 of 56 Semtech Figure 4-5: Multiplexed Luma and Chroma Over One Video Line - 1080p Table 4-6: 1080-line Progressive Horizontal Timing Progressive 30Hz, 30/1.001Hz, 60Hz, 60/1.001Hz 25Hz or 50Hz 24Hz or 24/1.001Hz H1 560 1440 1660 H2 4400 5280 5500 4.4.3.2 High Definition 720p Output Formats The Society of Motion Picture and Television Engineers (SMPTE) defines the standard for progressive scan 720-line HD image formats. SMPTE ST 296-2001 specifies the representation for 720p digital Y'C'BC'R 4:2:2 signals at pixel rates of 74.25MHz or 74.25/1.001 MHz. The GV7704 provides a 10-bit multiplexed output interface, doubling the pixel clock output rate to 148.5MHz or 148.5/1.001 MHz. LINE 1 V=1 BLANKING V=0 25 26 ACTIVE VIDEO (F=0) 745 V=1 746 BLANKING 750 H=1 EAV H=0 SAV Figure 4-6: 720p Digital Vertical Timing The frame rate determines the horizontal timing, which is shown in Table 4-7. Table 4-7: 720p Horizontal Timing Frame Rate H = 1 Sample Number H = 0 Sample Number Total Samples Per Line 25 2560 0 7920 30 or 30/1.001 2560 0 6600 50 2560 0 3960 60 or 60/1.001 2560 0 3300 4.4.3.3 BT.656 Video Output Timing Mode By default, the 10-bit parallel video output will contain two embedded TRS words, as defined in ITU-R BT.1120. Some commercially available CODEC devices cannot detect the presence of the double TRS in the HD video stream, and require that the 8/10-bit HD video contain only one TRS word, as per the ITU-R BT.656 Standard Definition format. When the BT656_ENABLE bit is HIGH, the GV7704 will re-format the parallel video GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 25 of 56 Semtech output to conform with BT.656 embedded TRS. The device will replace all data words from the second TRS, line number and line CRC with blanking values, as shown in Figure 4-7. Note that when BT.656 output mode is enabled, any embedded ancillary data in the horizontal balking will remain unchanged, and will not be contiguous from the EAV. This is shown in Figure 4-8 below. CHn_PCLK Cb, n-4 Y, n-4 Cr, n-4 Y, n-3 Cb, n-2 Y, n-2 Cr, n-2 Y, n-1 3FFh CHn_DOUT_[9:0] 000h 000h EAV 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h Y, 6 Cr, 6 Y, 7 Cb, 8 Y, 8 Cr, 8 040h 200h Inserted Blanking Words CHn_HOUT CHn_VOUT CHn_FOUT CHn_DOUT_[9:0] 200h 040h 200h 040h 200h 040h 3FFh 000h 000h SAV Cb, 0 Y, 0 Cr, 0 Y, 1 Cb, 2 Y, 2 Cr, 2 Y, 3 Cb, 4 Y, 4 Cr, 4 Y, 5 Cb, 6 Y, 9 Cb, 10 Inserted Blanking Words CHn_HOUT Figure 4-7: BT.656 Video Output Timing CHn_DOUT_[9:0] 3FFh 000h 000h EAV 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 000h Inserted Blanking Words 040h 3FFh 040h 3FFh 040h Ancillary Data Figure 4-8: Ancillary Data in BT.656 Video Output Timing Mode 4.4.3.4 3G-SDI 1080p Input Formats The Society of Motion Picture and Television Engineers (SMPTE) defines the standard for 3G-SDI image formats in ST 425. The GV7700 supports 1080p50/60 Y'C'BC'R 4:2:2 8/10 bit. For 3G formats the parallel interface uses a DDR pixel clock at 148.5MHz or 148.5/1.001MHz. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 26 of 56 Semtech Y’ 3 Y’ 2 Y’ 3 C’ R1 Y’ 1 C’ R0 C’ R1 Y’ 0 C’ B0 Y’ 2 SAV (XYZ) SAV (XYZ) C’ B1 SAV (000h) SAV (000h) C’ R0 C’ B1 Y’ 1 Y’ 0 C’ B0 Y’ n last sample Y’ (n-2) Y’ (n-1) C’B n last sample SAV (000h) SAV (000h) C’ R(n-1) CRC1 CRC1 SAV (3FFh) CRC0 CRC0 Replaced by Timing Reference Signal SAV (3FFh) LN1 LN1 C’ R963 LN0 LN0 Optional ancillary data space C’R n last Sample C’ B(n-1) Y’ (n-3) Y’ 1927 Y’ 1926 C’ B963 Y’ 1925 Y’ 1924 EAV (XYZ) EAV (XYZ) C’ R962 C’ B962 Y’ 1923 Y’ 1922 C’ B961 EAV (000h) EAV (000h) C’ R961 EAV (000h) EAV (000h) C’ R960 C’ B960 Y’ 1921 Y’ 1920 Y’ 1919 Y’ 1919 EAV (3FFh) C’ R959 Y’ 1918 Data Stream 2 (Interface clock frequency= 148.5 MHz or 148.5/1.001 MHz) Optional ancillary data space EAV (3FFh) Data Stream 1 (Interface clock frequency= 148.5 MHz or 148.5/1.001 MHz) C’ B959 C’R Data (Interface clock frequency= 74.25 MHz or 74.25/1.001 MHz) C’ B959 C’B Data (Interface clock frequency= 74.25 MHz or 74.25/1.001 MHz) C’ R959 Y’ Data (Interface clock frequency= 148.5 MHz or 148.5/1.001 MHz) Y’ 1918 For 60 or 60/1.001, n=2199 For 50, n=2639 Replaced by Timing Reference Signal Replaced by Line Number Replaced by Line CRC Figure 4-9: 20-bit Mapping Structure for 1920 x 1080 50/60Hz Progressive 4:2:2 (Y’C’BC’R) 8/10-bit Signals Table 4-8: 1080p Y’C’BC’R 4:2:0 & 4:2:2 10-bit Bit Structure Mapping Bit Number Data Stream 9 8 7 6 5 4 DS1 Y’[9:0] DS2 C’BC’R[9:0] 3 2 1 0 Note: For 8-bit systems, the data should be justified to the most significant bit (Y’9 and C’BC’R9), with the two least significant bits (Y’[1:0] and C’BC’R[1:0]) set to zero. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 27 of 56 Semtech 4.5 Parallel Video Data Outputs CHn_DOUT_[9:0] A 10-bit video output bus is provided for each received video channel. For HD formats the parallel data outputs are aligned to the rising edge of PCLK. For 3G formats the parallel data outputs are aligned to both rising and falling edge of PCLK. Each output provides a 10-bit multiplexed ITU-R BT.1120 compliant video bus with embedded TRS. The drive strength of the parallel video output pins (PCLK, HOUT, VOUT, FOUT, DOUT[9:0]) can be adjusted using the PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL bit. The device uses the low drive strength setting by default. For PCB trace longer than 6 inches the high drive strength setting should be used. data_* is launched on the positive edge of PCLK PCLK period CHn_PCLK CHn_DOUT[9:0], CHn_FOUT, CHn_HOUT, CHn_VOUT TH TOD data_0 transition zone TOD TSU data_1 transition zone data_0 data_0 transition zone TH data_1 Figure 4-10: SDR Parallel Video Output Timing Diagram DDR interface Note: DS = Data Stream as per SMPTE 425M 80% CH”N”_PCLK 80% 20% 20% tr tf DS1_* is launched on the posedge of PCLK DS2_* is launched on the negedge of PCLK 3.36ns CH”N”_PCLK CH”N”_DOUT[9:0], CH”N”_FOUT, CH”N”_HOUT, CH”N”VOUT TOH DS1_n-1 transition zone DS1_n-1 TOH TOD DS2_0 transition zone TOD DS1_0 transition zone DS2_0 DS1_0 Figure 4-11: DDR Parallel Video Output Timing Diagram Table 4-9: Digital Output Specifications Digital Parallel Video Output Interface Symbol Parallel Clock Frequency fPCLK Parallel Clock Duty Cycle DCPCLK Output Data Hold Time tOH Output Data Delay Time tOD GV7704 Final Data Sheet PDS-060376 Conditions Min Typ Max Units Notes — — 148.5 — MHz — — 40 — 60 % 0.4 — — ns — — — 2.66 ns — 1.89V operation, 6pF CLOAD, 0°C 1.71V operation, 6pF CLOAD, 85°C www.semtech.com Rev.4 March 2016 28 of 56 Semtech Table 4-9: Digital Output Specifications (Continued) Digital Parallel Video Output Interface Symbol Conditions Min Typ Max Units Notes 1.89V operation, 6 pF CLOAD, 0°C — — 0.4 ns — 1.71V operation, 15 pF CLOAD, 85°C — — 1.4 ns — tr/tf Output Data Rise/Fall Time 4.6 PCLK Control The CLOCKS_CFG_CFG_1_REG register can be used to control the phase of the output PCLK. PCLK_SELECT bits shift the phase of the clock according to Table 4-10. The clock can be inverted using the PCLK_INVERT bit. Table 4-10: PCLK Control PCLK_SELECT[2:1] PCLK Phase Adjustment for HD Formats PCLK Phase Adjustment for 3G Formats 0 0 0 1 90 90 2 180 N/A 3 270 N/A 4.7 Stream ID Packet Extraction The GV7704 will automatically detect and extract HDcctv Stream ID packets from all four video channels. Each channel’s 6 byte packet can be read from the host interface through the bits EXTRACT_STREAM_ID_BYTE[1:6] located in registers EXTRACT_STREAM_ID_REG[1:6] respectively. There are independent registers for each of the four channels. When the GV7704 is decoding HD-VLC streams, the device will automatically re-insert the correct Stream ID in the HD parallel video output. Only bytes 1 and 2 of the Stream ID packet will be updated, with all other bytes set to all zero. The re-inserted byte 1 and 2 data can be read from registers INS_ID_BYTE1_REG and INS_ID_BYTE_2_REG. Bytes 1 and 2 can be programmed from bits INS_ID_BYTE[1:2] located in registers INS_ID_BYTE_REG[1:2] respectively. Byte 1 of the Stream ID packet is interpreted according to Table 4-11 below. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 29 of 56 Semtech Table 4-11: Stream ID Packet Extraction Byte 1 Input Video Standard HD-VLC Encoding Byte 1 Value Original Video Standard 720p25 OFF 14h 720p25 625i25 ON 94h 720p25 720p29.97 OFF 12h 720p29.97 525i29.97 ON 92h 720p29.97 720p30 OFF 11h 720p30 525i30 ON 91h 720p30 1080i50 OFF E3h 1080i50 720p50 OFF 13h 720p50 625i25 ON 93h 720p50 1080i59.94 OFF E2h 1080i59.94 720p59.94 OFF 16h 720p59.94 525i29.97 ON 96h 720p59.94 1080i60 OFF E1h 1080i60 720p60 OFF 15h 720p60 525i30 ON 95h 720p60 1080p25 OFF 23h 1080p25 625i25 ON A3h 1080p25 1080p29.97 OFF 22h 1080p29.97 525i29.97 ON A2h 1080p29.97 1080p30 OFF 21h 1080p30 525i30 ON A1h 1080p30 625i25 ON F3h 1080i50 525i29.97 ON F2h 1080i59.94 525i30 ON F1h 1080i60 1080p50 OFF 26h 1080p50 625i50 ON A6h 1080p50 1080p59.94 OFF 25h 1080p59.94 525i59.94 ON A5h 1080p59.94 1080p60 OFF 24h 1080p60 525i60 ON A4h 1080p60 GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 30 of 56 Semtech Note: When the GV7704 is receiving HD-VLC encoded HD video formats at "true" 30 or 60 frames per second, the 270Mb/s serial data rate will be at 270 x 1.001 Mb/s. This multiplication factor is to account for the fractional increase in the original HD video frame rate. For all other HD frame rates, the HD-VLC encoded serial data rate will be exactly 270Mb/s. 4.8 Ancillary Data Extraction The GV7704 is capable of extracting ancillary data packets, with the type of packet specified by the user on a programmable 10 bit DID. The 2 MSBs of the DID are written to ANC_PACKET_DID_9_8 in register ANC_PACKET_DID_9_8_REG, and the next 8 bits are written to ANC_PACKET_DID_7_0 in register ANC_PACKET_DID_7_0_REG. Up to 16 User Data Words can be extracted per ancillary data packet. The chip will extract the DID-SDID/DBN-DC-UDWs-CS bytes, and they are available in 10-bit pairs (ANC_PACKET_UD W0_9_8, ANC_PACKET_UDW0_7_0) through to (ANC_PACKET_UD W15_9_8, ANC_PACKET_UDW15_7_0). The GV7704 looks for packets in the horizontal blanking region of a digital video signal. The vertical blanking region is used by the HD-VLC encoder of the GV7000 which inserts compression coefficients that cannot be overwritten. The payload of the ancillary data packet can be used to carry user-defined or proprietary data, which can be sent between an Aviia transmitter and receiver. The ancillary data packet is formatted according to the Figure 4-12 below. The packet must always begin with the Ancillary Data Flag (ADF), defined as the following 10-bit word sequence: 000h, 3FFh, 3FFh. The next data word is the 8-bit Data ID (DID), used to define the contents of the packet. For example, a unique DID can be used to denote alarm data, with another DID to denote status data. After the DID, there are two possible options, as shown in Figure 4-12. Type 1 Ancillary Data Packet MSB Not b8 Parity bit UDW11 UDW12 UDW13 UDW14 UDW15 CS UDW11 UDW12 UDW13 UDW14 UDW15 CS UDW10 UDW9 UDW8 UDW7 UDW6 UDW5 UDW4 UDW3 UDW2 UDW1 UDW0 DC DBN DID ADF LSB User Data Words Type 2 Ancillary Data Packet MSB Not b8 Parity bit UDW10 UDW9 UDW8 UDW7 UDW6 UDW5 UDW4 UDW3 UDW2 UDW1 UDW0 DC SDID DID ADF LSB User Data Words Figure 4-12: Ancillary Data Packets GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 31 of 56 Semtech A Type 1 packet defines an 8-bit Data Block Number (DBN) sequence, used to distinguish successive packets with the same DID. The DBN simply increments with each packet of the same DID, between 0 and 15. For a Type 2 packet, an 8-bit Secondary Data ID (SDID) word is defined, which can be used to denote variants of payloads with the same DID. For example, packets with a DID to denote error data may distinguish different error types using unique SDID's. After the DBN or SDID, the next data word is the 8-bit Data Count (DC). This word must be set to the number of user data words (UDW) that follow the DC, and must not exceed 16 (maximum payload size). The final word of the ancillary data packet is the 9-bit Checksum (CS). The CS value must be equal to the nine least significant bits of the sum of the nine least significant bits of the DID, the DBN or the SDID, the DC and all user data words (UDW) in the packet. For HD video formats, ancillary data packets are only extracted from the Luma channel. 4.9 Audio Extraction The GV7704 will de-embed audio from both HD and HD-VLC encoded data. The GV7704 can extract up to four channels of serial digital audio at an audio sampling rate of 32kHz, 44.1kHz, or 48kHz. By default, audio extraction for each channel is enabled, and it can be disabled on any channel by setting DISABLE_AUDIO to 01 in the AUDIO_CTRL_OVERRRIDE_REG register from the host interface. By default, the device will process audio at a sampling rate of 48kHz. When using a GV7700 to GV7704 chip set, audio sampled at 44.1kHz and 32kHz will be automatically detected by the GV7704. The GV7704 reads the Stream ID packet byte 3 to determine the audio sampling frequency. When receiving from a signal not transmitted by the GV7700, the audio sampling rate must be manually specified if different than 48kHz, first by setting AUDIO_SAMP_FREQ_MANUAL_MODE to 1, and then by specifying the sampling frequency through AUDIO_SAMP_FREQ. Refer to Table 4-12 below. Table 4-12: Register Settings for Manual Audio Sampling Frequency AUDIO_SAMP_FREQ Sampling Frequency 00 (default) 48khz 01 44.1kHz 10 32kHz 11 Reserved The device will continuously look for the programmable audio group DID and updates the audio packets present on every rising edge of the vertical blanking interval. If several audio groups are present in the video signal, the device will extract the lower Audio Group number (ex: Audio Group 2, Audio Group 8: Audio Group 2 will be extracted). As such, the programmable audio group DID is offered to the user as a method of selecting GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 32 of 56 Semtech the audio group of his choice for extraction or for specifying an audio DID that would be different from the 8 HD audio group DIDs specified in the SMPTE standards. The audio packet format is SMPTE ST 299-1, regardless of the input signal rate (270Mb/s or 1.485Gb/s). The GV7704 will compute ECC (Error Correcting Codes) and compare them to the ECC embedded in the audio packets, and it will correct errors wherever possible as well as report any errors found. Error correction can be disabled by setting DISABLE_ECC to 01 in the AUD_EXT_CONFIG_REG register, and the audio samples will be bypassed as found in the packets. The audio samples will be buffered and output on the four I2S channels via CHn_ACLK, CHn_WCLK, CHn_AIN_1_2, and CHn_AIN_3_4 pins. They will be formatted according to the standard I2S bus specifications, and the timing for this interface is shown in Figure 4-13 below. Not to scale 48kHz audio: 325.5ns 44.1kHz audio: 354.3ns 32kHz audio: 488.3ns CHn_ACLK CHn_AOUT_0_1, CHn_AOUT_2_3 DATA DATA CHn_WCLK toh tod Figure 4-13: ACLK to Audio Data and WCLK Signal Output Timing Table 4-13: GV7704 Serial Audio Data Outputs - AC Electrical Characteristics Parameter Symbol Conditions tOH Output Data Hold Time Min Typ Max Units 1.5 — — ns — — 7.0 ns 50% levels; 1.8V operation tOD Output Data Delay Time 4.9.1 Serial I2S Audio Data Format The GV7704 supports the I2S serial audio data format, as shown in Figure 4-14 below. CHn_WCLK Channel A (Left) Channel B (Right) CHn_ACLK CHn_AIN_0_1/CHn_AIN_2_3 23 22 6 5 4 MSB 3 2 1 0 23 LSB MSB 22 6 5 4 3 2 1 0 LSB Figure 4-14: I2S Audio Output Format GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 33 of 56 Semtech 4.9.2 Audio Mute The GV7704 can mute either pair of output audio channels using 2 host interface control bits for each video lane. The bits can mute channels 0 & 1 or channels 2 & 3. Channels 0 & 1 can be muted by asserting the MUTE 0_1 bit in the AUD_EXT_CONFIG_REG for any of the four video lanes. Channels 2 & 3 can be muted by asserting the MUTE_2_3 bit in the AUD_EXT_CONFIG_REG for any of the four video lanes. See Table 4-14. By default, the 4 channels will not be muted. Table 4-14: Audio Mute Controls Address Register Channel 0: 488Dh Channel 1: 548Dh Parameter MUTE_0_1 HIGH = Channels 0 & 1 are muted LOW = Channels 0 & 1 are not muted MUTE_2_3 HIGH = Channels 2 & 3 are muted LOW = Channels 2 & 3 are not muted AUD_EXT_CONFIG_ REG Channel 2: 608Dh Channel 3: 6C8Dh Description 4.10 GSPI Host Interface The GV7704 is controlled via the Gennum Serial Peripheral Interface (GSPI). The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK pin). The GV7704 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the application host processor. All read and write access to the device is initiated and terminated by the application host processor. 4.10.1 CS Pin The Chip Select pin (CS) is an active-low signal provided by the host processor to the GV7704. The HIGH-to-LOW transition of this pin marks the start of serial communication to the GV7704. The LOW-to-HIGH transition of this pin marks the end of serial communication to the GV7704. 4.10.2 SDIN Pin The SDIN pin is the GSPI serial data input pin of the GV7704. The 16-bit Command and Data Words from the host processor are shifted into the device on the rising edge of SCLK when the CS pin is LOW. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 34 of 56 Semtech 4.10.3 SDOUT Pin The SDOUT pin is the GSPI serial data output of the GV7704. All data transfers out of the GV7704 to the host processor occur from this pin. By default at power up or after system reset, the SDOUT pin provides a non-clocked path directly from the SDIN pin, only when the CS pin is LOW, except during the GSPI Data Word portion for read operations to the device. When the CS pin is HIGH, the SDOUT pin will be in a high-impedance state. For read operations, the SDOUT pin is used to output data read from an internal Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the device on the falling edge of SCLK, so that it can be read by the host processor on the subsequent SCLK rising edge. The current drive strength of the SDOUT pin can be adjusted using the GSPI_SDOUT_DRV_STRENGTH_SEL bit. 4.10.4 SCLK Pin The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided by the host processor. Serial data is clocked into the GV7704 SDIN pin on the rising edge of SCLK. Serial data is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read operation). SCLK is ignored when CS is HIGH. 4.10.5 Command Word Description All GSPI accesses are a minimum of 48 bits in length (a 16-bit Command Word, a 16-bit Extended Address field, and a 16-bit Data Word) and the start of each access is indicated by the HIGH-to-LOW transition of the chip select (CS) pin of the GV7704. The format of the Command Word and Data Words are shown in Figure 4-15. Data received immediately following this HIGH-to-LOW transition will be interpreted as a new Command Word. 4.10.5.1 R/W bit - B15 Command Word This bit indicates a read or write operation. When R/W is set to 1, a read operation is indicated and data is read from the register specified by the ADDRESS field of the Command Word. When R/W is set to 0, a write operation is indicated and data is written to the register specified by the ADDRESS field of the Command Word. 4.10.5.2 BROADCAST ALL - B14 Command Word This bit must always be set to 0. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 35 of 56 Semtech 4.10.5.3 EMEM - B13 Command Word This bit must always be set to 1. 4.10.5.4 AUTOINC - B12 Command Word When AUTOINC is set to 1, Auto-Increment read or write access is enabled. In Auto-Increment Mode, the device automatically increments the register address for each contiguous read or write access, starting from the address defined in the ADDRESS field of the Command Word. The internal address is incremented for each 16-bit read or write access until a LOW-to-HIGH transition on the CS pin is detected. When AUTOINC is set to 0, single read or write access is required. Auto-Increment write must not be used to update values in HOST_CONFIG. 4.10.5.5 UNIT ADDRESS - B11:B5 Command Word The 7 bits of the UNIT ADDRESS field of the Command Word should always be set to 0. 4.10.5.6 ADDRESS - B4:B0 Command Word, B15:B0 Extended Address The Address Word consists of bits [4:0] of the Command Word, plus another 16 bits [15:0] from the Extended Address Word. The total Command and Data Word format, including the Extended Address, is shown in Figure 4-15 below. Command Word MSB UNIT ADDRESS R/W 0 1 AUTOINC 0 0 0 0 A15 A14 A13 A12 A11 A10 A9 A8 LSB ADDRESS[20:16] 0 0 0 A20 A19 A18 A17 A16 A6 A5 A4 A3 A2 A1 A0 D6 D5 D2 D1 D0 ADDRESS[15:0] A7 Data Word REPETITION CODE D15 D14 D13 D12 D11 PAYLOAD (READ/WRITE DATA) D10 D9 D8 D7 D4 D3 Figure 4-15: Command and Data Word Format 4.10.6 Data Word Description The Data Word portion of the GSPI access consists of an 8-bit repetition code, followed by an 8-bit Read or Write access Payload. All registers in the GV7704 are 8 bits long, however since GSPI write commands are required to be 16 bits long, the Data Word will have the same byte repeated. For example, to write FCh to a register within the CSR, the 16-bit Data Word of the GSPI Command should be FCFCh. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 36 of 56 Semtech 4.10.7 GSPI Transaction Timing t0 t2 t1 t7 t4 SCLK t3 CS SDIN SDOUT R/W 0 R/W t8 Auto_ Inc 1 0 1 0 Auto_ Inc 0 0 0 0 0 0 0 0 A14 0 A13 A14 A3 A13 A2 A3 A1 A2 A1 A0 D15 A0 D14 D15 D14 D13 D12 D13 D11 D12 D10 D11 D9 D10 D8 D9 32 SCLK cycles D7 D8 D6 D7 D5 D6 D4 D5 D3 D4 D2 D3 D1 D2 D0 D1 D0 High-Z 16 SCLK cycles SDIN signal is looped out on SDOUT Write Mode t5 t9 SCLK t6 CS SDIN SDOUT R/W Auto_ Inc 1 0 R/W 0 1 0 Auto_ Inc 0 0 0 0 0 0 0 0 A14 0 A13 A14 A3 A13 A2 A3 A1 A2 A1 A0 A0 D15 D14 D13 32 SCLK cycles SDIN signal is looped out on SDOUT D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 High-Z 16 SCLK cycles Read Data is output on SDOUT Read Mode tcmd t9 SCLK CS SDIN COMMAND DATA SDOUT COMMAND DATA X High-Z COMMAND COMMAND Figure 4-16: GSPI External Interface Timing Table 4-15: GSPI Timing Parameters Parameter Symbol Min Typ Max Units CS LOW before SCLK rising edge t0 2.0 — — ns — — 55 MHz SCLK frequency SCLK period t1 18.2 — — ns SCLK duty cycle t2 40 50 60 % Input data setup time t3 2.7 — — ns SCLK idle time — write t4 41.7 — — ns SCLK idle time — read t5 162 — — ns Inter-command delay time tcmd 162 — — ns SDOUT after SCLK falling edge t6 — — 7.5 ns CS HIGH after final SCLK falling edge t7 0.0 — — ns Input data hold time t8 1.0 — — ns GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 37 of 56 Semtech Table 4-15: GSPI Timing Parameters (Continued) Parameter Symbol Min Typ Max Units CS HIGH time t9 57.0 — — ns — — 5.0 ns SDIN to SDOUT combinational delay 4.10.8 Single Read/Write Access Single read/write access timing for the GSPI interface is shown in Figure 4-17 and Figure 4-18. When performing a single read or write access, one Data Word is read from/written to the device per access. Each access is a minimum of 48-bits long, consisting of a Command Word, an Extended Address, and a single Data Word. The read or write cycle begins with a high-to-low transition of the CS pin. The read or write access is terminated by a low-to-high transition of the CS pin. The maximum interface clock frequency (SCLK) is 55MHz and the inter-command delay time indicated in the figures as tcmd, is a minimum of 162ns. For read access, the time from the last bit of the Command Word to the start of the data output, as defined by t5, corresponds to no less than 162ns. tCMD SCLK CS SDIN COMMAND [31:16] COMMAND [15:0] DATA [15:0] X COMMAND [31:16] SDOUT COMMAND [31:16] COMMAND [15:0] DATA [15:0] X COMMAND [31:16] Figure 4-17: GSPI Write Timing – Single Write Access SCLK t5 CS SDIN COMMAND [31:16] COMMAND [15:0] SDOUT COMMAND [31:16] COMMAND [15:0] DATA [15:0] Figure 4-18: GSPI Read Timing – Single Read Access 4.10.9 Auto-increment Read/Write Access Auto-increment read/write access timing for the GSPI interface is shown in Figure 4-19 and Figure 4-20. Auto-increment mode is enabled by the setting of the AUTOINC bit of the Command Word. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 38 of 56 Semtech In this mode, multiple Data Words can be read from/written to the device using only one starting address. Each access is initiated by a HIGH-to-LOW transition of the CS pin, and consists of a Command Word and one or more Data Words. The internal address is automatically incremented after the first read or write Data Word, and continues to increment until the read or write access is terminated by a LOW-to-HIGH transition of the CS pin. Note: Writing to HOST_CONFIG using Auto-increment access is not allowed. The maximum interface clock frequency (SCLK) is 55MHz and the inter-command delay time indicated in the diagram as tcmd, is a minimum of 162ns. For read access, the time from the last bit of the first Command Word to the start of the data output of the first Data Word as defined by t5, will be no less than 162ns. All subsequent read data accesses will not be subject to this delay during an Auto-Increment read. SCLK CS SDIN COMMAND [31:16] COMMAND [15:0] DATA 1 DATA 2 SDOUT COMMAND [31:16] COMMAND [15:0] DATA 1 DATA 2 Figure 4-19: GSPI Write Timing – Auto-Increment SCLK t5 CS SDIN COMMAND [31:16] COMMAND [15:0] SDOUT COMMAND [31:16] COMMAND [15:0] DATA 1 DATA 2 Figure 4-20: GSPI Read Timing – Auto-Increment 4.11 JTAG The GV7704 provides an IEEE 1149.1-compliant JTAG TAP interface for boundary scan test and debug. The GV7704 TAP interface consists of the TCK clock input, TRST, TDI and TMS inputs, and the TDO output as defined in the standard. TMS and TDI inputs are clocked with respect to the rising edge of TCK and the TDO output with respect to the falling edge of TCK. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 39 of 56 Semtech 4.12 Power Supply and Reset Timing VDD18 powering precedes VDD12 1.8V 1.2V VDD18 t_resetb Timing not critical VDD12 1.8V t_GSPI_ready RESET CSR (control & status registers) Indeterminate states reset states CSR accessible by GSPI T_resetb >= 10ms T_GSPI_ready = 10μs Figure 4-21: Power Supply and Reset Timing Note: To ensure correct digital functionality of the part the 1.8V supply must be powered before the 1.2V supply. GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 40 of 56 Semtech 5. Register Map Table 5-1: GV7704 Register Descriptions — Channel Controls Address Register Name Parameter Name 4078h GSPI_SDOUT_DRV_ STRENGTH_SEL_REG GSPI_SDOUT_DRV_ STRENGTH_SEL Bit Slice 0:0 R/W Reset Value RW 1b 5CF1h (Ch 2) INPUT_TERMINATION_ REG INPUT_TERMINATION 0:0 RW 1b PU_DRVN 44F2h (Ch 0) 5CF2h (Ch 2) 0:0 RW 0b POWER_UP_DRIVER_REG 68F2h (Ch 3) Termination is to VDD18. 0b = 50Ω 1b = 75Ω 68F1h (Ch 3) 50F2h (Ch 1) GSPI SDOUT drive strength select. 1b = high drive strength 0b = low drive strength Sets the receive input termination impedance. 44F1h (Ch 0) 50F1h (Ch 1) Description Power up control for the SDO_N path 0b = Power down 1b = Power up Power up control for the SDO_P path PU_DRVP 1:1 RW 0b 0b = Power down 1b = Power up Parallel to serial converter in transmit path clock buffer enable 44F3h (Ch 0) 50F3h (Ch 1) 5CF3h (Ch 2) P2S_CLK_EN_REG P2S_CLK_EN 0:0 RW 0b 68F3h (Ch 3) 44F4h (Ch 0) 50F4h (Ch 1) 5CF4h (Ch 2) P2S_RSTB_REG P2S_RSTB 0:0 RW 0b 68F4h (Ch 3) 5CF5h (Ch 2) CDR_TX_CLK_EN_REG CDR_TX_CLK_EN 0:0 RW 0b SDO_50_EN_REG SDO_50_EN 0:0 RW 0b 68F5h (Ch 3) 44F6h (Ch 0) 50F6h (Ch 1) 5CF6h (Ch 2) 0b = Hold p2s flops in reset 1b = P2s not in reset 0b = Turn off half rate clock to the p2s in the transmit path 1b = Turn on half rate clock to the p2s in the transmit path SDO_P/N 50Ω termination enable 68F6h (Ch 3) GV7704 Final Data Sheet PDS-060376 Parallel to serial converter in transmit path reset Enable for transmit path clock 44F5h (Ch 0) 50F5h (Ch 1) 0b = Clocks in the p2s are turned off 1b = Clocks in the p2s are enabled www.semtech.com Rev.4 March 2016 0b = 75Ω termination 1b = 50Ω termination 41 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name 4469h (Ch 0) 5069h (Ch 1) 5C69h (Ch 2) 6869h (Ch 3) Parameter Name Bit Slice R/W Reset Value DATALANE_FIFO_WR_ FLUSH 0:0 RW 0b Initiates a flush from the writer side on the FIFO. Active HIGH. 5:1 RW 4h Number or items that need to be written to FIFO before the read process starts. DATALANE_FIFO_CTRL_ REG DATALANE_FIFO_RD_ START_THRESH 4823h (Ch 0) 5423h (Ch 1) VIDEO_CTRL_OVERRIDE_ DISABLE_VIDEO_LANE REG 6023h (Ch 2) Description 5:4 RW 0h X0b = Lane n is enabled 11b = Lane n is enabled 01b = Lane n is disabled regardless of the presence of a valid signal 1:0 RW 0h X0b = Channel n Audio is enabled 11b = Channel n Audio is enabled 01b = Channel n Audio is disabled 6C23h (Ch 3) 4824h (Ch 0) 5424h (Ch 1) AUDIO_CTRL_OVERRIDE_ REG 6024h (Ch 2) DISABLE_AUDIO 6C24h (Ch 3) Manually specifies the audio sampling rate when AUDIO_SAMP_FREQ_MANUAL_ MODE = 1 AUDIO_SAMP_FREQ 2:1 RW 0h This mode only needs to be enabled if the audio sampling information is not present in the Stream ID packets. If the incoming signal is transmitted by a GV7700, the information will be present and this mode does not need to be enabled. 4825h (Ch 0) 5425h (Ch 1) 6025h (Ch 2) AUDIO_SAMP_FREQ_ OVERRIDE_REG 6C25h (Ch 3) AUDIO_SAMP_FREQ_ MANUAL_MODE 00b = 48kHz 01b = 44.1kHz 10b = 32kHz 11b = Reserved 0:0 RW 0b 1b = The audio sampling frequency will be manually specified according to AUDIO_SAMP_FREQ. 0b = The device will automatically detect the audio sampling frequency present within the Stream ID of the video signal. PCLK_INVERT 4829h (Ch 0) 5429h (Ch 1) 6029h (Ch 2) 3:3 0 CLOCKS_CFG_1_REG PCLK_SELECT 2:1 6C29h (Ch 3) GV7704 Final Data Sheet PDS-060376 RW www.semtech.com Rev.4 March 2016 RW 0 When HIGH, inverts the PCLK. In HD mode, the PCLK can be moved by 0°, 90°, 180°, or 270°. In 3G mode, the PCLK can be moved by 0° or 90°. 42 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name Parameter Name OUT_THREEG_HDB Bit Slice 4:4 R/W RW Reset Value 0 602Ch (Ch 2) When HIGH, indicates that the parallel output signal is 3G (Full HD). When LOW, indicates that the output signal is HD. 482Ch (Ch 0) 542Ch (Ch 1) Description GEN_VIDEO_CFG_0_ REG THREEG_HDB 2:2 RW 0 6C2Ch (Ch 3) When HIGH, indicates that the incoming signal is 3G. When LOW, indicates that the incoming signal is HD. When HIGH, indicates that the incoming signal is 270Mb/s. 1:1 RO 0b EXTRACT_STREAM_ID_ EXTRACT_STREAM_ID_ REG1 BYTE1 7:0 RO 0h Extract byte 1 information for the packet on DS1 (First UDW in the Stream ID packet) EXTRACT_STREAM_ID_ EXTRACT_STREAM_ID_ REG2 BYTE2 7:0 RO 0h Extract byte 2 information for the packet on DS1 (First UDW in the Stream ID packet) EXTRACT_STREAM_ID_ EXTRACT_STREAM_ID_ REG3 BYTE3 7:0 RO 0h Extract byte 3 information for the packet on DS1 (First UDW in the Stream ID packet) EXTRACT_STREAM_ID_ EXTRACT_STREAM_ID_ REG4 BYTE4 7:0 RO 0h Extract byte 4 information for the packet on DS1 (First UDW in the Stream ID packet) EXTRACT_STREAM_ID_ EXTRACT_STREAM_ID_ REG5 BYTE5 7:0 RO 0h Extract byte 5 information for the packet on DS1 (First UDW in the Stream ID packet) EXTRACT_STREAM_ID_ EXTRACT_STREAM_ID_ REG6 BYTE6 7:0 RO 0h Extract byte 6 information for the packet on DS1 (First UDW in the Stream ID packet) SD_HDB When LOW, indicates that the incoming signal is 1.485Gb/s. 4863h (Ch 0) 5463h (Ch 1) 6063h (Ch 2) 6C63h (Ch 3) 4864h (Ch 0) 5464h (Ch 1) 6064h (Ch 2) 6C64h (Ch 3) 4865h (Ch 0) 5465h (Ch 1) 6065h (Ch 2) 6C65h (Ch 3) 4866h (Ch 0) 5466h (Ch 1) 6066h (Ch 2) 6C66h (Ch 3) 4867h (Ch 0) 5467h (Ch 1) 6067h (Ch 2) 6C67h (Ch 3) 4868h (Ch 0) 5468h (Ch 1) 6068h (Ch 2) 6C68h (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 43 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name Parameter Name Bit Slice R/W Reset Value INS_ID_BYTE1_REG INS_ID_BYTE1 7:0 RWC 0h Identification code byte 1 INS_ID_BYTE2_REG INS_ID_BYTE2 7:0 RWC 0h Identification code byte 2 MUTE_2_3 3:3 RW 0h MUTE_0_1 2:2 RW 0h AUDIO_DID_9_8_REG AUDIO_DID_9_8 1:0 RW 0h Bits 8-9 of the audio packet DID to be extracted. AUDIO_DID_7_0_REG AUDIO_DID_7_0 7:0 RW 0h Bits 0-7 of the audio packet DID to be extracted. Description 487Dh (Ch 0) 547Dh (Ch 1) 607Dh (Ch 2) 6C7Dh (Ch 3) 487Eh (Ch 0) 547Eh (Ch 1) 607Eh (Ch 2) 6C7Eh (Ch 3) Audio Mute for channels 2 & 3. 488Dh (Ch 0) 548Dh (Ch 1) 608Dh (Ch 2) When HIGH, the device will set the CH1_AOUT_2_3 serial output to 0. AUD_EXT_CONFIG_REG Audio Mute for channels 0 & 1. 6C8Dh (Ch 3) When HIGH, the device will set the CH1_AOUT_0_1 serial output to 0. 488Eh (Ch 0) 548Eh (Ch 1) 608Eh (Ch 2) 6C8Eh (Ch 3) 488Fh (Ch 0) 548Fh (Ch 1) 608Fh (Ch 2) 6C8Fh (Ch 3) Audio Group detection status. 4892h (Ch 0) 5492h (Ch 1) 6092h (Ch 2) AUDIO_DETECT_0_REG AUDIO_GRP_DETECT 7:0 6C92h (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 RO 0h 10000000b = Group 8 DID detected 01000000b = Group 7 DID detected 00100000b = Group 6 DID detected 00010000b = Group 5 DID detected 00001000b = Group 4 DID detected 00000100b = Group 3 DID detected 00000010b = Group 2 DID detected 00000001b = Group 1 DID detected 44 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name Parameter Name Bit Slice R/W Reset Value 4893h (Ch 0) 5493h (Ch 1) 6093h (Ch 2) AUDIO_DETECT_1_REG AUDIO_DETECT_1 0:0 RO 0b When HIGH, indicates that an ancillary data packet having a DID matching audio_did has been detected in the video. 0h 10-bit DID that the device will seek and extract UDW’s from. ANC_PACKET_DID is considered a static signal. Bits [9:8] 0h 10-bit DID that the device will seek and extract UDW’s from. ANC_PACKET_DID is considered a static signal. Bits [7:0] 0b When HIGH, indicates that the packet the device has received contains more than 16 UDWs, which exceeds the maximum allowable amount. 0b Set HIGH when the device has finished extracting all the words from the desired packet type. Writing 1 to this bit clears the status. 6C93h (Ch 3) 48C6h (Ch 0) 54C6h (Ch 1) 60C6h (Ch 2) ANC_PACKET_DID_9_ 8_REG ANC_PACKET_DID_9_8 1:0 RW 6CC6h (Ch 3) 48C7h (Ch 0) 54C7h (Ch 1) 60C7h (Ch 2) ANC_PACKET_DID_7_ 0_REG ANC_PACKET_DID_7_0 7:0 RWC 6CC7h (Ch 3) ANC_PACKET_ INCOMPLETE 2:2 RO 48C8h (Ch 0) 54C8h (Ch 1) 60C8h (Ch 2) ANC_EXTRACT_STATUS_ REG ANC_EXTRACT_ UPDATE_TOGGLE 1:1 ROCW Description 6CC8h (Ch 3) 1b = Device is not currently extracting words from the desired DID packet. ANC_EXTRACT_IDLE 0:0 RO 0b 54C9h (Ch 1) ANC_PACKET_SDID_9_8_ ANC_PACKET_SDID_ REG 9_8 60C9h (Ch 2) 1:0 RO 0h Secondary Data Identification Word extracted from the ancillary data packet. Bits [9:8] 7:0 RO 0h Secondary Data Identification Word extracted from the ancillary data packet. Bits [7:0] 0b = Device is currently extracting words from the DID packet specified by ANS_PACKET_DID 48C9h (Ch 0) 6CC9h (Ch 3) 48CAh (Ch 0) 54CAh (Ch 1) ANC_PACKET_SDID_7_0_ ANC_PACKET_SDID_ REG 7_0 60CAh (Ch 2) 6CCAh (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 45 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name Parameter Name Bit Slice R/W Reset Value 48CBh (Ch 0) 54CBh (Ch 1) 60CBh (Ch 2) ANC_PACKET_DC_9_8_ REG ANC_PACKET_DC_9_ 8 1:0 RO 0h Data Word Count extracted from the ancillary data packet. Represents the number of User Data Words (UDW) in the ancillary data packet. Bits [9:8] 6CCBh (Ch 3) 48CCh (Ch 0) 54CCh (Ch 1) 60CCh (Ch 2) Description ANC_PACKET_DC_7_0_ REG ANC_PACKET_DC_7_ 0 7:0 RO 0h Data Word Count extracted from the ancillary data packet. Represents the number of User Data Words (UDW) in the ancillary data packet. Bits [7:0] ANC_PACKET_UDW0_ 9_8_REG ANC_PACKET_UDW0_ 9_8 1:0 RO 0h User Data Word 0 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW0_ 7_0_REG ANC_PACKET_UDW0_ 7_0 7:0 RO 0h User Data Word 0 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW1_ 9_8_REG ANC_PACKET_UDW1_ 9_8 1:0 RO 0h User Data Word 1 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW1_ 7_0_REG ANC_PACKET_UDW1_ 7_0 7:0 RO 0h User Data Word 1 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW2_ 9_8_REG ANC_PACKET_UDW2_ 9_8 1:0 RO 0h User Data Word 2 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW2_ 7_0_REG ANC_PACKET_UDW2_ 7_0 7:0 RO 0h User Data Word 2 extracted from the ancillary data packet. Bits [7:0] 6CCCh (Ch 3) 48CDh (Ch 0) 54CDh (Ch 1) 60CDh (Ch 2) 6CCDh (Ch 3) 48CEh (Ch 0) 54CEh (Ch 1) 60CEh (Ch 2) 6CCEh (Ch 3) 48CFh (Ch 0) 54CFh (Ch 1) 60CFh (Ch 2) 6CCFh (Ch 3) 48D0h (Ch 0) 54D0h (Ch 1) 60D0h (Ch 2) 6CD0h (Ch 3) 48D1h (Ch 0) 54D1h (Ch 1) 60D1h (Ch 2) 6CD1h (Ch 3) 48D2h (Ch 0) 54D2h (Ch 1) 60D2h (Ch 2) 6CD2h (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 46 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name Parameter Name Bit Slice R/W Reset Value ANC_PACKET_UDW3_ 9_8_REG ANC_PACKET_UDW3_ 9_8 1:0 RO 0h User Data Word 3 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW3_ 7_0_REG ANC_PACKET_UDW3_ 7_0 7:0 RO 0h User Data Word 3 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW4_ 9_8_REG ANC_PACKET_UDW4_ 9_8 1:0 RO 0h User Data Word 4 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW4_ 7_0_REG ANC_PACKET_UDW4_ 7_0 7:0 RO 0h User Data Word 4 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW5_ 9_8_REG ANC_PACKET_UDW5_ 9_8 1:0 RO 0h User Data Word 5 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW5_ 7_0_REG ANC_PACKET_UDW5_ 7_0 7:0 RO 0h User Data Word 5 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW6_ 9_8_REG ANC_PACKET_UDW6_ 9_8 1:0 RO 0h User Data Word 6 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW6_ 7_0_REG ANC_PACKET_UDW6_ 7_0 7:0 RO 0h User Data Word 6 extracted from the ancillary data packet. Bits [7:0] Description 48D3h (Ch 0) 54D3h (Ch 1) 60D3h (Ch 2) 6CD3h (Ch 3) 48D4h (Ch 0) 54D4h (Ch 1) 60D4h (Ch 2) 6CD4h (Ch 3) 48D5h (Ch 0) 54D5h (Ch 1) 60D5h (Ch 2) 6CD5h (Ch 3) 48D6h (Ch 0) 54D6h (Ch 1) 60D6h (Ch 2) 6CD6h (Ch 3) 48D7h (Ch 0) 54D7h (Ch 1) 60D7h (Ch 2) 6CD7h (Ch 3) 48D8h (Ch 0) 54D8h (Ch 1) 60D8h (Ch 2) 6CD8h (Ch 3) 48D9h (Ch 0) 54D9h (Ch 1) 60D9h (Ch 2) 6CD9h (Ch 3) 48DAh (Ch 0) 54DAh (Ch 1) 60DAh (Ch 2) 6CDAh (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 47 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Register Name Parameter Name Bit Slice R/W Reset Value ANC_PACKET_UDW7_ 9_8_REG ANC_PACKET_UDW7_ 9_8 1:0 RO 0h User Data Word 7 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW7_ 7_0_REG ANC_PACKET_UDW7_ 7_0 7:0 RO 0h User Data Word 7 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW8_ 9_8_REG ANC_PACKET_UDW8_ 9_8 1:0 RO 0h User Data Word 8 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW8_ 7_0_REG ANC_PACKET_UDW8_ 7_0 7:0 RO 0h User Data Word 8 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW9_ 9_8_REG ANC_PACKET_UDW9_ 9_8 1:0 RO 0h User Data Word 9 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW9_ 7_0_REG ANC_PACKET_UDW9_ 7_0 7:0 RO 0h User Data Word 9 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW10_ ANC_PACKET_UDW10_ 9_8_REG 9_8 1:0 RO 0h User Data Word 10 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW10_ ANC_PACKET_UDW10_ 7_0_REG 7_0 7:0 RO 0h User Data Word 10 extracted from the ancillary data packet. Bits [7:0] Description 48DBh (Ch 0) 54DBh (Ch 1) 60DBh (Ch 2) 6CDBh (Ch 3) 48DCh (Ch 0) 54DCh (Ch 1) 60DCh (Ch 2) 6CDCh (Ch 3) 48DDh (Ch 0) 54DDh (Ch 1) 60DDh (Ch 2) 6CDDh (Ch 3) 48DEh (Ch 0) 54DEh (Ch 1) 60DEh (Ch 2) 6CDEh (Ch 3) 48DFh (Ch 0) 54DFh (Ch 1) 60DFh (Ch 2) 6CDFh (Ch 3) 48E0h (Ch 0) 54E0h (Ch 1) 60E0h (Ch 2) 6CE0h (Ch 3) 48E1h (Ch 0) 54E1h (Ch 1) 60E1h (Ch 2) 6CE1h (Ch 3) 48E2h (Ch 0) 54E2h (Ch 1) 60E2h (Ch 2) 6CE2h (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 48 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Bit Slice R/W Reset Value ANC_PACKET_UDW11_ ANC_PACKET_UDW11_ 9_8_REG 9_8 1:0 RO 0h User Data Word 11 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW11_ ANC_PACKET_UDW11_ 7_0_REG 7_0 7:0 RO 0h User Data Word 11 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW12_ ANC_PACKET_UDW12_ 9_8_REG 9_8 1:0 RO 0h User Data Word 12 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW12_ ANC_PACKET_UDW12_ 7_0_REG 7_0 7:0 RO 0h User Data Word 12 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW13_ ANC_PACKET_UDW13_ 9_8_REG 9_8 1:0 RO 0h User Data Word 13 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW13_ ANC_PACKET_UDW13_ 7_0_REG 7_0 7:0 RO 0h User Data Word 13 extracted from the ancillary data packet. Bits [7:0] ANC_PACKET_UDW14_ ANC_PACKET_UDW14_ 9_8_REG 9_8 1:0 RO 0h User Data Word 14 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW14_ ANC_PACKET_UDW14_ 7_0_REG 7_0 7:0 RO 0h User Data Word 14 extracted from the ancillary data packet. Bits [7:0] Register Name Parameter Name Description 48E3h (Ch 0) 54E3h (Ch 1) 60E3h (Ch 2) 6CE3h (Ch 3) 48E4h (Ch 0) 54E4h (Ch 1) 60E4h (Ch 2) 6CE4h (Ch 3) 48E5h (Ch 0) 54E5h (Ch 1) 60E5h (Ch 2) 6CE5h (Ch 3) 48E6h (Ch 0) 54E6h (Ch 1) 60E6h (Ch 2) 6CE6h (Ch 3) 48E7h (Ch 0) 54E7h (Ch 1) 60E7h (Ch 2) 6CE7h (Ch 3) 48E8h (Ch 0) 54E8h (Ch 1) 60E8h (Ch 2) 6CE8h (Ch 3) 48E9h (Ch 0) 54E9h (Ch 1) 60E9h (Ch 2) 6CE9h (Ch 3) 48EAh (Ch 0) 54EAh (Ch 1) 60EAh (Ch 2) 6CEAh (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 49 of 56 Semtech Table 5-1: GV7704 Register Descriptions — Channel Controls (Continued) Address Bit Slice R/W Reset Value ANC_PACKET_UDW15_ ANC_PACKET_UDW15_ 9_8_REG 9_8 1:0 RO 0h User Data Word 15 extracted from the ancillary data packet. Bits [9:8] ANC_PACKET_UDW15_ ANC_PACKET_UDW15_ 7_0_REG 7_0 7:0 RO 0h User Data Word 15 extracted from the ancillary data packet. Bits [7:0] Register Name Parameter Name Description 48EBh (Ch 0) 54EBh (Ch 1) 60EBh (Ch 2) 6CEBh (Ch 3) 48ECh (Ch 0) 54ECh (Ch 1) 60ECh (Ch 2) 6CECh (Ch 3) CS Word extracted from the ancillary data packet. 48EDh (Ch 0) 54EDh (Ch 1) 60EDh (Ch 2) ANC_PACKET_CS_9_8_ REG ANC_PACKET_CS_9_ 8 1:0 RO 0h ANC_PACKET_CS_7_0_ REG ANC_PACKET_CS_7_ 0 7:0 RO 0h 6CEDh (Ch 3) Equal to the nine least significant bits of the sum of the nine least significant bits of the data identification (DID) word, the data block number (DBN)/ secondary data identification word (SDID), the data count (DC) word, and all user data words (UDW) in the packet. Bits [9:8] 48EEh (Ch 0) 54EEh (Ch 1) 60EEh (Ch 2) CS Word extracted from the ancillary data packet. Bits [7:0] 6CEEh (Ch 3) 48EFh (Ch 0) 54EFh (Ch 1) 60EFh (Ch 2) 1b = Device generates the BT656 10-bit YCbCr multiplexed video format OUTPUT_BLOCK_CFG_ REG BT656_ENABLE 0:0 RW 0b TX_WORD_CLK_ ENABLE_REG TX_WORD_CLK_ ENABLE 0:0 RW 0b Used in the procedure to enable SDO. See Section 4.3.2.1 for details 0b Parallel video output (PCLK, HOUT, VOUT, FOUT, DOUT[9:0]) drive strength select. 6CEFh (Ch 3) 0b = Device generates the default SMPTE 10-bit YCbCr multiplexed video format 48F4h (Ch 0) 54F4h (Ch 1) 60F4h (Ch 2) 6CF4h (Ch 3) 492Ch (Ch 0) 552Ch (Ch 1) 612Ch (Ch 2) PARALLEL_VIDEO_OUT _DRV_STRENGTH_SEL_ REG PARALLEL_VIDEO_ OUT_DRV_ STRENGTH_SEL 0:0 6D2Ch (Ch 3) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 RW 1b= high drive strength 0b = low drive strength 50 of 56 Semtech SYS_RST R18 10kΩ GND GND GND GND GND GND GND C25 1μF GND R19 GND 10kΩ GV7704 Final Data Sheet PDS-060376 Rev.4 March 2016 Figure 6-1: Typical Application Circuit (Part 1) GND 0Ω R20 DNP VCC1V8 R15 EXT_FW: High to load external firmware Low to load from internal firmware SYS_RST R14 100kΩ VCC1V8 K10 J10 J9 J6 J5 H10 H5 G5 G11 G10 F10 F5 E10 E9 E6 D10 N3 M2 M1 K3 J2 J1 G2 G1 E2 E1 D3 B2 B1 A3 D5 L3 K8 L1 C1 C2 K5 K9 D9 K4 D8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND EXT_FW GND GND RBIAS N/C N/C RSVD GND GND RESET GND U3-1 6.1 Typical Application Circuit 6. Application Information E7 E8 F9 G9 H9 J7 J8 B3 C3 E3 F3 G3 H3 J3 L2 M3 F6 F7 F8 G6 G7 G8 H6 H7 H8 E4 F4 G4 H4 J4 E5 D4 B5 A5 C4 C5 M5 L4 N5 L5 0Ω GND R21 C52 10nF C42 10nF C32 10nF C26 10nF R23 R17 C53 10nF C43 10nF C33 10nF C27 10nF GND 10kΩ 10kΩ C54 10nF C44 10nF C34 10nF C28 10nF SPI_CS_GV7704_1 SPI_SDIN_GV7704 SPI_CLK_GV7704 SPI_DOUT_GV7704_1 www.semtech.com VDD18_D_1 VDD18_D_2 VDD18_D_3 VDD18_D_4 VDD18_D_5 VDD18_D_6 VDD18_D_7 VDDA18_1 VDDA18_2 VDDA18_3 VDDA18_4 VDDA18_5 VDDA18_6 VDDA18_7 VDDA18_8 VDDA18_9 VDD12_D_1 GV7704 VDD12_D_2 VDD12_D_3 VDD12_D_4 VDD12_D_5 VDD12_D_6 VDD12_D_7 VDD12_D_8 VDD12_D_9 VDDA12_1 VDDA12_2 VDDA12_3 VDDA12_4 VDDA12_5 RSVD TRST TMS TCK TDI TDO CS SDIN SCLK SDOUT R16 4.7kΩ VCC1V8 C55 10nF C45 10nF C35 10nF C29 10nF C56 10nF C46 10nF C36 10nF C30 10nF C57 10nF C47 10nF C37 10nF C31 1μF VCC_A_1V2 SPI_CS_GV7704_1 SPI_SDIN_GV7704 SPI_CLK_GV7704 SPI_DOUT_GV7704_1 0Ω C49 10nF C39 10nF VCC1V2 C58 10nF C59 1μF VCC1V8 C48 10nF C38 10nF R25 C41 1μF C50 10nF C51 1μF VCC_A_1V8 C40 10nF VCC1V2 R2 0Ω VCC1V8 51 of 56 Semtech SDI INPUT0 UCBBJE20-1 C62 1μF N1 C61 1μF N2 CH0_DOUT9 CH0_DOUT8 CH0_DOUT7 CH0_DOUT6 CH0_DOUT5 CH0_DOUT4 CH0_DOUT3 CH0_DOUT2 CH0_DOUT1 CH0_DOUT0 CH0_SDIP CH0_SDIN R30 75Ω GV7704 N4 CH0_SDOP M4 C66 R33 75Ω CH0_PCLK CH0_FOUT CH0_VOUT CH0_HOUT CH0_WCLK CH0_ACLK CH0_AOUT1_2 CH0_AOUT3_4 CH0_SDON CH0_DOUT9 CH0_DOUT8 CH0_DOUT7 CH0_DOUT6 CH0_DOUT5 CH0_DOUT4 CH0_DOUT3 CH0_DOUT2 CH0_DOUT1 CH0_DOUT0 M11 L10 M10 N10 L9 M9 N9 L8 M8 N8 UCBBJE20-1 C68 4.7μF UCBBJE20-1 C71 1μF K1 C73 1μF K2 CH1_SDIP CH1_SDIN R40 75Ω H2 CH1_SDOP CH1_SDON 75Ω GND 1μF D2 CH2_SDIN F1 F2 C67 75Ω R3 CH1_DOUT9 CH1_DOUT8 CH1_DOUT7 CH1_DOUT6 CH1_DOUT5 CH1_DOUT4 CH1_DOUT3 CH1_DOUT2 CH1_DOUT1 CH1_DOUT0 CH1_DOUT9 CH1_DOUT8 CH1_DOUT7 CH1_DOUT6 CH1_DOUT5 CH1_DOUT4 CH1_DOUT3 CH1_DOUT2 CH1_DOUT1 CH1_DOUT0 H13 CH1_PCLK H12 CH1_FOUT H11 CH1_VOUT G12 CH1_HOUT K7 CH1_WCLK L7 CH1_ACLK CH1_AOUT1_2 M7 CH1_AOUT3_4 N7 C13 C12 B13 C11 CH2_PCLK F_CH2 V_CH2 H_CH2 I2S_WCLK_CH2 I2S_ACLK_CH2 I2S_D_A1/2_CH2 I2S_D_A3/4_CH2 UCBBJE20-1 SDI INPUT3 UCBBJE20-1 C72 1μF A1 C74 1μF A2 CH3_SDIP CH3_SDIN R42 75Ω CH3_DOUT9 CH3_DOUT8 CH3_DOUT7 CH3_DOUT6 CH3_DOUT5 CH3_DOUT4 CH3_DOUT3 CH3_DOUT2 CH3_DOUT1 CH3_DOUT0 CH3_DOUT9 CH3_DOUT8 CH3_DOUT7 CH3_DOUT6 CH3_DOUT5 CH3_DOUT4 CH3_DOUT3 CH3_DOUT2 CH3_DOUT1 CH3_DOUT0 C9 B9 C10 B10 A10 B11 A11 B12 A12 A13 GV7704 CH3_PCLK CH1_PCLK F_CH1 V_CH1 H_CH1 A4 I2S_WCLK_CH1 I2S_ACLK_CH1 I2S_D_A1/2_CH1 I2S_D_A3/4_CH1 B4 R43 75Ω 4.7μF C78 4.7μF J8 UCBBJE20-1 CH2_DOUT9 CH2_DOUT8 CH2_DOUT7 CH2_DOUT6 CH2_DOUT5 CH2_DOUT4 CH2_DOUT3 CH2_DOUT2 CH2_DOUT1 CH2_DOUT0 SDI INPUT2 loop-through GND C69 4.7μF J11 J12 J13 K11 K12 K13 L11 J12 L13 M13 CH2_PCLK CH2_FOUT CH2_VOUT CH2_HOUT D11 D12 D13 E11 E12 E13 F11 F12 F13 G13 A7 CH2_WCLK B7 CH2_ACLK C7 CH2_AOUT1_2 CH2_AOUT3_4 D7 CH2_SDOP CH2_SDON 4.7μF SDI INPUT1 loop-through C79 4.7μF C65 CH2_DOUT9 CH2_DOUT8 CH2_DOUT7 CH2_DOUT6 CH2_DOUT5 CH2_DOUT4 CH2_DOUT3 CH2_DOUT2 CH2_DOUT1 CH2_DOUT0 CH2_SDIP GV7704 C77 R44 4.7μF D1 I2S_WCLK_CH0 I2S_ACLK_CH0 I2S_D_A1/2_CH0 I2S_D_A3/4_CH0 K6 L6 M6 N6 GV7704 H1 1μF CH0_PCLK F_CH0 V_CH0 H_CH0 N11 N13 M12 N12 UCBBJE20-1 SDI INPUT1 C64 R32 75Ω SDI INPUT0 loop-through GND 4.7μF C76 SDI INPUT2 GND CH3_SDOP CH3_SDON A9 CH3_FOUT C8 B8 CH3_VOUT CH3_HOUT A8 A6 CH3_WCLK B6 CH3_ACLK CH3_AOUT1_2 C6 CH3_AOUT3_4 D6 CH3_PCLK F_CH3 V_CH3 H_CH3 I2S_WCLK_CH3 I2S_ACLK_CH3 I2S_D_A1/2_CH3 I2S_D_A3/4_CH3 SDI INPUT3 loop-through UCBBJE20-1 Figure 6-2: Typical Application Circuit (Part 2) Reserved for Power White/Orange Orange White/Green Blue White/Blue Green White/Brown Brown 1 2 3 4 5 6 7 8 1μF N1 CH0_SDIP 1μF N2 CH0_SDIN GV7704 Reserved for UCC RJ45 Figure 6-3: Alternative CATx Input Circuit GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 52 of 56 Semtech 7. Packaging Information 7.1 Package Dimensions BOTTOM VIEW TOP VIEW Øeee M Øddd M PIN A1 CORNER 1 2 3 C A1 CORNER C A B Øb (n X) 4 5 6 7 8 9 B 10 11 12 13 13 12 11 10 9 8 7 6 5 4 3 2 1 A A B B C D D E E eD C F G D F G D1 H H J J K K L L M M N N eE E A E1 aaa (4X) Symbol Common Dimensions Package: LBGA A 1.470 ± 0.100 Mold Thickness: M 0.700 Ref. Substrate Thickness: S 0.560 Ref. A1 0.160 ~ 0.260 SIDE VIEW 0.300 Ball Diameter: Stand Off: b 0.270 ~ 0.370 Package Edge Tolerance: aaa 0.050 Mold Flatness: bbb 0.100 Coplanarity: ddd 0.080 Ball Offset (Package): eee 0.150 Ball Offset (Ball): fff 0.050 Ball Width: Ball Count: Edge Ball Center to Center: X Y n 169 E1 D1 9.600 9.600 bbb C C 5. SEATING PLANE A Total Thickness: Ball Pitch: A1 11.000 11.000 0.800 0.800 M E D eE eD S X Y X Y Body Size: ddd C 3. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M – 1994. 2. SOLDER BALL POSITION DESIGNATION PER JESD 95–1, SPP–010. 3. THIS DIMENSION INCLUDES STAND-OFF HEIGHT, PACKAGE BODY THICKNESS AND LID HEIGHT, BUT DOES NOT INCLUDE ATTACHED FEATURES, E.G., EXTERNAL HEATSINK OR CHIP CAPACITORS. AN INTEGRAL HEATSLUG IS NOT CONSIDERED AN ATTACHED FEATURE. 4. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 5. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 6. ALL DIMENSIONS ARE IN MILLIMETERS. Figure 7-1: GV7704 Package Dimensions GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 53 of 56 Semtech 7.2 Recommended PCB Footprint 0.8 0.35 9.6 9.6 Note: All dimensions in millimeters Figure 7-2: GV7704 PCB Footprint 7.3 Marking Diagram Pin 1 ID GV7704 XXXXE3 YYWW XXXX - Last 4 digits of Assembly Lot. E3 - Pb-free & Green indicator YYWW - Date Code Figure 7-3: GV7704 Marking Diagram GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 54 of 56 Semtech 7.4 Solder Reflow Profile Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 7-4: Maximum Pb-free Solder Reflow Profile 7.5 Packaging Data Table 7-1: GV7704 Packaging Data Parameter Value Package Type/Dimensions/Pad Pitch 169 WB-BGA 11mm x 11mm, 0.8mm pitch Moisture Sensitivity Level (MSL) 3 Junction to Case Thermal Resistance, θj-c 12.1°C/W Junction to Ambient Thermal Resistance (zero airflow), θj-a 35.4°C/W Junction-to-Top of Package Characterization, θj-t 0.14°C/W Junction to Board Thermal Resistance, θj-b 25.7°C/W Pb-free and RoHS Compliant Yes 7.6 Ordering Information Table 7-2: GV7704 Ordering Information Part Package GV7704-IBE3 169-pin LBGA (176 pc/Tray) GV7704 Final Data Sheet PDS-060376 www.semtech.com Rev.4 March 2016 55 of 56 Semtech IMPORTANT NOTICE Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. 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Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose. All rights reserved. © Semtech 2016 Contact Information Semtech Corporation 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com GV7704 Final Data Sheet PDS-060376 Rev.4 March 2016 56 of 56 Semtech 56