ETC TW9920

Techwell, Inc.
TW9920 – Analog Video Decoder /
Encoder
Preliminary Data Sheet
Techwell Confidential. Information may change without notice.
Disclaimer
This document provides technical information for the user. Techwell, Inc. reserves the right to
modify the information in this document as necessary. The customer should make sure that they
have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that
may appear in this document. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third
parties and does not infringe upon or assist others to infringe upon such rights.
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TW9920
Techwell, Inc. ...............................................................................1
Features........................................................................................4
Functional Description...............................................................5
General description..................................................................6
Analog Front-end .....................................................................6
Video Source Selection........................................................6
Clamping and Automatic Gain Control ................................7
Analog to Digital Converter ..................................................7
Sync Processing ......................................................................7
Horizontal sync processing ..................................................7
Vertical sync processing ......................................................7
Color Decoding ........................................................................8
Y/C separation......................................................................8
Color demodulation ..............................................................8
Automatic Chroma Gain Control..........................................9
Low Color Detection and Removal......................................9
Automatic standard detection ..............................................9
Video Format support.........................................................10
Component Processing .........................................................10
Luminance Processing.......................................................10
Gamma...............................................................................10
Sharpness...........................................................................10
The Hue and Saturation.....................................................11
Color Transient Improvement ............................................11
Power Management ..............................................................11
Control Interface.....................................................................11
Down-scaling and Cropping...............................................11
TW9920 Down-Scaling ......................................................11
TW9920 Cropping ..............................................................12
VDELAY + VACTIVE < Total number of lines per field........13
Output Interface .....................................................................14
ITU-R BT.656 .....................................................................14
VIP (Video Interface Port) ..................................................14
Horizontal Down Scaling Output........................................15
Vertical Down Scaling Output ............................................16
Raw VBI data output ..........................................................16
VBI Data Processing..............................................................17
Raw VBI data output ..........................................................17
VBI Data Slicer ...................................................................17
Sliced VBI Data output format............................................18
Audio clock generation ..........................................................24
Analog Video Encoder...........................................................26
Timing Interface and Control .................................................29
Two Wire Serial Bus Interface...............................................30
Test Modes ............................................................................32
Filter Curves...........................................................................33
Decimation filter..................................................................33
Anti-alias filter .....................................................................33
Chroma Band Pass Filter Curves......................................34
Luma Notch Filter Curve for NTSC and PAL/SECAM......35
Chrominance Low-Pass Filter Curve.................................35
Horizontal Scaler Pre- Filter curves ...................................36
Vertical Interpolation Filter curves......................................36
Peaking Filter Curves.........................................................37
Control Register ........................................................................38
TW9920 Register SUMMARY...........................................38
0x00 – Product ID Code Register (ID)..............................41
0x01 – Chip Status Register I (STATUS1)........................41
0x02 – Input Format (INFORM).........................................42
0x03 – Output Format Control Register (OPFORM) ........43
0x04 – GAMMA and HSYNC Delay Control.....................43
0x05 – Output Control I ......................................................44
0x06 – Analog Control Register (ACNTL) .........................45
0x07 – Cropping Register, High (CROP_HI) ....................45
0x08 – Vertical Delay Register, Low (VDELAY_LO) ........46
0x09 – Vertical Active Register, Low (VACTIVE_LO).......46
0x0A – Horizontal Delay Register, Low (HDELAY_LO) ...46
0x0B – Horizontal Active Register, Low (HACTIVE_LO)..46
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0x0C – Control Register I (CNTRL1).................................47
0x0D – Vertical Scaling Register, Low (VSCALE_LO).....47
0x0E – Scaling Register, High (SCALE_HI) .....................47
0x0F – Horizontal Scaling Register, Low (HSCALE_LO).48
0x10 – BRIGHTNESS Control Register (BRIGHT) ..........48
0x11 – CONTRAST Control Register (CONTRAST) .......48
0x12 – SHARPNESS Control Register I (SHARPNESS) 48
0x13 – Chroma (U) Gain Register (SAT_U) .....................49
0x14 – Chroma (V) Gain Register (SAT_V)......................49
0x15 – Hue Control Register (HUE)..................................49
0x16 – Sharpness Control II (SHARP2)............................49
0x17 – Vertical Sharpness (VSHARP)..............................50
0x18 – Coring Control Register (CORING).......................50
0x19 – VBI Control Register (VBICNTL)...........................51
0x1A – Analog Control II....................................................52
0x1B – Output Control II ....................................................52
0x1C – Standard Selection (SDT) .....................................53
0x1D – Standard Recognition (SDTR)..............................54
0x1E – Component Video Format (CVFMT) ....................54
0x1F – Test Control Register (TEST)................................55
0x20 – Clamping Gain (CLMPG) ......................................56
0x21 – Individual AGC Gain (IAGC)..................................56
0x22 – AGC Gain (AGCGAIN) ..........................................56
0x23 – White Peak Threshold (PEAKWT)........................56
0x24– Clamp level (CLMPL)..............................................56
0x25– Sync Amplitude (SYNCT).......................................57
0x26 – Sync Miss Count Register (MISSCNT).................57
0x27 – Clamp Position Register (PCLAMP) .....................57
0x28 – Vertical Control I (VCNTL1)...................................58
0x29 – Vertical Control II (VCNTL2)..................................58
0x2A – Color Killer Level Control (CKILL).........................58
0x2B – Comb Filter Control (COMB).................................59
0x2C – Luma Delay and H Filter Control (LDLY)..............59
0x2D – Miscellaneous Control I (MISC1)..........................60
0x2E – LOOP Control Register (LOOP) ...........................60
0x2F – Miscellaneous Control II (MISC2) .........................61
0x30 – Macrovision Detection (MVSN) .............................62
0x31 – Chip STATUS II (STATUS2) ................................62
0x32 – H monitor (HFREF)................................................63
0x33 – CLAMP MODE (CLMD) ........................................63
0x34 – ID Detection Control (IDCNTL)..............................63
0x35 – Clamp Control I (CLCNTL1) ..................................64
0x40 – 0x48
AUDIO CLOCK....................................65
0x40 – Audio Clock Increment (ACKI) ..............................65
0x41 – Audio Clock Increment (ACKI) ..............................65
0x42 – Audio Clock Increment (ACKI) ..............................65
0x43 – Audio Clock Number (ACKN)................................65
0x44 – Audio Clock Number (ACKN)................................65
0x45 – Audio Clock Number (ACKN)................................65
0x46 – Serial Clock Divider (SDIV)....................................66
0x47 – Left/Right Clock Divider (LRDIV)...........................66
0x48 – Audio Clock Control (ACCNTL).............................66
0x4E – HBLEN...................................................................67
0x4F – WSS3 .....................................................................67
0x50 – FILLDATA ..............................................................67
0x51 – SDID.......................................................................67
0x52 – DID..........................................................................68
0x53 – WSS1 .....................................................................68
0x54 – WSS2 .....................................................................68
0x55 – VVBI .......................................................................69
0x56~6A LCTL6~LCTL26 .................................................69
0x6B – HSGEGIN ..............................................................70
0x6C – HSEND ..................................................................70
0x6D – OVSDLY................................................................70
0x6E – OVSEND................................................................70
0x6F – VBIDELAY .............................................................71
0x70 – ENCODER CONTROL1........................................71
0x71 – ENCODER CONTROL2........................................72
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0x72 – ENCODER CONTROL3........................................73
0x73 – ENCODER CONTROL4........................................73
0x74 – ENCODER CONTROL5........................................74
0x75 – ENCODER CONTROL6........................................74
0x76 – ENCODER & DAC Power Down...........................75
0x77 – DAC Control1 .........................................................76
0x78 – DAC Control12 .......................................................76
0x79 – DAC Control13 .......................................................77
0x7a – Encoder YDEL .......................................................77
0x7b – Encoder SYNC_L & BLK_L...................................78
0x7c – Encoder YBRT .......................................................78
0x7d – Encoder CBURST..................................................79
Pin Diagram ...............................................................................80
Pin Description .......................................................................81
Encoder ..............................................................................82
Power and Ground Pins.....................................................83
Parametric Information ............................................................84
AC/DC Electrical Parameters ................................................84
Clock Timing Diagram........................................................86
Mechanical Data ....................................................................87
Copyright Notice.....................................................................88
Disclaimer...............................................................................88
Life Support Policy .................................................................88
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TW9920
TW9920 – Analog Video Decoder / Encoder
Features
Video decoder
− NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N
combination), PAL (60), SECAM support with automatic
format detection
Video Encoder
− Software selectable analog inputs allows any of the
following combinations, e.g. 4 CVBS or ( 3 CVBS and 1
Y/C ).
− ITU-R 656 compatible video interface
− Two 9-bit ADCs and analog clamping circuit.
− Stable 27MHz crystal clock for subcarrier generation
− Fully programmable static gain or automatic gain control
− Five 10-bit Digital-to-Analog Converters at 27Mhz sample
rate for generating CVBS or Y/C and YCbCr
simultaneously
for the Y channel
− Support NTSC/PAL and its sub-standard format output
− Luminance and chrominance filter
− Programmable white peak control for the Y or CVBS
channel
Miscellaneous
− 4-H adaptive comb filter Y/C separation
− Two wire MPU serial bus interface
− PAL delay line for color phase error correction
− Power-down mode
− Image enhancement with 2D peaking and CTI.
− Field locked audio clock generation
− Digital sub-carrier PLL for accurate color decoding
− Typical power consumption 0.62W
− Digital Horizontal PLL for synchronization processing and
pixel sampling
− Single 27MHz crystal for all standards
− Advanced synchronization processing and sync detection
for handling non-standard and weak signal
− Programmable hue, brightness, saturation, contrast,
sharpness, Gamma control, and noise suppression
− Supports 24.54MHz and 29.5MHz crystal for high
resolution square pixel format decoding
− 3V tolerant I/O
− 2.5/3.3 V power supply
− VFBGA package
− Automatic color control and color killer
− Detection of level of copy protection according to
Macrovision standard
− Programmable output cropping
− ITU-R 601 or ITU-R 656 compatible YCbCr(4:2:2) output
format
− VBI slicer supporting industrial standard data services
− VBI data pass through, raw ADC data for Intercast™
Video scaler
− High quality horizontal filtered scaling with arbitrary scale
down ratio
− Phase accuracy better than 1/32 pixel
− Selectable anti-alias filter
− Vertical down scaling by line dropping
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TW9920
Functional Description
Y
Video Interface
V
Luma/Chroma
processor
Chroma
Demodulation
4H Comb Y/C
separation
9-bit
ADC
9-bit
ADC
AGC
U
VD(9:0)
HS
VS
CLKx2
FIELD
DVALID
MPOUT
Sync
Processor
27 Mhz
VD (19:10)
CLKX1
Line-lock
clock
Generator
MUX0
MUX1
MUX2
MUX3
MUX
CIN 1
MUX
CIN 0
Clock
Analog Video In
VBI Slicer
Figure 1: TW9920 Block Diagram
ASCLK
Audio
ALRCLK
AMCLK
AMXCLK
PDN
SCLK
SDAT
Y
Cb
Cr
2 Wire
Serial Bus
C LPF
C
DACs
Y LPF
Sync Insertion
PDCLK
PD[9:0]
Mod
Video
Interface
CVBS/Y
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General description
The TW9920 is a multi-standard video decoder and encoder chip that is designed for
multimedia applications. It uses the mixed-signal 2.5V CMOS technology to provide a lowpower integrated solution.
The video encoder is used to encoder digital YCbCr input into analog CVBS or S-video output.
With five built-in DACs, it can simultaneously support analog YCbCr output in addition to Svideo output for various applications. It can support both NTSC (60Hz) and PAL (50Hz) output.
A stable crystal generated 27MHz clock is used for all necessary sub-carrier generation. It
accepts ITU-R 656 compatible digital input externally.
The video decoder decodes the analog CVBS or S-video signals into digital YCbCr for output.
It consists of analog front-end with input source selection, variable gain amplifier and analogto-digital converters, Y/C separation circuit, multi-standard color decoder (PAL BGHI, PAL M,
PAL N, combination PAL N, NTSC M, NTSC 4.43 and SECAM) and synchronization circuitry.
The Y/C separation is done with highly adaptive 4H comb filter for reduced cross color and
cross luminance. The advanced synchronization processing circuitry can produce stable
pictures for non-standard signal as well as weak signal. A video scaler is provided to arbitrarily
scale down the output video. The output of the decoder is formatted to the ITU-R 656
compatible output. It includes various control circuits like brightness, contrast, saturation, and
dynamic aperture correction for best video quality.
A 2-wire serial MPU interface is used to simplify system integration. All the functions can be
controlled through this interface.
Analog Front-end
The analog front-end converts analog video signals to the required digital format. There are
two analog channels with clamping circuits and ADCs. The Y channel has 4-input multiplexer,
and a variable gain amplifier for automatic gain control (AGC). Its four inputs are identified as
MUX0, MUX1, MUX2, and MUX3. The C channel has a 2-input multiplexer. Its two inputs are
identified as Cin0 and Cin1. The C channel is internally clamped to the zero level of the bipolar
input source when enabled.
Video Source Selection
All analog signals should be AC-coupled to these inputs.
The Y channel analog multiplexer selects one of the four inputs MUX[0-3]. MUX[0-3] can be
connected to composite video inputs or the Y signal of an S-Video or component input. When
decoding a S-Video input, the Y signal should connect to one of the MUX inputs and the C
signal to Cin0 or Cin1.
Software selectable analog inputs allow several possible input combinations:
1. Up to four composite video inputs. 2. Three composites and one S-video input. 3. Two
composite and two S-Video inputs.
The input video signals in any certain channel maybe momentarily connected together through
the equivalent of a 200 ohm resistor during multiplexer switching. Therefore, the multiplexer
cannot be used for switching on a real-time pixel-by-pixel basis.
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Clamping and Automatic Gain Control
All two analog channels have built-in clamping circuit that restores the signal DC level. The Y
channel restores the back porch of the digitized video to a level of 60 or a programmable level.
The C channel restores the back porch of the digitized video to a level of 128. This operation is
automatic through internal feedback loop.
The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at
a desired level. A programmable white peak protection logic is included to prevent saturation in
the case of abnormal proportion between sync and white peak level.
Analog to Digital Converter
TW9920 contains two 9-bit pipelined ADCs that consume less power than conventional flash
ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite
input or the Y signal of the S-Video input. The second ADC digitizes the C signal when
decoding S-video signal.
Sync Processing
The sync processor of TW9920 detects horizontal synchronization and vertical synchronization
signals in the composite video or in the Y signal of an S-video or component signal. The
processor contains a digital phase-locked-loop and decision logic to achieve reliable sync
detection in stable signal as well as in unstable signals such as those from VCR fast forward or
backward.
Horizontal sync processing
The horizontal synchronization processing contains a sync separator, a phase-locked-loop
(PLL), and the related decision logic.
The horizontal sync detector detects the presence of a horizontal sync tip by examining lowpass filtered input samples whose level is lower than a threshold. After sufficient low levels are
detected, a horizontal sync is recognized. Additional logic is also used to avoid false detection
on glitches.
The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter
free image output. From there, the PLL also provides orthogonal sampling raster for the down
stream processor. The PLL has free running frequency that matches the standard raster
frequency. It also has wide lock-in range for tracking any non-standard video signal.
In case the horizontal sync is missing, a “free-wheel” mechanism keeps generating horizontal
sync signal until horizontal sync is detected again. This option can also be turned off for some
applications that determine video loss by detecting the existence of horizontal sync.
Vertical sync processing
The vertical sync separator detects the vertical synchronization pattern in the input video
signals. In addition, the actual sync determination is controlled by a detection window to
provide more reliable synchronization. It achieves the functionality of a PLL without the
complexity of a PLL. An option is available to provide faster responses for certain applications.
The field status is determined at vertical synchronization time. When the location of the
detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field
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start. Otherwise, it indicates an even field. The field logic can also be controlled to toggle
automatically while tracking the input.
Color Decoding
Y/C separation
The color-decoding block contains the luma/chroma separation for the composite video signal
and multi-standard color demodulation. For NTSC and PAL standard signals, the luma/chroma
separation can be done either by comb filter or notch/band-pass filter combination. For
SECAM standard signals, only notch/band-pass filter is available. The default selection for
NTSC/PAL is comb filter. The characteristics of the band-pass filter are shown in the filter
curve section.
In the case of comb filter, the TW9920 separates luma (Y) and chroma © of a NTSC
composite video signal using a proprietary 2H adaptive comb filter. The filter uses a two-line
buffer. Adaptive logic combines the upper-comb and the lower-comb results based on the
signal changes among the previous, current and next lines. This technique leads to good Y/C
separation with small cross luma and cross color at both horizontal and vertical edges. Due to
the 90-degree phase difference on adjacent lines of a PAL chroma signal, the 4H adaptive
comb filter is used to give better performance.
Due to the line buffer used in the comb filter, there is always two lines processing delay in the
output images no matter what standard or filter option is chosen.
If notch/band-pass filter is selected, the characteristics of the filters are shown in the filter curve
section.
Color demodulation
The color demodulation for NTSC and PAL standard is done by first quadrature mixing the
chroma signal to the base band. The mixing frequency is equal to the sub-carrier frequency for
NTSC and PAL. After the mixing, a low-pass filter is used to remove carrier signal and yield
chroma components. The low-pass filter characteristic can be selected for optimized transient
color performance. For the PAL system, the PAL ID or the burst phase switching is identified to
aid the PAL color demodulation.
For SECAM, the mixing frequency is 4.286Mhz. After the mixer and low-pass filter, it yields the
FM modulated chroma. The SECAM demodulation process therefore consists of low-pass
filter, FM demodulator and de-emphasis filter. The filter characteristics are shown in filter curve
section. During the FM demodulation, the chroma carrier frequency is identified and used to
control the SECAM color demodulation.
The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis
PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any
sub-standard of NTSC and PAL to be demodulated easily with single crystal frequency.
During S-video operation, the Y signal bypasses the comb filter. The C signal connects directly
to the color demodulator. During component input operation, all the chroma processing and
color demodulator blocks are bypassed.
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Automatic Chroma Gain Control
The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by
high-frequency loss in video signal. In the NTSC/PAL standard, the color reference signal is
the burst on the back porch. This color-burst amplitude is calculated and compared to standard
amplitude. The chroma (Cx) signals are then increased or decreased in amplitude accordingly.
The range of ACC control is –6db to +26db.
This function is always enabled to provide consistent image quality under different signal
conditions.
Low Color Detection and Removal
For low color amplitude signals, black and white video, or very noisy signals, the color will be
“killed”. The color killer uses the burst amplitude measurement to switch-off the color when the
measured burst amplitude falls below a programmed threshold. The threshold has
programmed hysteresis to prevent oscillation of the color killer function. The color killer function
can be disabled by programming a low threshold value.
Automatic standard detection
The TW9920 has build-in automatic standard discrimination circuitry. The circuit uses burstphase, burst-frequency and frame rate to identify NTSC, PAL or SECAM color signals. The
standards that can be identified are NTSC (M), NTSC (4.43), PAL (B, D, G, H, I), PAL (M),
PAL (N), PAL (60) and SECAM (M). Each standard can be included or excluded in the
standard recognition process by software control. The identified standard is indicated by the
Standard Selection (SDT) register. Automatic standard detection can be overridden by
software controlled standard selection.
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Video Format support
TW9920 supports all common video formats as shown in Table 1. The video decoder needs to
be programmed appropriately for each of the composite video input formats.
Table 1. Video Input Formats Supported by the TW9920
Format
Lines
Fields
Fsc
Country
NTSC-M
525
60
3.579545 MHz
U.S., many others
NTSC-Japan (1)
525
60
3.579545 MHz
Japan
PAL-B, G, N
625
50
4.433619 MHz
Many
PAL-D
625
50
4.433619 MHz
China
PAL-H
625
50
4.433619 MHz
Belgium
PAL-I
625
50
4.433619 MHz
Great Britain, others
PAL-M
525
60
3.575612 MHz
Brazil
PAL-CN
625
50
3.582056 MHz
Argentina
SECAM
625
50
4.406MHz
4.250MHz
PAL-60
525
60
4.433619 MHz
China
NTSC (4.43)
525
60
4.433619 MHz
Transcoding
France, Eastern Europe,
Middle East, Russia
Notes: (1). NTSC-Japan has 0 IRE setup.
Component Processing
Luminance Processing
The TW9920 adjusts brightness by adding a programmable value (in register BRIGHTNESS)
to the Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of
the Y signal.
The TW9920 video decoder also performs a coring function. It can force all values below a
certain level, programmed in the Coring Control Register, to zero. This is useful because
human eyes are sensitive to variations in nearly black images. Changing levels near black to
true black, can make the image appears clearer.
Gamma
Y Gamma function is provided to compensate for different display types. Four preprogrammed Gamma levels can be selected through registers.
Sharpness
The TW9920 also provides a sharpness control function through control registers. It provides
the control in 16 steps up to +12db. The center frequency of the enhancement curve is around
3.5Mhz. It also provides a high frequency coring function to minimize the amplification of high
frequency noise. The coring level is adjustable through the Coring Control register. The same
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function can also be used to soften the images. This can be used to provide noise reduction on
noisy signal.
To further enhance the image, a programmable vertical peaking function is provided for up to
+6db of enhancement. A programmable coring level can be adjusted to minimize the noise
enhancement.
The Hue and Saturation
When decoding NTSC signals, TW9920 can adjust the hue of the chroma signal. The hue is
defined as a phase shift of the subcarrier with respect to the burst. This phase shift can be
programmed through a control register.
The color saturation can be adjusted by changing the gain of Cb and Cr signals for all NTSC,
PAL and SECAM formats. The Cb and Cr gain can be adjusted independently for flexibility.
Color Transient Improvement
A programmable Color Transient Improvement circuit is provided to enhance the color
bandwidth. Low level noise enhancement can be suppressed by a programmable coring logic.
Overshoot and undershoot are also removed by special circuit to prevent false color
generation at the color edge.
Power Management
The TW9920 can be put into power-down mode in which its clock is turned off for most of the
circuits. The Y and C path can be separately powered down.
Control Interface
The TW9920 registers are accessed via 2-WIRE SERIAL MPU interface. It operates as a
slave device. Serial clock and data lines, SCL and SDA, transfer data from the bus master at a
rate of 400 Kbits/s. The TW9920 has one serial interface address select pins to program up to
two unique serial addresses TW9920. This allows as many as two TW9920 to share the same
serial bus. Reset signals are also available to reset the control registers to their default values.
Down-scaling and Cropping
The TW9920 provides two methods to reduce the amount of output video pixel data,
downscaling and cropping. The downscaling provides full video image at lower resolution.
Cropping provides only a portion of the video image output. All these mechanisms can be
controlled independently to yield maximum flexibility in the output stream.
TW9920 Down-Scaling
The TW9920 can independently reduce the output video image size in both horizontal and
vertical directions using arbitrary scaling ratios up to 1/16 in each direction. The horizontal
scaling employs a dynamic 6-tap 32-phase interpolation filter for luma and a 2-tap 8-phase
interpolation filter for chroma because of the limited bandwidth of the chroma data. The vertical
scaling uses the simple line dropping method. It is recommended to choose integer vertical
scaling ratio for best result.
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Downscaling is achieved by programming the horizontal scaling ratio register (HSCALE) and
vertical scaling ratio register (VSCALE). When outputting unscaled video, the TW9920 will
output CCIR601 compatible 720 pixels per line or any number of pixels per line as specified by
the HACTIVE register. The standard output for Square Pixel mode is 640 pixels for 60 Hz
system and 768 pixels for 50 Hz systems. If the number of output pixels required is smaller
than 720 in CCIR601 compatible mode or the number specified by the HACTIVE register. The
12-bit HSCALE register, which is the concatenation of two 8-bit registers SCALE_HI and
HSCALE_LO, is used to reduce the output pixels to the desired number.
Following is an example using pixel ratio to determine the horizontal scaling ratio. These
equations should be used to determine the scaling ratio to be written into the 12-bit HSCALE
register assuming HACTIVE is programmed with 720 active pixels per line:
NTSC:
HSCALE = [720/Npixel_desired] * 256
PAL:
HSCALE = [(720/Npixel_desired)] * 256
Where:
Npixel_desired is the nominal number of pixel per line.
For example, to output a CCIR601 compatible NTSC stream at SIF resolution, the HSCALE value
can be found as:
HSCALE = [(720/320)] * 256 = 576 = 0x0240
However, to output a SQ compatible NTSC stream at SIF resolution, the HSCALE value should be
found as:
HSCALE = [(640/320)] * 256 = 512 = 0x200
In this case, with total resolution of 768 per line, the HACTIVE should have a value of 640.
The vertical scaling determines the number of vertical lines output by the TW9920. The vertical
scaling register (VSCALE) is a 12-bit register, which is the concatenation of a 4-bit register
SCALE_HI and an 8-bit register VSCALE_LO. The maximum scaling ratio is 16:1. Following
equations should be used to determine the scaling ratio to be written into the 12-bit VSCALE
register assuming VACTIVE is programmed with 240 or 288 active lines per field.
60Hz system:
VSCALE = [240/ Nline_desired] * 256
50Hz system:
VSCALE = [288/ Nline_desired] * 256
Where: Nline_desired is the number of active lines output per field.
The scaling ratios for some popular formats are listed in Table 3.
TW9920 Cropping
Cropping allows only subsection of a video image to be output. The VACTIVE signal can be
programmed to indicate the number of active lines to be displayed in a video field, and the
HACTIVE signal can be programmed to indicate the number of active pixels to be displayed in
a video line. The start of the field or frame in the vertical direction is indicated by the leading
edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge
of the HSYNC. The start of the active lines from vertical sync edge is indicated by the VDELAY
register. The start of the active pixels from the horizontal edge is indicated by the HDELAY
register. The sizes and location of the active video are determined by HDELAY, HACTIVE,
VDELAY, and VACTIVE registers. These registers are 8-bit wide, the lower 8-bits is,
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respectively, in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2bit shares the same register CROP_HI.
The Horizontal delay register (HDELAY) determines the number of pixels delay between the
leading edge of HSYNC and the leading edge of the HACTIVE. Note that this value is
referenced to the unscaled pixel number. The Horizontal active register (HACTIVE)
determines the number of active pixels to be output or scaled after the delay from the sync
edge is met. This value is also referenced to the unscaled pixel number. Therefore, if the
scaling ratio is changed, the active video region used for scaling remain unchanged as set by
the HACTIVE register, but the valid pixels output are equal or reduced due to down scaling. In
order for the cropping to work properly, the following equation should be satisfied.
HDELAY + HACTIVE < Total number of pixels per line.
For NTSC output at 13.5 MHz pixel rate, the total number of pixels is 858. The HDELAY
should be set to 106 and HACTIVE set to 720. For PAL output at 13.5 MHz rate, the total
number of pixels is 864. The HDELAY should be set to 108 and HACTIVE set to 720.
The Vertical delay register (VDELAY) determines the number of lines delay between the
leading edge of the VSYNC and the start of the active video lines. It indicates number of lines
to skip at the start of a frame before asserting the VACTIVE signal. This value is referenced to
the incoming scan lines before the vertical scaling. The number of scan lines is 525 for the
60Hz systems and 625 for the 50Hz systems. The Vertical active register (VACTIVE)
determines the number of lines to be used in the vertical scaling. Therefore, the number of
scan lines output is equal or less than the value set in this register depending on the vertical
scaling ratio. In order for the vertical cropping to work properly, the following equation should
be observed.
VDELAY + VACTIVE < Total number of lines per field
Table 3 shows some popular video formats and its recommended register settings. The
CCIR601 format refers to the sampling rate of 13.5 MHz. The SQ format for 60 Hz system
refers to the sampling rate of 12.27 MHz, and the SQ format for 50 Hz system refers to the use
of sampling rate of 14.75 MHz.
Scaling Ratio
Format
1:1
NTSC SQ
NTSC CCIR601
PAL SQ
PAL CCIR601
NTSC SQ
NTSC CCIR601
PAL SQ
PAL CCIR601
NTSC SQ
NTSC CCIR601
PAL SQ
PAL CCIR601
2:1 (CIF)
4:1 (QCIF)
Total
Resolution
Output
Resolution
HSCALE
values
VSCALE
(frame)
780x525
858x525
944x625
864x625
390x262
429x262
472x312
432x312
195x131
214x131
236x156
216x156
640x480
720x480
768x576
720x576
320x240
360x240
384x288
360x288
160x120
180x120
192x144
180x144
0x0100
0x0100
0x0100
0x0100
0x0200
0x0200
0x0200
0x0200
0x0400
0x0400
0x0400
0x0400
0x0100
0x0100
0x0100
0x0100
0x0200
0x0200
0x0200
0x0200
0x0400
0x0400
0x0400
0x0400
Table 3. HSCALE and VSCALE value for some popular video formats.
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Output Interface
ITU-R BT.656
ITU-R BT.656 defines strict EAV/SAV Code, video data output timing, H blanking timing, and V
Blanking timing. In this mode, VD[19:12] pins are effective and VCLK pin should be used for data
clock signal. MSB bit of forth byte in EAV/SAV code must be “1” in ITU-R BT.656 standard. For
that reason, VIPCFG Register bit must be set to “1”.
ITU-R BT.656 SAV and EAV code sequence
VD19
VD18
VD17
VD16
1
1
1
1
First byte
0
0
0
0
Second byte
0
0
0
0
Third byte
*C
F
V
H
Forth byte
H = 0 - SAV, 1 – EAV
VD15
1
0
0
V XOR H
VD14
1
0
0
F XOR H
V = 1 – blanking, 0 – elsewhere
VD13
1
0
0
F XOR V
VD12
1
0
0
F XOR V XOR H
F = 0 – field 1, 1 – field 2
*C is set by VIPCFG register bit.
For complete ITU-R BT.656 standard,following registers are required.
ITU-R BT.656 Register set up.
Register
525 line system
625 line system
1
1
MODE
0
0
LEN
0x012
0x018
VDELAY
0X0F4
0x120
VACTIVE
0x2D0
0x2D0
HACTIVE
1
1
HA_EN
1
1
VIPCFG
1
0
NTSC656
ITU-R BT.656 for 525-line system has 244 video active lines in odd field and 243 vide active lines
in even field. NTSC656 register bit controls this video active line length.
VIP (Video Interface Port)
Video port in VIP standard is the upgraded standard that has more functions in addition to ITU-R
BT.656. Invalid data is set to 0x00 during the period from SAV to EAV if CTL656 register is set to
“1” for this VIP application. In case of Vertical down Scaling mode, invalid line does NOT have
EAV/SAV code by default setting. This mode is most popular in current VIP application. TW9920
also supports all line EAV/SAV output modes optionally. In this case, VSCTL register should be set
to “1”. All data will be 0x00 invalid data from SAV to EAV on invalid line in this mode. Starting
position of vertical active output video line is programmable by VDELAY register. The number of
active video lines is also programmable by VACTIVE register.
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Horizontal Down Scaling Output
TW9920 generates Horizontal down scaling output data. Figure 9 shows 8 bit mode Horizontal
Down Scaling output timing and Figure 10 shows 16 bit mode Horizontal Down Scaling output
timing. As shown Figure 9 and Figure 10, Horizontal Down Scaled data are generated by
continuous data stream. The trailing edge of DVALID signal changes with the trailing edge of
HACTIVE signal. Data value from the leading edge of HACTIVE to the leading edge of DVALID is
programmable by CNTL656 register. If CNTL656 is set to “1”, all Y and CbCr data will be 0x00. If
CNTL656 is set to “0”, all Y data will be 0x10 and all CbCr data will be 0x80. VIP application
normally uses 0x00 data as invalid data. Figure9 and Figure 10 show 360 active pixels output
timing after horizontal downscaling.
VCLK
HACTIVE x 2 VCLK
HACTIVE
360x2 VCLK
DVALID
VD[15:8]
0x00
Cb0
Y0
Cr0
Y1
...
Cb2
Cb358
Y358
Cr358
Y359
Figure 9. 8 bit m ode Horizontal Dow n Scaling O utput
VCLK
HACTIVE VCLK
HACTIVE
360 VCLK
DVALID
VD[15:8]
0x00
Y0
Y1
...
Y358
Y359
VD[7:0]
0x00
Cb0
Cr0
...
Cb358
Cr358
Figure 10. 16 bit m ode Horizontal Dow n Scaling Output
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Vertical Down Scaling Output
TW9920 generates Vertical Down Scaling output data. Figure 11 shows its timing. As shown on
Figure 11, HACTIVE is NOT generated on invalid line as default (VSCTL is “0”). If VSCTL is set to
“1”, HACTIVE is generated on every lines during VACTIVE active period. DVALID is not generated
on invalid lines in each setting. Invalid lines for Vertical down scaling are generated during
VACTIVE active period. If MODE bit is set to “1” for VIP mode, EAV/SAV codes are not generated
on those lines without HACTIVE signal. All CbCr data will be 80H and all Y data will be 10H the
same as H-blanking data in ITU-R BT.656 data stream.
HSYNC
HACTIVE
DVALID
VACTIVE
LVALID
(OPTION)
Figure 11. Vertical Dow n Scaling Output
Raw VBI data output
TW9920 supports raw VBI data output. Raw VBI data output has the same vertical line delay
timing as video output. Horizontal output timing is also programmable by VBIDELAY register. Raw
VBI data is generated during HACTIVE active period (from SAV to EAV) as Video data output.
Total pixel number of raw VBI data per line is twice as many as HACTIVE register value. If VBI EN
register is set to “1”, all vertical blanking output while VACTIVE is inactive will be raw VBI data
output. If VVBI registers are set to more than “1”, the VVBI number lines from top video active lines
will also be raw VBI data output lines.
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VBI Data Processing
Raw VBI data output
TW9920 supports raw VBI data output. Raw VBI data output has the same vertical line delay
timing as video output. Horizontal output timing is also programmable by VBIDELAY register.
Raw VBI data is generated during HACTIVE active period (from SAV to EAV) as Video data
output. Total pixel number of raw VBI data per line is twice as many as HACTIVE register
value. If VBI EN register is set to “1”, all vertical blanking output while VACTIVE is inactive will
be raw VBI data output. If VVBI registers are set to more than “1”, the VVBI number lines from
top video active lines will also be raw VBI data output lines.
VBI Data Slicer
The following VBI standards are supported by VBI Data slicer. The VBI Data slicing is
controlled by the registers LCTL6 to LCTL26. Registers LCTL6 to LCTL26 are controlling the
slicing process itself. LCTL6 to LCTL26 defines the Data Type to be decoded. The Data Type
can be specified on a line by line basis for line6 to line26 and for even and odd field depending
on the detected TV system standard. The setting for LCTL26 is valid for the rest of the
corresponding field. Normally no text data 0H (video data) should be selected to render the
VBI Data slicer inactive during active video. LCTRL26 is useful for Full-Field Teletext mode in
the case of NABTS.
NABTS is 525 Teletext-C. Japan’s MOJI is 525 Teletext-D. Didon Antiope is 625 Teletext-A.
VBI Data slicer supports up to Physical layer, Link layer in ITU-R BT.653-2. Japan’s EIAJ
CPR-1204 shown as 525 WSS has the same physical layer protocol as that of CGMS.
The sliced VBI data is embedded in the ITU-R BT.656 output stream, using the intervals
between the End of Active Video (EAV) and the Start of Active Vide(SAV) codes of each line
and formatted according to ITU-R BT.1364 Ancillary data packet Type 2.
Table 4. VBI Standard.
STANDARD TYPE
625 Teletext-B
525 Teletext-B
625 Teletext-C
525 Teletext-C
625 Teletext-D
525 Teletext-D
625 CC
525 CC
625 WSS
525 WSS(CGMS)
625 VITC
525 VITC
Gemstar 2x
Gemstar 1x
VPS
625 Teletext-A
TECHWELL, INC.
TV Systems
(lines/freq)
625/50
525/60
625/50
525/60
625/50
525/60
625/50
525/60
626/50
525/60
625/50
525/60
525/60
525/60
625/50
625/50
Bit Rate
(Mbits/s)
6.9375
5.727272
5.734375
5.727272
5.6427875
5.727272
0.500
0.503
5
0.447443
1.8125
1.7898
1.007
0.503
5
6.203125
17
Modulation
Data Type
NRZ
NRZ
NRZ
NRZ
NRZ
NRZ
NRZ
NRZ
Bi-phase
NRZ
NRZ
NRZ
NRZ
NRZ
Bi-phase
NRZ
1H
1H
2H
2H
3H
3H
4H
4H
5H
5H
6H
6H
7H
8H
9H
AH
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Sliced VBI Data output format
After 4 bytes of EAV code, sliced VBI ANC data packets are generated by following format.
Byte1 to Byte4N+7 data stream is formatted according to ITU-R BT.1364 ANC data packet
type2. BC data byte is optional and not included in ANC data packet type 2 BC data byte is
inserted after ANC data packet type2.
Table 5. Sliced VBI ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
4N+6
4N+7
4N+8
1.
D7
MSB
0
1
1
NEP
NEP
NEP
OP
OP
NCS6
OP
D6
D5
0
1
1
EP
EP
EP
FID
LN2
0
1
1
0
SDID5
DC5
LN8
LN1
CS6
0
D4
D3
D2
0
0
0
1
1
1
1
1
1
DID4
DID3
DID2
SDID4
SDID3
SDID2
DC4
DC3
DC2
LN7
LN6
LN5
LN0
DT3
DT2
Sliced VBI Data byte 1
Sliced VBI Data byte 2
Sliced VBI Data byte 3
Sliced VBI Data byte 4
Sliced VBI Data byte 5
.
.
Sliced VBI Data byte last or FILLDATA
CS5
CS4
CS3
CS2
BC5
BC4
BC3
BC2
D1
0
1
1
DID1
SDID1
DC1
LN4
DT1
D0
LSB
0
1
1
DID0
SDID0
DC0
LN3
DT0
CS1
BC1
CS0
BC0
DESCRIPTION
Ancillary data flag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
Sliced VBI Data No.1. UDW3
Sliced VBI Data No.2. UDW4
Sliced VBI Data No.3 UDW5
Sliced VBI Data No.4. UDW6
Sliced VBI Data No.5. UDW7
Sliced VBI Data Last or FILLDATA. UDW 4N
CS
BC
EP is Even Parity of bits 5 to 0 in same 1 byte.
2.
NEP is inverted EP in same 1 byte.
3.
{DID4,DID3,DID2,DID1,DID0} is DID register value.
4.
{SDID5,SDID4,SDID3,SDID2,SDID1,SDID0} is SDID register value.
5.
{DC5,DC4,DC3,DC2,DC1,DC0} is the number of DOWRD data length from UDW1 to UDW4N.On this table,
{DC5,DC4,DC3,DC2,DC1,DC0} is N(decimal).
6.
OP is Odd Parity of bits 6 to 0 in same 1 byte.
7.
FID=0: odd field ; FID=1: even field.
8.
{LN8,LN7,LN6,LN5,LN4,LN3,LN2,LN1,LN0} is the line number of current sliced VBI data.
9.
{DT3,DT2,DT1,DT0} is the Data Type shown on Table
10.
NCS6 is inverted CS6.
11.
{CS6,CS5,CS4,CS3,CS2,CS1,CS0} is the checksum value calculated from DID to UDW4N.
12.
UDW1 to UDW4N are the User data words(UDW) shown on ITU-R BT.1364 ANC data packet type 2.
13.
[BC5,BC4,BC3,BC2,BC1,BC0] is the number of valid bytes from UDW1 to UDW4N.
14.
FILLDATA is FILLDATA register value. FILLDATA is inserted after last valid bytes to make 4N number byte stream sometimes.
TECHWELL, INC.
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Following shows various type of ANC data packet to be outpu
Table 6. Closed Captioning ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
12
D7
MSB
0
1
1
NEP
NEP
0
OP
OP
D6
D5
0
1
1
EP
EP
1
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
NCS6
0
CS6
0
CS5
0
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
0
LN7
LN6
LN0
0
st
1 Character byte
nd
2 Character byte
CS4
CS3
0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
1
0
1
1
DID1
SDID1
0
LN4
0
D0
LSB
0
1
1
DID0
SDID0
1
LN3
0
CS2
1
CS1
0
CS0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
1
0
1
1
DID1
SDID1
1
LN4
0
D0
LSB
0
1
1
DID0
SDID0
0
LN3
1
CS2
1
CS1
1
CS0
0
DESCRIPTION
Ancillary data flag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
CS
BC
Table 7. CGMS ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D7
MSB
0
1
1
NEP
NEP
0
OP
OP
D6
D5
0
1
1
EP
EP
1
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
NCS6
1
CS6
0
CS5
0
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
0
LN7
LN6
LN0
0
WSS[7:0]
WSS[15:8]
{0H,WSS[19:16]}
CRCERRORCODE
FILLDATA
FILLDATA
CS4
CS3
0
0
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW6
UDW7
UDW8
CS
BC
1.CRCERRORCODE is optional byte. 41H means “this wss data has CRC Error”. 80H means no CRC error.
Table 8. 625 line Wide Screen signaling ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
12
13
D7
MSB
0
1
1
NEP
NEP
0
OP
OP
D6
D5
0
1
1
EP
EP
1
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
NCS6
0
CS6
0
CS5
0
TECHWELL, INC.
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
0
LN7
LN6
LN0
0
WSS[7:0]
{00b,WSS[13:8]
CS4
CS3
0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
1
0
1
1
DID1
SDID1
0
LN4
0
D0
LSB
0
1
1
DID0
SDID0
1
LN3
1
CS2
1
CS1
0
CS0
0
19
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
CS
BC
REV. D
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TW9920
Table 9. 625 Teletext-A ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
.
.
46
47
48
49
50
51
52
D7
MSB
0
1
1
NEP
NEP
0
OP
OP
NCS6
0
D6
D5
0
1
1
EP
EP
1
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
CS6
0
CS5
1
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
1
LN7
LN6
LN0
1
FRAME CDDE
BYTE4
BYTE5
.
.
BYTE40
HAMM84ERROR
FILLDATA
FILLDATA
FILLDATA
CS4
CS3
0
1
D2
D1
0
1
1
DID2
SDID2
0
LN5
0
0
1
1
DID1
SDID1
1
LN4
1
CS2
0
CS1
0
D0
LSB
0
1
1
DID0
SDID0
1
LN3
0
CS0
1
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW40
UDW41
UDW42
UDW43
UDW44
CS
BC
1.FRAME CODE is E7H if it’s received correctly.
2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
Table 10. 625 Teletext-B ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
.
.
50
51
52
53
54
55
56
D7
MSB
0
1
1
NEP
NEP
1
OP
OP
NCS6
1
D6
D5
0
1
1
EP
EP
0
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
CS6
0
CS5
1
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
1
LN7
LN6
LN0
0
FRAME CDDE
BYTE4
BYTE5
.
.
BYTE44
BYTE45
HAMM84ERROR
FILLDATA
FILLDATA
CS4
CS3
0
1
D2
D1
0
1
1
DID2
SDID2
1
LN5
0
0
1
1
DID1
SDID1
0
LN4
0
CS2
1
CS1
1
D0
LSB
0
1
1
DID0
SDID0
0
LN3
1
CS0
0
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW44
UDW45
UDW46
UDW47
UDW48
CS
BC
1.FRAME CODE is 27H if it’s received correctly.
2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
TECHWELL, INC.
20
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TW9920
Table 11. 525 Teletext-B ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
.
.
30
31
32
33
34
35
36
D7
MSB
0
1
1
NEP
NEP
1
OP
OP
NCS6
1
D6
D5
0
1
1
EP
EP
0
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
CS6
0
CS5
1
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
1
LN7
LN6
LN0
0
FRAME CDDE
BYTE4
BYTE5
.
.
BYTE36
BYTE37
HAMM84ERROR
FILLDATA
FILLDATA
CS4
CS3
0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
0
0
1
1
DID1
SDID1
1
LN4
0
CS2
1
CS1
1
D0
LSB
0
1
1
DID0
SDID0
0
LN3
1
CS0
0
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW36
UDW37
UDW38
UDW39
UDW40
CS
BC
1.FRAME CODE is 27H if it’s received correctly.
2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
Table 12. 625 Teletext-C and 525 Teletext-C ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
.
.
42
43
44
45
46
47
48
D7
MSB
0
1
1
NEP
NEP
1
OP
OP
NCS6
0
D6
D5
0
1
1
EP
EP
0
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
CS6
0
CS5
1
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
1
LN7
LN6
LN0
0
FRAME CDDE
BYTE4
BYTE5
.
.
BYTE36
HAMM84ERROR
FILLDATA
FILLDATA
FILLDATA
CS4
CS3
0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
0
0
1
1
DID1
SDID1
1
LN4
1
CS2
1
CS1
0
D0
LSB
0
1
1
DID0
SDID0
0
LN3
0
CS0
1
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW36
UDW37
UDW38
UDW39
UDW40
CS
BC
1.FRAME CODE is E7H if it’s received correctly.
2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
TECHWELL, INC.
21
REV. D
08/29/2005
TW9920
Table 13. 625 Teletext-D and 525 Teletext-D ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
.
.
42
43
44
45
46
47
48
D7
MSB
0
1
1
NEP
NEP
1
OP
OP
NCS6
0
D6
D5
0
1
1
EP
EP
0
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
CS6
0
CS5
1
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
1
LN7
LN6
LN0
0
FRAME CDDE
BYTE4
BYTE5
.
.
BYTE36
BYTE37
FILLDATA
FILLDATA
FILLDATA
CS4
CS3
0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
0
0
1
1
DID1
SDID1
1
LN4
1
CS2
1
D0
LSB
0
1
1
DID0
SDID0
0
LN3
1
CS1
0
CS0
1
D1
D0
LSB
0
1
1
DID0
SDID0
1
LN3
1
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW36
UDW37
UDW38
UDW39
UDW40
CS
BC
1.FRAME CODE is A7H if it’s received correctly.
Table 14. Line16 VPS ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
.
.
22
23
24
25
26
27
28
D7
MSB
0
1
1
NEP
NEP
1
OP
OP
NCS6
1
D6
D5
0
1
1
EP
EP
0
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
CS6
0
CS5
0
D4
D3
D2
0
0
0
1
1
1
1
1
1
DID4
DID3
DID2
SDID4
SDID3
SDID2
0
0
1
LN7
LN6
LN5
LN0
1
0
START CDDE1(51H)
START CODE2(99H)
BYTE3
.
.
BYTE14
BYTE15
BI-PHASEERROR
FILLDATA
FILLDATA
CS4
CS3
CS2
1
0
0
0
1
1
DID1
SDID1
0
LN4
0
CS1
1
CS0
0
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW16
UDW17
UDW18
UDW19
UDW20
CS
BC
1.START CODE1 is the first byte of Start Code by 5Mbps slicing.
2.START CODE2 is the second byte of Start Code by 5Mbps slicing.
3.BYTE3~BYTE15 are data bytes by 5/2 Mbps Bi-phase slicing.
4.BI-PHASEEROOR is Bi-phase coding error detection.80H means No error.41H means Bi-phase coding error is detected.
TECHWELL, INC.
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REV. D
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TW9920
Table 15. VITC ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D7
MSB
0
1
1
NEP
NEP
1
OP
OP
D6
D5
0
1
1
EP
EP
0
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
NCS6
1
CS6
0
CS5
0
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
0
LN7
LN6
LN0
0
Bit[9:2]
Bit[19:12]
Bit[29:22]
.Bit[39:32]
.Bit[49:42]
Bit[59:52]
Bit[69:62]
Bit[79:72]
Bit[89:82]
CRCERROR
CS4
CS3
0
1
D2
D1
0
1
1
DID2
SDID2
0
LN5
1
0
1
1
DID1
SDID1
1
LN4
1
D0
LSB
0
1
1
DID0
SDID0
1
LN3
0
CS2
1
CS1
0
CS0
0
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW6
UDW7
UDW8
UDW9
UDW10
UDW11
UDW12
CS
BC
1.CRCERROR is CRC Error information.41H means CRC Error is deteced.80H means no CRC error.
Table 16. Gemstar 1X ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
12
D7
MSB
0
1
1
NEP
NEP
0
OP
OP
D6
D5
0
1
1
EP
EP
1
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
NCS6
0
CS6
0
CS5
0
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
0
LN7
LN6
LN0
1
st
1 Character byte
2 nd Character byte
CS4
CS3
0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
0
0
1
1
DID1
SDID1
0
LN4
0
D0
LSB
0
1
1
DID0
SDID0
1
LN3
0
CS2
1
CS1
0
CS0
0
D2
D1
0
1
1
DID2
SDID2
0
LN5
1
0
1
1
DID1
SDID1
1
LN4
1
D0
LSB
0
1
1
DID0
SDID0
0
LN3
1
CS2
0
CS1
0
CS0
0
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
CS
BC
Table 17. Gemstar 2X ANC data packet
BYTE
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D7
MSB
0
1
1
NEP
NEP
0
OP
OP
D6
D5
0
1
1
EP
EP
1
FID
LN2
0
1
1
0
SDID5
0
LN8
LN1
NCS6
0
CS6
0
CS5
0
D4
D3
0
0
1
1
1
1
DID4
DID3
SDID4
SDID3
0
0
LN7
LN6
LN0
0
FRAMECODE1
FRAMECODE2
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
CS4
CS3
0
1
DESCRIPTION
Ancillary dataflag
DID
SDID
DC
IDI1. UDW1
IDI2. UDW 2
UDW3
UDW4
UDW5
UDW6
UDW7
UDW8
CS
BC
1.FRAMCODE1 is B9H if Frame Code is correctly received.
2.FRAMCODE2 is 05H if Frame Code is correctly received.
TECHWELL, INC.
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TW9920
Audio clock generation
(Register 40 to 48)
TW9920 has built-in field locked audio clock generator for use in video capture applications.
The circuitry will generate the same predefined number of audio sample clocks per field to
ensure synchronous playback of video and audio after digital recording or compression. The
audio clock is digitally synthesized from the crystal clock input with reference to the incoming
video.
The master audio clock frequency is programmable through ACKN and ACKI register based
following two equations.
ACKN = round ( F audio / F field ), it gives the Audio master Clock Per Field.
ACKI = round ( F audio / F crystal * 2^23 ), it gives the Audio master Clock Nominal Increment.
Following table provides setting example of some common used audio frequency assuming
crystal frequency of 27MHz.
AMCLK(Mhz)
FIELD[Hz]
ACKN dec
ACKN hex
ACKI dec
ACKI hex
12.288
50
245760
3-C0-00
3817749
3A-41-15
12.288
59.94
205005
3-20-CD
3817749
3A-41-15
11.2896
50
225792
3-72-00
3507556
35-85-65
11.2896
59.94
188348
2-DF-BC
3507556
35-85-65
8.192
50
163840
2-80-00
2545166
26-D6-0E
8.192
59.94
136670
2-15-DE
2545166
26-D6-0E
2.048
50
40960
A0-00
636291
9-B5-83
2.048
59.94
34168
85-78
636291
9-B5-83
256 x 48 KHz
256 x 44.1KHz
256 x 32 KHz
256 x 8 KHz
Two further divided down clocks are available on pin ASCLK and pin ALRCLK. These two
clocks are derived from AMXCLK input based on following two equations. The frequency of
these two slower digital clocks can be controlled by registers SDIV and LRDIV as shown.
TECHWELL, INC.
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08/29/2005
TW9920
f amxclk
f asclk =
(SDIV+1) * 2
f asclk
f alrclk =
LRDIV * 2
Some other Audio Clock related control functions are explained here.
ACPL
Audio PLL control
0 – PLL loop closed
1 – PLL loop open
SRPH
ASCLK phase control
0 – Invert AMXCLK, ASCLK transition is triggered by falling edge of AMXCLK
1 – Normal AMXCLK, ASCLK transition is triggered by rising edge of AMXCLK
LRPH
ALRCLK phase control
0 – Invert ASCLK, ALRCLK transition is triggered by falling edge of ASCLK
1 – Normal ASCLK, ALRCLK transition is triggered by rising edge of ASCLK
APG, APZ
TECHWELL, INC.
Audio PLL dynamic control
25
REV. D
08/29/2005
TW9920
Analog Video Encoder
The TW9920 supports analog video output using built-in video encoder which generates
composite or S-video and YCbCr with five10 bits DACs. The incoming digital video are
adjusted for gain and offset according to NTSC or PAL standard. Both the luminance and
chrominance are band-limited and interpolated to 27MHz sampling rate for digital to analog
conversion. The NTSC output can be selected to include a 7.5IRE pedestal. The TW9920 also
provides internal test color bar generation.
Output Standard Selection
The TW9920 supports various video standard outputs via SYS5060 (1x70) and FSC, PHALT,
PED (1x70) registers as described in the following table.
Table 18. Supporting analog video standards
Line/Fv
(Hz)
Fh (KHz)
Fsc (MHz)
SYS5060
FSC
PHALT
525/59.94
15.734
3.579545
0
0
0
NTSC-4.43
525/59.94
15.734
4.43361875
0
1
0
1
NTSC-N
625/50
15.625
3.579545
1
0
0
0
625/50
15.625
4.43361875
1
1
1
PAL-M
525/59.94
15.734
3.57561149
0
2
1
0
PAL-NC
625/50
15.625
3.58205625
1
3
1
0
PAL-60
525/59.94
15.734
4.43361875
0
1
1
0
Format
NTSC-M
NTSC-J
PAL-BDGHI
PAL-N
PED
1
0
0
1
If ALTRST (1x70) register is set to “1”, phase alternation can be reset every 8 field so that
phase alternation keeps same phase every 8 field.
TECHWELL, INC.
26
REV. D
08/29/2005
TW9920
Luminance Filter
The luminance signal keeps flat up to 6MHz as shown in the following Fig 12.
0
-5
-10
)
B
d(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
-15
-20
-25
-30
-35
-40
-45
0
2
4
6
8
Frequency (Hertz)
10
12
6
x 10
Fig 12. Characteristics of luminance filter
Chrominance Filter
The band of chrominance signal can be selected as shown in the following Fig 13.
0
-5
)
B
d(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
-10
-15
-20
-25
0
0.5
1
1.5
Frequency (Hertz)
2
2.5
3
6
x 10
Fig 13. Characteristics of chrominance Filter
TECHWELL, INC.
27
REV. D
08/29/2005
TW9920
Digital-to-Analog Converter
Digital video data from video encoder is converted to analog video signal by DAC (Digital to
Analog Converter). Analog video signal format can be selected for composite or Y out via
DAC_OUT (1x75) register. Each DAC can be disabled independently to save power by
DAC_PD 0,1,2,3,4 (1x76) register.
A simple reconstruction filter is required externally to reject noise as shown in Fig 14.
L
VDOUT
L
1uH
RCA JACK
L
2.7uH
0.68uH
R
C
C
C
75
470pF
330pF
56pF
Fig 14. Example of reconstruction filter
TECHWELL, INC.
28
REV. D
08/29/2005
TW9920
Timing Interface and Control
The TW9920 can be operated in slave mode. In master mode, TW9920 receives all of timing
information from ITU-R 656 video input data in slave mode.
The polarity of horizontal, vertical sync and field flag can be controlled by HSPOL, VSPOL and
FLDPOL (1x71) register respectively for slave mode. The TW9920 can detect field polarity
from vertical sync and horizontal sync via ENC_FLD (1x71) register or can detect vertical sync
from field flag via ENC_VS (1x71) register.
The TW9920 extracts the timing information from input video data streams. To adjust these
timing, TW9920 has ENC_HSDEL (1x73), ENC_VSDEL and ENC_VSOFF (1x72) register
which control only the related signal timing regardless of digital video input data. The detailed
timing diagram is illustrated in following FIG 15.
L IN E _ O S
E ven E nd
L in e N u m b e r
524
O d d S ta rt
V B I F u ll In te rv a l
E N C _ L IN K
525
1
2
3
4
5
6
7
8
9
10
11
1217
18
19
20
A n a lo g O u t p u t
V (656 )
F (656 )
H (65 6)
V S E N C + O S E N C (O d d )
VSENC
FLD EN C
HSENC
P IX E L _ O S
A n a lo g O u t p u t
A c tiv e D a ta / L in e
H (65 6)
HSENC
HSENC
L IN E _ O S
O dd End
E v e n S ta rt
V B I F u ll In te rv a l
E N C _ L IN K
L in e N u m b e r
262
263
264
265
266
267
268
269
270
271
272
273
274281
282
283
284
285
286
A n a lo g O u t p u t
V (656)
F (656)
H (65 6)
V S E N C + O S E N C (E ve n)
VSENC
FLD EN C
HSENC
Fig 15. Horizontal and vertical timing control
TECHWELL, INC.
29
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08/29/2005
TW9920
Two Wire Serial Bus Interface
Start Condition
Stop Condition
SDA
SCL
Figure 16. Definition of the serial bus interface bus start and stop
Device ID (1-7)
R/W
Index (1-8)
SDAT
SCLK
Start
Condition
Ack
Ack
Device ID (1-7)
Re-start
Condition
Data (1-8)
R/W
Stop
Nack Condition
Ack
Figure 17. One complete register read sequence via the serial bus interface
Device ID (1-7)
Index (1-8)
R/W
Data (1-8)
SDAT
SCLK
Ack
Start
Condition
Ack
Ack
Stop
Condition
Figure 18. One complete register write sequence via the serial bus interface
TECHWELL, INC.
30
REV. D
08/29/2005
TW9920
The two wire serial bus interface is used to allow an external micro-controller to write control
data to, and read control or other information from the TW9920 registers. SCLK is the serial
clock and SDAT is the data line. Both lines are pulled high by resistors connected to VDD. ICs
communicate on the bus by pulling SCLK and SDAT low through open drain outputs. In
normal operation the master generates all clock pulses, but control of the SDAT line alternates
back and forth between the master and the slave. For both read and write, each byte is
transferred MSB first, and the data bit is valid whenever SCLK is high.
The TW9920 is operated as a bus slave device. It can be programmed to respond to one of
two 7-bit slave device addresses by tying the SIAD (Serial Interface Address) pin ether to VDD
or VSS (See Table 19). If the SIAD pin is tied to VDD, then the least significant bit of the 7-bit
address is a “1”. If the SIAD pin is tied to VSS then the least significant bit of the 7-bit address
is a “0”. The most significant 6-bits are fixed. The 7-bit address field is concatenated with the
read/write control bit to form the first byte transferred during a new transfer. If the read/write
control bit is high the next byte will be read from the slave device. If it is low the next byte will
be a write to the slave. When a bus master (the host microprocessor) drives SDA from high to
low, while SCL is high, this is defined to be a start condition (See Figure 16.). All slaves on the
bus listen to determine when a start condition has been asserted.
After a start condition, all slave devices listen for the their device addresses. The host then
sends a byte consisting of the 7-bit slave device ID and the R/W bit. This is shown in Figure 8.
(For the TW9920, the next byte is normally the index to the TW9920 registers and is a write to
the TW9920 therefore the first R/W bit is normally low.)
After transmitting the device address and the R/W bit, the master must release the SDAT line
while holding SCLK low, and wait for an acknowledgement from the slave. If the address
matches the device address of a slave, the slave will respond by driving the SDAT line low to
acknowledge the condition. The master will then continue with the next 8-bit transfer. If no
device on the bus responds, the master transmits a stop condition and ends the cycle. Notice
that a successful transfer always includes nine clock pulses.
To write to the internal register of theTW9920, the master sends another 8-bits of data, the
TW9920 loads this to the register pointed by the internal index register. The TW9920 will
acknowledge the 8-bit data transfer and automatically increment the index in preparation for
the next data. The master can do multiple writes to the TW9920 if they are in ascending
sequential order. After each 8-bit transfer the TW9920 will acknowledge the receipt of the 8bits with an acknowledge pulse. To end all transfers to the TW9920 the host will issue a stop
condition.
Serial Bus Interface 7-bit Slave Address
1
0
0
0
1
0
SIAD0
Read/Write
bit
1=Read
0=Write
Table 19 TW9920 serial bus interface 7-bit slave address and read write bit
A TW9920 read cycle has two phases. The first phase is a write to the internal index register.
The second phase is the read from the data register. (See figure 17). The host initiates the first
phase by sending the start condition. It then sends the slave device ID together with a 0 in the
R/W bit position. The index is then sent followed by either a stop condition or a second start
condition. The second phase starts with the second start condition. The master then resends
the same slave device ID with a 1 in the R/W bit position to indicate a read. The slave will
transfer the contents of the desired register. The master remains in control of the clock. After
transferring eight bits, the slave releases and the master takes control of the SDAT line and
TECHWELL, INC.
31
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08/29/2005
TW9920
acknowledges the receipt of data to the slave. To terminate the last transfer the master will
issue a negative acknowledge (SDAT is left high during a clock pulse) and issue a stop
condition.
Test Modes
The input pin TMODE combining with RESET# provide different test modes selection. If this
pin is low at the rising edge of the RESET# pin and remaining low afterwards, TW9920 is in
the normal operating mode. Other test modes can be obtained as shown in Table 20.
Table 20. Test mode selection and description
Test mode
TMODE TMODE
before
after
RESET# RESET#
rising
rising
edge
edge
Description
Normal
0
0
Normal operation mode.
Pin tri-state
0
1
In this mode, all pin output drivers are tri-stated. Pin
leakage current parameters can be measured.
Outputs high
1
0
In this mode, all pin output drivers are forced to the high
output state. Pin output high voltage, VOH and IOH, can
be measured.
Outputs low
1
1
In this mode, all pin output drivers are forced to the low
output state. Pin output low voltage, VOL and IOL, can be
measured.
TECHWELL, INC.
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TW9920
Filter Curves
Decimation filter
0
-5
-10
)
B
d
(
e
s
n
o
p
s
e
R
e
d
u
ti
n
g
a
M
-15
-20
-25
-30
-35
-40
-45
-50
0
2
4
6
8
Frequency (Hertz)
10
12
6
x 10
Anti-alias filter
5
0
-5
-10
)
B
d(
ni
a
G
-15
-20
-25
-30
-35
-40
0
TECHWELL, INC.
2
4
6
8
10
12
Frequency (Hertz)
33
14
16
18
20
REV. D
08/29/2005
TW9920
Chroma Band Pass Filter Curves
0
-5
-10
)
B
d
(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
-15
PAL/SECAM
-20
NTSC
-25
-30
-35
-40
-45
-50
0
TECHWELL, INC.
1
2
3
4
5
Frequency (Hertz)
34
6
7
8
9
6
x 10
REV. D
08/29/2005
TW9920
Luma Notch Filter Curve for NTSC and PAL/SECAM
0
-10
-20
)
B
d
(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
PAL/SECAM
-30
NTSC
-40
-50
-60
-70
-80
0
1
2
3
4
5
Frequency (Hertz)
6
7
8
9
6
x 10
Chrominance Low-Pass Filter Curve
0
-5
-10
)
B
d
(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
High
-15
-20
Low
-25
Med
-30
-35
-40
-45
-50
0
TECHWELL, INC.
0.5
1
1.5
2
2.5
3
Frequency (Hertz)
35
3.5
4
4.5
5
6
x 10
REV. D
08/29/2005
TW9920
Horizontal Scaler Pre- Filter curves
0
-5
)
B
d
(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
HFLT[1:0]=1
-10
HFLT[1:0]=2
-15
-20
HFLT[1:0]=3
-25
-30
-35
-40
0
0.05
0.1
0.15
0.2
0.25
0.3
Fsig/Fsample
0.35
0.4
0.45
0.5
Vertical Interpolation Filter curves
0
-5
)
B
d
(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
-10
-15
-20
-25
-30
0
TECHWELL, INC.
0.05
0.1
0.15
0.2
0.25
0.3
Fv / Line Rate
36
0.35
0.4
0.45
0.5
REV. D
08/29/2005
TW9920
Peaking Filter Curves
NTSC
16
14
12
)
B
d(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
10
8
6
4
2
0
0
1
2
3
4
Frequency (Hertz)
5
6
7
6
x 10
PAL
16
14
12
)
B
d
(
e
s
n
o
p
s
e
R
e
d
ut
i
n
g
a
M
10
8
6
4
2
0
0
TECHWELL, INC.
1
2
3
4
5
Frequency (Hertz)
37
6
7
8
9
6
x 10
REV. D
08/29/2005
TW9920
Control Register
TW9920 Register SUMMARY
Index
(HEX)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
7
6
5
VDLOSS
HLOCK
SLOCK
YSEL2
FC27
MODE
LEN
4
3
2
FIELD
VLOCK
1
ID
REV
IFSEL
LLCMODE
GMEN
MONO
DET50
CSEL
SEL
YSEL
AINC
VSCTL
OEN
CKHY
TRI_SEL
HSDLY
VSP
VSSL
SRESET
0
IREF
HSP
VREF
VDELAY_HI
AGC_EN
HSSL
CLKPDN
VACTIVE_HI
Y_PDN
C_PDN
HDELAY_HI
-
HACTIVE_HI
VDELAY_LO
VACTIVE_LO
HDELAY_LO
HACTIVE_LO
PBW
DEM
PALSW
SET7
COMB
HCOMP
YCOMB
PDLY
VSCALE_LO
VSCALE_HI
HSCALE_HI
HSCALE_LO
BRIGHTNESS
CONTRAST
SCURVE
VSF
CTI
SHARPNESS
SAT_U
SAT_V
HUE
-
-
SHCOR
-
CTCOR
VBI_EN
LLCTEST
CCOR
VBI_BYT
VBI_FRAM
HA_EN
CTL656
PLL_PDN
-
-
YFLEN
CK2S
CK1S
DTSTUS
START
-
TECHWELL, INC.
VSHP
VCOR
PALCN
YSV
CFLEN
FLP
STDNOW
PAL60
CIF
RTSEL
ATREG
PALM
NTSC4
CVSTD
STANDARD
SECAM
CVFMT
TEST
38
CSV
FLSL
PALB
NTSC
Reset
(hex)
3A
00
40
04
00
00
00
02
12
F0
0F
D0
CC
00
11
00
00
5C
51
80
80
00
53
80
44
58
00
50
07
7F
08
00
REV. D
08/29/2005
TW9920
Index
(HEX)
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
4E
4F
50
7
6
5
4
3
2
CLPEND
1
0
CLPST
NMGAIN
WPGAIN
Agcgain8
AGCGAIN[7:0]
PEAKWT
CLMPLD
CLMPL
SYNCTD
SYNCT
MISSCNT
HSWIN
PCLAMP
VLCKI
VLCKO
VMODE
DETV
BSHT
CKILMAX
CKLM
VTL
YDLY
-
EVCNT
PALC
HPM
NKILL
VINT
CKILMIN
HTL
-
AFLD
VSHT
SDET
HFLT
TBC_EN
ACCT
PKILL
SKILL
BYPASS
SYOUT
SPM
CBAL
FCS
HADV
CBW
LCS
CCS
BST
sf
pf
ff
kf
CSBAD
MCVSN
CSTRIPE
CTYPE
VCR
WKAIR
WKAIR1
VSTD
NINTL
WSSDET
EDSDET
CCDET
HFREF
FRM
YNR
CLMD
IDX
CTEST
PSP
NSEN / SSEN / PSEN / WKTH
YCLEN
CCLEN
VCLEN
GTEST
VLPF
CKLY
CKLC
Reset
(hex)
50
22
F0
F8
BC
B8
44
38
00
00
78
44
30
14
A5
E0
00
00
x
05
1A
00
ACKI[7:0]
ACKI[15:8]
-
ACKI[21:16]
ACKN[7:0]
ACKN[15:8]
ACKN[17:16]
-
SDIV
-
TECHWELL, INC.
LRDIV
APZ
APG
-
ACPL
HBLEN
WSS[19:14]
FILLDATA
39
SRPH
LRPH
64
85
35
BC
DF
02
01
20
60
8A
X
A0
REV. D
08/29/2005
TW9920
Index
(HEX)
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
7
6
5
NODAEN
SYRM
ANCEN
YCBCR42
2
CRCERR
WSSFLD
HA656
EAVSWAP
4
3
2
1
0
Reset
(hex)
22
31
SDID
VIPCFG
DID
X
X
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
2C
60
00
20
24
WSS[13:8]
WSS[7:0]
HAMM84
NTSC656
VVBI
LCTL6
LCTL7
LCTL8
LCTL9
LCTL10
LCTL11
LCTL12
LCTL13
LCTL14
LCTL15
LCTL16
LCTL17
LCTL18
LCTL19
LCTL20
LCTL21
LCTL22
LCTL23
LCTL24
LCTL25
LCTL26
HSBEGIN
HSEND
OVSDLY
HSPIN
OFDLY
PDNSVBI
HASYNC
SYS5060
INTERLACE
VSMODE
OVSEND
VBIDELAY
Encoder
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
ENC_IN_ORDER
FSC
ENC_VS
ENC_FLD
-
PHALT
ALTRST
PED
HSPOL
VSPOL
FLDPOL
ENC_CK
ENC_VSOFF
ENC_VSDEL
ENC_HSDEL
ENC_YBW
ENC_CBW
CKILL
DAC_OUT
DBL
ENC_LOOP
ENC_BAR
ENC_PD
DAC_PD0
DAC_PD1
DAC_IREF0
-
DAC_PD2
DAC_IREF3
-
NONSTA
-
-
FRUN
DAC_IREF4
ENC_YDEL
ENC_SYNC_L
ENC_BLK_L
ENC_YBRT
-
TECHWELL, INC.
-
DAC_PD3
DAC_IREF1
DAC_IREF2
-
ENC_TCSEL
TEST_MODE
-
ENC_CBURST_L
40
DAC_PD4
40
20
10
45
F0
30
00
FF
FF
0F
0F
25
00
00
REV. D
08/29/2005
TW9920
0x00 – Product ID Code Register (ID)
Bit
Function
R/W
Description
Reset
7-3
ID
R
The TW9920 Product ID code is 00111.
7
2-0
Revision
R
The revision number.
2
0x01 – Chip Status Register I (STATUS1)
Bit
7
Function
VDLOSS
R/W
Description
Reset
R
1 = Video not present. (sync is not detected in number of
consecutive line periods specified by Misscnt register)
0
0 = Video detected.
6
HLOCK
R
1 = Horizontal sync PLL is locked to the incoming video source.
0
0 = Horizontal sync PLL is not locked.
5
SLOCK
R
1 = Sub-carrier PLL is locked to the incoming video source.
0
0 = Sub-carrier PLL is not locked.
4
FIELD
R
0 = Odd field is being decoded.
0
1 = Even field is being decoded.
3
VLOCK
R
1 = Vertical logic is locked to the incoming video source.
0
0 = Vertical logic is not locked.
2
1
MONO
R
Reserved
0
1 = No color burst signal detected.
0
0 = Color burst signal detected.
0
DET50
R
0 = 60Hz source detected
0
1 = 50Hz source detected
The actual vertical scanning frequency depends on the current
standard invoked.
TECHWELL, INC.
41
REV. D
08/29/2005
TW9920
0x02 – Input Format (INFORM)
Bit
Function
R/W
Description
Reset
7
YSEL2
R/W
See YSEL
0
6
FC27
R/W
1 = Input crystal clock frequency is 27MHz.
1
0 = Square pixel mode. Must use 24.54MHz for 60Hz field rate
source or 29.5MHz for 50Hz field rate source.
5-4
IFSEL
R/W
01 = S-video decoding
0
00 = Composite video decoding
3-2
YSEL
R/W
YSEL2 together with these two bits control the Y input video
selection.
0
000 = Mux0 selected
001 = Mux1 selected
010 = Mux2 selected
011 = Mux3 selected
100-111 = Invalid
1
CSEL
R/W
This bit selects the chroma channel input.
0
0 = CIN0
1 = CIN1
0
TECHWELL, INC.
R/W
Reserved
0
42
REV. D
08/29/2005
TW9920
0x03 – Output Format Control Register (OPFORM)
Bit
7
Function
MODE
R/W
Description
Reset
R/W
0 = CCIR601 compatible YCrCb 4:2:2 format with separate syncs
and flags.
0
1 = ITU-R-656 compatible data sequence format.
6
LEN
R/W
0 = 8/10-bit YCrCb 4:2:2 output format.
0
1 = 16/20-bit YCrCb 4:2:2 output format.
5
LLCMODE
R/W
1 = LLC output mode.
0 = free-run output mode
4
AINC
R/W
Serial interface indexing control
0 = auto-increment
3
VSCTL
R/W
0
0
1 = non-auto
1 = Vertical scale-downed output controlled by DVALID only.
0
0 = Vertical scale-downed output controlled by both HACTIVE and
DVALID.
2
OEN
R/W
0 = Enable outputs.
1
1 = Tri-state outputs defined by Tri-state select bits of this register.
1-0
TRI_SEL
R/W
These bits select the outputs to be tri-stated when the OEN bit is
asserted high. There are three major groups that can be
independently tri-stated: timing group (HS, VS, DVALID, MPOUT,
FLD), data group (VD[19:0]), and clock group (CLKX1, CLKX2)
according to following definition.
0
00 = Timing and data group only.
01 = Data group only.
10 = All three groups.
11 = Clock and data group only.
0x04 – GAMMA and HSYNC Delay Control
Bit
Function
R/W
Description
7
GMEN
R/W
Reserved for test
6-5
CKHY
R/W
Color killer hytheresis
0 – fastest
4-0
HSDLY
TECHWELL, INC.
RW
Reset
0
0
1 – fast
Reserved for test.
2 – medium
3 - slow
0
43
REV. D
08/29/2005
TW9920
0x05 – Output Control I
Bit
7
Function
VSP
R/W
R/W
Description
0 = VS pin output polarity is active high
Reset
0
1 = VS pin output polarity is active low.
6-4
VSSL
R/W
VS pin output control
0
0 = VSYNC
1 = VACT
2 = HACT
3 = VVALID
4 - 7 = Reserved
3
HSP
R/W
0 = HS pin output polarity is active high
0
1 = HS pin output polarity is active low.
2-0
HSSL
R/W
HS pin output control
0
0 = HACT
1 = HSYNC
2 = VSYNC
3 = Hlock
4 – 7 = Reserved
TECHWELL, INC.
44
REV. D
08/29/2005
TW9920
0x06 – Analog Control Register (ACNTL)
Bit
Function
7
SRESET
6
IREF
R/W
Description
Reset
W
An 1 written to this bit resets the device to its default state but all
register content remain unchanged. This bit is self-resetting.
0
0 = Internal current reference 1.
0
R/W
1 = Internal current reference 2.
5
VREF
R/W
1 = Internal voltage reference.
0
0 = external voltage reference using VCOM, VREFP and VREFN.
4
AGC_EN
R/W
0 = AGC loop function enabled.
0
1 = AGC loop function disabled. Gain is set to by AGCGAIN.
3
CLK_PDN
R/W
0 = Normal clock operation.
0
1 = System clock in power down mode, but the MPU INTERFACE
module and output clocks (CLKX1 and CLKX2) are still active.
2
Y_PDN
R/W
0 = Luma ADC in normal operation.
0
1 = Luma ADC in power down mode.
1
C_PDN
R/W
0 = Chroma ADC in normal operation.
0
1 = Chroma ADC in power down mode.
0
R/W
Reserved for future use
0
0x07 – Cropping Register, High (CROP_HI)
Bit
Function
R/W
7-6
VDELAY_
HI
R/W
These bits are bit 9 to 8 of the 10-bit Vertical Delay register.
0
5-4
VACTIVE_
HI
R/W
These bits are bit 9 to 8 of the 10-bit VACTIVE register. Refer to
description on Reg09 for its shadow register.
0
3-2
HDELAY_
HI
R/W
These bits are bit 9 to 8 of the 10-bit Horizontal Delay register.
0
1-0
HACTIVE
_HI
R/W
These bits are bit 9 to 8 of the 10-bit HACTIVE register.
2
TECHWELL, INC.
Description
45
Reset
REV. D
08/29/2005
TW9920
0x08 – Vertical Delay Register, Low (VDELAY_LO)
Bit
Function
R/W
Description
Reset
7-0
VDELAY_
LO
R/W
These bits are bit 7 to 0 of the 10-bit Vertical Delay register. The
two MSBs are in the CROP_HI register. It defines the number of
lines between the leading edge of VSYNC and the start of the
active video.
12
0x09 – Vertical Active Register, Low (VACTIVE_LO)
Bit
Function
R/W
Description
Reset
7-0
VACTIVE_
LO
R/W
These bits are bit 7 to 0 of the 10-bit Vertical Active register. The
two MSBs are in the CROP_HI register. It defines the number of
active video lines per frame output.
F0
The VACTIVE register has a shadow register for use with 50Hz
source when Atreg of Reg0x1C is not set. This register can be
accessed through the same index address by first changing the
format standard to any 50Hz standard.
0x0A – Horizontal Delay Register, Low (HDELAY_LO)
Bit
Function
R/W
Description
Reset
7-0
HDELAY_
LO
R/W
These bits are bit 7 to 0 of the 10-bit Horizontal Delay register. The
two MSBs are in the CROP_HI register. It defines the number of
pixels between the leading edge of the HSYNC and the start of the
image cropping for active video.
0F
The HDELAY_LO register has two shadow registers for use with
PAL and SECAM sources respectively. These register can be
accessed using the same index address by first changing the
decoding format to the corresponding standard.
0x0B – Horizontal Active Register, Low (HACTIVE_LO)
Bit
Function
R/W
Description
Reset
7-0
HACTIVE
_LO
R/W
These bits are bit 7 to 0 of the 10-bit Horizontal Active register. The
two MSBs are in the CROP_HI register. It defines the number of
active pixels per line output.
D0
TECHWELL, INC.
46
REV. D
08/29/2005
TW9920
0x0C – Control Register I (CNTRL1)
Bit
7
Function
PBW
R/W
R/W
Description
1 = Wide Chroma BPF BW
Reset
1
0 = Normal Chroma BPF BW
6
DEM
R/W
Secam control
1
1 = reduction
5
PALSW
R/W
0 = normal
1 = PAL switch sensitivity low.
0
0 = PAL switch sensitivity normal.
4
SET7
R/W
1 = The black level is 7.5 IRE above the blank level.
0
0 = The black level is the same as the blank level.
3
COMB
R/W
1 = Adaptive comb filter on for NTSC
1
0 = Notch filter
2
HCOMP
R/W
1 = operation mode 1. (recommended)
1
0 = mode 0.
1
YCOMB
R/W
This bit controls the Y comb.
0
1 = Y output is the averaging of two adjacent lines.
0 = No comb.
0
PDLY
R/W
PAL delay line.
1 = enabled.
0
0 = disabled.
0x0D – Vertical Scaling Register, Low (VSCALE_LO)
Bit
Function
R/W
7-0
VSCALE_
LO
R/W
Description
These bits are bit 7 to 0 of the 12-bit vertical scaling ratio register
Reset
00h
0x0E – Scaling Register, High (SCALE_HI)
Bit
Function
R/W
Description
Reset
7-4
VSCALE_
HI
R/W
These bits are bit 11 to 8 of the 12-bit vertical scaling ratio register.
1
3-0
HSCALE_
HI
R/W
These bits are bit 11 to 8 of the 12-bit horizontal scaling ratio
register.
1
TECHWELL, INC.
47
REV. D
08/29/2005
TW9920
0x0F – Horizontal Scaling Register, Low (HSCALE_LO)
Bit
Function
R/W
Description
Reset
7-0
HSCALE_
LO
R/W
These bits are bit 7 to 0 of the 12-bit horizontal scaling ratio
register.
00
0x10 – BRIGHTNESS Control Register (BRIGHT)
Bit
7-0
Function
BRIGHT
R/W
R/W
Description
These bits control the brightness. They have value of –128 to
127 in 2’s complement form. Positive value increases brightness.
A value 0 has no effect on the data.
Reset
00
0x11 – CONTRAST Control Register (CONTRAST)
Bit
7-0
Function
CNTRST
R/W
Description
Reset
R/W
These bits control the contrast. They have value of 0 to 3.98 (FFh).
A value of 1 (‘100_0000‘) has no effect on the video data.
5C
0x12 – SHARPNESS Control Register I (SHARPNESS)
Bit
7
Function
SCURVE
R/W
R/W
Description
This bit controls the sharpness filter center frequency.
0 = Normal
Reset
0
1 = High
6
VSF
R/W
This bit is for internal used.
1
5-4
CTI
R/W
CTI level selection. 0 = lowest. 3 = hightest.
1
3-0
SHARP
R/W
These bits control the amount of sharpness enhancement on the
luminance signals. There are 16 levels of control with ‘0’ having no
effect on the output image. 1 through 7 provides sharpness
enhancement with ‘7’ being the strongest. Value 8 through 15 are
provided for noise reduction purpose.
1
TECHWELL, INC.
48
REV. D
08/29/2005
TW9920
0x13 – Chroma (U) Gain Register (SAT_U)
Bit
7-0
Function
SAT_U
R/W
Description
Reset
R/W
These bits control the digital gain adjustment to the U (or Cb)
component of the digital video signal. The color saturation can be
adjusted by adjusting the U and V color gain components by the
same amount in the normal situation. The U and V can also be
adjusted independently to provide greater flexibility. The range of
adjustment is 0 to 200%.
80
0x14 – Chroma (V) Gain Register (SAT_V)
Bit
7-0
Function
SAT_V
R/W
Description
Reset
R/W
These bits control the digital gain adjustment to the V (or Cr)
component of the digital video signal. The color saturation can be
adjusted by adjusting the U and V color gain components by the
same amount in the normal situation. The U and V can also be
adjusted independently to provide greater flexibility. The range of
adjustment is 0 to 200%.
80
0x15 – Hue Control Register (HUE)
Bit
7-0
Function
HUE
R/W
Description
Reset
R/W
These bits control the color hue as 2’s complement number. They
o
o
have value from +36 (7Fh) to -36 (80h) with an increment of
o
0.28 . The positive value gives greenish tone and negative value
o
gives purplish tone. The default value is 0 (00h). This is effective
only on NTSC system.
00
0x16 – Sharpness Control II (SHARP2)
Bit
Function
R/W
Description
Reset
7-4
R/W
Reserved for future use.
5
3-0
R/W
Reserved for future use.
3
TECHWELL, INC.
49
REV. D
08/29/2005
TW9920
0x17 – Vertical Sharpness (VSHARP)
Bit
7-4
Function
SHCOR
R/W
R/W
3
2-0
VSHP
R/W
Description
Reset
These bits provide coring function for the sharpness control.
8
Reserved
0
Vertical peaking level. 0 = none. 7 = highest.
0
0x18 – Coring Control Register (CORING)
Bit
Function
R/W
Description
Reset
7-6
CTCOR
R/W
These bits control the coring for CTI.
1
5-4
CCOR
R/W
These bits control the low level coring function for the Cb/Cr output.
0
3-2
VCOR
R/W
These bits control the coring function of vertical peaking.
1
1-0
CIF
R/W
These bits control the IF compensation level.
0
0 = None
TECHWELL, INC.
1 = 1.5dB
50
2 = 3dB
3 = 6dB
REV. D
08/29/2005
TW9920
0x19 – VBI Control Register (VBICNTL)
Bit
7
Function
VBI_EN
R/W
R/W
Description
0 = VBI capture disabled.
Reset
0
1 = VBI capture enabled.
6
VBI Byte
Order
R/W
If LEN(Reg0x03[6]) is “1”
1
0 = Pixel 1, 3, 5 … on the VD[19:12] data bus, and pixel 2, 4, 6, …
on the VD[9:2] data bus.
1 = Pixel 1, 3, 5, … on the VD[9:2] data bus, and pixel 2, 4, 6, …
on the VD[19:12] data bus.
If LEN is “0”
0 = Pixel 2,1,4,3,6,5,…. on the VD[19:12] data bus.
1 = Pixel 1,2,3,4,5,6,…. on the VD[19:12] data bus.
5
VBI_
FRAM
R/W
0 = Normal mode
0
1 = ADC output mode
VD[19:12] is Y-ADC data,VD[9:0] pin is C-YADC data
4
HA_EN
R/W
0 = HACTIVE output is disabled during vertical blanking period.
1
1 = HACTIVE output is enabled during vertical blanking period.
3
CNTL656
R/W
0 = 0x80 and 0x10 code will be output as invalid data during active
video line.
1
1 = 0x00 code will be output as invalid data during active video line.
2-0
RTSEL
R/W
These bits control the real time signal output from the MPOUT pin.
0
000 = Video loss
001 = H-lock
010 = S-lock
011 = V-lock
100 = MONO
101 = Det50
110 = LVALID
111 = RTCO
TECHWELL, INC.
51
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TW9920
0x1A – Analog Control II
Bit
Function
R/W
Description
Reset
7
LLCTEST
R/W
LLC test mode
0
6
PLL_PDN
R/W
0 = LLC PLL in normal operation.
0
1 = PLL in power down mode.
5-4
3
YFLEN
R/W
Reserved
0
Y-Ch anti-alias filter control
0
1 = enable
2
YSV
R/W
Y-Ch power saving mode
1 = enable
1
CFLEN
R/W
CSV
R/W
0
0 = disable
C-Ch anti-alias filter control
1 = enable
0
0 = disable
0
0 = disable
C-Ch power saving mode
1 = enable
0
0 = disable
0x1B – Output Control II
Bit
7-6
Function
CK2S
R/W
R/W
Description
CLKX2 pin output control
Reset
1
0 = CLKX2
1 = VCLK
2 = LLCK
3 = LLCK2
5-4
CK1S
R/W
CLKX1 pin output control
1
0 = VCLK
1 = CLKX1
2 = LLCK
3 = LLCK4
3
FLP
R/W
0 = FLD pin output polarity is active high
0
1 = FLD pin output polarity is active low.
TECHWELL, INC.
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TW9920
2-0
FLSL
R/W
FLD pin output control
0
0 = FLD
1 = Vlock
2 = Slock
3 = Vdloss
4 – 7 = Reserved
0x1C – Standard Selection (SDT)
Bit
Function
R/W
Description
7
DETSTUS
R
0 = Idle
6-4
STDNOW
R
Current standard invoked
1 = detection in progress
Reset
0
0
0 = NTSC(M)
1 = PAL (B,D,G,H,I)
2 = SECAM
3 = NTSC4.43
4 = PAL (M)
5 = PAL (CN)
6 = PAL 60
7 = Not valid
3
ATREG
R/W
1 = Disable the shadow registers.
0
0 = Enable VACTIVE and HDELAY shadow registers value
depending on standard
2-0
STD
R/W
Standard selection
7
0 = NTSC(M)
1 = PAL (B,D,G,H,I)
2 = SECAM
3 = NTSC4.43
4 = PAL (M)
5 = PAL (CN)
6 = PAL 60
7 = Auto detection
TECHWELL, INC.
53
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TW9920
0x1D – Standard Recognition (SDTR)
Bit
Function
R/W
Description
Reset
7
ATSTART
R/W
Writing 1 to this bit will manually initiate the auto format detection
process. This bit is a self-resetting bit.
0
6
PAL6_EN
R/W
1 = enable recognition of PAL60.
1
0 = disable recognition.
5
PALN_EN
R/W
1 = enable recognition of PAL (CN).
1
0 = disable recognition.
4
PALM_EN
R/W
1 = enable recognition of PAL (M).
1
0 = disable recognition.
3
NT44_EN
R/W
1 = enable recognition of NTSC 4.43.
1
0 = disable recognition.
2
SEC_EN
R/W
1 = enable recognition of SECAM.
1
0 = disable recognition.
1
PALB_EN
R/W
1 = enable recognition of PAL (B,D,G,H,I).
1
0 = disable recognition.
0
NTSC_EN
R/W
1 = enable recognition of NTSC (M).
1
0 = disable recognition.
0x1E – Component Video Format (CVFMT)
Bit
Function
7
6-4
CVSTD
R/W
Description
Reset
R
Reserved
0
R
Component video input format detection.
0
0 = 480i,
1 = 576i,
2 = 480p,
3 = 576p
3-0
CVFMT
R/W
Component video format selection.
8
0 = 480i,
1 = 576i,
2 = 480p,
3 = 576p,
8 = Auto
TECHWELL, INC.
54
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TW9920
0x1F – Test Control Register (TEST)
Bit
7-0
Function
TEST
R/W
Description
Reset
R/W
This register is reserved for testing purpose. In normal operation,
only 0 should be written into this register.
0
1 = Analog test mode. Y and C channel portion of the device can
be tested in this mode. The Y channel ADC output can be obtained
from VD[19-10]. The C channel ADC output can be obtained from
VD[9-0].
2 = Clamp test mode. Clamp control YU, YUX, YD, YDX, CU,
CUX, CD, and CDX are mapped to PD[7-0].
3 = Reserved
4 = Digital test mode1. This is the CVBS test mode. The 9-bit input
corresponds to PD[9-1] in the order of bit 8 to 0.
5 = Digital test mode 2. This is the Y/C test mode. Y input is
defined by test mode 1. The C channel data is inputted from VD[91]. In this mode, only 8/10-bit output format is allowed.
6 = Digital test mode 3. Encoder output test mode. The 20-bit
Encoder output corresponds to VD[19-0].
7 = Digital test mode 4. Encoder in-out test mode. In this mode. 9bit data inputted from PD[9-1] to decoder. 20-bit Encoder output
corresponds to VD[19-0].
8 = Reserved
9 = Sync output mode. The 6-bit Sync output corresponds to VD[50] in the order of bit 5 to 0. Y and Cb/Cr outputs correspond to
VD[19-10] in 422 format
A = DAC test mode. In this mode, the 10-bit DAC input
corresponds to PD[9:0] bus.
TECHWELL, INC.
55
REV. D
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TW9920
0x20 – Clamping Gain (CLMPG)
Bit
Function
R/W
Description
Reset
7-4
CLPEND
R/W
These 4 bits set the end time of the clamping pulse in the
increment of 8 system clocks. The clamping time is determined by
this together with CLPST.
5
3-0
CLPST
R/W
These 4 bits set the start time of the clamping pulse in the
increment of 8 system clocks. It is referenced to PCLAMP position.
0
0x21 – Individual AGC Gain (IAGC)
Bit
Function
R/W
Description
Reset
7-4
NMGAIN
R/W
These bits control the normal AGC loop maximum correction
value.
2
3-1
WPGAIN
R/W
Peak AGC loop gain control.
1
0
AGCGAIN
8
R/W
This bit is the MSB of the 9-bit register that controls the AGC gain
when AGC loop is disabled.
0
0x22 – AGC Gain (AGCGAIN)
Bit
Function
R/W
Description
Reset
7-0
AGCGAIN
R/W
These bits are the lower 8 bits of the 9-bit register that controls the
AGC gain when AGC loop is disabled.
F0
0x23 – White Peak Threshold (PEAKWT)
Bit
Function
R/W
Description
Reset
7-0
PEAKWT
R/W
These bits control the white peak detection threshold. This function
can be disabled by setting ‘FF’.
F8
0x24– Clamp level (CLMPL)
Bit
7
Function
CLMPLD
R/W
R/W
Description
0 = Clamping level is set by CLMPL.
Reset
1
1 = Clamping level preset at 60d.
6-0
CLMPL
TECHWELL, INC.
R/W
These bits determine the clamping level of the Y channel.
56
3C
REV. D
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TW9920
0x25– Sync Amplitude (SYNCT)
Bit
7
Function
SYNCTD
R/W
R/W
Description
0 = Reference sync amplitude is set by SYNCT.
Reset
1
1 = Reference sync amplitude is preset to 38h.
6-0
SYNCT
R/W
These bits determine the standard sync pulse amplitude for AGC
reference.
38
0x26 – Sync Miss Count Register (MISSCNT)
Bit
Function
R/W
Description
Reset
7-4
MISSCNT
R/W
MISSCNT[3] controls the speed of VDLOSS detection with ‘0’
being fast and ‘1’ being slow. MISSCNT[2:0] control the threshold
of horizontal sync miss detection per field.
4
3-0
HSWIN
R/W
These bits determine the VCR mode Hsync detection window.
4
0x27 – Clamp Position Register (PCLAMP)
Bit
7-0
Function
PCLAMP
TECHWELL, INC.
R/W
R/W
Description
These bits set the clamping position from the PLL sync edge
57
Reset
38
REV. D
08/29/2005
TW9920
0x28 – Vertical Control I (VCNTL1)
Bit
7-6
Function
VLCKI
R/W
R/W
Description
Vertical lock in time.
0 = fastest
5-4
VLCKO
R/W
3
VMODE
R/W
0
3 = slowest.
Vertical lock out time.
0 = fastest
Reset
0
3 = slowest.
This bit controls the vertical detection window.
0
1 = search mode.
0 = vertical count down mode.
2
DETV
R/W
1 = recommended for special application only.
0
0 = Normal Vsync logic
1
AFLD
R/W
Auto field generation control
0 = Off
0
VINT
R/W
1 = On
Vertical integration time control.
1 = long
0
0
0 = normal
0x29 – Vertical Control II (VCNTL2)
Bit
Function
R/W
Description
Reset
7-5
BSHT
R/W
Burst PLL center frequency control.
0
5-0
VSHT
R/W
Vsync output delay control in the increment of half line length.
00
0x2A – Color Killer Level Control (CKILL)
Bit
Function
R/W
Description
Reset
7-6
CKILMAX
R/W
These bits control the amount of color killer hysteresis. The
hysteresis amount is proportional to the value.
1
5-0
CKILMIN
R/W
These bits control the color killer threshold. Larger value gives
lower killer level.
28
TECHWELL, INC.
58
REV. D
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TW9920
0x2B – Comb Filter Control (COMB)
Bit
Function
R/W
Description
Reset
7-4
HTL
R/W
Adaptive Comb filter control.
4
3-0
VTL
R/W
Adaptive Comb filter combing strength control. Higher value
provides stronger comb filtering.
4
0x2C – Luma Delay and H Filter Control (LDLY)
Bit
7
Function
CKLM
R/W
R/W
Description
Color Killer mode.
0 = normal
6-4
3
Reset
0
1 = fast ( for special application)
YDLY
R/W
Luma delay fine adjustment. This 2’s complement number provide
–4 to +3 unit delay control.
3
EVCNT
R/W
1 = Even field counter in special mode.
0
0 = Normal operation
2-0
HFLT
R/W
Pre-filter selection for horizontal scaler
0
1** = Bypass
000 = Auto selection based on Horizontal scaling ratio.
001 = Recommended for CIF size image
010 = Recommended for QCIF size image
011 = Recommended for ICON size image
TECHWELL, INC.
59
REV. D
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TW9920
0x2D – Miscellaneous Control I (MISC1)
Bit
Function
7-6
R/W
Description
Reset
R/W
Reserved for future use.
0
5
PALC
R/W
Reserved for future use.
0
4
SDET
R/W
ID detection sensitivity. A ‘1’ is recommended.
1
3
TBC_EN
R/W
1:TBC enable in freerun clock mode. 0:Disable
0
2
BYPASS
R/W
It controls the standard detection and should be set to ‘1’ in normal
use.
1
1
SYOUT
R/W
1 = Hsync output is disabled when video loss is detected
0
0 = Hsync output is always enabled
0
HADV
R/W
This bit advances the HACTIVE and DVALID pin output by one
data clock when set.
0
0x2E – LOOP Control Register (LOOP)
Bit
7-6
Function
HPM
R/W
R/W
Description
Horizontal PLL acquisition time.
3 = Fast
5-4
ACCT
R/W
SPM
R/W
CBW
R/W
2
1 = Auto2
0 = Slow
2
1 = slow
2 = medium
3 = fast
Burst PLL control.
0 = Slowest
1-0
2 = Auto1
ACC time constant
0 = No ACC
3-2
Reset
1
1 = Slow
2 = Fast
Chroma low pass filter bandwidth control.
3 = Fastest
1
Refer to filter curves.
TECHWELL, INC.
60
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TW9920
0x2F – Miscellaneous Control II (MISC2)
Bit
7
Function
NKILL
R/W
R/W
Description
1 = Enable noisy signal color killer function in NTSC mode.
Reset
1
0 = Disabled.
6
PKILL
R/W
1 = Enable automatic noisy color killer function in PAL mode.
1
0 = Disabled.
5
SKILL
R/W
1 = Enable automatic noisy color killer function in SECAM mode.
1
0 = Disabled.
4
CBAL
R/W
0 = Normal output
0
1 = special output mode.
3
FCS
R/W
1 = Force decoder output value determined by CCS.
0
0 = Disabled.
2
LCS
R/W
1 = Enable pre-determined output value indicated by CCS when
video loss is detected.
0
0 = Disabled.
1
CCS
R/W
When FCS is set high or video loss condition is detected when
LCS is set high, one of two colors display can be selected.
0
1 = Blue color.
0 = Black.
0
BST
R/W
1 = Enable blue stretch.
0
0 = Disabled.
TECHWELL, INC.
61
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TW9920
0x30 – Macrovision Detection (MVSN)
Bit
Function
R/W
Description
Reset
7
SF
R
0
6
PF
R
0
5
FF
R
0
4
KF
R
0
3
CSBAD
R
1 = Macrovision color stripe detection may be un-reliable
0
2
MCVSN
R
1 = Macrovision AGC pulse detected.
0
0 = Not detected.
1
CSTRIPE
R
1 = Macrovision color stripe protection burst detected.
0
0 = Not detected.
0
CTYPE
R
This bit is valid only when color stripe protection is detected, i.e.
Cstripe=1.
0
1 = Type 2 color stripe protection
0 = Type 3 color stripe protection
0x31 – Chip STATUS II (STATUS2)
Bit
Function
R/W
Description
Reset
7
VCR
R
VCR signal indicator
0
6
WKAIR
R
Weak signal indicator 2.
0
5
WKAIR1
R
Weak signal indicator controlled by WKTH.
0
4
VSTD
R
1 = Standard signal
0 = Non-standard signal
0
3
NINTL
R
1 = Non-interlaced signal
0 = interlaced signal
0
2
WSSDET
R
1 = WSS data detected. 0 = Not detected.
0
1
EDSDET
R
1 = EDS data detected. 0 = Not detected.
0
0
CCDET
R
1 = CC data detected.
0
TECHWELL, INC.
0 = Not detected.
62
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TW9920
0x32 – H monitor (HFREF)
Bit
7-0
Function
R/W
HFREF
R
Description
Reset
Horizontal line frequency indicator
X
0x33 – CLAMP MODE (CLMD)
Bit
7-6
Function
R/W
FRM
R/W
Description
Free run mode control
0 = Auto
5-4
YNR
R/W
CLMD
R/W
PSP
R/W
3 = default to 50Hz
0
1 = smallest
2 = small
3 = medium
Clamping mode control.
0 = Sync top
1-0
0
2 = default to 60Hz
Y HF noise reduction
0 = None
3-2
Reset
1
1 = Auto
2 = Pedestal
3 = N/A
Slice level control
0 = low
1
1 = medium
2 = high
0x34 – ID Detection Control (IDCNTL)
Bit
Function
7-6
IDX
5-0
NSEN
SSEN
PSEN
WKTH
/
/
/
R/W
Description
Reset
R/W
These two bits indicates which of the four lower 6-bit registers is
currently be controlled. The write sequence is a two steps process
unless the same register is written. A write of {ID,000000} selects
one of the four registers to be written. A subsequent write will
actually write into the register.
0
R/W
IDX = 0 controls the NTSC ID detection sensitivity (NSEN).
IDX = 1 controls the SECAM ID detection sensitivity (SSEN).
IDX = 2 controls the PAL ID detection sensitivity (PSEN).
1A /
20 /
1C /
11
IDX = 3 controls the weak signal detection sensitivity (WKTH).
TECHWELL, INC.
63
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TW9920
0x35 – Clamp Control I (CLCNTL1)
Bit
Function
R/W
Description
Reset
7
CTEST
R/W
Clamping control for debugging use.
0
6
YCLEN
R/W
1 = Y channel clamp disabled
0
0 = Enabled.
5
CCLEN
R/W
1 = C channel clamp disabled
0
0 = Enabled.
4
VCLEN
R/W
Reserved
0
3
GTEST
R/W
1 = Test.
0
0 = Normal operation.
2
VLPF
R/W
Sync filter control.
0
1
CKLY
R/W
Clamping current control 1.
0
0
CKLC
R/W
Clamping current control 2.
0
TECHWELL, INC.
64
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TW9920
0x40 – 0x48
AUDIO CLOCK
0x40 – Audio Clock Increment (ACKI)
Bit
7-0
Function
ACKI
R/W
RW
Description
Bit 7-0 of ACKI
Reset
64
0x41 – Audio Clock Increment (ACKI)
Bit
7-0
Function
ACKI
R/W
RW
Description
Bit 15-8 of ACKI
Reset
85
0x42 – Audio Clock Increment (ACKI)
Bit
5-0
Function
ACKI
R/W
RW
Description
Bit 21-16 of ACKI
Reset
35
0x43 – Audio Clock Number (ACKN)
Bit
7-0
Function
ACKN
R/W
RW
Description
Bit 7-0 of Audio clock number per field
Reset
BC
0x44 – Audio Clock Number (ACKN)
Bit
7-0
Function
ACKN
R/W
RW
Description
Bit 15-8 of ACKN
Reset
DF
0x45 – Audio Clock Number (ACKN)
Bit
1-0
Function
ACKN
TECHWELL, INC.
R/W
RW
Description
Bit 17-16 of ACKN
Reset
2
65
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TW9920
0x46 – Serial Clock Divider (SDIV)
Bit
5-0
Function
SDIV
R/W
RW
Description
Serial Clock divider
Reset
01
0x47 – Left/Right Clock Divider (LRDIV)
Bit
5-0
Function
LRDIV
R/W
RW
Description
Left/Right Clock divider
Reset
20
0x48 – Audio Clock Control (ACCNTL)
Bit
Function
R/W
Description
Reset
6
APZ
RW
Loop control
1
5-4
APG
RW
Loop control
2
2
ACPL
RW
0 = Loop closed
1
SPH
RW
ASCLK divider trigger phase
0
0
LRPH
RW
ALRCLK divider trigger phase
0
TECHWELL, INC.
1 = Loop open
66
0
REV. D
08/29/2005
TW9920
0x4E – HBLEN
Bit
7-0
Function
HBLEN
R/W
Description
Reset
R/W
These bits are effective when HASYNC bit is set to 1.These bits
set up the length of EAV to SAV code when HASYNC bit is 1.
8A
0x4F – WSS3
Bit
Function
R/W
Description
Reset
7-0
WSS[19:1
4]
R
CGMS(WSS525) Bit19-14 in 525 line video system.These bits
show CRC 6bits in CGMS(WSS525). These bits are only valid in
525 line video system.
X
Description
Reset
0x50 – FILLDATA
Bit
Function
R/W
7-0
FILLDATA
R/W
Filled data as dummy data in ANC Dword data packet.
A0
0x51 – SDID
Bit
Function
R/W
Description
Reset
7
NODAEN
R/W
1:Bit7 in 4th byte of EAV/SAV code will be 0 when sync lost(No
Video input.)
0
0: Bit7 in 4th byte of EAV/SAV is always VIPCFG register bit.
6
SYRM
R/W
1: Minimum value in raw VBI will be 0x10 for Sync Level remove.
0
0:none.
5-0
SDID
TECHWELL, INC.
R/W
Secondary data ID in ANC data packet type 2
67
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TW9920
0x52 – DID
Bit
Function
R/W
Description
Reset
7
ANCEN
R/W
1:ANC data packet output enable. 0:disable.
0
6
YCBCR42
2
R/W
1: Average process YCbCr 4:2:2 output
0
VIPCFG
R/W
Set up Bit7 in 4th byte of EAV/SAV code.
1
DID
R/W
Data ID in ANC data packet type 2.
11
5
4-0
0:Normal process YCbCr 4:2:2 output
0x53 – WSS1
Bit
Function
R/W
7
CRCERR
R
Description
This bit is only valid in 525 line video system.
Reset
X
1:CGMS(WSS525) CRC error detected in current field.
0:No CRC error
6
WSSFLD
R
0:current WSS data is received in Oddfield.
X
1: current WSS data is received in Even field.
5-0
WSS[13:8]
R
CGMS(WSS525) Bit13-8 in 525 line video system.
X
Wide Screen Signaling Bit13-8 in 625 line video system.
0x54 – WSS2
Bit
7-0
Function
WSS[7:8]
R/W
R
Description
CGMS(WSS525) Bit7-0 in 525 line video system.
Reset
X
Wide Screen Signaling Bit7-0 in 625 line video system.
TECHWELL, INC.
68
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TW9920
0x55 – VVBI
Bit
7
Function
HA656
R/W
Description
Reset
R/W
1:HACTIVE signal is same as DVALID signal in H Down scaled
video output.
0
0:HACTIVE signal is always HACTIVE register’s length.
6
1:EAV-SAV code is swapped.
0
EAVSWA
P
R/W
5
HAMM84
R/W
1:enable 84 Hamming Code checking BI Slicer.0: disable.
0
4
NTSC656
R/W
1:Number of Even Field Video output line is (the number of Odd
field Video output line – 1). This bit is required for ITU-R BT.656
output for 525 line system standard.
0
0:EAV-SAV code is not swapped(standard 656 output mode)
0: Number of Even Field Video output line is same as the number
of Odd field Video output line.
3-0
VVBI
R/W
The number of raw VBI data output line counted from top video
active line signal timing.
0
0x56~6A LCTL6~LCTL26
Bit
7-4
Function
LCTLn
R/W
R/W
Description
Set up VBI Data Slicer Decoding mode on Line-n.
Reset
0
Value is set up by upper bit7-4 meaning for Line-n in odd field.
3-0
R/W
Value is set up by below bit3-0 meaning for Line-n in even field.
0
0h:disable decoding.
1h:Teletext-B
2h:Teletext-C
3h:Teletext-D
4h:Closed Captioning and Extended Data service. (EIA-608 type).
5h:CGMS (WSS525) in 525 line system or WSS625 in 625 line
system.
6h:VITC
7h:Gemstar 1x
8h:Gemstar 2x
9h:VPS (Line16 VPS type)
Ah: Teletext-A
Bh~Fh: reserved
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TW9920
0x6B – HSGEGIN
Bit
Function
R/W
7-0
HSBEGIN
R/W
Description
HSYNC Start position.
Reset
2C
0x6C – HSEND
Bit
7-0
Function
HSEND
R/W
R/W
Description
HSYNC End position.
Reset
60
0x6D – OVSDLY
Bit
7-0
Function
OVSDLY
R/W
R/W
Description
VSYNC Start position.
Reset
00
0x6E – OVSEND
Bit
7
Function
HSPIN
R/W
R/W
Description
1:HSYNC output is HACTIVE.
Reset
0
0:HSYNC output is HSYNC.
6-4
OFDLY
R/W
2
FIELD output delay.
0h:0H line delay FIELD output. (601 mode only)
1h-6h: 1H-6H line delay FIELD output.
7h:FIELD output is synchronized to the leading edge of VACTIVE.
3
VSMODE
R/W
1:VSYNC output is HACTIVE-VSYNC mode.
0
0:VSYNC output is HSYNC-VSYNC mode.
2-0
OVSEND
TECHWELL, INC.
R/W
Line delay for VSYNC end position.
70
0
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08/29/2005
TW9920
0x6F – VBIDELAY
Bit
Function
R/W
7
PDNSVBI
R/W
Description
1:VBI data slicer enable
Reset
0
0: VBI data slicer is in reset and power-down mode
6
HASYNC
R/W
1:the length of EAV to SAV is set up and fixed by HBLEN registers.
0:the length of SAV to EAV is set up and fixed by HACTIVE
registers.
0
5-0
VBIDELA
Y
R/W
Raw VBI output delay
24
0x70 – ENCODER CONTROL1
Bit
7
Function
SYS5060
R/W
Description
R/W Input/Output Field Rate Selection.
1:50Hz
Reset
0
0:60Hz
6
INTERLACE
R/W Output Scan Format Selection.
1:Interlace
1
0:Non-Interlace
5-4
FSC
R/W Set color sub-carrier frequency for video encoder.
3: 3.58205625 MHz
0
2: 3.57561149 MHz
1: 4.43361875 MHz
0: 3.57954545 MHz
3
2
PHALT
R/W Reserved for future use.
0
R/W Set phase alternation.
1:Enable phase alternation for line-by-line
0
0:Disable phase alternation for line-by-line
1
ALTRST
R/W Reset phase alternation for every 8 fields
1:Enable phase alternation reset for every 8 fields
0
0:Disable phase alternation reset for every 8 fields
0
PED
R/W Set 7.5 IRE for pedestal level
1:Enable 7.5 IRE for pedestal level
0
0:Disable 7.5 IRE for pedestal level
TECHWELL, INC.
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TW9920
0x71 – ENCODER CONTROL2
Bit
Function
7-6
ENC_IN_OR
DER
R/W
Description
R/W Encoder Digital Video Data Input port order selection.
3:Video Input Data [0:7]
Reset
0
2:Video Input Data [7:0]
1:Video Input Data [2:9]
0:Video Input Data [9:2]
5
ENC_VS
R/W Define vertical sync detection type.
1:Detect vertical sync from combination of HSYNC and FIELD
information
1
0:Detect vertical sync from VSYNC information
4
ENC_FLD
R/W Define field polarity detection type.
1:Detect field polarity from combination of HSYNC and VSYNC
information
0
0:Detect field polarity from FIELD information
3
HSPOL
R/W Control horizontal sync polarity.
1:Active high
0
0:Active low
2
VSPOL
R/W Control vertical sync polarity.
1:Active high
0
0:Active low
1
FLDPOL
R/W Control field polarity.
1:Odd field is high
0
0:Even field is high
0
ENC_CK
R/W Encoder Input Clock polarity Control.
1:Invert PDCLK
0
0:PDCLK
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0x72 – ENCODER CONTROL3
Bit
Function
7-6
ENC_VSOFF
R/W
Description
R/W Compensate field offset for first active video line.
3:Applied ENC_VSDEL for odd and {ENC_VSDEL+2} for even
field
Reset
0
2:Applied ENC_VSDEL for odd and {ENC_VSDEL+1} for even
field
1:Applied {ENC_VSDEL+1} for odd and ENC_VSDEL for even
field
0:Applied same ENC_VSDEL for odd and even field
5-0
ENC_VSDEL
R/W Control vertical delay of active video line from vertical sync by 1
line/step.
10
63: 63 Lines delayed
:
:
0: No delayed
0x73 – ENCODER CONTROL4
Bit
Function
7-0
ENC_HSDEL
R/W
Description
R/W Control horizontal delay of active video pixel from horizontal
sync by 2 pixels/step.
Reset
45
255: 510 pixels delayed
:
:
0: No delayed
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TW9920
0x74 – ENCODER CONTROL5
Bit
Function
7-6
ENC_YBW
R/W
Description
R/W Control luminance bandwidth of video encoder.
3:Do not use
Reset
3
2:Wide bandwidth
1:Do not use
0:Narrow bandwidth
5-4
ENC_CBW
R/W Control chrominance bandwidth of video encoder.
3:Do not use
3
2: 1.35 MHz
1: 1.15 MHz
0: 0.8 MHz
3
ENC_BAR
R/W Enable test pattern output.
0
1:Internal color bar with 100% amplitude 100% saturation
0:Normal operation
2-0
ENC_TCSEL
R/W Test pattern color selection control.
7:Blue color
6: Red color
5:Magenta color
4:Green color
3:Cyan color
2:Black color
1:White color
0:Color bar
0
0x75 – ENCODER CONTROL6
Bit
7
Function
CKILL
R/W
Description
R/W Color killer
1:Color is killed
Reset
0
0:Normal operation
6
DAC_OUT
R/W Define analog video format.
1: S-Video output
0
0: CVBS output
5-0
TEST_MODE
TECHWELL, INC.
R/W Encoder TEST Mode control
74
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TW9920
0x76 – ENCODER & DAC Power Down
Bit
7
Function
DBL
R/W
R/W
Description
Double DAC output current control.
Reset
0
1 : 2 mA / 1 step
0 : 1mA / 1 step
6
ENC_LOOP
R/W
Decoder to Encoder loop test mode.
0
1:Decoder output direct connect to Encoder input for Test
purpose
0:Normal Decoder & Encoder operation
5
ENC_PD
R/W
Encoder Power Down mode.
0
1:Encoder Power Down mode ON
0:Encoder Power Down mode OFF
4
DAC_PD0
R/W
CVBS/Y Output DAC Power Down mode.
0
1:DAC0 Power Down mode ON
0:DAC0 Power Down mode OFF
3
DAC_PD1
R/W
COUT DAC Power Down mode.
0
1:DAC1 Power Down mode ON
0:DAC1 Power Down mode OFF
2
DAC_PD2
R/W
YOUT DAC Power Down mode.
0
1:DAC2 Power Down mode ON
0:DAC2 Power Down mode OFF
1
DAC_PD3
R/W
CBOUT DAC Power Down mode.
0
1:DAC3 Power Down mode ON
0:DAC3 Power Down mode OFF
0
DAC_PD4
R/W
CROUT DAC Power Down mode.
0
1:DAC4 Power Down mode ON
0:DAC4 Power Down mode OFF
TECHWELL, INC.
75
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TW9920
0x77 – DAC Control1
Bit
Function
R/W
Description
Reset
7-4
DAC_IREF0
R/W
CVBS/Y Output DAC IREF control. (1mA or 2mA / 1 step
decrease, please see DBL.)
F
15: 1mA
:
:
0: Full Scale = 16mA
3-0
DAC_IREF1
R/W
COUT DAC IREF control. (1mA or 2mA / 1 step decrease,
please see DBL.)
F
15: 1mA
:
:
0: Full Scale = 16 mA
0x78 – DAC Control12
Bit
Function
R/W
Description
Reset
7-4
DAC_IREF2
R/W
YOUT DAC IREF control. (1mA or 2mA / 1 step decrease,
please see DBL.)
F
15: 1mA
:
:
0: Full Scale = 16 mA
3-0
DAC_IREF3
R/W
CBOUT DAC IREF control . (1mA or 2mA / 1 step decrease,
please see DBL.)
F
15: 1mA
:
:
0: Full Scale = 16 mA
TECHWELL, INC.
76
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TW9920
0x79 – DAC Control13
Bit
Function
7-6
R/W
Description
Reset
R/W
Reserved for future use.
0
5
NONSTA
R/W
Horizontal Range Change for Non-standard input (1: Enable)
0
4
FRUN
R/W
Free Run mode for Encoder (1: Free Run Mode)
0
3-0
DAC_IREF4
R/W
CROUT DAC IREF control. (1mA or 2mA / 1 step decrease,
please see DBL.)
F
15: 1mA
:
:
0: Full Scale = 16 mA
0x7a – Encoder YDEL
Bit
Function
7-5
4-0
ENC_YDEL
R/W
Description
Reset
R/W
Reserved for future use.
0
R/W
Encoder Y Output delay control (27MHz 1-clock / step)
0F
31: 16 clocks delayed
:
:
15: 0 clock delayed
:
:
0: -15 clocks delayed
TECHWELL, INC.
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TW9920
0x7b – Encoder SYNC_L & BLK_L
Bit
Function
R/W
7-4
ENC_SYNC_L
R/W
Description
Encoder DAC Output Sync Level control
Reset
2
15: Sync Level : 10’d181
:
:
6: Sync Level : 10’d63
:
:
3: Sync Level : 10’d26
2: Sync Level : 10’d11
:
:
0: Sync Level : 10’d0
3-0
ENC_BLK_L
R/W
Encoder DAC Output Blank Level control
5
15: Blank Level : 10’d318
:
:
5: Blank Level : 10’d240
:
:
1: Blank Level : 10’d212
0: Blank Level : 10’d198
0x7c – Encoder YBRT
Bit
Function
R/W
7-0
ENC_YBRT
R/W
Description
Encoder Y Data Brightness Control
Reset
00
FF: Brightness Control Level : -8’d127
:
:
00: Brightness Control Level : 8’d0
:
:
7F: Brightness Control Level : +8’d127
TECHWELL, INC.
78
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TW9920
0x7d – Encoder CBURST
Bit
Function
7-5
4-0
ENC_CBURST_L
R/W
Description
Reset
R/W
Reserved for future use.
0
R/W
Encoder Color Burst Level control
0F
( 0x70 : Bit2==0 Æ 1.2% / step )
( 0x70 : Bit2==1 Æ 1.25% / step )
0Fh : Increase of Color Burst Level
:
:
00h : Standard Color Burst Level
10h : Standard Color Burst Level
:
:
1Fh : Decrease of Color Burst Level
TECHWELL, INC.
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Pin Diagram
BOTTOM VIEW
A
B
C
D
E
F
G
H
J
K
10 9
TECHWELL, INC.
8
7
80
6
5
4
3
2
1
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TW9920
Pin Description
Pin#
I/O
Pin Name
Description
Analog video signals
J8
I
MUX0
Analog CVBS or Y input. Connect used input to AGND through 0.1uF capacitor.
K9
I
MUX1
Analog CVBS or Y input. Connect used input to AGND through 0.1uF capacitor.
K10
I
MUX2
Analog CVBS or Y input. Connect used input to AGND through 0.1uF capacitor.
J10
I
MUX3
Analog CVBS or Y input. Connect used input to AGND through 0.1uF capacitor.
K7
I
CIN0
Analog chroma input. Connect unused input to AGND through 0.1uF capacitor.
K8
I
CIN1
Analog chroma input. Connect unused input to AGND through 0.1uF capacitor.
H9
O
VREFP
The positive reference for the ADC. It should be connected to AVSS through 0.1uF
capacitor. NC pin.
H10
O
VREFN
The negative reference for the ADC. It should be connected to AVSS through a
0.1uF capacitor. NC pin.
G9
O
VCOM
The common mode node. It should be connected to analog VSS through a 0.1uF
capacitor. NC pin.
J9
I
AVSY
Y signal return.
J7
I
AVSC
C signal return.
G1
I
XTI
External clock input
H1
O
XTO
External clock output
J1
I
SCLK
The MPU Serial interface Clock Line.
H2
I/O
SDAT
The MPU Serial interface Data Line.
J2
I
SIAD0
The MPU interface address select pin 0. This pin is used to select one of the two
addresses that chip will respond. It is internally pulled down to ground.
Clock Signals
Host Interface
General signals
G3
I
RSTB
Reset input. Low active.
G2
I
PDN
Power down control pin. It is high active.
K1
I
TMODE
Test pin. It should be low for normal operation.
H3
-
TEST2
NC pin.
C3, C7,
H6
-
NC
NC pin.
Video output Signals
B4
O
HS
Horizontal sync and multi-purpose output pin. See register for control
A3
O
VS
Vertical Sync and multi-purpose output. See register for control information.
B3
O
FLD
Field indicator and multi-purpose output pin. See register for control information.
C4
O
DVALID
Data valid flag and multi-purpose output pin. See register for control information.
A2
O
MPOUT
Multi-purpose output pin.
TECHWELL, INC.
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B2
O
CLKX1
Multi-function clock output pin.
A1
O
CLKX2
Multi-function clock output pin.
B1
O
VD[19]
Digitized Video Data Outputs of Y/YCbCr. VD[10] is the LSB and VD[19] is the
MSB.
C2
O
VD[18]
Digitized Video Data Outputs of Y/YCbCr.
D3
O
VD[17]
Digitized Video Data Outputs of Y/YCbCr.
C1
O
VD[16]
Digitized Video Data Outputs of Y/YCbCr.
D2
O
VD[15]
Digitized Video Data Outputs of Y/YCbCr.
D1
O
VD[14]
Digitized Video Data Outputs of Y/YCbCr.
E2
O
VD[13]
Digitized Video Data Outputs of Y/YCbCr.
E1
O
VD[12]
Digitized Video Data Outputs of Y/YcbCr.
F1
O
VD[11]
Digitized Video Data Outputs of Y/YcbCr.
F2
O
VD[10]
Digitized Video Data Outputs of Y/YcbCr.
K2
I/O
VD[9]
Digitized video data output of CbCr. VD[9] is the MSB and VD[0] is the LSB.
J3
I/O
VD[8]
Digitized video data output of CbCr.
H4
I/O
VD[7]
Digitized video data output of CbCr.
K3
I/O
VD[6]
Digitized video data output of CbCr.
J4
I/O
VD[5]
Digitized video data output of CbCr.
K4
I/O
VD[4]
Digitized video data output of CbCr.
J5
I/O
VD[3]
Digitized video data output of CbCr.
K5
I/O
VD[2]
Digitized video data output of CbCr.
K6
I/O
VD[1]
Digitized video data output of CbCr.
J6
I/O
VD[0]
Digitized video data output of CbCr.
Audio Clock Signals
A4
I
AMXCLK
Audio clock input. It should be connected to AMCLK in normal operation.
A5
O
AMCLK
Field locked audio clock output
B5
O
ASCLK
Audio bit serial clock
A6
O
ALRCLK
Audio frame clock
Encoder
Pin#
I/O
Pin Name
Description
Analog output Signals
G10
O
CVBS
CVBS/Y output pin. A load resistor is required.
F9
O
COUT
Chroma output pin. A load resistor is required.
F10
O
YOUT
Y output pin. A load resistor is required.
E10
O
CBOUT
Cb output pin. A load resistor is required.
E9
O
CROUT
Cr output pin. A load resistor is required.
TECHWELL, INC.
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TW9920
Pin#
D10
I/O
I
Pin Name
Description
RSET
DAC current setting resistor pin. NC pin.
Digital Video Input
C10
I
PD[9]
Encoder data input bus. PD[9] is MSB and PD[0] is LSB.
C9
I
PD[8]
Encoder data input bus
B10
I
PD[7]
Encoder data input bus
B9
I
PD[6]
Encoder data input bus
A10
I
PD[5]
Encoder data input bus
A9
I
PD[4]
Encoder data input bus
B8
I
PD[3]
Encoder data input bus
A8
I
PD[2]
Encoder data input bus
B7
I
PD[1]
Encoder data input bus
A7
I
PD[0]
Encoder data input bus
B6
I
PDCLK
Encoder data input clock.
Power and Ground Pins
Pin#
I/O
Pin Name
Description
E3, G4,
G6, C6
I
VDD
2.5V digital core power.
E4, F5,
F6, E6,
D6
I
VSS
2.5V digital core return
F3, H5,
C5. D4
I
VDDE
3.3V digital I/O power.
E5, F4,
G5, D5
I
VSSE
3.3V digital I/O return
H7, G8,
I
AVDD
2.5V analog ADC supply
G7, H8
I
AVSS
2.5V analog ADC return
D7, D8
I
AVDDC
2.5V analog DAC supply
E7, D9
I
AVSSC
2.5V analog DAC return
E8, C8
I
AVSSC
2.5V analog DAC return
F8
I
DVDD
2.5V digital ADC and DAC supply
F7
I
DVSS
2.5V digital ADC and DAC return
TECHWELL, INC.
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Parametric Information
AC/DC Electrical Parameters
Table 21. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
AVDD (measured to AVSS)
V DD (measured to DVSS)
Voltage on any signal pin (See the note below)
VDDAM
VDDM
-
-
-
2.7
2.7
V
V
V
-
Analog Input Voltage
Storage Temperature
Junction Temperature
Vapor Phase Soldering(15 Seconds)
TS
TJ
T VSOL
DVSS –
0.5
AVSS –
0.5
–65
-
-
VDDAM +
0.5
VDDM +
0.5
+150
+125
+220
V
°C
°C
°C
NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress
rating only, and functional operation at these or any other conditions above those listed in the
operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
This device employs high-impedance CMOS devices on all signal pins. It must be handled as an
ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more
than +0.5 V or drops below ground by more than 0.5 V can induce destructive latchup.
Table 22. characteristics
Parameter
Symbol
Min
Typ
VDDE
VDDA
VDD
3.15
2.4
2.3
-
3.3
2.5
2.5
-
3.6
2.8
2.6
0.3
V
V
V
V
0.5
1.00
2.00
V
0.5
1.00
2.00
V
176
+70
-
15
52
-
°C
mA
MA
MA
MA
2.0
-
V DDM +
0.5
0.8
Supply
Power Supply — IO
Power Supply — Analog
Power Supply — Digital
Maximum |V DD – AVDD|
MUX0, MUX1 , MUX2 and MUX3 Input Range
(AC coupling required)
CIN0 and CIN1 Amplitude Range (AC coupling
required)
Ambient Operating Temperature
Analog Supply current
TA
Iaa
Digital Supply current
Digital Core Supply Current
Idd
Digital Inputs
Input High Voltage (TTL)
V IH
0
-
Input Low Voltage (TTL)
V IL
-
-
Input High Voltage (XTI)
V IH
2.0
-
Input Low Voltage (XTI)
V IL
VSS -0.5
-
TECHWELL, INC.
84
Max
V DDM +
0.5
1.0
Units
V
V
V
V
REV. D
08/29/2005
TW9920
-
10
µA
-
-
–10
µA
-
5
-
pF
Symbol
Min
Typ
Digital Outputs
Output High Voltage (I OH = –4 mA)
V OH
2.4
-
V DD
V
Output Low Voltage (I OL = 4 mA)
V OL
-
0.2
0.4
V
3-State Current
I OZ
-
-
10
µA
Output Capacitance
CO
-
5
-
pF
Vi
CA
-
1
7
-
Vpp
pF
ADCR
AINL
-
10
±1
-
bits
LSB
ADNL
-
LSB
24
-
±1
27
10
-
fADC
BW
30
-
MHz
MHz
fLN
fLN
∆fH
-
15.625
15.734
-
6.2
KHz
KHz
%
fSC
fSC
fSC
fSC
-
∆fH
±450
3579545
4433619
3575612
3582056
-
-
Hz
Hz
Hz
Hz
Hz
-
27
-
-
MHz
ppm
0
-
20
80
-
27
-
-
-
Input High Current (V IN =V DD )
I IH
-
Input Low Current (V IN =VSS)
I IL
Input Capacitance (f=1 MHz, V IN =2.4 V)
C IN
Parameter
Analog Input
Analog Pin Input voltage
Analog Pin Input Capacitance
ADCs
ADC resolution
ADC integral Non-linearity
ADC differential non-linearity
ADC clock rate
Video bandwidth (-3db)
Horizontal PLL
Line frequency (50Hz)
Line frequency (60Hz)
static deviation
Subcarrier PLL
subcarrier frequency (NTSC-M)
subcarrier frequency (PAL-BDGHI)
subcarrier frequency (PAL-M)
subcarrier frequency (PAL-N)
lock in range
Crystal spec
nominal frequency (fundamental)
deviation
Temperature range
load capacitance
series resistor
Ta
CL
RS
Oscillator Input
nominal frequency
deviation
duty cycle
TECHWELL, INC.
85
Max
±50
70
-
±25
55
Units
o
C
pF
Ohm
MHz
ppm
%
REV. D
08/29/2005
TW9920
Parameter
Symbol
Output CLK
CLKX1
CLKX2
CLKX1 Duty Cycle
CLKX2 Duty Cycle
CLKX2 to CLKX1 Delay
CLKX1 to Data Delay
CLKX2 to Data Delay
CLKX1 (Falling Edge) to VCLK (Rising Edge)
CLKX2 (Falling Edge) to VCLK (Rising Edge)
Output Video Data
10-bit Mode (1)
Data to VCLK (Rising Edge) Delay
VCLK (Rising Edge) to Data Delay
20-bit Mode (1)
Data to VCLK (Rising Edge) Delay
VCLK (Rising Edge) to Data Delay
Min
Typ
Max
Units
4
5
6
41
42
12
24
-
13.5
27
5
5
0
0
15
30
55
55
2
-
MHz
MHz
%
%
ns
ns
ns
ns
ns
7b
8b
-
18
18
-
ns
ns
7a
8a
-
37
37
-
ns
ns
Clock Timing Diagram
1
3
2
XT
(10-bit
output
mode)
VCLK
Data
7b
6
8b
42
CLKX2
4
(20-bit
output
mode)
41
CLKX1
VCLK
5
Data
7a
TECHWELL, INC.
86
8a
REV. D
08/29/2005
TW9920
Mechanical Data
100L VFBGA Package Mechanical Drawing: Package Size: 8x8x1.0 mm
TOP VIEW
BOTTOM VIEW
∅0.08
∅0.15
A1 CORNER
M
M
C
CAB
A1 CORNER
∅0.27~0.37(100X)
1
2
3
4
5
6
7
8
9
10
A
A
B
B
C
C
D
D
E
E
E1
E
F
F
G
G
H
H
J
J
K
K
A
b
e
A2
// 0.10 C
D
D1
B
0.15(4X) C
A
A3
SEATING PLANE
A1
C
UNIT
D1
D
E1
E
A
A1
A2
A3
b
e
mm
8±0.05
6.75
8±0.05
6.75
1.0 MAX
0.18~0.28
0.45
0.21
0.3
0.75
TECHWELL, INC.
87
REV. D
08/29/2005
TW9920
Copyright Notice
This manual is copyrighted by Techwell, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the express written permission of Techwell,
Inc.
Disclaimer
This document provides technical information for the user. Techwell, Inc. reserves the right to
modify the information in this document as necessary. The customer should make sure that they
have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that
may appear in this document. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third
parties and does not infringe upon or assist others to infringe upon such rights.
Life Support Policy
Techwell, Inc. products are not authorized for use as critical components in life support devices or
systems.
Revision history
Revision
Date
File name
REV. C1
4/08/2005
TW9920CSPEC0408.PDF
REV.D
08/02/2005
TECHWELL, INC.
Supply Currents are added.
Revision D
88
REV. D
08/29/2005