Low Distortion, High Speed Rail-to-Rail Input/Output Amplifier AD8065-KGD-CHIP Known Good Die FEATURES GENERAL DESCRIPTION FET input amplifier 1 pA input bias current Low cost High speed: 145 MHz, −3 dB bandwidth (G = +1) 180 V/µs slew rate (G = +2) Low noise 7 nV/√Hz (f = 10 kHz) 0.6 fA/√Hz (f = 10 kHz) Wide supply voltage range: 5 V to 24 V Single-supply and rail-to-rail output Low offset voltage 1.5 mV maximum High common-mode rejection ratio: −100 dB SFDR −88 dBc @ 1 MHz Low power: 6.4 mA/amplifier typical supply current Known good die (KGD): these die are fully guaranteed to data sheet specifications The AD8065-KGD-CHIP FastFET™ amplifier is a voltage feedback amplifier with a FET input offering high performance and ease of use. With a wide supply voltage range from 5 V to 24 V, and the ability to operate on single supplies, with a bandwidth of 145 MHz, the AD8065-KGD-CHIP is designed to work in a variety of applications. For added versatility, the amplifier also features a rail-to-rail output. APPLICATIONS Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/µs, excellent distortion (SFDR of −88 dBc at 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065-KGD-CHIP operates using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current. The AD8065-KGD-CHIP is rated to work over the industrial temperature range of −40°C to +85°C. Photodiode preamps Filters A/D drivers Level shifting Buffering Additional application and technical information can be found in the AD8065 data sheet. Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1 1 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8065-KGD-CHIP Known Good Die TABLE OF CONTENTS Features ...................................................................................... 1 ESD Caution .......................................................................... 5 Applications ............................................................................... 1 Pad Configuration and Function Descriptions .................... 6 General Description ................................................................. 1 Outline Dimensions ................................................................. 7 Revision History ....................................................................... 2 Die Specifications and Assembly Recommendations ...... 7 Specifications............................................................................. 3 Ordering Guide ..................................................................... 7 Absolute Maximum Ratings .................................................... 5 REVISION HISTORY 10/12—Revision 0: Initial Version Rev. 0 | Page 2 of 8 Known Good Die AD8065-KGD-CHIP SPECIFICATIONS VS = ±5 V at TA = 30°C, RL = 1 kΩ to midsupply, G = 1, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Test Conditions/Comments Min Typ G = +1, VO = 0.2 V p-p G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, −5.5 V to +5.5 V G = −1, −5.5 V to +5.5 V G = +2, VO = 4 V step G = +2, VO = 2 V step G = +2, VO = 8 V step 100 145 50 42 7 175 170 180 55 205 130 fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 8 V p-p fC = 10 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω −88 −67 −73 24 7 0.6 0.02 0.02 VCM = 0 V 0.4 1 2 25 1 1 113 TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio 1 TMIN to TMAX VO = ±3 V, RL = 1 kΩ 100 Max Status Unit GBD 1 MHz MHz MHz MHz ns ns V/µs ns ns GBD1 dBc dBc dBc dBm nV/√Hz fA/√Hz % Degrees 1.5 17 Tested GBD1 Tested 1000 || 2.1 1000 || 4.5 VCM = −1 V to +1 V RL = 1 kΩ GΩ || pF GΩ || pF −5 to +1.7 −85 −5.0 to +2.4 −100 GBD1 Tested V dB −4.88 to +4.9 −4.94 to +4.95 Tested V RL = 150 Ω VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30% overshoot G = +1 −4.8 to +4.7 35 V mA 90 20 mA pF 5 VS ± 2 V mV µV/°C pA pA pA pA dB −85 GBD = Guaranteed By Design. Rev. 0 | Page 3 of 8 6.4 −100 24 7.2 Tested Tested Tested V mA dB AD8065-KGD-CHIP Known Good Die VS = ±12 V at TA = 30°C, RL = 1 kΩ to midsupply, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range FET Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY Power Supply Rejection Ratio Quiescent Current per Amplifier 1 Test Conditions/Comments Min Typ G = +1, VO = 0.2 V p-p G = +2, VO = 4 V step 100 130 145 180 Status Unit GBD 1 GBD1 MHz V/µs VO = ±10 V 103 0.4 1 3 2 114 Tested GBD1 Tested mV µV/°C pA pA dB VCM = −1 V to +1 V −12 to +8.5 −85 −12.0 to +9.5 −100 GBD1 Tested V dB RL = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 Tested V VS ± 2 V −84 −93 6.6 7.4 Tested Tested dB mA Max Status Unit GBD 1 GBD1 MHz V/µs Tested GBD1 Tested mV µV/°C pA pA dB VCM = 0 V Max 1.5 17 GBD = Guaranteed By Design. VS = +5 V at TA = 30°C, RL = 1 kΩ to midsupply, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range FET Input Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY Power Supply Rejection Ratio Quiescent Current per Amplifier 1 Test Conditions/Comments Min Typ G = +1, VO = 0.2 V p-p G = +2, VO = 2 V step 125 105 155 160 VO = 1 V to 4 V 100 0.4 1 1 1 113 VCM = 1 V to 2 V 0 to 1.7 −78 0 to 2.4 −91 GBD1 Tested V dB RL = 1 kΩ 0.1 to 4.85 0.03 to 4.95 Tested V VS ± 2 V −78 −100 6.4 Tested Tested dB mA VCM = 1.0 V GBD = Guaranteed by Design. Rev. 0 | Page 4 of 8 1.5 17 7.0 Known Good Die AD8065-KGD-CHIP ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 4. Parameter Supply Voltage Common-Mode Input Voltage Differential Input Voltage Storage Temperature Operating Temperature Range Junction Temperature Rating 26.4 V VEE − 0.5 V to VCC + 0.5 V ±1.8 V –65°C to +125°C –40°C to +105°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 8 AD8065-KGD-CHIP Known Good Die PAD CONFIGURATION AND FUNCTION DESCRIPTIONS 2 7 6 4 NC 11011-001 3 Figure 1. AD8065 Die Pad Configuration Table 5. Pad Function Descriptions Pad No. 2 3 4 6 7 X-Axis −485 −485 201 343 485 Y-Axis 254 −172 −301 −189 25 Mnemonic −IN +IN −VS VOUT +VS Rev. 0 | Page 6 of 8 Description Inverting Input. Noninverting Input. Negative Supply. Output. Positive Supply. Known Good Die AD8065-KGD-CHIP OUTLINE DIMENSIONS 0.483 1.205 2 7 3 6 0.885 NC TOP VIEW (CIRCUIT SIDE) SIDE VIEW 0.092 × 0.092 08-31-2012-A 4 Figure 2. 6-Pad Bare Die [CHIP] (C-6-5) Dimensions shown in millimeters DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS Table 6. Typical Die Specifications Parameter Chip Size Die Size Thickness Bond Pads (Min Size) Bond Pad Composition Backside Passivation ESD Value 1205 × 855 47.4 × 33.7 483 92 × 92 1% Copper Doped Aluminum Si Doped oxide/SiN HBM 1000 Unit μm Mil μm μm % Not Applicable Not Applicable V Table 7. Assembly Recommendations Assembly Component Die Attach Bonding Method Recommendation Ablestik 84-1LMIS R4 1 mil gold ORDERING GUIDE Model AD8065-KGD-CHIP Temperature Range –40°C to +85°C Package Description 6-Pad Bare Die [CHIP] Rev. 0 | Page 7 of 8 Package Option C-6-5 AD8065-KGD-CHIP Known Good Die NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11011-0-10/12(0) Rev. 0 | Page 8 of 8