Obsolete Device 24LC164 16K 2.5V Cascadable I2C™ Serial EEPROM FEATURES PDIP VCC 7 WP 6 SCL 4 5 SDA A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA 1 A1 2 A2 3 VSS SOIC 24LC164 BLOCK DIAGRAM WP A2 A1 A0 HV GENERATOR I/O CONTROL LOGIC DESCRIPTION The Microchip Technology Inc. 24LC164 is a cascadable 16 Kbit Electrically Erasable PROM (EEPROM). The device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and active currents of only 5 µA and 1 mA respectively. The 24LC164 also has a page-write capability for up to 16 bytes of data. The 24LC164 is available in the standard 8-pin DIP and 8-lead surface mount SOIC packages. 8 A0 24LC164 • Single supply with operation down to 2.5V • Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V - 5 µA standby current typical at 3.0V • Organized as eight blocks of 256 bytes (8 x 256 x 8) • 2-wire serial interface bus, I2C™ compatible • Functional address inputs for cascading up to 8 devices • Schmitt trigger, filtered inputs for noise suppression • Output slope control to eliminate ground bounce • 100 kHz (2.5V) and 400 kHz (5V) compatibility • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 16 bytes • 2 ms typical write cycle time for page-write • Hardware write protect for entire memory • Can be operated as a serial ROM • Factory programming (QTP) available • ESD protection > 4,000V • 1,000,000 Erase/Write cycles guaranteed • Data retention > 200 years • 8-pin DIP, 8-lead SOIC packages • Available temperature ranges: - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C PACKAGE TYPES MEMORY CONTROL LOGIC XDEC EEPROM ARRAY (8 x 256 x 8) PAGE LATCHES SDA SCL YDEC VCC VSS SENSE AMP R/W CONTROL The three select pins, A0, A1 and A2, function as chip select inputs and allow up to eight devices to share a common bus, for up to 128 Kbits total system EEPROM. I2C is a trademark of Philips Corporation. 2004 Microchip Technology Inc. DS21093I-page 1 24LC164 1.0 ELECTRICAL CHARACTERISTICS 1.1 TABLE 1-1: PIN FUNCTION TABLE Name Maximum Ratings* VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.3V to VCC +1.0V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD protection on all pins ..................................................≥ 4 kV Function VSS Ground SDA Serial Address/Data I/O SCL Serial Clock WP Write Protect Input VCC +2.5V to 5.5V Power Supply A0, A1, A2 Chip Address Inputs *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC CHARACTERISTICS VCC = +2.5V to +5.5V Commercial (C): Industrial (I): Parameter Symbol Min. High level input voltage VIH Low level input voltage VIL TAMB = 0°C to +70°C TAMB = -40°C to +85°C Max. Units Conditions .7 VCC — V — — .3 VCC V — VHYS .05 VCC — V (Note) VOL — .40 V IOL = 3.0 mA, VCC = 2.5V Input leakage current ILI -10 10 µA VIN = 0.1V to VCC Output leakage current ILO -10 10 µΑ VOUT = 0.1V to VCC Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note) TAMB = 25°C, FCLK = 1MHz Operating current ICC Write ICC Read — — 3 1 mA mA VCC = 5.5V, SCL = 400 kHz ICCS — — 30 100 µΑ µΑ VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC A0 = A1 = A2 = WP = VSS WP, SCL and SDA pins: Hysteresis of Schmitt trigger inputs Low level output voltage Standby current Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START DS21093I-page 2 STOP 2004 Microchip Technology Inc. 24LC164 TABLE 1-3: AC CHARACTERISTICS STANDARD MODE Parameter VCC = 4.5V - 5.5V FAST MODE Symbol Min. Max. Min. Max. Units Clock frequency FCLK — 100 — 400 kHz — Clock high time THIGH 4000 — 600 — ns — Clock low time TLOW 4700 — 1300 — ns — SDA and SCL rise time TR — 1000 — 300 ns (Note 1) SDA and SCL fall time TF — 300 — 300 ns (Note 1) THD:STA 4000 — 600 — ns After this period the first clock pulse is generated START condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated START condition 0 — 0 — ns — START condition hold time Data input hold time THD:DAT Remarks Data input setup time TSU:DAT 250 — 100 — ns — STOP condition setup time TSU:STO 4000 — 600 — ns — TAA — 3500 — 900 ns (Note 2) Bus free time Output valid from clock TBUF 4700 — 1300 — ns Time the bus must be free before a new transmission can start Output fall time from VIH min to VIL max TOF — 250 20 + 0.1 Cb 250 ns (Note 1), CB ≤ 100 pF Input filter spike suppression (SDA and SCL pins) TSP — 50 — 50 ns (Note 3) Write cycle time TWR — 10 — 10 ms Byte or Page mode — 1M — 1M — Endurance cycles 25°C, VCC = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s website at www.microchip.com. FIGURE 1-2: BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TBUF TAA TAA SDA OUT 2004 Microchip Technology Inc. DS21093I-page 3 24LC164 2.0 FUNCTIONAL DESCRIPTION The 24LC164 supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter and if receiving data, as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions, while the 24LC164 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.. Note: Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 3.4 The 24LC164 does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC164) will leave the data line HIGH to enable the master to generate the STOP condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (D) (C) (A) SCL SDA DS21093I-page 4 DATA ALLOWED TO CHANGE STOP CONDITION 2004 Microchip Technology Inc. 24LC164 3.6 Device Addressing A control byte is the first byte received following the start condition from the master device. The first bit is always a one. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used to select which of the eight devices are to be accessed. The A1 bit must be the inverse of the A1 device select pin. The next three bits of the control byte are the block select bits (B2, B1, B0). They are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to one, a read operation is selected. When set to ‘0’ a write operation is selected. Following the start condition, the 24LC164 looks for the slave address for the device selected. Depending on the state of the R/W bit, the 24LC164 will select a read or write operation. Operation Control Code Block Select R/W Read 1 A2 A1 A0 Block Address 1 Write 1 A2 A1 A0 Block Address 0 FIGURE 3-2: CONTROL BYTE ALLOCATION START READ/WRITE SLAVE ADDRESS 1 A2 A1 A0 B2 MSB 2004 Microchip Technology Inc. R/W B1 B0 LSB A 4.0 WRITE OPERATION 4.1 Byte Write Following the start condition from the master, the device code (4 bits), the block address (3 bits) and the R/W bit, which is a logic LOW, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC164. After receiving another acknowledge signal from the 24LC164, the master device will transmit the data word to be written into the addressed memory location. The 24LC164 acknowledges again and the master generates a stop condition. This initiates the internal write cycle. During this time the 24LC164 will not generate acknowledge signals (Figure 4-1). 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC164 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 16 data bytes to the 24LC164 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remains constant. If the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2). Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. DS21093I-page 5 24LC164 FIGURE 4-1: BUS ACTIVITY MASTER SDA LINE BYTE WRITE S T A R T CONTROL BYTE S 1 A A 2 1 SDA LINE BUS ACTIVITY DS21093I-page 6 P A C K FIGURE 4-2: S T O P DATA A B B B 0 2 1 0 BUS ACTIVITY BUS ACTIVITY MASTER WORD ADDRESS A C K A C K PAGE WRITE S T A R T CONTROL BYTE S A A A B B B 2 1 0 2 1 0 WORD ADDRESS (n) DATA (n + 1) DATA (n) S T O P DATA (n + 15) P A C K A C K A C K A C K A C K 2004 Microchip Technology Inc. 24LC164 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command 7.0 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 7.1 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC164 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a ‘1’. The 24LC164 will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC164 discontinues transmission (Figure 7-2). Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 No Yes Next Operation 6.0 Current Address Read The 24LC164 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the 24LC164 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC164 discontinues transmission (Figure 7-1). 7.2 Did Device Acknowledge (ACK = 0)? READ OPERATION WRITE PROTECTION The 24LC164 can be used as a serial ROM when the WP pin is connected to VCC. Programming will be inhibited and the entire memory will be write-protected. 7.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24LC164 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC164 to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24LC164 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows an entire device memory contents to be serially read during one operation. 7.4 Noise Protection The 24LC164 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 2004 Microchip Technology Inc. DS21093I-page 7 24LC164 FIGURE 7-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S 1 A2A1A0B2B1B0 CONTROL BYTE DATA (n) P S T A R T CONTROL BYTE S T A R T WORD ADDRESS (n) S 1 A2 A1A0B2B1B0 S T O P DATA (n) P A C K A C K BUS ACTIVITY CONTROL BYTE S SDA LINE BUS ACTIVITY MASTER A C K RANDOM READ BUS ACTIVITY MASTER FIGURE 7-3: N O A C K BUS ACTIVITY FIGURE 7-2: S T O P A C K N O A C K SEQUENTIAL READ CONTROL BYTE DATA (n) DATA (n + 1) DATA (n + 2) S T O P DATA (n + X) SDA LINE BUS ACTIVITY P A C K A C K A C K A C K N O A C K 8.0 PIN DESCRIPTIONS 8.3 8.1 SDA Serial Address/Data Input/ Output This pin must be connected to either VSS or VCC. WP If tied to VSS, normal memory operation is enabled (read/write the entire memory 000-7FF). This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pullup resistor to VCC (typical 10kΩ for 100 kHz, 2kΩ for 400 kHz). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. For normal data transfer SDA is allowed to change only during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions. 8.4 8.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. This feature allows the user to use the 24LC164 as a serial ROM when WP is enabled (tied to VCC). A0, A1, A2 These pins are used to configure the proper chip address in multiple-chip applications (more than one 24LC164 on the same bus). The levels on these pins are compared to the corresponding bits in the slave address. The chip is selected if the compare is true. Note: The level on A1 is compared to the inverse of the slave address. Up to eight 24LC164s may be connected to the same bus. These pins must be connected to either VSS or VCC. DS21093I-page 8 2004 Microchip Technology Inc. 24LC164 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN YYWW 24LC164 XXXXXNNN 0025 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: XX...X YY WW NNN Note: * Example 24LC164 XXXX0025 NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. DS21093I-page 9 24LC164 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21093I-page 10 2004 Microchip Technology Inc. 24LC164 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2004 Microchip Technology Inc. DS21093I-page 11 24LC164 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Explorer. Files are also available for FTP download from our FTP site. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events DS21093I-page 12 2004 Microchip Technology Inc. 24LC164 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: 24LC164 Y N Literature Number: DS21093I Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? 2004 Microchip Technology Inc. DS21093I-page 13 24LC164 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Device 24LC164: VDD range 2.5V to 5.5V 24LC164T: (Tape and Reel) Temperature Range I = = 0°C to +70°C -40°C to +85°C Package P SN = = Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Pattern QTP, SQTP or Special Requirements. Blank for standard devices. Examples: a) 24LC164–/P Commercial Temp, PDIP package b) 24LC164–/SN Commercial Temp., SOIC package Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21093I-page 14 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21093I-page 15 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Singapore Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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