Precision Low Power Single-Supply JFET Amplifiers AD8625/AD8626/AD8627 Data Sheet FEATURES PIN CONFIGURATIONS 8-Lead SOIC (R-8 Suffix) SC70 package Very low IB: 1 pA max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±13 V Rail-to-rail output Low supply current: 630 μA/amp typ Low offset voltage: 500 μV max Unity gain stable No phase reversal 8 NC NC 1 –IN 2 +IN 3 5-Lead SC70 (KS Suffix) OUT A 1 V– 2 +IN 3 7 V+ AD8627 V– 4 6 OUT 5 5 V+ AD8627 4 –IN NC NC = NO CONNECT 8-Lead SOIC (R-8 Suffix) 8 V+ OUT A 1 Photodiode amplifiers ATEs Line-powered/battery-powered instrumentation Industrial controls Automotive sensors Precision filters Audio –IN A 2 +IN A 3 7 OUT B AD8626 V– 4 6 –IN B 5 OUT A –IN A +IN A V– 14 OUT D –IN A 2 13 –IN D AD8625 4 5 V+ OUT B –IN B +IN B 14-Lead TSSOP (RU-Suffix) OUT A 1 V+ 4 8 AD8626 +IN B 14-Lead SOIC (R-Suffix) +IN A 3 1 12 +IN D 11 V– +IN B 5 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C OUT A –IN A +IN A V+ +IN B –IN B OUT B 1 14 AD8625 7 8 OUT D –IN D +IN D V– +IN C –IN C OUT C 03023-001 APPLICATIONS 8-Lead MSOP (RM-Suffix) Figure 1. GENERAL DESCRIPTION The AD862x is a precision JFET input amplifier. It features true single-supply operation, low power consumption, and rail-to-rail output. The outputs remain stable with capacitive loads of over 500 pF; the supply current is less than 630 μA/amp. Applications for the AD862x include photodiode transimpedance amplification, ATE reference level drivers, battery management, both line powered and portable instrumentation, and remote sensor signal conditioning, which includes automotive sensors. The 5 MHz bandwidth and low offset are ideal for precision filters. The AD862x is fully specified over the industrial temperature range. (−40°C to +85°C). The AD8627 is available in both 5-lead SC70 and 8-lead SOIC surface-mount packages (SC70 packaged parts are available in tape and reel only). The AD8626 is available in MSOP and SOIC packages, while the AD8625 is available in TSSOP and SOIC packages. The AD862x’s ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables it to be used to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8625/AD8626/AD8627 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications ....................................................................................... 1 Applications Information .............................................................. 13 Pin Configurations ........................................................................... 1 Minimizing Input Current ........................................................ 15 General Description ......................................................................... 1 Photodiode Preamplifier Application...................................... 15 Revision History ............................................................................... 2 Output Amplifier for DACs ...................................................... 16 Specifications..................................................................................... 3 Eight-Pole Sallen Key Low-Pass Filter ..................................... 17 Electrical Characteristics ............................................................. 3 Outline Dimensions ....................................................................... 18 Absolute Maximum Ratings ............................................................ 5 Ordering Guide .......................................................................... 20 ESD Caution .................................................................................. 5 REVISION HISTORY 5/13—Rev. E to Rev. F 1/04—Rev. A to Rev. B Changes to Applications Information Section............................ 13 Changes to Ordering Guide .......................................................... 20 Change to General Description .......................................................1 Change to Figure 10 ..........................................................................7 Change to Figure13 ...........................................................................7 Change to Figure 37 ....................................................................... 11 Changes to Figure 38...................................................................... 12 Change to Output Amplifier for DACs Section ......................... 15 Updated Outline Dimensions ....................................................... 19 12/10—Rev. D to Rev. E Removed Table Summary Conditions Above Table 3 ................. 5 Updated Outline Dimensions ....................................................... 18 3/09—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 11/04—Rev. B to Rev. C Updated Figure Codes ....................................................... Universal Changes to Figure 17 and 18 ........................................................... 8 Changes to Figure 33 and Figure 37............................................. 11 Changes to Figure 38 ...................................................................... 12 Changes to Figure 39 and Figure 40............................................. 13 Changes to Figure 41 to Figure 44 ................................................ 14 10/03—Rev. 0 to Rev. A Addition of Two New Parts ............................................... Universal Change to General Description .......................................................1 Changes to Pin Configurations .......................................................1 Change to Specifications Table ........................................................3 Changes to Figure 31...................................................................... 10 Changes to Figure 32...................................................................... 11 Changes to Figure 38...................................................................... 12 Changes to Figure 46...................................................................... 16 Changes to Figure 47...................................................................... 16 Changes to Figure 49...................................................................... 17 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 Rev. F | Page 2 of 20 Data Sheet AD8625/AD8626/AD8627 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @VS = 5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 0.05 0.5 1.2 1 60 0.5 25 3 87 230 2.5 mV mV pA pA pA pA V dB V/mV µV/°C ±10 V V V V mA −40°C < TA < +85°C Input Bias Current IB 0.25 –40°C < TA < +85°C Input Offset Current IOS –40°C < TA < +85°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High CMRR AVO ∆VOS/∆T VCM = 0 V to 2.5 V RL = 10 kΩ, VO = 0.5 V to 4.5 V –40°C < TA < +85°C VOH IL = 2 mA, –40°C < TA < +85°C Output Voltage Low 0 66 100 4.92 4.90 VOL 0.075 0.08 IL = 2 mA, –40°C < TA < +85°C Output Current POWER SUPPLY Power-Supply Rejection Ratio Supply Current/Amplifier IOUT PSRR ISY VS = 5 V to 26 V 80 104 630 –40°C < TA < +85°C DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Channel Separation SR GBP ØM en p-p en in Cs 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f = 1 kHz Rev. F | Page 3 of 20 785 800 dB µA µA 5 5 60 V/µs MHz Degrees 1.9 17.5 0.4 104 µV p-p nV/√Hz fA/√Hz dB AD8625/AD8626/AD8627 Data Sheet @VS = ±13 V; VCM = 0 V; TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 0.35 0.75 1.35 1 60 0.5 25 +11 105 310 2.5 mV mV pA pA pA pA V dB V/mV µV/°C ±15 V V V V mA –40°C < TA < +85°C Input Bias Current IB 0.25 –40°C < TA < +85°C Input Offset Current IOS –40°C < TA < +85°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current POWER SUPPLY Power-Supply Rejection Ratio Supply Current/Amplifier CMRR AVO ∆VOS/∆T VOH VOH VOL VOL IOUT PSRR ISY VCM = –13 V to +10 V RL = 10 kΩ, VO = –11 V to +11 V –40°C < TA < +85°C IL = 2 mA, –40°C < TA < +85°C –13 76 150 +12.92 +12.91 –12.92 –12.91 IL = 2 mA, –40°C < TA < +85°C VS = ±2.5 V to ±13 V 80 104 710 –40°C < TA < +85°C DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Channel Separation SR GBP ØM en p-p en in Cs 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f = 1 kHz Rev. F | Page 4 of 20 850 900 dB µA µA 5 5 60 V/µs MHz Degrees 2.5 16 0.5 105 µV p-p nV/√Hz fA/√Hz dB Data Sheet AD8625/AD8626/AD8627 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range, R Package Operating Temperature Range Junction Temperature Range, R Package Lead Temperature Range (Soldering, 60 sec) Ratings 27 V VS– to VS+ ± Supply Voltage Indefinite −65°C to +125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified for worst-case conditions when devices are soldered in circuit boards for surface-mount packages. Table 4. Package Type 5-Lead SC70 (KS) 8-Lead MSOP (RM) 8-Lead SOIC (R) 14-Lead SOIC (R) 14-Lead TSSOP (RU) ESD CAUTION Rev. F | Page 5 of 20 θJA 376 210 158 120 180 θJC 126 45 43 36 35 Unit °C/W °C/W °C/W °C/W °C/W AD8625/AD8626/AD8627 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 16 VSY = ±12V TA = 25°C VSY = +3.5V/–1.5V 14 20 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 25 15 10 12 10 8 6 4 5 –600 –400 –200 0 200 400 0 600 03023-005 03023-002 0 1 2 Figure 2. Input Offset Voltage 50 VSY = ±13V 40 6 7 8 9 10 VSY = ±13V TA = 25°C 6 4 03023-003 0 1 2 3 4 5 6 7 8 9 20 10 0 –10 –20 –30 03023-006 8 2 –40 –50 –15.0–12.5–10.0 –7.5 –5.0 –2.5 0 2.5 VCM (V) 10 OFFSET VOLTAGE (µV/°C) 5.0 7.5 10.0 12.5 15.0 Figure 6. Input Bias Current vs. VCM Figure 3. Offset Voltage Drift 0 18 VSY = +3.5V/–1.5V –0.1 14 –0.2 INPUT BIAS CURRENT (pA) 16 12 10 8 6 4 03023-004 NUMBER OF AMPLIFIERS 5 30 INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS 10 2 0 4 Figure 5. Offset Voltage Drift 12 0 3 OFFSET VOLTAGE (µV/°C) VOLTAGE (µV) –400 –300 –200 –100 0 100 200 VSY = ±13V TA = 25°C –0.3 –0.4 –0.5 –0.6 –0.7 03023-007 0 2 –0.8 –0.9 2.5 –15.0–12.5–10.0 –7.5 –5.0 –2.5 0 VCM (V) 300 VOLTAGE (µV) Figure 4. Input Offset Voltage 5.0 7.5 10.0 12.5 15.0 Figure 7. Input Bias Current vs. VCM Rev. F | Page 6 of 20 Data Sheet AD8625/AD8626/AD8627 100 500 VSY = 5V 10 1 0.1 –50 125 100 50 75 25 TEMPERATURE (°C) 0 –25 300 200 100 0 –100 –200 –300 03023-011 INPUT OFFSET VOLTAGE (µV) 400 03023-008 INPUT BIAS CURRENT (pA) VSY = ±13V VCM = 0V –400 –500 –1 150 0 1 2 3 4 VCM (V) Figure 8. Input Bias Current vs. Temperature Figure 11. Input Offset Voltage vs. VCM 10M 2.0 VSY = +5V OR ±5V 0.5 0 –0.5 –1.0 –4 –3 –2 –1 0 1 2 3 4 VSY = ±13V VSY = +5V 100k 10k 0.1 5 1 10 LOAD RESISTANCE (kΩ) VCM (V) Figure 12. Open-Loop Gain vs. Load Resistance Figure 9. Input Bias Current vs. VCM 1000 1000 VSY = ±13V a 800 OPEN-LOOP GAIN (V/mV) d 700 600 500 400 300 200 100 03023-010 INPUT OFFSET VOLTAGE (µV) 900 0 –100 –15 100 –12 –9 –6 –3 0 3 VCM (V) 6 9 12 b 100 c e 10 a. VSY = ±13V, VO = ±11V, RL = 10kΩ b. VSY = ±13V, VO = ±11V, RL = 2kΩ c. VSY = +5V, VO = +0.5V/+4.5V, RL = 2kΩ d. VSY = +5V, VO = +0.5V/+4.5V, RL = 10kΩ e. VSY = +5V, VO = +0.5V/+4.5V, RL = 600Ω 1 –40 15 Figure 10. Input Offset Voltage vs. VCM 25 95 TEMPERATURE (°C) Figure 13. Open-Loop Gain vs. Temperature Rev. F | Page 7 of 20 03023-013 –2.0 –5 03023-009 –1.5 1M 03023-012 1.0 OPEN-LOOP GAIN (V/V) INPUT BIAS CURRENT (pA) 1.5 125 AD8625/AD8626/AD8627 10k VSY = ±13V VSY = ±13V OFFSET VOLTAGE (µV) 400 VSY – OUTPUT VOLTAGE (mV) 500 RL = 10kΩ 300 200 RL = 100kΩ 100 0 RL = 600Ω –100 100 VOL 10 03023-014 –200 1k –300 –400 –15 –10 –5 0 5 OUTPUT VOLTAGE (V) 10 1 0.001 15 Figure 14. Input Error Voltage vs. Output Voltage for Resistive Loads 250 RL = 1kΩ 200 VOH 03023-017 600 Data Sheet 0.01 0.1 1 LOAD CURRENT (mA) 10 100 Figure 17. Output Saturation Voltage vs. Load Current 10k VSY = ±5V VSY = 5V 50 0 RL = 10kΩ RL = 1kΩ NEG RAIL VOL 10 VOH 03023-015 –150 100 –200 –250 0 50 100 150 200 250 OUTPUT VOLTAGE FROM SUPPLY RAILS (mV) 1 0.001 300 Figure 15. Input Error Voltage vs. Output Voltage within 300 mV of Supply Rails 0.1 1 LOAD CURRENT (mA) 10 100 Figure 18. Output Saturation Voltage vs. Load Current 70 800 VSY = ±13V RL = 2kΩ CL = 40pF 60 700 +125°C 50 600 +25°C 500 –55°C 315 270 225 40 180 GAIN GAIN (dB) QUIESCENT CURRENT (µA) 0.01 400 300 30 135 20 90 PHASE 10 45 0 –0 PHASE (Degrees) –50 –100 1k 03023-018 RL = 100kΩ RL = 10kΩ 100 200 03023-016 100 0 0 4 16 20 8 12 TOTAL SUPPLY VOLTAGE (V) 24 –10 –45 –20 –90 –30 10k 28 Figure 16. Quiescent Current vs. Supply Voltage at Different Temperatures Rev. F | Page 8 of 20 100k 1M FREQUENCY (Hz) 10M –135 50M Figure 19. Open-Loop Gain and Phase Margin vs. Frequency 03023-019 INPUT VOLTAGE (µV) 150 VSY – OUTPUT VOLTAGE (mV) POS RAIL Data Sheet AD8625/AD8626/AD8627 140 50 315 VSY = 5V RL = 2kΩ 270 CL = 40pF 225 40 180 80 135 20 90 PHASE 45 0 –0 –45 –20 –90 100k 1M FREQUENCY (Hz) –135 50M 10M 40 20 0 –10 –30 10k 60 –20 03023-023 10 100 CMRR (dB) 30 –40 –60 1k 10k Figure 20. Open-Loop Gain and Phase Margin vs. Frequency 100k FREQUENCY (Hz) 1M 10M Figure 23. CMRR vs. Frequency 70 140 VSY = ±13V 60 RL = 2kΩ CL = 40pF 50 120 VSY = 5V 100 40 80 CMRR (dB) GAIN (dB) G = +100 30 20 G = +10 10 0 60 40 20 0 G = +1 –20 –30 1k 10k 100k 1M FREQUENCY (Hz) 10M –40 –60 1k 50M Figure 21. Closed-Loop Gain vs. Frequency 50 10k 100k FREQUENCY (Hz) 1M 10M Figure 24. CMRR vs. Frequency 70 60 03023-024 –20 03023-021 –10 140 VSY = 5V RL = 2kΩ CL = 40pF 120 VSY = ±13V 100 40 80 G = +100 +PSRR PSRR (dB) 30 20 G = +10 10 0 60 40 –PSRR 20 0 G = +1 –20 –20 –30 1k 10k 100k 1M FREQUENCY (Hz) 10M 03023-025 –10 03023-022 GAIN (dB) GAIN (dB) GAIN VSY = ±13V 120 PHASE (Degrees) 60 03023-020 70 –40 –60 1k 50M Figure 22. Closed-Loop Gain vs. Frequency 10k 100k FREQUENCY (Hz) Figure 25. PSRR vs. Frequency Rev. F | Page 9 of 20 1M 10M AD8625/AD8626/AD8627 Data Sheet 140 VSY = ±13V INPUT VSY = 5V 120 100 VOLTAGE (10V/DIV) PSRR (dB) 80 60 40 +PSRR 20 –PSRR OUTPUT 0 03023-026 03023-029 –20 –40 –60 1k 10k 100k FREQUENCY (Hz) 1M TIME (400µs/DIV) 10M Figure 29. No Phase Reversal Figure 26. PSRR vs. Frequency 270 15 VSY = ±13V 10 240 TS + (1%) OUTPUT SWING (V) 180 150 120 90 G = +10 0 TS – (0.1%) –5 TS – (1%) –10 03023-027 G = +100 30 10k TS + (0.1%) G = +1 60 0 1k 5 100k 1M FREQUENCY (Hz) 10M –15 1.5 1.0 SETTLING TIME (µs) 2.0 2.5 Figure 30. Output Swing and Error vs. Settling Time Figure 27. Output Impedance vs. Frequency 70 300 240 VS = ±13V RL = 10kΩ 60 VIN = 100mV p-p AV = +1 210 50 VSY = 5V OVERSHOOT (%) 270 180 150 120 90 G = +10 40 OS– 30 OS+ 20 G = +1 60 G = +100 30 0 1k 10k 10 03023-028 ZOUT (Ω) 0.5 0 100M 100k 1M FREQUENCY (Hz) 10M 0 10 100M 03023-031 ZOUT (Ω) 210 03023-030 300 100 CAPACITANCE (pF) Figure 31. Small-Signal Overshoot vs. Load Capacitance Figure 28. Output Impedance vs. Frequency Rev. F | Page 10 of 20 1k Data Sheet AD8625/AD8626/AD8627 56 70 VS = ±2.5V RL = 10kΩ 60 VIN = 100mV p-p AV = +1 42 VOLTAGE (nV) 50 OVERSHOOT (%) VSY = ±13V 49 40 30 35 19.7nV/ Hz 28 21 OS+ 20 14 OS– 0 10 100 CAPACITANCE (pF) 03023-035 7 03023-032 10 0 0 1k 1 Figure 32. Small-Signal Overshoot vs. Load Capacitance 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 8 9 10 Figure 35. Voltage Noise Density 56 VSY = ±13V AVO = 100,000V/V VSY = 5V 42 VOLTAGE (nV) VOLTAGE (50mV/DIV) 49 0 35 16.7nV/ Hz 28 21 03023-033 14 03023-036 7 0 TIME (1s/DIV) 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 Figure 36. Voltage Noise Density Figure 33. 0.1 Hz to 10 Hz Noise –40 VSY = ±2.5V AVO = 100,000V/V THD + NOISE (dB) –60 0 –70 VSY = ±5V, VIN = 9V p-p –80 VSY = ±13V, VIN = 18V p-p –90 VSY = ±2.5V, VIN = 4.5V p-p –110 10 TIME (1s/DIV) 03023-037 –100 03023-034 VOLTAGE (50mV/DIV) –50 100 1k FREQUENCY (Hz) 10k 100k Figure 37. Total Harmonic Distortion + Noise vs. Frequency Figure 34. 0.1 Hz to 10 Hz Noise Rev. F | Page 11 of 20 AD8625/AD8626/AD8627 Data Sheet 20kΩ 2kΩ VIN 2kΩ 2kΩ –80 –100 VIN = 9V p-p VIN = 4.5V p-p VIN = 18V p-p –110 –120 –130 –140 –150 –160 10 03023-049 CHANNEL SEPARATION (dB) –90 100 1k 10k FREQUENCY (Hz) 100k Figure 38. Channel Separation Rev. F | Page 12 of 20 Data Sheet AD8625/AD8626/AD8627 APPLICATIONS INFORMATION INPUT VOLTAGE (2V/DIV) 4V 0V 4V OUTPUT 03023-038 0V TIME (2µs/DIV) Figure 39. Unity Gain Follower Response to 0 V to 4 V Step VSY = 5V 5V INPUT 0V 4V OUTPUT 0V 03023-039 The AD862x does not experience phase reversal with input signals close to the positive rail, as shown in Figure 29. For input voltages greater than +VSY, a resistor in series with the AD862x’s noninverting input prevents phase reversal at the expense of greater input voltage noise. This current-limiting resistor should also be used if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV, or if an input voltage is applied to the AD862x when ±VSY = 0. Either of these conditions damages the amplifier if the condition exists for more than 10 seconds. A 10 kΩ resistor allows the amplifier to withstand up to 10 V of continuous overvoltage, while increasing the input voltage noise by a negligible amount. VSY = 5V VOLTAGE (2V/DIV) The AD862x is one of the smallest and most economical JFETs offered. It has true single-supply capability and has an input voltage range that extends below the negative rail, allowing the part to accommodate input signals below ground. The rail-to-rail output of the AD862x provides the maximum dynamic range in many applications. To provide a low offset, low noise, high impedance input stage, the AD862x uses n-channel JFETs. The input common-mode voltage extends from 0.2 V below –VS to 2 V below +VS. Driving the input of the amplifier, configured in the unity gain buffer, closer than 2 V to the positive rail causes an increase in common-mode voltage error, as illustrated in Figure 15, and a loss of amplifier bandwidth. This loss of bandwidth causes the rounding of the output waveforms shown in Figure 39 and Figure 40, which have inputs that are 1 V and 0 V from +VS, respectively. TIME (2µs/DIV) Figure 40. Unity Gain Follower Response to 0 V to 5 V Step Rev. F | Page 13 of 20 AD8625/AD8626/AD8627 Data Sheet 20kΩ The AD862x can safely withstand input voltages 15 V below VSY if the total voltage between the positive supply and the input terminal is less than 26 V. Figure 41 through Figure 43 show the AD862x in different configurations accommodating signals close to the negative rail. The amplifier input stage typically maintains picoamp-level input currents across that input voltage range. 10kΩ +5V 0V –10mV –30mV VSY = 5V 20kΩ +5V VOLTAGE (10mV/DIV) 10kΩ 0V –2.5V VSY = 5V, 0V 5V 03023-042 VOLTAGE (1V/DIV) 0V TIME (2µs/DIV) Figure 43. Gain-of-Two Inverter Response to 20 mV Step, Centered 20 mV below Ground 03023-040 0V TIME (2µs/DIV) Figure 41. Gain-of-Two Inverter Response to 2.5 V Step, Centered 1.25 V below Ground The AD862x has a unique bipolar rail-to-rail output stage that swings within 5 mV of the rail when up to 2 mA of current is drawn. At larger loads, the drop-out voltage increases, as shown in Figure 17 and Figure 18. The AD862x’s wide bandwidth and fast slew rate allows it to be used with faster signals than older single-supply JFETs. Figure 44 shows the response of the AD862x, configured in unity gain, to a VIN of 20 V p-p at 50 kHz. The full-power bandwidth (FPBW) of the part is close to 100 kHz. 60mV 20mV 0V The AD862x is designed for 16 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies, as shown in Figure 35. This noise performance, along with the AD862x’s low input current and current noise, means that the AD862x contributes negligible noise for applications with large source resistances. 5V 600Ω VSY = 5V RL = 600Ω 03023-041 0V TIME (2µs/DIV) 03023-043 0V VOLTAGE (5V/DIV) VOLTAGE (10mV/DIV) VSY = ±13V RL = 600Ω Figure 42. Unity Gain Follower Response to 40 mV Step, Centered 40 mV above Ground TIME (5µs/DIV) Figure 44. Unity Gain Follower Response to 20 V, 50 kHz Input Signal Rev. F | Page 14 of 20 Data Sheet AD8625/AD8626/AD8627 MINIMIZING INPUT CURRENT PHOTODIODE PREAMPLIFIER APPLICATION The AD862x is guaranteed to 1 pA maximum input current with a ±13 V supply voltage at room temperature. Careful attention to how the amplifier is used maintains or possibly betters this performance. The amplifier’s operating temperature should be kept as low as possible. Like other JFET input amplifiers, the AD862x’s input current doubles for every 10°C rise in junction temperature, as illustrated in Figure 8. On-chip power dissipation raises the device operating temperature, causing an increase in input current. Reducing supply voltage to cut power dissipation reduces the AD862x’s input current. Heavy output loads can also increase chip temperature; maintaining a minimum load resistance of 1 kΩ is recommended. The low input current and offset voltage levels of the AD862x, together with its low voltage noise, make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applications. In a typical photovoltaic preamp circuit, shown in Figure 45, the output of the amplifier is equal to The AD862x is designed for mounting on PC boards. Maintaining picoampere resolution in those environments requires a lot of care. Both the board and the amplifier’s package have finite resistance. Voltage differences between the input pins and other pins, as well as PC board metal traces may cause parasitic currents larger than the AD862x’s input current, unless special precautions are taken. To ensure the best result, refer to the ADI website for proper board layout seminar materials. Two common methods of minimizing parasitic leakages that should be used are guarding of the input lines and maintaining adequate insulation resistance. Contaminants, such as solder flux on the board’s surface and the amplifier’s package, can greatly reduce the insulation resistance between the input pin and traces with supply or signal voltages. Both the package and the board must be kept clean and dry. VOUT = − ID(R f ) = −R p (P)R f where: ID = photodiode signal current (A). Rp = photodiode sensitivity (A/W). Rf = value of the feedback resistor, in Ω. P = light power incident to photodiode surface, in W. The amplifier’s input current, IB, contributes an output voltage error proportional to the value of the feedback resistor. The offset voltage error, VOS, causes a small current error due to the photodiode’s finite shunt resistance, RD. The resulting output voltage error, VE, is equal to Rf V E = 1 + RD VOS + R f (I B ) A shunt resistance on the order of 100 MΩ is typical for a small photodiode. Resistance RD is a junction resistance that typically drops by a factor of two for every 10°C rise in temperature. In the AD862x, both the offset voltage and drift are low, which helps minimize these errors. With IB values of 1 pA and VOS of 50 mV, VE for Figure 45 is very negligible. Also, the circuit in Figure 45 results in an SNR value of 95 dB for a signal bandwidth of 30 kHz. CF 5pF PHOTODIODE VOS RF 1.5MΩ IB C4 I 15pF B AD8627 Figure 45. A Photodiode Model Showing DC Error Rev. F | Page 15 of 20 03023-044 OUTPUT RD 100MΩ AD8625/AD8626/AD8627 Data Sheet OUTPUT AMPLIFIER FOR DACs 2.5V 5V 10µF 0.1µF 0.1µF 5V SERIAL INTERFACE VREFS * VREFF* VDD CS DIN SCLK AD8627 AD5551/AD5552 UNIPOLAR OUTPUT OUT 03023-045 LDAC* AGND DGND *AD5552 ONLY Figure 46. Unipolar Output 10kΩ 10kΩ +13V 10V VREF 5kΩ ADR01 1/2 AD8626 VOUT –10V < VOUT < +10V –13V VDD VREFX RFBX ONE CHANNEL AD5544 VSS AGNDF AGNDX 1/2 AD8626 DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY In applications with full 4-quadrant multiplying capability or a bipolar output swing, the circuit in Figure 47 can be used. In this circuit, the first and second amplifiers provide a total gain of 2, which increases the output voltage span to 20 V. Biasing the external amplifier with a 10 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. Rev. F | Page 16 of 20 Figure 47. 4-Quadrant Multiplying Application Circuit 03023-046 Many system designers use amplifiers as buffers on the output of amplifiers to increase the DAC’s output driving capability. The high resolution current output DACs need high precision amplifiers on their output as current-to-voltage converters (I/V). Additionally, many DACs operate with a single supply of 5 V. In a single-supply application, selection of a suitable op amp may be more difficult because the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the DAC’s specified performance, unless the application does not use codes near zero. The selected op amp needs to have very low offset voltage—for a 14-bit DAC, the DAC LSB is 300 µV with a 5 V reference—to eliminate the need for output offset trims. Input bias current should also be very low because the bias current multiplied by the DAC output impedance (about 10 kΩ in some cases) adds to the zero-code error. Rail-to-rail input and output performance is desired. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The AD862x, with a very high input impedance, IB of 1 pA, and a fast slew rate, is an ideal amplifier for these types of applications. A typical configuration with a popular DAC is shown in Figure 46. In these situations, the amplifier adds another time constant to the system, increasing the settling time of the output. The AD862x, with 5 MHz of BW, helps in achieving a faster effective settling time of the combined DAC and amplifier. Data Sheet AD8625/AD8626/AD8627 EIGHT-POLE SALLEN KEY LOW-PASS FILTER 1.2 The AD862x’s high input impedance and dc precision make it a great selection for active filters. Due to the very low bias current of the AD862x, high value resistors can be used to construct low frequency filters. The AD862x’s picoamp-level input currents contribute minimal dc errors. Figure 49 shows an example of a 10 Hz, 8-pole Sallen Key filter constructed using the AD862x. Different numbers of the AD862x can be used depending on the desired response, which is shown in Figure 48. The high value used for R1 minimizes interaction with signal source resistance. Pole placement in this version of the filter minimizes the Q associated with the lower pole section of the filter. This eliminates any peaking of the noise contribution of resistors in the preceding sections, minimizing the inherent output voltage noise of the filter. V3 VOLTAGE (V) 0.8 V1 03023-047 0.4 0 0.1 1 10 100 1k FREQUENCY (Hz) Figure 48. Frequency Response Output at Different Stages of the Low-Pass Filter R2 162.3kΩ VDD 3 4 U1 1 2 D C2 96.19µF D C3 100µF R10 V1 191.4kΩ 1/4 11 AD8625 R5 191.4kΩ VEE R3 25kΩ R11 286.5kΩ U2 C5 100µF V2 1/4 AD8625 C4 69.14µF R7 286.5kΩ R4 25kΩ V3 R9 815.8kΩ 1/4 AD8625 C6 30.86µF C7 100µF R12 815.8kΩ U3 D V4 D R6 25kΩ U4 1/4 AD8625 C8 3.805µF D R8 25kΩ Figure 49. 10 Hz, 8-Pole Sallen Key Low-Pass Filter Rev. F | Page 17 of 20 03023-048 V3 V2 C1 100µF R1 162.3kΩ VIN V4 AD8625/AD8626/AD8627 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 5 2.40 2.10 1.80 4 1 2 3 0.65 BSC 1.10 0.80 0.10 MAX COPLANARITY 0.10 SEATING PLANE 0.30 0.15 0.40 0.10 0.46 0.36 0.26 0.22 0.08 072809-A 1.00 0.90 0.70 COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 50. 5-Lead Plastic Surface-Mount Package [SC70] (KS-5) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 51. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 18 of 20 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Data Sheet AD8625/AD8626/AD8627 3.20 3.00 2.80 5.15 4.90 4.65 5 8 3.20 3.00 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.80 0.55 0.40 0.23 0.09 6° 0° 0.40 0.25 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 52. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 8 14 1 7 6.20 (0.2441) 5.80 (0.2283) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 14-Lead Standard Small Outline Package [SOIC_N] (R-14) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. F | Page 19 of 20 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 AD8625/AD8626/AD8627 Data Sheet ORDERING GUIDE Model 1, 2 AD8625ARUZ AD8625ARUZ-REEL AD8625ARZ AD8625ARZ-REEL AD8625ARZ-REEL7 AD8626ARMZ-REEL AD8626ARMZ AD8626ARZ AD8626ARZ-REEL AD8626ARZ-REEL7 AD8627AKSZ-REEL AD8627AKSZ-REEL7 AD8627AKSZ-R2 AD8627ARZ AD8627ARZ-REEL AD8627ARZ-REEL7 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 14-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 5-Lead SC70 5-Lead SC70 5-Lead SC70 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Z = RoHS Compliant Part; # denotes product may be top or bottom marked. For the AD8627AKS models, pre-0542 parts were branded with B9A without #. ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03023-0-5/13(F) Rev. F | Page 20 of 20 Package Option RU-14 RU-14 R-14 R-14 R-14 RM-8 RM-8 R-8 R-8 R-8 KS-5 KS-5 KS-5 R-8 R-8 R-8 Branding BJA BJA B9B B9B B9B