a 7 MHz Rail-to-Rail Low Voltage Operational Amplifiers AD8517/AD8527 FEATURES Single Supply Operation: 1.8 V to 6 V Space-Saving SOT-23, SOIC Packaging Wide Bandwidth: 7 MHz @ 5 V Low Offset Voltage: 3.5 mV Max Rail-to-Rail Output Swing and Rail-to-Rail Input 8 V/s Slew Rate Only 900 A Supply Current @ 5 V APPLICATIONS Portable Communications Portable Phones Sensor Interface Active Filters PCMCIA Cards ASIC Input Drivers Wearable Computers Battery-Powered Devices New Generation Phones Personal Digital Assistants PIN CONFIGURATIONS 5-Lead SOT-23 (RT Suffix) 5 V+ V– 2 +IN A 3 4 –IN A 8-Lead SOIC (R Suffix) OUT A 1 8 –IN A 2 AD8527 +IN A 3 V– 4 V+ 7 OUT B 6 –IN B 5 +IN B 8-Lead MSOP (RM Suffix) GENERAL DESCRIPTION The AD8517 brings precision and bandwidth to the SOT-23-5 package even at single supply voltages as low as 1.8 V. The small package makes it possible to place the AD8517 next to sensors, reducing external noise pickup. The AD8527 dual amplifier is offered in the space-saving MSOP package. AD8517 OUT A 1 OUT A –IN A +IN A V– 1 8 AD8527 4 5 V+ OUT B –IN B +IN B The AD8517 and AD8527 are rail-to-rail input and output bipolar amplifiers with a gain bandwidth of 7 MHz and typical voltage offset of 1.3 mV from a 1.8 V supply. The low supply current makes these parts ideal for battery-powered applications. The 8 V/µs slew rate makes the AD8517/AD8527 a good match for driving ASIC inputs, such as voice codecs. The AD8517/AD8527 is specified over the extended industrial (–40°C to +125°C) temperature range. The AD8517 single is available in 5-lead SOT-23 surface-mount packages. The dual AD8527 is available in 8-lead SOIC and MSOP packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD8517/AD8527–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V = 5.0 V, V– = 0 V, V S Parameter Symbol INPUT CHARACTERISTICS Offset Voltage AD8517ART (SOT-23-5) VOS AD8527 VOS Input Bias Current IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio VCM CMRR Large Signal Voltage Gain AVO Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low Short Circuit Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier ∆VOS/∆T ∆IB/∆T VOH VOL ISC PSRR ISY CM = 2.5 V, TA = 25ⴗC unless otherwise noted) Conditions Min Typ Max Unit 1.3 3.5 5 3.5 5 450 900 ± 225 ± 750 5 mV mV mV mV nA nA nA nA V –40°C ≤ TA ≤ +125°C 1.3 –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C 0 0 V ≤ VCM ≤ 5.0 V, –40°C ≤ TA ≤ +125°C RL = 2 kΩ, 0.5 V < VOUT < 4.5 V RL = 10 kΩ, 0.5 V < VOUT < 4.5 V RL = 10 kΩ, –40°C ≤ TA ≤ +125°C 60 50 30 70 20 100 dB V/mV V/mV V/mV µV/°C pA/°C 2 500 IL = 250 µA, –40°C ≤ TA ≤ +125°C IL = 5 mA IL = 250 µA, –40°C ≤ TA ≤ +125°C IL = 5 mA Short to Ground, Instantaneous 4.965 4.70 V V 35 200 ± 10 mV mV mA VS = 2.2 V to 6 V –40°C ≤ TA ≤ +125°C VOUT = 2.5 V –40°C ≤ TA ≤ +125°C 90 65 900 8 7 400 50 V/µs MHz ns Degrees 0.5 15 1.2 µV p-p nV/√Hz pA/√Hz DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Settling Time Phase Margin SR GBP TS φm 1 V < VOUT < 4 V, RL = 10 kΩ NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 4 V Step, 0.1% 1,200 1,400 dB dB µA µA Specifications subject to change without notice. –2– REV. B AD8517/AD8527 ELECTRICAL CHARACTERISTICS (V = 2.2 V, V– = 0 V, V S Parameter Symbol INPUT CHARACTERISTICS Offset Voltage AD8517ART (SOT-23-5) VOS AD8527 VOS Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio IB IOS VCM CMRR Large Signal Voltage Gain AVO OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low VOH VOL CM = 1.1 V, TA = 25ⴗC unless otherwise noted) Conditions Min Typ Max Unit 1.3 3.5 5 3.5 5 450 ± 225 2.2 mV mV mV mV nA nA V –40°C ≤ TA ≤ +125°C 1.3 –40°C ≤ TA ≤ +125°C 0 0 V ≤ VCM ≤ 2.2 V, –40°C ≤ TA ≤ +125°C RL = 2 kΩ, 0.5 V < VOUT < 1.7 V RL = 10 kΩ IL = 250 µA IL = 2.5 mA IL = 250 µA IL = 2.5 mA 55 20 70 20 50 dB V/mV V/mV 2.165 1.9 35 200 V V mV mV 1,100 1,300 µA µA POWER SUPPLY Supply Current/Amplifier ISY VOUT = 1.1 V –40°C ≤ TA ≤ +125°C 750 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin SR GBP φm RL = 10 kΩ 8 7 50 V/µs MHz Degrees NOISE PERFORMANCE Voltage Noise Density Current Noise Density en in f = 1 kHz f = 1 kHz 15 1.2 nV/√Hz pA/√Hz Specifications subject to change without notice. REV. B –3– AD8517/AD8527–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V = 1.8 V, V– = 0 V, V S Parameter Symbol INPUT CHARACTERISTICS Offset Voltage AD8517ART (SOT-23-5) VOS AD8527 VOS Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio IB IOS VCM CMRR Large Signal Voltage Gain AVO OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier VOH VOL PSRR ISY CM = 0.9 V, TA = 25ⴗC unless otherwise noted) Conditions Min Typ Max Unit 1.3 3.5 5 3.5 5 450 ± 225 1.8 mV mV mV mV nA nA V 0°C ≤ TA ≤ 125°C 1.3 0°C ≤ TA ≤ 125°C 0 0 V ≤ VCM ≤ 1.8 V, 0°C ≤ TA ≤ 125°C RL = 2 kΩ, 0.5 V < VOUT < 1.3 V RL = 10 kΩ IL = 250 µA IL = 2.5 mA IL = 250 µA IL = 2.5 mA VS = 1.7 V to 2.2 V, 0°C ≤ TA ≤ 125°C VOUT = 0.9 V 0°C ≤ TA ≤ 125°C 50 20 70 20 50 dB V/mV V/mV 1.765 1.5 50 65 650 35 200 V V mV mV 1,100 1,300 dB µA µA DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin SR GBP φm RL = 10 kΩ 7 7 50 V/µs MHz Degrees NOISE PERFORMANCE Voltage Noise Density Current Noise Density en in f = 1 kHz f = 1 kHz 15 1.2 nV/√Hz pA/√Hz Specifications subject to change without notice. –4– REV. B AD8517/AD8527 ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For supply voltages less than 6 V the input voltage is limited to less than or equal to the supply voltage. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 0.6 V Internal Power Dissipation SOT-23 (RT) . . . . . . . . . . . . See Thermal Resistance Chart SOIC (R) . . . . . . . . . . . . . . . See Thermal Resistance Chart µSOIC (RM) . . . . . . . . . . . . See Thermal Resistance Chart Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . Indefinite for TA < +40°C Storage Temperature Range R, RM and RT Packages . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD8517, AD8527 . . . . . . . . . . . . . . . . . . –40°C to +125°C Junction Temperature Range R, RM and RT Packages . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300°C Package Type JA1 JC Unit 5-Lead SOT-23 (RT) 8-Lead SOIC (R) 8-Lead µSOIC (RM) 230 158 210 146 43 45 °C/W °C/W °C/W NOTE 1 θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered in circuit board for SOT-23 and SOIC packages. ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Information AD8517ART-REEL AD8527AR AD8527ARM-REEL –40°C to +125°C –40°C to +125°C –40°C to +125°C 5-Lead SOT-23 8-Lead SOIC 8-Lead µSOIC RT-5 SO-8 RM-8 ADA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8517/AD8527 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 950 120 VS = 5V VCM = 2.5V TA = 25ⴗC COUNT = 935 OP AMPS 900 90 SUPPLY CURRENT – A QUANTITY OF AMPLIFIERS AFA 60 30 850 800 750 700 650 0 ⴚ4 ⴚ3 ⴚ2 ⴚ1 0 1 2 INPUT OFFSET VOLTAGE – mV 3 600 4 2 3 4 SUPPLY VOLTAGE – V 5 6 Figure 2. Supply Current per Amplifier vs. Supply Voltage Figure 1. Input Offset Voltage Distribution REV. B 1 –5– AD8517/AD8527–Typical Characteristics 60 1,200 VS = 5V 1,000 900 800 700 GAIN 30 20 90 PHASE 10 45 0 0 ⴚ10 ⴚ45 ⴚ20 ⴚ90 PHASE SHIFT – Degrees 40 OPEN-LOOP GAIN – dB SUPPLY CURRENT – A VS = 5V TA = 25ⴗC 50 1,100 ⴚ30 600 ⴚ50 ⴚ25 0 25 50 75 TEMPERATURE – ⴗC 100 125 ⴚ40 100k 150 Figure 3. Supply Current per Amplifier vs. Temperature 10M 1M FREQUENCY – Hz 100M Figure 6. Open-Loop Gain vs. Frequency 600 60 VS = ⴞ2.5V TA = 25ⴗC VS = 5V TA = 25ⴗC CL ⱕ 10pF 40 CLOSED-LOOP GAIN – dB INPUT BIAS CURRENT – nA 400 200 0 ⴚ200 0 ⴚ20 ⴚ400 ⴚ600 ⴚ3 20 ⴚ2 0 ⴚ1 1 COMMON-MODE VOLTAGE – V ⴚ40 3 2 Figure 4. Input Bias Current vs. Common-Mode Voltage 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M 100M Figure 7. Closed-Loop Gain vs. Frequency 0 140 TA = 25ⴗC VS = ⴞ2.5V TA = 25ⴗC 120 SINKⴚ CMRR – dB OUTPUT VOLTAGE – mV 20 100 80 60 40 60 SOURCE+ 40 80 20 0 10 100 1k 100 LOAD CURRENT – A 10k Figure 5. Output Voltage to Supply Rail vs. Load Current 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 8. CMRR vs. Frequency –6– REV. B AD8517/AD8527 100 0 VS = ⴞ2.5V TA = 25ⴗC 20 80 OUTPUT IMPEDANCE – ⍀ ⴚPSRR 40 PSRR – dB VS = 5V TA = 25ⴗC 90 60 ⴙPSRR 80 70 60 50 40 30 AVCC = 1 20 100 10 120 0 100 10 10k 100k 1k FREQUENCY – Hz 1M 10M Figure 9. PSRR vs. Frequency 1k 10k 100k FREQUENCY – Hz 1M 10M 100M 40 VS = 5V TA = 25ⴗC Hz VS = 5V VCM = 2.5V R L = 10k⍀ TA = 25ⴗC VIN = ⴞ50mV AV = 1 VOLTAGE NOISE DENSITY – nV/ OVERSHOOT – % 100 50 50 ⴚOS 30 20 +OS 10 0 10 100 CAPACITANCE – pF 40 30 20 10 0 10 1k 100 1k FREQUENCY – Hz 10k Figure 13. Voltage Noise Density vs. Frequency Figure 10. Overshoot vs. Capacitance Load 12 6 4 3 2 1 0 10k 100k 1M FREQUENCY – Hz VS = 5V TA = 25ⴗC Hz 5 VS = 5V A V = +1 R L = 10k⍀ TA = 25ⴗC CL = 15pF CURRENT NOISE DENSITY – pA/ DISTORTION = 3% MAXIMUM OUTPUT SWING – V p-p 10 Figure 12. Output Impedance vs. Frequency 60 8 4 0 10 10M 100 1k FREQUENCY – Hz 10k Figure 14. Current Noise Density vs. Frequency Figure 11. Output Swing vs. Frequency REV. B AVCC = 10 –7– AD8517/AD8527 VOLTAGE – 20mV/Div VOLTAGE – 20mV/Div VS = ⴞ2.5V AV = 120k TA = 25ⴗC VS = ⴞ2.5V AV = 1 TA = 25ⴗC CL = 100pF R L = 10k⍀ TIME – 500ns/Div TIME – 1s/Div Figure 17. Small Signal Transient Response Figure 15. 0.1 Hz to 10 Hz Noise 0 VOLTAGE – 1V/Div 0 VS = ⴞ2.5V AV = 1 RL = 10k⍀ TA = 25ⴗC VOLTAGE – 500mV/Div VS = ⴞ2.5V AV = + 1 VIN = SINEWAVE TA = 25ⴗC 0 0 0 0 0 0 TIME – 200ns/Div TIME – 200s/Div Figure 16. No Phase Reversal Figure 18. Large Signal Transient Response configuration. The output swing when sinking or sourcing 250 µA is 35 mV from each rail. THEORY OF OPERATION The AD85x7 is a rail-to-rail operational amplifier that can operate at supply voltages as low as 1.8 V. This family is fabricated using Analog Devices’ high-speed complementary bipolar process, also called XFCB. The process trench isolates each transistor to minimize parasitic capacitance thereby allowing high-speed performance. Figure 19 shows a simplified schematic of the AD85x7 family. The input bias current characteristics depend on the commonmode voltage, see Figure 4. As the input voltage reaches about 1 V below VCC, the PNP pair (Q3 and Q4) turns off. The 1 kΩ input resistor R1 and R2, together with the diodes D7 and D8, protect the input pairs against avalanche damage. The input stage consists of two parallel complementary differential pair: one NPN pair (Q1 and Q2) and one PNP pair (Q3 and Q4). The voltage drops across R7. R8, R9, and R10 are kept low for rail-to-rail operation. The major gain stage of the op amp is a double-folded cascode consisting of transistors Q5, Q6, Q8, and Q9. The output stage, which also operates rail-to-rail, is driven by Q14. The transistors Q13 and Q10 act as level-shifters to give more headroom during 1.8 V operation. The AD85x7 family exhibits no phase reversal as the input signal exceeds the supply by more than 0.6 V. Excessive current can flow through the input pins via the ESD diodes D1–D2 or D3–D4, in the event their ~0.6 V thresholds are exceeded. Such fault currents must be limited to 5 mA or less by the use of external series resistance(s). LOW VOLTAGE OPERATION Battery Voltage Discharge As the voltage at the base of Q13 increases, Q18 starts to sink current. When the voltage at the base of Q13 decreases, I8 flows through D16 and Q15 increasing the VBE of Q17, then Q20 sources current. The AD8517 operates at supply voltages as low as 1.8 V. This amplifier is ideal for battery-powered applications since it can operate at the end of discharge voltage of most popular batteries. Table I lists the Nominal and End of Discharge Voltages of several typical batteries. The output stage also furnishes gain, which depends on the load resistance, since the output transistors are in common emitter –8– REV. B AD8517/AD8527 VCC VCC R8 R7 R14 I8 I7 Q6 D1 D3 ESD I1 ESD ⴚIN Q3 R1 Q1 Q4 R2 Q14 D9 C4 C2 Q10 R6 D8 Q18 C1 Q8 D4 ESD ESD R11 Q9 Q17 Q15 R9 I2 VOUT C3 Q13 Q11 ⴙIN D7 R5 D2 Q2 Q20 Q7 I3 R4 R3 Q19 Q5 R10 I6 I5 I4 D6 D16 R12 R13 VEE VEE Figure 19. Simplified Schematic Table I. Typical Battery Life Voltage Range Battery Nominal Voltage (V) End of Voltage Discharge (V) Lead-Acid Lithium NiMH NiCd Carbon-Zinc 2 2.6-3.6 1.2 1.2 1.5 1.8 1.7-2.4 1 1 1.1 INPUT BIAS CONSIDERATION The input bias current (IB) is a nonideal, real-life parameter that affects all op amps. IB can generate a somewhat significant offset voltage. This offset voltage is created by IB when flowing through the negative feedback resistor RF. If IB is 500 nA (worst case), and RF is 100 kΩ, the corresponding generated offset voltage is 50 mV (VOS = IB ⫻ RF). Obviously the lower RF the lower the generated voltage offset. Using a compensation resistor, RB, as shown in Figure 21, can significantly minimize this effect. With the input bias current minimized, we still need to be aware of the input offset current (IOS) which will generate a slight offset error. Figure 21 shows three different configurations to minimize IB-induced offset errors. RAIL-TO-RAIL INPUT AND OUTPUT The AD8517 features an extraordinary rail-to-rail input and output with supply voltages as low as 1.8 V. With the amplifier’s supply range set to 1.8 V, the input can be set to 1.8 V p-p, allowing the output to swing to both rails without clipping. Figure 20 shows a scope picture of both input and output taken at unity gain, with a frequency of 1 kHz, at VS = 1.8 V and VIN = 1.8 V p-p. RF RI VI ⱍⱍ RB = RI RF VS = ⴞ0.9V VIN = 1.8 V p-p AD8517 VOUT INVERTING CONFIGURATION RF RI ⱍⱍ RB = RI RF VIN VI AD8517 VOUT NONINVERTING CONFIGURATION RF = RS VOUT RS VI AD8517 VOUT UNITY GAIN BUFFER Figure 21. Input Bias Cancellation Circuits TIME – 200s/Div Figure 20. Rail-to-Rail Input Output The rail-to-rail feature of the AD8517 can be observed over the supply voltage range, 1.8 V to 5 V. Traces are shown offset for clarity. REV. B –9– AD8517/AD8527 DRIVING CAPACITIVE LOAD Gain vs. Capacitive Load F = 250kHz AV = +1 C = 680pF VOLTAGE – 200mV/Div Most amplifiers have difficulty driving capacitance due to degradation of phase caused by additional phase lag from the capacitive load. Higher capacitance at the output can increase the amount of overshoot and ringing in the amplifier’s step response and could even affect the stability of the device. The value of capacitance load an amplifier can drive before oscillation varies with gain, supply voltage, input signal, temperature, and frequency, among others. Unity gain is the most challenging configuration for driving capacitance load. However, the AD8517 offers good capacitance driving ability. Table II shows the AD8517’s ability to capacitance load at different gains before instability occurs. This table is good for all VSY. TIME – 1s/Div Table II. Gain and Capacitance Load Figure 23. Photo of a Ringing Square Wave Gain Max Capacitance 1 2 2.5 3 400 pF 1.5 nF 8 nF Unconditionally Stable By connecting a series R–C from the output of the device to ground, known as the “snubber” network, this ringing and overshoot can be significantly reduced. Figure 24 shows the network setup, and Figure 25 shows the improvement of the output response with the “snubber” network added. In-the-Loop Compensation Technique for Driving Capacitive Loads 5V When driving capacitive loads in unity configuration, the in-theloop compensation technique is recommended to avoid oscillation as is illustrated in Figure 22. AD8517 VIN RF VOUT RX CL CX RG VIN CF Figure 24. Snubber Network Compensation for Capacitive Loads RX AD8517 VOUT F = 250kHz AV = +1 C = 680pF CL RO RG RF WHERE RO = OPEN-LOOP OUTPUT RESISTANCE CF = 1+ 冉 1 ACL 冊冉 RF + RG RF 冊 VOLTAGE – 200mV/Div RX = CLRO Figure 22. In-the-Loop Compensation Technique for Driving Capacitive Loads Snubber Network Compensation for Driving Capacitive Loads As load capacitance increases, the overshoot and settling time will increase and the unity gain bandwidth of the device will decrease. Figure 23 shows an example of the AD8517 configured for unity gain and driving a 10 kΩ resistor and a 680 pF capacitor placed in parallel, with a square wave input set to a frequency of 250 kHz and unity gain. TIME – 1s/Div Figure 25. Photo of a Square Wave with the Snubber Network Compensation The network operates in parallel with the load capacitor, CL, and provides compensation for the added phase lag. The actual values of the network resistor and capacitor have to be empirically determined. Table III shows some values of snubber network for large capacitance load. –10– REV. B AD8517/AD8527 Table III. Snubber Network Values for Large Capacitive Loads MICROPHONE PREAMPLIFIER CLOAD Rx Cx The AD8517 is ideal to use as a microphone preamplifier. Figure 28 shows this implementation. 680 pF 1 nF 10 nF 300 Ω 100 Ω 400 Ω 3 nF 10 nF 30 nF R3 220k⍀ VCC R1 2.2k⍀ VCC C1 R2 0.1F 22k⍀ VIN TOTAL HARMONIC DISTORTION + NOISE The AD85x7 family offers a low total harmonic distortion, which makes this amplifier ideal for audio applications. Figure 26 shows a graph of THD + N, for a VS > 3 V the THD + N is about 0.001% and 0.03% for VS ≥ 1.8 V in a noninverting configuration with a gain of 1. In an inverting configuration, the noise is 0.003% for all VSY. 1 AV = +2 AD8517 ELECTRET MIC VOUT | AV | = VREF R3 R2 Figure 28. A Microphone Preamplifier R1 is used to bias an electret microphone and C1 blocks dc voltage from the amplifier. The magnitude of the gain of the amplifier is approximately R3/R2 when R2 ≥ 10 × R1. VREF should be equal to 1/2 1.8 V for maximum voltage swing. Direct Access Arrangement for Telephone Line Interface 0.1 Figure 28 illustrates a 1.8 V transmit/receive telephone line interface for 600 Ω transmission systems. It allows full duplex transmission of signals on a transformer-coupled 600 Ω line in a differential manner. Amplifier A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured to apply the largest possible signal on a single supply to the transformer. Amplifier A3 is configured as a difference amplifier for two reasons: (1) It prevents the transmit signal from interfering with the receive signal and (2) it extracts the receive signal from the transmission line for amplification by A4. A4’s gain can be adjusted in the same manner as A1’s to meet the modem’s input signal requirements. Standard resistor values permit the use of SIP (Single In-line Package) format resistor arrays. Couple this with the AD8517/AD8527’s 5-lead SOT-23, 8-lead MSOP, and 8-lead SOIC footprint and this circuit offers a compact solution. THD + N – % VS = 1.8V 0.01 VS > 3V TO 5V 0.001 0.0001 10 100 10k 20k 1k FREQUENCY – Hz Figure 26. THD + N vs. Frequency Graph A MICROPOWER REFERENCE VOLTAGE GENERATOR Many single supply circuits are configured with the circuit-biased to one-half of the supply voltage. In these cases, a false-ground reference can be created by using a voltage divider buffered by an amplifier. Figure 27 shows the schematic for such a circuit. P1 Tx GAIN ADJUST The two 1 MΩ resistors generate the reference voltages while drawing only 0.9 µA of current from a 1.8 V supply. A capacitor connected from the inverting terminal to the output of the op amp provides compensation to allow for a bypass capacitor to be connected at the reference output. This bypass capacitor helps establish an ac ground for the reference output. 1.8V TO 5V TO TELEPHONE LINE 1:1 6.2V R5 10k⍀ T1 MIDCOM 671-8005 7 R11 10k⍀ 2 3 100⍀ 1F R12 10k⍀ VREF 0.9V TO 2.5V 1F TRANSMIT TxA +1.8V DC A3 A2 1 1/2 AD8527 R7 10k⍀ 5 10F R8 10k⍀ P2 Rx GAIN R13 R14 ADJUST 10k⍀ 14.3k⍀ 2k⍀ 6 5 A4 7 C2 0.1F RECEIVE RxA 1/2 AD8527 Figure 29. A Single-Supply Direct Access Arrangement for Modems Figure 27. A Micropower Reference Voltage Generator REV. B R6 10k⍀ 1/2 AD8517 R10 10k⍀ 0.022F AD8517 A1 3 6 10k⍀ 1M⍀ 1 C1 0.1F R1 10k⍀ 2 1/2 AD8517 6.2V R9 10k⍀ 1M⍀ 2k⍀ R3 360⍀ ZO 600⍀ R2 9.09k⍀ –11– identical to the actual AD8517 performance, which is a critical feature with a rail-to-rail amplifier model. The model also accurately simulates many ac effects, such as gain-bandwidth product, phase margin, input voltage noise, CMRR and PSRR versus frequency, and transient response. Its high degree of model accuracy makes the AD8517 macro-model one of the most reliable and true-to-life models available for any amplifier. SPICE Model The SPICE model for the AD8517 amplifier is available and can be downloaded from the Analog Devices’ web site at http://www.analog.com. The macro-model accurately simulates a number of AD8517 parameters, including offset voltage, input common-mode range, and rail-to-rail output swing. The output voltage versus output current characteristics of the macro-model is OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Narrow Body SOIC (SO-8) 8-Lead MSOP (RM-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) 8 5 0.199 (5.05) 0.187 (4.75) 0.122 (3.10) 0.114 (2.90) 1 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) ⴛ 45ⴗ 0.0099 (0.25) 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 8ⴗ 0ⴗ 0.0500 (1.27) 0.0160 (0.41) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.011 (0.28) 0.003 (0.08) 33ⴗ 27ⴗ 0.028 (0.71) 0.016 (0.41) 5-Lead SOT-23 (RT-5) 0.1181 (3.00) 0.1102 (2.80) 0.0669 (1.70) 0.0590 (1.50) 5 1 4 2 0.1181 (3.00) 0.1024 (2.60) 3 PIN 1 0.0374 (0.95) BSC 0.0748 (1.90) BSC 0.0512 (1.30) 0.0354 (0.90) 0.0059 (0.15) 0.0019 (0.05) 0.0079 (0.20) 0.0031 (0.08) 0.0571 (1.45) 0.0374 (0.95) 0.0197 (0.50) 0.0138 (0.35) SEATING PLANE –12– 10ⴗ 0ⴗ PRINTED IN U.S.A. 0.1574 (4.00) 0.1497 (3.80) 0.122 (3.10) 0.114 (2.90) C3736b–2.5–7/00 (rev. B) 01020 AD8517/AD8527 0.0217 (0.55) 0.0138 (0.35) REV. B