24AA256UID
256K I2C™ Serial EEPROM with EUI-48™, EUI-64™ and
Unique 32-Bit Serial Number
Device Selection Table
Part Number
24AA256UID
Note 1:
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
Page
Size
EUI-48™
EUI-64™
Unique ID
Length
1.7-5.5V
400 kHz(1)
I
64-byte
Yes
Yes
32-bit
100 kHz for VCC < 2.5V.
Features:
Description:
• Pre-Programmed 32-Bit Serial Number:
- Unique across all UID-family EEPROMs
- Scalable to 48-bit, 64-bit, 128-bit, 256-bit,
and other lengths
• Pre-Programmed Globally Unique, 48-bit or 64-bit
Node Address:
- Compatible with EUI-48™ and EUI-64™
• Codes Stored in Permanently Write-Protected
Upper 1/8th of EEPROM Array
• Single Supply with Operation Down to 1.7V
• Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Packages Include 8-lead PDIP, SOIC and TSSOP
• RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40C to +85C
The Microchip Technology Inc. 24AA256UID is a 32K x
8 (256 Kbit) Serial Electrically Erasable PROM with
pre-programmed EUI-48 and EUI-64 node addresses
and a 32-bit Unique ID, capable of operation across a
broad voltage range (1.7V to 5.5V). This device also
has a page write capability of up to 64 bytes of data.
This device is available in the standard 8-pin plastic
DIP, SOIC and TSSOP packages.
2013 Microchip Technology Inc.
Block Diagram
A0 A1A2
I/O
Control
Logic
Memory
Control
Logic
HV Generator
EEPROM
Array
XDEC
Page Latches
I/O
SCL
YDEC
SDA
VCC
Sense Amp.
R/W Control
VSS
Package Types
1
A1
2
A2
3
VSS
4
SOIC/TSSOP
8
VCC
A0
1
7
NC
A1
2
6
SCL
A2
3
5
SDA VSS
4
24AA256UID
A0
24AA256UID
PDIP
8
VCC
7
NC
6
SCL
5
SDA
DS20005215A-page 1
24AA256UID
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ..................................................................................................-40°C to +85°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
—
A0, A1, A2, SCL and
SDA pins:
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
Min.
Max.
Units
—
—
—
—
TA = -40°C to +85°C
Conditions
D1
VIH
High-level input voltage
0.7 VCC
—
V
—
D2
VIL
Low-level input voltage
—
0.3 VCC
0.2 VCC
V
V
VCC 2.5V
VCC < 2.5V
D3
VHYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC
—
V
VCC 2.5V (Note)
D4
VOL
Low-level output voltage
—
0.40
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
VIN = VSS or VCC
D5
ILI
Input leakage current
—
±1
A
D6
ILO
Output leakage current
—
±1
A
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICC Read Operating current
—
400
A
VCC = 5.5V, SCL = 400 kHz
ICC Write
—
3
mA
VCC = 5.5V
—
1
A
TA = -40°C to +85°C
SCL = SDA = VCC = 5.5V
A0, A1, A2 = VSS
D9
Note:
ICCS
Standby current
This parameter is periodically sampled and not 100% tested.
DS20005215A-page 2
2013 Microchip Technology Inc.
24AA256UID
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
AC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
TA = -40°C to +85°C
Conditions
1
FCLK
Clock frequency
—
—
100
400
kHz
1.7V VCC 2.5V
2.5V VCC 5.5V
2
THIGH
Clock high time
4000
600
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
3
TLOW
Clock low time
4700
1300
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
4
TR
SDA and SCL rise time
(Note 1)
—
—
1000
300
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
5
TF
SDA and SCL fall time
(Note 1)
—
300
ns
—
6
THD:STA Start condition hold time
4000
600
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
7
TSU:STA Start condition setup time
4700
600
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
8
THD:DAT Data input hold time
0
—
ns
(Note 2)
9
TSU:DAT Data input setup time
250
100
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
10
TSU:STO Stop condition setup time
4000
600
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
11
TAA
Output valid from clock
(Note 2)
—
—
3500
900
ns
1.7 V VCC 2.5V
2.5 V VCC 5.5V
12
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
—
—
ns
1.7V VCC 2.5V
2.5V VCC 5.5V
13
TOF
Output fall time from VIH
minimum to VIL maximum
CB 100 pF
10 + 0.1CB
250
ns
(Note 1)
14
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Notes 1 and 3)
15
TWC
Write cycle time (byte or
page)
—
5
ms
—
16
—
Endurance
1,000,000
—
Note 1:
2:
3:
4:
cycles Page mode, 25°C, 5.5V (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
2013 Microchip Technology Inc.
DS20005215A-page 3
24AA256UID
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
IN
D3
2
3
8
9
4
10
6
14
12
11
SDA
OUT
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
8-pin
PDIP
8-pin
SOIC
8-pin
TSSOP
A0
1
1
1
User Configurable Chip Select
A1
2
2
2
User Configurable Chip Select
Name
Function
A2
3
3
3
User Configurable Chip Select
VSS
4
4
4
Ground
SDA
5
5
5
Serial Data
SCL
6
6
6
Serial Clock
NC
7
7
7
Not Connected
VCC
8
8
8
+1.7V to 5.5V
2.1
A0, A1, A2 Chip Address Inputs
2.2
Serial Data (SDA)
The A0, A1 and A2 inputs are used by the 24AA256UID
for multiple device operations. The levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
DS20005215A-page 4
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2013 Microchip Technology Inc.
24AA256UID
3.0
FUNCTIONAL DESCRIPTION
The 24AA256UID supports a bidirectional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24AA256UID works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Note:
The 24AA256UID does not generate any
Acknowledge bits
if an internal
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24AA256UID) will leave the data line high to
enable the master to generate the Stop condition.
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
2013 Microchip Technology Inc.
DS20005215A-page 5
24AA256UID
FIGURE 4-1:
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
FIGURE 4-2:
Data
Allowed
to Change
Stop
Condition
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
Data from transmitter
SDA
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
DS20005215A-page 6
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
2013 Microchip Technology Inc.
24AA256UID
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
24AA256UID, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24AA256UID devices
on the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bits are a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24AA256UID monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24AA256UID will select a
read or write operation.
FIGURE 5-2:
0
1
Control
Code
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
A2
0
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24AA256UID devices on the
same bus. In this case, software can use A0 of the
control byte as address bit A15; A1 as address bit
A16; and A2 as address bit A17. It is not possible to
sequentially read across device boundaries.
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
CONTROL BYTE
FORMAT
0
A
2
A
1
Address High Byte
A
0 R/W
Chip
Select
Bits
2013 Microchip Technology Inc.
x
A A A A A
14 13 12 11 10
Address Low Byte
A
9
A
8
A
7
•
•
•
•
•
•
A
0
x = “don’t care” bit
DS20005215A-page 7
24AA256UID
6.0
WRITE OPERATIONS
6.3
6.1
Byte Write
The upper eighth of the array (7000h-7FFFh) is permanently write-protected. Write operations to this address
range are inhibited. Read operations are not affected.
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24AA256UID. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24AA256UID, the master
device will transmit the data word to be written into the
addressed memory location. The 24AA256UID
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24AA256UID will not generate
Acknowledge signals (Figure 6-1).
Note:
6.2
When doing a write of less than 64 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Write Protection
The remainder of the array (0000h-6FFFh) can be written to and read from normally.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA256UID in much the
same way as in a byte write. The exception is that
instead of generating a Stop condition, the master
transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a
Stop condition. Upon receipt of each word, the six lower
Address Pointer bits are internally incremented by one.
If the master should transmit more than 64 bytes prior
to generating the Stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
Stop condition is received, an internal write cycle will
begin (Figure 6-2).
DS20005215A-page 8
2013 Microchip Technology Inc.
24AA256UID
FIGURE 6-1:
BYTE WRITE
SDA Line
S
T
A
R
T
Bus Activity
AA
S1 0 10A
2 10 0
Bus Activity
Master
Control
Byte
Bus Activity
Master
SDA Line
Bus Activity
Address
Low Byte
S
T
O
P
Data
x
P
A
C
K
x = “don’t care” bit
FIGURE 6-2:
Address
High Byte
A
C
K
A
C
K
A
C
K
PAGE WRITE
S
T
A
R
T
Control
Byte
Address
High Byte
AAA
S101 02 1 00
x = “don’t care” bit
2013 Microchip Technology Inc.
Address
Low Byte
S
T
O
P
Data Byte 63
Data Byte 0
P
x
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS20005215A-page 9
24AA256UID
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
the flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
DS20005215A-page 10
2013 Microchip Technology Inc.
24AA256UID
8.0
READ OPERATION
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24AA256UID as part of a write operation (R/W bit set to
‘0’). Once the word address is sent, the master generates a Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24AA256UID will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24AA256UID to discontinue transmission (Figure 8-2). After a random
Read command, the internal address counter will point
to the address location following the one that was just
read.
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24AA256UID contains an address counter that
maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24AA256UID issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24AA256UID discontinues transmission (Figure 8-1).
FIGURE 8-1:
8.3
S
T
A
R
T
SDA Line
S 1 0 1 0 A AA 1
2 1 0
Control
Byte
FIGURE 8-2:
Bus Activity
Master
SDA Line
P
A
C
K
Bus Activity
S
T
O
P
Data
Byte
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24AA256UID transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a
random read. This acknowledge directs the
24AA256UID to transmit the next sequentially
addressed 8-bit word (Figure 8-3). Following the final
byte transmitted to the master, the master will NOT
generate an acknowledge, but will generate a Stop
condition. To provide sequential reads, the
24AA256UID contains an internal Address Pointer
which is incremented by one at the completion of each
operation. This Address Pointer allows the entire memory contents to be serially read during one operation.
The internal Address Pointer will automatically roll over
from address 7FFF to address 0000 if the master
acknowledges the byte received from the array
address 7FFF.
CURRENT ADDRESS
READ
Bus Activity
Master
Random Read
N
O
A
C
K
RANDOM READ
S
T
A
R
T
Control
Byte
Address
High Byte
S1 01 0 AAA0
2 1 0
x
A
C
K
A
C
K
Bus Activity
S
T
A
R
T
Address
Low Byte
A
C
K
Control
Byte
S 1 0 1 0 A A A1
2 1 0
S
T
O
P
Data
Byte
P
N
O
A
C
K
A
C
K
x = “don’t care” bit
FIGURE 8-3:
Bus Activity
Master
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
S
T
O
P
Data (n + x)
Data (n + 2)
P
SDA Line
Bus Activity
2013 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
DS20005215A-page 11
24AA256UID
9.0
PRE-PROGRAMMED SERIAL
NUMBER AND NODE
ADDRESSES
The 24AA256UID is programmed at the factory with
globally unique EUI-48 and EUI-64 node addresses,
and a 32-bit serial number stored in the upper eighth of
the array and permanently write-protected. The
remaining 229,376 bits are available for application
use.
FIGURE 9-1:
MEMORY ORGANIZATION
0000h
(User – Writable)
6FFFh
7000h
Unused (Read as 0xFF)
7F79h
7F7Ah
7F7Fh
Unused (Read as 0xFF)
EUI-64™ Node Address
7FB8h
7FBFh
Note:
7FFAh
7FFFh
Shaded region is permanently write-protected
DS20005215A-page 12
The 24AA256UID features a unique 32-bit serial
number stored in array locations 0x7FFC through
0x7FFF, as shown in Figure 9-2.
Note:
9.1.1
The 32-bit serial number is unique across
all Microchip UID-family serial EEPROM
devices.
MANUFACTURER AND DEVICE
IDENTIFIERS
In addition to the serial number, a manufacturer code is
stored at location 0x7FFA and a device identifier is
stored at 0x7FFB. The manufacturer code is fixed as
0x29. For the 24AA256UID, the device identifier is
0x48. The ‘4’ indicates the I2C™ family and the ‘8’ indicates a 256 Kbit memory density.
EXTENDING THE 32-BIT SERIAL
NUMBER
For applications that require serial numbers larger than
32 bits, additional data bytes can be used to pad the
provided serial number to meet the required length.
Any data byte values can be used for padding as the
32-bit serial number ensures the extended serial
number remains unique.
The padding can be performed in two ways. The first
method is to pad the data in software by combining the
32-bit serial number from the 24AA256UID with fixed
data. The second method is to extend the number of
bytes read from the 24AA256UID to meet the required
length. Table 9-1 shows example address ranges and
their corresponding serial number lengths.
TABLE 9-1:
Unused (Read as 0xFF)
32-Bit Serial Number and Identifiers
32-Bit Serial Number
9.1.2
Standard EEPROM
EUI-48™ Node Address
9.1
Start Address
EXTENDED READ EXAMPLES
End Address
Serial Number
Length
0x7FFC
0x7FFF
32 bits
0x7FFA
0x7FFF
48 bits
0x7FF8
0x7FFF
64 bits
0x7FF0
0x7FFF
128 bits
0x7FE0
0x7FFF
256 bits
2013 Microchip Technology Inc.
24AA256UID
FIGURE 9-2:
SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE
Description
Manufacturer
Code
Device
Code
Data
29h
48h
Type
Array
Address
9.2
32-bit Serial Number
12h
34h
Fixed
7FFAh
7FFBh
7FFCh
7FFDh
9.3
The 6-byte EUI-48 node address value is stored in
array locations 0x7F7A through 0x7F7F, as shown in
Figure 9-3. The first three bytes are the
Organizationally Unique Identifier (OUI) assigned to
Microchip by the IEEE Registration Authority. Currently,
Microchip’s OUIs are 0x0004A3 and 0x001EC0,
though this will change as addresses are exhausted.
The remaining three bytes are the Extension Identifier,
and are generated by Microchip to ensure a globally
unique, 48-bit value.
7FFEh
7FFFh
EUI-64 Node Address
The 8-byte EUI-64 node address value is stored in
array locations 0x7FB8 through 0x7FBF, as shown in
Figure 9-4. The first three bytes are the
Organizationally Unique Identifier (OUI) assigned to
Microchip by the IEEE Registration Authority. Currently,
Microchip’s OUIs are 0x0004A3 and 0x001EC0,
though this will change as addresses are exhausted.
The remaining five bytes are the Extension Identifier,
and are generated by Microchip to ensure a globally
unique, 64-bit value.
Note:
Description
78h
Serialized
EUI-48 Node Address
FIGURE 9-3:
56h
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values are specifically reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE
24-bit Extension
Identifier
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
7F7Ah
04h
A3h
12h
34h
56h
7F7Fh
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56
2013 Microchip Technology Inc.
DS20005215A-page 13
24AA256UID
FIGURE 9-4:
EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE
24-bit Organizationally
Unique Identifier
Description
Data
00h
Array
Address
7FB8h
04h
A3h
40-bit Extension
Identifier
12h
34h
56h
78h
90h
7FBFh
Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90
DS20005215A-page 14
2013 Microchip Technology Inc.
24AA256UID
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
8-Lead PDIP (300 mil)
4A256UID
I/P e3 017
1321
XXXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
YYWW
NNN
Legend: XX...X
T
Y
YY
WW
NNN
e3
Example:
Example:
4A256UID
SN e3 1321
017
Example:
AAAP
1321
017
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
2013 Microchip Technology Inc.
DS20005215A-page 15
24AA256UID
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
N
NOTE 1
E1
1
3
2
D
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9'&!
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7,8.
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9
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: *+
1,
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!#.#
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1,21!'!
&$& "!
**&
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* ,<1
DS20005215A-page 16
2013 Microchip Technology Inc.
24AA256UID
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005215A-page 17
24AA256UID
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005215A-page 18
2013 Microchip Technology Inc.
24AA256UID
!
""#$%& !'
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
2013 Microchip Technology Inc.
DS20005215A-page 19
24AA256UID
() )"* !
(+%+(
!
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
6&!
'!
9'&!
7"')
%!
99..
7
7
7:
;
<
&
: 8&
=
?1,
=
##44!!
<
&#
%%
=
: >#&
.
##4>#&
.
-
?1,
##49&
-
-
3
&9&
9
?
3
&&
9
.3
3
&
R
=
<R
9#4!!
=
9#>#&
)
=
-
!"#$%&"' ()"&'"!&)
&#*&&&#
'!
!#.#
&"#'
#%!
&"!
!
#%!
&"!
!!
&$#''!#
- '!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
.32 %'!
("!"*&
"&&
(%
%
'&
"
!!
* ,<?1
DS20005215A-page 20
2013 Microchip Technology Inc.
24AA256UID
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005215A-page 21
24AA256UID
APPENDIX A:
REVISION HISTORY
Revision A (06/2013)
Initial Release.
DS20005215A-page 22
2013 Microchip Technology Inc.
24AA256UID
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration
instructions.
2013 Microchip Technology Inc.
DS20005215A-page 23
24AA256UID
NOTES:
DS20005215A-page 24
2013 Microchip Technology Inc.
24AA256UID
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
Device
Device:
Temperature
Range
Package
24AA256UID = 256 Kbit 1.7V I2C Serial
EEPROM, with EUI-48 and
EUI-64 Node Identities and 32-bit
Serial Number
24AA256UIDT = 256 Kbit 1.7V I2C Serial
EEPROM, with EUI-48 and
EUI-64 Node Identities and 32-bit
Serial Number (Tape and Reel)
Temperature I
Range:
Package:
/XX
P
SN
ST
=
Examples:
a)
24AA256UID-I/P: Industrial Temp.,
1.7V, PDIP package.
b)
24AA256UIDT-I/SN: Tape and Reel,
Industrial Temp., 1.7V, SOIC
package.
c)
24AA256UID-I/ST: Industrial Temp.,
1.7V, TSSOP package.
-40C to +85C
= Plastic DIP (300 mil body), 8-lead
= Plastic SOIC (3.90 mm body), 8-lead
= Plastic TSSOP (4.4 mm), 8-lead
2013 Microchip Technology Inc.
DS20005215A-page 25
24AA256UID
NOTES:
DS20005215A-page 26
2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620772911
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005215A-page 27
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
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Tel: 216-447-0464
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Tel: 408-961-6444
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Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS20005215A-page 28
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
2013 Microchip Technology Inc.