ETC STK17T88

STK17T88
TM
nvTime Event Data Recorder
32K x 8 AutoStoreTM nvSRAM
With Real-Time Clock
FEATURES
• Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
o Low Power, 300 nA Max, RTC current
o Capacitor or battery backup for RTC
• Watchdog Timer
• Clock Alarm with programmable Interrupts
• 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic STORE on Power Down
with only a small capacitor
• STORE to QuantumTrap™ Initiated by
Software , device pin, or on Power Down
• RECALL to SRAM Initiated by Software or
Power Up
• Unlimited READ, WRITE and RECALL Cycles
• High-reliability
o Endurance to 1 Million Cycles
o Retention to 100 years at 125 ºC
• 5mA Typical ICC at 200ns Cycle Time
• Single 3V +20%, -10% Operation
• SSOP and DIP Packages, (ROHS compliant)
DESCRIPTION
The Simtek STK17T88 combines a 256 Kbit
nonvolatile static RAM with a full-featured real-time
clock in a reliable, monolithic integrated circuit. The
embedded
nonvolatile
elements
incorporate
Simtek’s QuantumTrap™ technology producing the
world’s most reliable nonvolatile memory. The
SRAM can be read and written an unlimited number
of times, while independent, nonvolatile data resides
in the nonvolatile elements.
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic seconds,
minutes, hours, or days. There is also a programmable Watchdog Timer for process control.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
INPUT BUFFERS
Quantum Trap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
VRTCbat
VRTCcap
HSB
SOFTWARE
DETECT
A13 – A0
COLUMN I/O
COLUMN DEC
RTC
X1
X2
INT
A 0 A 1 A 2 A 3 A 4 A10
MUX
A14 – A0
G
E
W
Figure 1. Block Diagram
April 2005
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Document Control #ML0024 rev 1.2
STK17T88
PACKAGES
VCAP
A14
A12
A7
A6
A5
INT
A4
VSS
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48 Pin SSOP
VCC
VCAP
HSB
W
A13
A8
A9
A14
A11
INT
A4
VSS
A12
A7
A6
A5
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
X1
X2
VSS
VRTCcap
DQ6
G
A10
E
DQ7
DQ5
DQ4
DQ3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
HSB
W
A13
A8
A9
A11
VSS
G
A10
E
DQ7
DQ6
VRTCcap
DQ5
DQ4
DQ3
VCC
40 Pin PDIP
48 Pin SSOP
Relative PCB area usage.
See website for detailed
package size specifications.
PIN DESCRIPTIONS
Pin Name
I/O
A14 – A0
Input
DQ7 –DQ0
I/O
E
Input
W
Input
Description
Address: The 15 address inputs select one of 32,752 bytes in the nvSRAM array or one of 16 bytes in the clock
register map.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and RTC.
Chip Enable: The active low E
input selects the device.
Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the
falling edge of E .
G
X1
X2
VRTCcap
VRTCbat
VCC
HSB
INT
Input
Output
Input
Power Supply
Power Supply
Power Supply
I/O
Output
VCAP
Power Supply
VSS
(Blank)
Power Supply
No Connect
April 2005
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high
causes the DQ pins to tri-state.
Crystal Connection, drives crystal on startup.
Crystal Connection for 32.768 kHz crystal.
Capacitor supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used.)
Battery supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used.)
Power 3.0V +20%, -10%
Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external
to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not
connected. (Connection Optional)
Interrupt Output: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor.
Programmable to either active high (push/pull) or active low (open-drain).
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile
elements.
Ground
Unlabeled pins have no internal connection.
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Document Control #ML0024 rev 1.2
STK17T88
ABSOLUTE MAXIMUM RATINGSa
-0.5V to +4.1V
Power Supply Voltage
-0.5V to (VCC + 0.5V)
Voltage on Input Relative to VSS
-0.5V to (VCC + 0.5V)
Voltage on Outputs
Temperature under Bias
–55°C to 125°C
Junction Temperature
–55°C to 140°C
Storage Temperature
–65°C to 150°C
Power Dissipation
1W
DC Output Current (1 output at a time, 1s duration)
15mA
Notes
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Symbol
Parameter
ICC1
Average VCC Current
ICC2
Average VCC Current during STORE
Commercial
MIN
MAX
Industrial
MIN
MAX
Units
Notes
65
55
50
70
60
55
mA
mA
mA
3
3
mA
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE).
Average VCC Current at tAVAV = 200ns
ICC3
ICC4
3V, 25°C, Typical
Average VCAP Current during
AutoStore™ Cycle
5
5
mA
3
3
mA
W ≥ (VCC – 0.2V)
All Others Inputs Cycling, at CMOS Levels.
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE).
mA
E ≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle is complete.
VCC Standby Current
ISB
IILK
(Standby, Stable CMOS Input Levels)
2
2
VCC = max
Input Leakage Current
±1
±1
µA
±1
±1
µA
VIN = VSS to VCC, E or G ≥ VIH
V
All Inputs
IOLK
Off-State Output Leakage Current
VIH
Input Logic “1” Voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
VSS – 0.5
0.8
VSS – 0.5
0.8
VIL
Input Logic “0” Voltage
VOH
Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
TA
Operating Temperature
2.4
2.4
0.4
0.4
VIN = VSS to VCC
VCC = max
V
All Inputs
V
IOUT = –2mA
V
IOUT = 4mA
o
0
70
–40
85
VCC
Operating Voltage
2.7
3.6
2.7
3.6
V
3.0V +20%, -10%
VCAP
Storage Capacitor
17
57
17
57
µF
Between Vcap pin and Vss, 6.3V rated.
April 2005
3
C
Document Control #ML0024 rev 1.2
STK17T88
AC TEST CONDITIONS
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
≤ 5ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figure 2 and Figure 3
CAPACITANCE
b
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
CIN
Input Capacitance
7
pF
∆V = 0 to 3V
COUT
Output Capacitance
7
pF
∆V = 0 to 3V
Notes
b: These parameters are guaranteed but not tested
3.0V
3.0V
577 Ohms
577 Ohms
OUTPUT
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
789 Ohms
Figure 2. AC Output Loading
April 2005
530
pFpF
INCLUDING
SCOPE AND
FIXTURE
Figure 3. AC Output Loading,
for tristate specs (
tHZ, tLZ, tWLQZ, tWHQZ,
tGLQX, tGHQZ )
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Document Control #ML0024 rev 1.2
STK17T88
RTC DC CHARACTERISTICS
Symbol
IBAK
VRTCbat
VRTCcap
tOSCS
Parameter
Commercial
RTC Capacitor Pin Voltage
Units
Notes
MAX
MIN
MAX
-
300
-
350
nA
1.8
3.3
1.8
3.3
V
1.2
2.7
1.2
2.7
V
-
1
1
min
10
-
From either VRTCcap or VRTCbat
Typical = 3.0 Volts during normal
operation
Typical = 2.4 Volts during normal
operation
@ MIN Temperature from Power up
or Enable
10
sec
@25ºC from Power up or Enable
RTC Backup Current
RTC Battery Pin Voltage
Industrial
MIN
RTC Oscillator time to start
Y1
C2
RF
C1
RTC RECOMMENDED COMPONENT CONFIGURATION
X1
X2
Recommended Values
Y1 = 32.768 KHz
RF = 10M Ohm
C1 = 2.2 pF
C2 = 47 pF
Figure 4. RTC COMPONENT CONFIGURATION
April 2005
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Document Control #ML0024 rev 1.2
STK17T88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
1
c
2
tAVAV
3
tAVQV
STK17T88-35
STK17T88-45
MIN
MIN
MIN
UNITS
Alt.
MAX
tELQV
tACS
Chip Enable Access Time
tAVAVc
tRC
Read Cycle Time
tAA
Address Access Time
25
tOE
Output Enable to Data Valid
12
d
tGLQV
4
5
STK17T88-25
PARAMETER
d
tAXQX
25
25
45
ns
35
45
ns
15
20
ns
35
45
ns
Output Hold after Address Change
3
3
3
ns
tLZ
Chip Enable to Output Active
3
3
3
ns
tELQX
7
tEHQZ
tHZ
Chip Disable to Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZ
tOHZ
Output Disable to Output Inactive
10
tELICCb
tPA
Chip Enable to Power Active
11
tEHICC
b
tPS
Chip Disable to Power Standby
e
35
MAX
tOH
6
e
MAX
10
0
13
0
10
0
15
0
13
0
15
0
25
35
ns
ns
ns
ns
45
ns
Notes
c: W must be high during SRAM READ cycles
d: Device is continuously selected with E and G both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledc,f
2
tAVAV
ADDRESS
E
1
tELQV
6
11
tEHICCL
tELQX
7
tEHQZ
G
9
tGHQZ
4
8
tGLQX
DQ (DATA OUT)
tGLQV
DATA VALID
10
tELICCH
ICC
April 2005
ACTIVE
STANDBY
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Document Control #ML0024 rev 1.2
STK17T88
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
PARAMETER
#2
Alt.
STK17T88-25
STK17T88-35
STK17T88-45
MIN
MIN
MIN
MAX
MAX
UNITS
MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
35
45
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
25
30
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
25
30
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
12
15
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
25
30
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
20
tWLQZe,g
tWZ
Write Enable to Output Disable
21
tWHQX
tOW
Output Active after End of Write
0
10
3
0
13
ns
15
3
3
ns
ns
Notes
g: If W is low when E goes low, the outputs remain in the high-impedance state.
h: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
13
tWLWH
tAVWL
W
15
tDVWH
16
tWHDX
DATA VALID
DATA IN
20
tWLQZ
DATA OUT
HIGH IMPEDANCE
PREVIOUS DATA
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledh,f
12
tAVAV
ADDRESS
14
tELEH
18
tAVEL
19
tEHAX
E
17
tAVEH
W
13
tWLEH
16
tEHDX
15
tDVEH
DATA IN
DATA OUT
April 2005
DATA VALID
HIGH IMPEDANCE
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Document Control #ML0024 rev 1.2
STK17T88
MODE SELECTION
E
W
G
A13 - A0
MODE
I/O
POWER
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
i, j, k
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
i, j, k
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
L
L
L
H
H
H
H
L
NOTES
Active
i, j, k
ICC2
Active
i, j, k
Notes
i: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
j: While there are 15 addresses on the STK17T88, only the lower 14 are used to control software modes
k: I/O state depends on the state of G . The I/O table shown assumes G low.
April 2005
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Document Control #ML0024 rev 1.2
STK17T88
AutoStore™ /POWER-UP RECALL
SYMBOLS
PARAMETER
STK17T88
NO.
Standard
22
tHRECALL
23
tSTORE
24
VSWITCH
25
tVCCRISE
Alternate
MIN
Power-up RECALL Duration
tHLHZ
STORE Cycle Duration
2.55
Low Voltage Trigger Level
VCC Rise Time
Notes
l: tHRECALL starts from the time VCC rises above VSWITCH
m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
UNITS
NOTES
20
ms
l
12.5
ms
m
MAX
2.65
µs
STORE occurs only if a
SRAM write has
happened.
AutoStore™/POWER-UP RECALL
V
150
No STORE occurs
without at least one
SRAM write.
VCC
24
VSWITCH
25
tVCCRISE
AutoStoreTM
23
tSTORE
23
tSTORE
POWER-UP RECALL
22
tHRECALL
22
tHRECALL
Read & Write Inhibited
POWER-UP
RECALL
BROWN OUT
TM
AutoStore
POWER-UP
RECALL
POWER DOWN
TM
AutoStore
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH.
April 2005
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Document Control #ML0024 rev 1.2
STK17T88
SOFTWARE-CONTROLLED STORE/RECALL CYCLEn,o
SYMBOLS
NO.
E
G
cont
STK17T88-25
STK17T88-35
STK17T88-45
MIN
MIN
MIN
PARAMETER
Alt.
MAX
MAX
UNITS
NOTES
45
ns
o
MAX
cont
26
tAVAV
tAVAV
tRC
STORE/RECALL Initiation Cycle Time
27
tAVEL
28
tELEH
29
tELAX
tGLAX
25
35
tAVGL
tAS
Address Set-up Time
0
0
0
ns
tGLGH
tCW
Clock Pulse Width
20
25
30
ns
Address Hold Time
20
20
20
ns
30
tRECALL
tRECALL
40
RECALL Duration
Notes
n: The software sequence is clocked with E controlled READs or G controlled READs.
o: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W
40
40
µs
must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
ADDRESS
E
27
tAVEL
26
tAVAV
26
tAVAV
ADDRESS #1
ADDRESS #6
28
tELEH
29
tELAX
G
23
tSTORE
DQ (DATA)
DATA VALID
DATA VALID
/
30
tRECALL
HIGH IMPEDENCE
SOFTWARE STORE/RECALL CYCLE: G Controlledo
ADDRESS
26
tAVAV
26
tAVAV
ADDRESS #1
ADDRESS #6
E
27
tAVGL
28
tGLGH
G
23
tSTORE
29
tGLAX
DQ (DATA)
April 2005
DATA VALID
DATA VALID
10
/
30
tRECALL
HIGH IMPEDENCE
Document Control #ML0024 rev 1.2
STK17T88
HARDWARE STORE CYCLE
SYMBOLS
STK17T88
NO.
PARAMETER
Standard
31
tDELAY
32
tHLHX
Alternate
tHLQZ
MIN
UNITS
NOTES
p
MAX
Time Allowed to Complete SRAM Cycle
1
µs
Hardware STORE Pulse Width
15
ns
tHLBL
Hardware STORE Low to STORE Busy
33
Notes
p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
300
ns
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
HSB (OUT)
33
tHLBL
23
tSTORE
HIGH IMPEDENCE
HIGH IMPEDENCE
31
tDELAY
DQ (DATA OUT)
April 2005
DATA VALID
DATA VALID
11
Document Control #ML0024 rev 1.2
DEVICE OPERATION
nvSRAM
The STK17T88 nvSRAM is made up of two functional
components paired in the same physical cell. These
are a SRAM memory cell and a
nonvolatile
QuantumTrap™ cell. The SRAM memory cell
operates as a standard fast static RAM. Data in the
SRAM can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique
architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL
operations SRAM READ and WRITE operations are
inhibited. The STK17T88 supports unlimited reads
and writes just like a typical SRAM. In addition, it
provides unlimited RECALL operations from the
nonvolatile cells and up to 1 million STORE
operations.
SRAM READ
The STK17T88 performs a READ cycle whenever
E and G are low while W and HSB are high.
The address specified on pins A14-0 determines which
of the 32,752 data bytes will be accessed. When the
READ is initiated by an address transition, the
outputs will be valid after a delay of tAVQV (READ
cycle #1). If the READ is initiated by E or G , the
outputs will be valid at tELQV or at tGLQV, whichever is
later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
tAVQV access time without the need for transitions on
any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W or HSB is brought low.
W
0.1µF
VCC
VCAP
VCAP
10k Ohm
VCC
SRAM WRITE
A WRITE cycle is performed whenever E and W
are low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry will
turn off the output buffers tWLQZ after W goes low.
AutoStore™ OPERATION
The STK17T88 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
actived by an address sequence, and AutoStore™, on
device power down.
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK17T88.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc. A
STORE operation will be initiated with power provided
by the Vcap capacitor.
Figure 5 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer
to the DC CHARACTERISTICS table for the size of
Vcap. The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB signal can be monitored by the system to detect
an AutoStore™ cycle is in progress.
Figure 5: AutoStoreTM Mode
April 2005
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Document Control #ML0000 1.2
STK17T88
HARDWARE STORE ( HSB ) OPERATION
The STK17T88 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK17T88 will
conditionally initiate a STORE operation after tDELAY.
An actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17T88 will
continue SRAM operations for tDELAY. During tDELAY,
multiple SRAM READ operations may take place. If
a WRITE is in progress when HSB is pulled low it
will be allowed a time, tDELAY, to complete. However,
any SRAM WRITE cycles requested after HSB goes
low will be inhibited until HSB returns high.
During any STORE operation, regardless of how it
was initiated, the STK17T88 will continue to drive
the HSB pin low, releasing it only when the STORE
is complete. Upon completion of the STORE
operation the STK17T88 will remain disabled until
the HSB pin returns high.
If
HSB
is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will
automatically be initiated and will take tHRECALL to
complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the
nonvolatile memory by a software address sequence.
The STK17T88 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations in exact order. During
the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and no
STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1.
2.
3.
4.
5.
6.
13
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence may be clocked with
controlled READs or G controlled READs.
E
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory
to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of
READ operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the
following sequence of E controlled READ operations
must be performed:
1.
2.
3.
4.
5.
6.
April 2005
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Document Control #ML0024 rev 1.2
STK17T88
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. After the tRECALL cycle time the SRAM will once
again be ready for READ and WRITE operations.
The RECALL operation in no way alters the data in
the nonvolatile elements.
PREVENTING AUTOSTORETM
The AutoStore™ function can be disabled by initiating an AutoStore Disable sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence
of E controlled read operations must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
AutoStore Disable
NOISE CONSIDERATIONS
The STK17T88 is a high-speed memory and so must
have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and VSS,
using leads and traces that are as short as possible.
As with all high-speed CMOS ICs, careful routing of
power, ground and signals will reduce circuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK17T88 this the
benefit of drawing significantly less current when it is
cycled at times longer than 50ns. Figure 6 shows the
relationship between ICC and READ/WRITE cycle
time. Worst-case current consumption is shown for
commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current
is drawn when the chip is disabled. The overall
average current drawn by the STK17T88 depends on
the following items:
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
AutoStore Enable
If the AutoStore™ function is disabled or re-enabled
a manual STORE operation (Hardware or Software)
needs to be issued to save the AutoStore state
through subsequent power down cycles. The part
comes from the factory with AutoStore™ enabled.
DATA PROTECTION
The STK17T88 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC < VSWITCH .
If the STK17T88 is in a WRITE mode (both E and
W low ) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
April 2005
14
Average Active Current (mA)
The AutoStore™ can be re-enabled by initiating an
AutoStore Enable sequence. A sequence of read
operations is performed in a manner similar to the
software RECALL initiation. To initiate the AutoStore
Enable sequence, the following sequence of E
controlled read operations must be performed:
The duty cycle of chip enable.
The overall cycle rate for accesses.
The ratio of READs to WRITEs.
The operating temperature.
The VCC level.
I/O loading.
50
40
30
Writes
20
10
Reads
0
50
100 150 200 300
Cycle Time (ns)
Figure 6 Current vs. Cycle time
Document Control #ML0024 rev 1.2
STK17T88
REAL TIME CLOCK OPERATION
nvTIME OPERATION
SETTING THE CLOCK
The STK17T88 offers internal registers that contain
Clock, Alarm, Watchdog, Interrupt, and Control
functions. Internal double buffering of the clock and
the clock/timer information registers prevents
accessing transitional internal clock data during a
read or write operation. Double buffering also circumvents disrupting normal timing counts or clock
accuracy of the internal clock while accessing clock
data. Clock and Alarm Registers store data in BCD
format.
Setting the write bit “W” (in the flags register at
0x7FF0) to a “1” halts updates to the STK17T88
registers. The correct day, date and time can then be
written into the registers in 24-hour BCD format. The
time written is referred to as the “Base Time.” This
value is stored in nonvolatile registers and used in
calculation of the current time. Resetting the write bit
to “0” transfers those values to the actual clock
counters, after which the clock resumes normal
operation.
BACKUP POWER
CLOCK OPERATIONS
The clock registers maintain time up to 9,999 years in
one second increments. The user can set the time to
any calendar time and the clock automatically keeps
track of days of the week and month, leap years and
century transitions. There are eight registers
dedicated to the clock functions which are used to set
time with a write cycle and to read time during a read
cycle. These registers contain the Time of Day in
BCD format. Bits defined as “X” are currently not used
and are reserved for future use by Simtek.
READING THE CLOCK
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
STK17T88 clock registers before reading clock data
to prevent the reading of data in transition. Stopping
the internal register updates does not affect clock
accuracy.
The updating process is stopped by writing a “1” to
the read bit “R” (in the flags register at 0x7FF0), and
will not restart until a “0” is written to the read bit. The
RTC registers can then be read while the internal
clock continues to run.
Within 20ms after a “0” is written to the read bit, all
STK17T88 registers are simultaneously updated.
The RTC in the STK17T88 is intended for
permanently powered operation. Either the VRTCcap or
VRTCbat pin is connected depending on whether a
capacitor or battery is chosen for the application.
When primary power, Vcc, fails and drops below Vswitch
the device will switch to the backup power supply.
The clock oscillator uses very little current, which
maximizes the backup time available from the backup
source. Regardless of clock operation with the
primary source removed, the data stored in nvSRAM
is secure, having been stored in the nonvolatile
elements as power was lost. Factors to be considered
when choosing a backup power source include: the
expected duration of power outages and the cost
trade-off of using a battery versus a capacitor.
During backup operation the STK17T88 consumes a
maximum of 300 nanoamps at 2 volts. Capacitor or
battery values should be chosen according to the
application. Backup time values based on maximum
current specs are shown below. Nominal times are
approximately 3 times longer.
Capacitor Value
Backup Time
0.1 F
72 hours
0.47 F
14 days
1.0 F
30 days
Using a capacitor has the obvious advantage of
recharging the backup source each time the system is
powered up.
April 2005
15
Document Control #ML0024 rev 1.2
STK17T88
If a battery is used, a 3V lithium is recommended and
the STK17T88 will only source current from the battery when the primary power is removed. The battery
will not, however, be recharged at any time by the
STK17T88. The battery capacity should be chosen
for total anticipated cumulative down-time required
over the life of the system.
STOPPING AND STARTING THE OSCILLATOR
The OSCEN bit in calibration register at 0x7FF8
controls the starting and stopping of the oscillator.
This bit is nonvolatile and shipped to customers in the
"enabled" (set to 0) state. To preserve battery life
while system is in storage OSCEN should be set to a
1. This will turn off the oscillator circuit extending the
battery life. If the OSCEN bit goes from disabled to
enabled, it will take approximately 5 seconds (10
seconds max) for the oscillator to start.
The STK17T88 has the ability to detect oscillator
failure. This is recorded in the OSCF (Oscillator
Failed bit) of the flags register at address 0x7FF0.
When the device is powered on (VCC goes above
Vswitch) the OSCEN bit is checked for "enabled" status.
If the OSCEN bit is enabled and the oscillator is not
active, the OSCF bit is set. The user should check for
this condition and then write a 0 to clear the flag. It
should be noted that in addition to setting the OSCF
flag bit, the time registers are reset to the “Base Time”
(see the section “Setting the Clock”), which is the
value last written to the timekeeping registers. The
Control/Calibration register and the OSCEN bit are not
affected by the oscillator failed condition.
If the voltage on the backup supply (either VRTCcap or
VRTCbat) falls below their respective minimum level the
oscillator may fail, leading to the oscillator failed
condition which can be detected when system power
is restored.
The value of OSCF should be reset to 0 when the
time registers are written for the first time. This will
initialize the state of this bit which may have become
set when the system was first powered on.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal,
usually specified to 35 ppm limits at 25°C. This error
could equate to + 1.53 minutes per month. The
STK17T88 employs a calibration circuit that can
improve the accuracy to +1/-2 ppm at 25°C. The
April 2005
16
calibration circuit adds or subtracts counts from the
oscillator divider circuit.
The number of times pulses are suppressed (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into the
five calibration bits found in calibration register at
0x7FF8. Adding counts speeds the clock up;
subtracting counts slows the clock down. The
Calibration bits occupy the five lower order bits in the
control register 8. These bits can be set to represent
any value between 0 and 31 in binary form. Bit D5 is a
Sign bit, where a “1” indicates positive calibration and
a “0” indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so
on. Therefore each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register.
In order to determine how to set the calibration one
may set the CAL bit in the flags register at 0x7FF0 to
1, which causes the INT pin to toggle at a nominal
512 Hz. Any deviation measured from the 512 Hz will
indicate the degree and direction of the required
correction. For example, a reading of 512.010124 Hz
would indicate a +20 ppm error, requiring a -10
(001010) to be loaded into the Calibration register.
Note that setting or changing the calibration register
does not affect the frequency test output frequency.
ALARM
The alarm function compares user-programmed values to the corresponding time-of-day values. When a
match occurs, the alarm event occurs. The alarm
drives an internal flag, AF, and may drive the INT pin
if desired.
There are four alarm match fields. They are date,
hours, minutes and seconds. Each of these fields also
has a Match bit that is used to determine if the field is
used in the alarm match logic. Setting the Match bit to
“0” indicates that the corresponding field will be used
in the match process.
Depending on the Match bits, the alarm can occur as
specifically as one particular second on one day of
the month, or as frequently as once per second
Document Control #ML0024 rev 1.2
STK17T88
continuously. The MSB of each alarm register is a
Match bit. Selecting none of the Match bits (all 1’s)
indicates that no match is required. The alarm occurs
every second. Setting the match select bit for seconds
to “0” causes the logic to match the seconds alarm
value to the current time of day. Since a match will
occur for only one value per minute, the alarm occurs
once per minute. Likewise, setting the seconds and
minutes Match bits causes an exact match of these
values. Thus, an alarm will occur once per hour.
Setting seconds, minutes and hours causes a match
once per day. Lastly, selecting all match values
causes an exact time and date match. Selecting other
bit combinations will not produce meaningful results;
however the alarm circuit should follow the functions
described.
There are two ways a user can detect an alarm event,
by reading the AF flag or monitoring the INT pin. The
AF flag in the flags register at 0x7FF0 will indicate
that a date/time match has occurred. The AF bit will
be set to 1 when a match occurs. Reading the
Flags/Control register clears the alarm flag bit (and all
others). A hardware interrupt pin may also be used to
detect an alarm event.
WATCHDOG TIMER
The watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The oscillator must be running for
the watchdog to function. It begins counting down
from the value loaded in the Watchdog Timer register.
The counter consists of a loadable register and a free
running counter. On power up, the watchdog time-out
value in register 0x7FF7 is loaded into the counter
load register. Counting begins on power up and
restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to 1. The counter is
compared to the terminal value of 0. If the counter
reaches this value, it causes an internal flag and an
optional interrupt output. The user can prevent the
time-out interrupt by setting WDS bit to 1 prior to the
counter reaching 0. This causes the counter to be
reloaded with the watchdog time-out value and to be
restarted. As long as the user sets the WDS bit prior
to the counter reaching the terminal value, the interrupt and flag never occurs.
New time-out values can be written by setting the
watchdog write bit to 0. When the WDW is 0 (from the
previous operation), new writes to the watchdog timeout value bits D5-D0 allow the time-out value to be
modified. When WDW is a 1, then writes to bits D5-D0
will be ignored. The WDW function allows a user to
April 2005
17
set the WDS bit without concern that the watchdog
timer value will be modified. A logical diagram of the
watchdog timer is shown below. Note that setting the
watchdog time-out value to 0 would be otherwise
meaningless and therefore disables the watchdog
function.
Clock
Divider
Oscillator
32.768KH2
32 Hz
Counter
Zero
Compare
WDF
Load
Register
WDS
WDW
1 Hz
D Q
Q
write to
Watchdog
Register
Watchdog
Register
Figure 7. Watchdog Timer Block Diagram
The output of the watchdog timer is a flag bit WDF
that is set if the watchdog is allowed to time-out. The
flag is set upon a watchdog time-out and cleared
when the Flags/Control register is read by the user.
The user can also enable an optional interrupt source
to drive the INT pin if the watchdog time-out occurs.
POWER MONITOR
The STK17T88 provides a power management
scheme with power-fail interrupt capability. It also
controls the internal switch to backup power for the
clock and protects the memory from low-VCC access.
The power monitor is based on an internal band-gap
reference circuit that compares the VCC voltage to
various thresholds.
As described in the AutoStore™ section previously,
when Vswitch is reached as VCC decays from power
loss, a data store operation is initiated from SRAM to
the nonvolatile elements, securing the last SRAM
data state. Power is also switched from VCC to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source no data may
be read or written and the clock functions are not
available to the user. The clock continues to operate
in the background. Updated clock data is available to
Document Control #ML0024 rev 1.2
STK17T88
the user after tHRECALL delay (See AutoStore™
/POWER-UP RECALL) after VCC has been restored
to the device.
INTERRUPTS
The STK17T88 provides three potential interrupt
sources. They include the watchdog timer, the power
monitor, and the clock/calendar alarm. Each can be
individually enabled and assigned to drive the INT pin.
In addition, each has an associated flag bit that the
host processor can use to determine the cause of the
interrupt.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when an
interrupt occurs. A functional diagram of the interrupt
logic is shown below.
WIE
Power
Monitor
PF
P/L
PFE
Pin
Driver
H/L
VINT
VCC
INT
VSS
AF
Clock
Alarm
Power Fail Interrupt Enable - PFE. When set to 1, the
power fail monitor drives the pin as well as an internal
flag. When set to 0, the power fail monitor affects only
the internal flag.
High/Low - H/L. When set to a 1, the INT pin is active
high and the driver mode is push-pull. The INT pin
can drive high only when VCC>Vswitch. When set to a 0,
the INT pin is active low and the drive mode is opendrain. Active low (open drain) is operational even in
battery backup mode.
AIE
Figure 8. Interrupt Block Diagram
The three interrupts each have a source and an
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
output. Only one source is necessary to drive the pin.
The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to 0
when the register is read. The cycle must be a
complete read cycle ( WE high); otherwise the flags
will not be cleared. The power monitor has two programmable settings that are explained in the power
monitor section.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
April 2005
Watchdog Interrupt Enable - WIE. When set to 1, the
watchdog timer drives the INT pin as well as an
internal flag when a watchdog time-out occurs. When
WIE is set to 0, the watchdog timer affects only the
internal flag.
Alarm Interrupt Enable - AIE. When set to 1, the alarm
match drives the INT pin as well as an internal flag.
When set to 0, the alarm match only affects to internal
flag.
WDF
Watchdog
Timer
According to the programming selections, the pin can
be driven in the backup mode for an alarm interrupt.
In addition, the pin can be an active low (open-drain)
or an active high (push-pull) driver. If programmed for
operation during backup mode, it can only be active
low. Lastly, the pin can provide a one-shot function so
that the active condition is a pulse or a level condition.
In one-shot mode, the pulse width is internally fixed at
approximately 200 ms. This mode is intended to reset
a host microcontroller. In level mode, the pin goes to
its active polarity until the Flags/Control register is
read by the user. This mode is intended to be used as
an interrupt to a host microcontroller. The control bits
are summarized as follows:
18
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, an external host can read the Flags/Control register to determine the cause. Remember that all flags
will be cleared when the register is read. If the INT pin
is programmed for Level mode, then the condition will
clear and the INT pin will return to its inactive state. If
the pin is programmed for Pulse mode, then reading
the flag also will clear the flag and the pin. The pulse
will not complete its specified duration if the
Flags/Control register is read. If the INT pin is used as
a host reset, then the Flags/Control register should
not be read during a reset.
Document Control #ML0024 rev 1.2
STK17T88
During a power-on reset with no battery, the interrupt
register is automatically loaded with the value 24h.
This causes power-fail interrupt to be enabled with an
active-low pulse.
RTC Register Map
Register
D7
0x7FFF
D6
D5
10s Years
0
0
BCD Format Data
D4
D3
D2
D1
Years
10s
Months
D0
Function / Range
Years: 00-99
0x7FFE
0
0x7FFD
0
0x7FFC
0x7FFB
0x7FFA
0x7FF9
0
0
0
0x7FF8
OSCEN
0x7FF7
WDS
WDW
0x7FF6
WIE
AIE
0x7FF5
M
0
0x7FF4
M
0
0x7FF3
M
10 Alarm Minutes
Alarm Minutes
Alarm, minutes: 00-59
0x7FF2
M
10 Alarm Seconds
Alarm Seconds
Alarm, seconds: 00-59
10s Day of
Month
0
0
0
0
10s Hours
10s Minutes
10s Seconds
Cal
0
Sign
0
Months: 01-12
Day of Month
0
Day of Month: 01-31
Day of Week
Hours
Minutes
Seconds
Day of week: 01-07
Hours: 00-23
Minutes: 00-59
Seconds: 00-59
Calibration
Calibration values*
WDT
PFE
ABE
H/L
10s Alarm
Date
10s Alarm
Hours
0x7FF1
10s Centuries
0x7FF0
WDF
AF
PF
OSCF
* - Is a binary value, not a BCD value.
0 - Not implemented, reserved for future use.
April 2005
Months
0
19
Watchdog*
P/L
0
0
Interrupts*
Alarm Day
Alarm, Day of Month:
01-31
Alarm Hours
Alarm, hours: 00-23
Centuries
CAL
W
R
Centuries: 00-99
Flags*
Document Control #ML0024 rev 1.2
STK17T88
Register Map Detail
0x7FFF
0x7FFE
0x7FFD
0x7FFC
0x7FFB
0x7FFA
0x7FF9
April 2005
Timekeeping – Years
D6
D5
D4
D3
D2
D1
D0
10s Years
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper
nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the
register is 0-99.
D7
Timekeeping – Months
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
10s Month
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the
register is 1-12.
Timekeeping – Date
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for
the register is 1-31. Leap years are automatically adjusted for.
Timekeeping – Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter
that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the
day is not integrated with the date.
Timekeeping – Hours
D7
D6
D5
D4
D3
D2
D1
D0
12/24
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The
range for the register is 0-23.
Timekeeping – Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register
is 0-59.
Timekeeping – Seconds
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 059.
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STK17T88
0x7FF8
OSCEN
Calibration
Sign
Calibration
0x7FF7
WDS
WDW
WDT
0x7FF6
WIE
AIE
PFIE
ABE
H/L
P/L
April 2005
D7
D6
D5
Calibration / Control
D4
D3
D2
D1
D0
Calibration
OSCEN
0
Calibration
Sign
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs.
Disabling the oscillator saves battery/capacitor power during storage. On a no-battery power-up,
this bit is set to 0.
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base.
These five bits control the calibration of the clock.
D7
D6
WDS
WDW
D5
Watchdog Timer
D4
D3
D2
D1
D0
WDT
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0
has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is
write only. Reading it always will return a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog time-out value (WDT5-WDT0) so
it cannot be written. This allows the user to strobe the watchdog without disturbing the time-out
value. Setting this bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register.
The new value will be loaded on the next internal watchdog clock after the write cycle is complete.
This function is explained in more detail in the watchdog timer section.
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or time-out
value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3Fh). Setting
the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit
was cleared to 0 on a previous cycle.
D7
D6
D5
WIE
AIE
PFIE
Interrupt Status / Control
D4
D3
D2
ABE
H/L
P/L
D1
D0
0
0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer
drives the INT pin as well as the WDF flag. When set to 0, the watchdog time-out affects only the
WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag.
When set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the power-fail monitor affects only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when Vcc>Vswitch.
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L ) by an interrupt
source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set
by H/L ) until the Flags/Control register is read.
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STK17T88
0x7FF5
M
0x7FF4
M
0x7FF3
D7
D6
M
0
0x7FF2
D7
D6
M
0
0x7FF1
April 2005
D2
10s Alarm Date
D1
D0
Alarm Date
D5
D4
Alarm – Hours
D3
D2
10s Alarm Hours
D1
D0
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the hours value.
D7
D6
D5
Alarm – Minutes
D4
D3
D2
10s Alarm Minutes
D1
D0
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit
to 1 causes the match circuit to ignore the minutes value.
D7
D6
M
M
Alarm – Day
D3
D4
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
M
M
D5
D5
Alarm – Seconds
D4
D3
D2
10s Alarm Seconds
D1
D0
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’
value.
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this
bit to 1 causes the match circuit to ignore the seconds value.
D7
0
D6
0
Timekeeping – Centuries
D5
D4
D3
D2
10s Centuries
22
D1
Centuries
D0
Document Control #ML0024 rev 1.2
STK17T88
0x7FF0
WDF
AF
PF
OSCF
CAL
W
R
April 2005
Flags
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0
without being reset by the user. It is cleared to 0 when the Flags/Control register is read.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the Flags/Control register is read.
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold
Vswitch. It is cleared to 0 when the Flags/Control register is read.
Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is not running in the first 5ms of
power-on operation. This indicates that time counts are no longer valid. The user must reset this
bit to 0 to clear this condition. The chip will not clear this flag. This bit survives power cycles.
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0,
the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then
write them with updated values. Setting the W bit to 0 causes the contents of the time registers to
be transferred to the timekeeping counters.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places
them in a holding register. The user can then read them without concerns over changing values
causing system errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must
be returned to 0 prior to reading again.
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ORDERING INFORMATION
STK17T88 – R F 45 I
Temperature Range
Blank = Commercial (0 to 70º C)
I = Industrial (-40 to 85ºC)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85% Sn / 15% Pb
F = 100% Sn (Matte Tin) ROHS Compliant
Package
R = Plastic 48-pin 300 mil SSOP (25 mil pitch)
W = Plastic 40-pin 600 mil DIP (100 mil pitch)
April 2005
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STK17T88
Document Revision History
Revision
0.0
Date
February 2003
0.1
March 2003
Summary
Publish new datasheet
Remove 525 mil SOIC, Add 48 Pin SSOP and 40 Pin DIP packages; Modified Block
Diagram in AutoStore description section
Parameter
1.0
Vcap Min
tVCCRISE
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Ind.
ICC1 Max Ind.
ICC1 Max Ind.
ICC2 Max
ICC4 Max
tHRECALL
tSTORE
tRECALL
tGLQV
December 2004
1.1
January 2005
1.2
April 2005
Old Value
New Value
10µF
NA
35 mA
40 mA
50 mA
35 mA
45 mA
55 mA
1.5 mA
0.5 mA
5 ms
10 ms
20 µs
10 ns
17 µF
150 µs
50 mA
55 mA
65 mA
55 mA
60 mA
70 mA
3.0 mA
3 mA
20 ms
12.5 ms
40 µs
12 ns
Notes
New Spec
@ 45ns access
@ 35ns access
@ 25ns access
@ 45ns access
@ 35ns access
@ 25ns access
Com. & Ind.
Com & Ind.
@ 25ns access
Changed “N” package reference to “R” package.
Changed RTC register unused bits “X” to require zero “0” value when writing values.
SIMTEK STK17T88 Data Sheet, April 2005
Copyright 2005, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form
or means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate,
but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein
constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right.
April 2005
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Document Control #ML0024 rev 1.2