TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 PMU for Bluetooth Headsets Check for Samples: TPS65720 TPS65721 FEATURES 1 • • 2 • • • • • • • • • • • • • • Battery Charger With Power Path Management 28 V Rated Power Path With: – 100 mA Input Current Limit – 500 mA input Current Limit 300 mA Charge Current 200 mA Step-Down Converter for TPS65720 400 mA Step-Down Converter for TPS65721 Up to 92% Efficiency VIN Range for DCDC Converter From 2.3V to 5.6V 2.25 MHz Fixed Frequency Operation Power Save Mode at Light Load Current Output Voltage Accuracy in PWM Mode ±2% 100% Duty Cycle for Lowest Dropout 1 General Purpose 200mA LDO VIN Range for LDO From 1.8V to 5.6V I2C Compatible Interface 4GPIOs Available in a 25 Ball WCSP With 0,4mm Pitch and in 4mm × 4mm 32-Pin QFN Package APPLICATIONS • • Bluetooth Headsets Handheld Equipment DESCRIPTION The TPS65720 is a small power management unit targeted for Bluetooth headsets or other portable low power consumer end equipments. It contains an USB friendly Lithium-Ion battery charger, a high efficient step down converter, a low dropout linear regulator and additional supporting functions. The device is controlled by an I2C interface. Several settings can be customized by the use of non volatile memory which is factory programmed. The 2.25MHz step-down converter enters a low power mode at light load for maximum efficiency across the widest possible range of load currents. For low noise applications the devices can be forced into fixed frequency PWM mode using the I2C compatible interface. The device allows the use of small inductors and capacitors to achieve a small solution size. TPS65720 provides an output current of up to 200mA on the DCDC converter. The TPS65720 also integrates one 200mA LDO. The LDO operates with an input voltage range between 1.8V and 5.6V allowing it to be supplied from the output of the step-down converter or directly from the system voltage. The TPS65720 comes in a small 25-ball wafer chip scale package (WCSP) with 0,4mm ball pitch or a 4mm × 4mm QFN package with a 0,4mm pitch (TPS65721). TPS65720 BAT AC BAT 1uF charger / power path 10k LiIon NTC SYS ISET 3k for a charge current of 150mA TS SYS 4.7uF / 6.3V R5 L1 DCDC 1 200 mA 2.2uH VDCDC 1=2.05 V R1 360 k 4.7uF 22pF FB_DCDC1 R2 150k bluetooth chip VINLDO1 2.2uF LDO1 200 mA VLDO 1 = 1.85V VLDO1 4.7uF / 4V 2 x 3.3k Vin 2 x 100k reset generator / startup logic SYS RESET Reset INT INT HOLD_LDO1 R6 GPIO HOLD_DCDC1 PB_IN ON / OFF SCLK PGND I2C interface SCLK SDAT SDAT GPIO0 AGND GPIO or 5mA current sink GPIO1 GPIO2 GPIO3 to SYS or VDCDC1 depending on LED forward voltage indication LEDs 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PART NUMBER -40°C TO 85°C TPS65720 -40°C TO 85°C TPS65721 (1) (1) SIZE FOR WCSP VERSION PACKAGE CODE PACKAGE PACKAGE MARKING D = 2105 μm ±25 μm E = 2105 μm ±25 μm YFF WCSP TPS65720 RSN QFN (1) 65720 The RSN and YFF package is available in tape and reel. Add R suffix (TPS65720YFFR; TPS65721RSNR) to order quantities of 3000 parts per reel. Add T suffix (TPS65720YFFT; TPS65721RSNT) to order quantities of 250 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE / UNIT Input voltage range on all pins except A/PGND, AC, GPIOx pins with respect to AGND –0.3 to 7 V Input voltage range on GPIOx pins with respect to AGND –0.3 to VSYS Input voltage range on AC pin with respect to AGND –0.3 to 28 V Voltage range on pin VLDO1, FB_LDO1, TS_OUT, TS with respect to AGND –0.3 to 3.6 V Current at AC, BAT, SYS, L1, VLDO1, VINLDO1, PGND 600 mA Current at GPIOx, AGND 20 mA Current at all other pins 3 mA Continuous total power dissipation See dissipation rating table Operating free-air temperature, TA –40°C to 85°C Maximum junction temperature, TJ 125°C Storage temperature, TST –65°C to 150°C DISSIPATION RATINGS (1) PACKAGE RθJA TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C YFF 55 K/W 1.8 W RSN 38 K/W 2.6 W (1) TA = 70°C POWER RATING TA = 85°C POWER RATING 18 mW/K 1W 0.7 W 26 mW/K 1.4 W 1W The thermal resistance was measured on a high K board. RECOMMENDED OPERATING CONDITIONS MIN VAC Input voltage range at AC pin VSYS Voltage range at SYS pin IINUSB NOM MAX UNIT 4.35 28 2.2 5.6 V Input current at AC 500 mA IOUTSYS Output current at SYS 400 mA IBAT Average current into / out of BAT pin 300 mA VINDCDC1 Input voltage range for step-down converter DCDC1 2.3 5.6 V VDCDC1 Output voltage range for DCDC1 step-down converter; externally adjustable 0.6 VINDCDC1 V IOUTDCDC1 Output current at L L Inductor at L (1) 2.2 VINLDO1 Input voltage range for LDO1 1.8 VLDO1 Output voltage range for LDO1 0.8 ILDO1 Output current at LDO1 (1) 2 3.3 V 400 mA 4.7 μH VSYS V 3.3 V 200 mA See application section for more details Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT CINAC Input capacitor at AC (1) 0.1 1 μF CBAT Capacitor at BAT (1) 0.1 4.7 μF CSYS Capacitor at SYS (1) 4.7 10 μF (1) 4.7 μF CINDCDC1 Input capacitor at VINDCDC1 SYS and CINDCDC1 COUTDCDC1 Output capacitor at VDCDC1 (1) 4.7 CINLDO1 Input capacitor at VINLDO1 (1) 2.2 μF COUTLDO1 Output capacitor at LDO1 (1) 2.2 μF RISET Minimum RISET value for proper operation; lower values may trigger the short circuit protection on ISET 700 Ω TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C ; if connected to SYS, only one 4.7μF cap required for 10 μF 22 ELECTRICAL CHARACTERISTICS VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DCDC1 enabled, IOUT = 0mA. PFM mode enabled; device not switching 36 45 DCDC1 enabled, IOUT = 0mA. PWM mode 2.8 Operating quiescent current when LDO1 and DCDC1 are enabled Current into BAT pin (PFM mode) 33 50 μA Current into VINLDO1 13 18 μA Shutdown current after voltage was applied to BAT but device never enabled before (shipping mode) For VINLDO1=0V (LDO1 supplied by DCDC1); powered by VBAT=3.6V 4 13 μA Shutdown current after first power-up For VINLDO1=0V (LDO1 supplied by DCDC1); powered by VBAT=3.6V 12 17 μA Shutdown current after first power-up For VINLDO1≠0V (LDO1 supplied by SYS); powered by VBAT=3.6V 12 18 μA SUPPLY CURRENT IQ IQ ISD Operating quiescent current when only DCDC1 converter is enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 μA mA 3 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD VIH High level input voltage for SCLK, SDAT, GPIOx, HOLD_DCDC1, HOLD_LDO1, PB_IN GPIOs configured as input 1.2 VSYS V VIL Low level input voltage for SCLK, SDAT, GPIOx, HOLD_DCDC1, HOLD_LDO1, PB_IN GPIOs configured as input 0 0.4 V VOL Low level output voltage for SDAT, GPIOx, INT, RESET GPIOs configured as output; Io=1mA; no internal pull-up 0 0.4 V Sink current for GPIO2, GPIO3 GPIO2, GPIO3 configured as current sink; VOL=0.4V ; for Tj=0°C to 85°C Sink current for GPIOx GPIOx configured as open drain output ; output = LOW Minimum voltage for proper current regulation from GPIO2 or GPIO3 to GND if programmed as a current sink Io=5mA; current sink turned on IOL VOL VRESET-falling –20% 5 20% mA 3 mA 0.4 V VLDO1, nom-13% Falling edge; Reset is asserted LOW for TPS65720 VLDO1, nom-7% V LDO1 out of regulation reset voltage Rising edge; Reset is released HIGH for TPS65720 after TRESET VRESET-rising Low to high transition of RESET pin, depending on setting of Bit RESET_DELAY TRESET Reset delay time on pin RESET VLDO1, nom-4% 9 70 HIGH to LOW transition of RESET pin RESET will go low by HOLD pin going LOW AND HOLD Bit set to 0 OR voltage at Vreset falling below the threshold VTHRESHOLD_down Threshold voltage for reset input Falling voltage; QFN package only VTHRESHOLD_hys Hysteresis on THRESHOLD Rising voltage; QFN package only Tdebounce Debounce time at PB_IN Rising and falling voltage ILKG Input leakage current PB_IN, SDAT, SCLK, GPIOx configured as output, INT, RESET, output high impedance 11 90 V 13 110 μs 10 –3% 570 3% 30 39 50 ms mV mV 60 ms 0.2 μA 5.6 V STEP-DOWN CONVERTER VSYS Input voltage for DCDC1 UVLO 2.3 Internal undervoltage lockout threshold hysteresis VSYS falling 2.15 2.2 2.25 V VSYS rising 120 mV VSYS = VINDCDC1 = 3.6V, YFF package 350 600 VSYS = VINDCDC1 = 3.6V, RSN package 400 650 1 μA VINDCDC1/2 = 3.6 V, YFF package 300 500 mΩ VINDCDC1/2 = 3.6 V, RSN package 350 550 mΩ POWER SWITCH RDS(ON) High side MOSFET on-resistance ILK_HS High side MOSFET leakage current mΩ VDS = 5.6V RDS(ON) Low side MOSFET on-resistance ILK_LS Low side MOSFET leakage current VDS = 5.6 V 2.3 V ≤ VIN ≤ 5.6 V, TPS65720 425 ILIMF Forward current limit high-side and low side MOSFET 2.3 V ≤ VIN ≤ 5.6 V, TPS65721 625 Io DC output current 1 μA 600 775 mA 850 1150 mA VSYS > 2.7 V; TPS65720 200 VSYS > 2.7 V ; TPS65721 400 mA OSCILLATOR fSW Oscillator Frequency 2.03 2.25 2.48 MHz Vin V 0.1 μA OUTPUT VOUT Output Voltage Range VFB Feedback voltage IFB FB pin input current DC Output voltage accuracy (1) VOUT 0.6 0.6 VIN = 2.3 V to 5.6 V; PFM operation, 0 mA < IOUT < IOUTMAX VIN = 2.3 V to 5.6 V, PWM operation, 0 mA < IOUT < IOUTMAX DC output voltage load regulation PWM operation VPGOOD-falling PGOOD threshold at falling output voltage <PGOODZ_DCDC1> is set to 1 VPGOOD-rising PGOOD threshold at rising output voltage <PGOODZ_DCDC1> is set to 0 tStart Start-up time tRamp VOUT ramp time (1) 4 1% –2% V 3% 2% 0.5 VDCDC1, nom-14% %/A VDCDC1, nom-7% V VDCDC1, nom-5% V Time from active EN to Start switching 170 μs Time to ramp from 5% to 95% of VOUT 250 μs Output voltage specification does not include tolerance of external voltage programming resistors Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER RDIS Internal discharge resistor at L TEST CONDITIONS MIN TYP DCDC1 disabled; the discharge function can be disabled as an EEPROM option MAX UNIT 300 400 Ω THERMAL PROTECTION FOR DCDC1 AND LDO1 TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 30 °C VLDO1 LOW DROPOUT REGULATOR VINLDO Input voltage range for LDO1 1.8 5.6 V VLDO1 LDO1 output voltage range 0.8 3.3 V VLDO1 LDO1 output voltage Default output voltage for TPS65720 only VFB_LDO1 Feedback voltage Externally adjustable version only: TPS65721 IFB_LDO1 FB pin input current IO Output current for LDO1 ISC LDO1 short circuit current limit VLDO1 = GND; VinLDO1=2.05V Dropout voltage at LDO1, YFF package IO = 200 mA, VINLDO = 2.05 V Dropout voltage at LDO1, RSN package IO = 200 mA, VINLDO = 2.05 V Output voltage accuracy for LDO1 IO = 200 mA Line regulation for LDO1 Load regulation for LDO1 PGOOD debounce time Internal PGOOD comparator at VOUTLDO1 is debounced by tRamp VOUT Ramp time Internal soft-start when LDO is enabled; Time to ramp from 5% to 95% of VOUT RDIS Internal discharge resistor at VLDO1 LDO disabled, discharge function per default disabled in register 250 Battery voltage comparator threshold voltage Depending on Bits <VBAT0>, <VBAT1>; falling voltage –3% Battery voltage comparator threshold voltage hysteresis Rising voltage VUVLO Undervoltage lockout VAC: 0V → 4V 3.2 VHYS-UVLO Hysteresis on UVLO VAC: 4V → 0V 200 VIN-DT Input power detection threshold (Input power detected if VIN > VBAT + VIN-DT) VBAT = 3.6V, VIN: 3.5V → 4V 40 VHYS-INDT Hysteresis on VIN-DT VBAT = 3.6 V, VIN: 4V → 3.5V 20 tDGL(PGOOD) Deglitch time, input power detected status Time measured from VIN: 0V → 5V 1μs rise-time to PGOOD = LO VOVP Input over-voltage protection threshold VAC: 5 V → 7 V VHYS-OVP Hysteresis on OVP VAC: 11V → 5V tBLK(OVP) Input over-voltage blanking time 1.85 V 0.8 350 V 0.1 μA 200 mA 500 mA 180 mV 120 mV –1.5% 2.5% VINLDO1 = VLDO1 + 0.5V (min. 1.8V) to 5.6 V (VSYS), IO = 50 mA –1% 1% IO = 0 mA to 200 mA for LDO1 –1% 2% 80 μs 250 μs 400 Ω BATTERY VOLTAGE COMPARATOR 3% 200 V mV POWER PATH 3.3 80 3.45 V 300 mV 140 mV mV 2 6.4 Time measured from VAC: 11V → 5V 1μs fall-time to <CH_PGOOD>=0 6.6 ms 6.8 V 105 mV 50 μs 2 ms tREC(OVP) Input over-voltage recovery time AC pin to SYS pin dropout voltage VAC – VSYS ISYS = 0.3A, VAC = 4.35V, VBAT =4.2V; YFF package 170 285 mV VDO(AC-SYS) ISYS = 0.3A, VAC = 4.35V, VBAT =4.2V; RSN package 210 325 mV Battery to SYS pin dropout voltage VBAT – VSYS ISYS = 0.2A, VAC = 0V, VBAT > 3V; YFF package 80 mV ISYS = 0.2A, VAC = 0V, VBAT > 3V; RSN package 120 mV VDO(BAT-SYS) VSYS(REG) SYS pin voltage regulation selectable register <CHGCONFIG0> Bits <VSYS1>; <VSYS0> 00: VAC > VSYS + VDO(AC-SYS), VBAT < 3.3V –5% 3.4 5% 00: VAC > VSYS + VDO(AC-SYS), VBAT >/= 3.3V –5% VBAT + 200mV 5% 01: VAC > VSYS + VDO(AC-SYS) –5% 4.4 5% 10: VAC > VSYS + VDO(AC-SYS) –5% 5.0 5% 11: VAC > VSYS + VDO(AC-SYS) –5% 5.5 5% 90 95 100 mA Bit < AC input current1, AC input current0> = 01 or 10 450 475 500 mA 4.35 4.5 4.65 V Bit <AC input current1, AC input current0> = 00 V IAC-MAX Maximum Input Current Register <CHCONFIG0> VAC-LOW Input voltage threshold when input current is reduced Input current is reduced if voltage at AC falls below VAC-LOW to keep the AC voltage above 4.5V Output voltage threshold when charging current is reduced Bit <V_DPPM> = 1 VO(REG) –100mV V VDPM Register <CHCONFIG2> Bit <V_DPPM> = 0 4.3 V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 5 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VBSUP1 Enter battery supplement mode VOUT ≤ VBAT –40mV VBSUP2 Exit battery supplement mode VOUT ≥ VBAT –20mV VO(SC1) Output short-circuit detection threshold, power-on 0.8 0.9 1 VO(SC2) Output short-circuit detection threshold, supplement mode VBAT – VOUT > VO(SC2) indicates short-circuit 200 250 300 tDGL(SC2) Deglitch time, supplement mode short circuit tREC(SC2) Recovery time, supplement mode short circuit UNIT V V V mV 250 μs 60 ms BATTERY CHARGER QUIESCENT CURRENT VIN = 5V; ACinputcurrent[1,0]=11 IIACSTDBY) Standby current into AC pin ICC Active supply current, AC pin IBAT(SC) Source current for BAT pin short-circuit detection VBAT(SC) BAT pin short-circuit detection threshold Vo(BATREG) 60 VIN = 28V; ACinputcurrent[1,0]=11 VIN = 5V, no load on DCDC1, LDO1, SYS pin, VSYS[1,0]=11; ACinputcurrent[1,0]=10; CH_EN=0 Depending on setting in CHGCONFIG3 And internal EEPROM Default = 4.2V Battery charger voltage 80 μA 530 μA 2 mA 4 7.5 11 mA 1.6 1.8 2.0 V –1% 4.15 1% –1% 4.175 1% –1% 4.20 1% –1% 4.225 1% –1% 4.25 1% –1% 4.275 1% –1% 4.30 1% –1% 4.325 1% 2.9 3.0 3.1 V VLOWV Pre-charge to fast-charge transition threshold tDGL1(LOWV) Deglitch time on pre-charge to fast-charge transition 25 ms tDGL2(LOWV) Deglitch time on fast-charge to pre-charge transition 25 ms Maximum battery fast charge current ICHG Minimum battery fast charge current Battery fast charge current set factor KISET IPRECHG 6 300 mA VBAT(REG) > VBAT > VLOWV, VIN = VAC or VUSB = 5V 10 VBAT > VLOWV, VIN = 5V, IIN-MAX > ICHG, No load on SYS pin, thermal loop not active, DPPM loop not active V KISET/ RISET mA A at 300mA for ICH_SCL[1,0]=11 (charge current scaling is 100% of ISET value) –15% 450 15% at 40mA for ICH_SCL[1,0]=11 (charge current scaling is 100% of ISET value) –20% 450 20% at 225mA range for ICH_SCL[1,0]=10 (charge current scaling is 75% of ISET value) –15% 338 15% at 30mA for ICH_SCL[1,0]=10 (charge current scaling is 75% of ISET value) –20% 338 20% at 150mA for ICH_SCL[1,0]=01 (charge current scaling is 50% of ISET value) –10% 225 10% at 20mA for ICH_SCL[1,0]=01 (charge current scaling is 50% of ISET value) –15% 225 15% at 75mA for ICH_SCL[1,0]=00 (charge current scaling is 25% of ISET value) –10% 112 10% at 10mA for ICH_SCL[1,0]=00 (charge current scaling is 25% of ISET value) Fast charge current factor AΩ –20% 112 20% for I_PRE[1,0]=11 (pre-charge current scaling is 20% of charge current) 0.15×ICHG 0.2×ICHG 0.25×ICHG for I_PRE[1,0]=10 (pre-charge current scaling is 15% of charge current) 0.11×ICHG 0.15×ICHG 0.19×ICHG for I_PRE[1,0]=01 (pre-charge current scaling is 10% of charge current) 0.07×ICHG 0.1×ICHG 0.13×ICHG for I_PRE[1,0]=00 (pre-charge current scaling is 5% of charge current) 0.03×ICHG 0.05×ICHG 0.08×ICHG Pre-charge current Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER ITERM TEST CONDITIONS Charge current value for termination detection threshold (internally set) MIN TYP MAX for I_TERM[1,0]=11 (termination current is 20% of charge current) 0.15×ICHG 0.2×ICHG 0.27×ICHG for I_TERM[1,0]=10 (termination current is 15% of charge current) 0.11×ICHG 0.15×ICHG 0.21×ICHG for I_TERM[1,0]=01 (termination current is 10% of charge current) 0.07×ICHG 0.1×ICHG 0.15×ICHG for I_TERM[1,0]=00 (termination current is 5% of charge current) 0.03×ICHG 0.05×ICHG 0.08×ICHG 165 100 25 UNIT tDGL(TERM) Deglitch time, termination detected VRCH Recharge detection threshold tDGL(RCH) Deglitch time, recharge threshold detected tDGL(NO-IN) Delay time, input power loss to charger turn-off IBAT(DET) Sink current for battery detection tDET Battery detection timer TCHG Charge safety timer Safety timer range selectable by I2C; default setting without DPPM or thermal loop active –35% 5 35% h TPRECHG Precharge timer Pre charge timer range; default setting –35% 30 35% min Voltage below nominal charger voltage VBAT = 3.6V. Time measured from VIN: 5V → 3.3V 1μs fall-time 5 ms 60 62.5 ms 20 ms 7.5 10 250 Product Folder Link(s): TPS65720 TPS65721 mA ms Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated mV 7 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Thermistor high temperature detection resistance (equals 45°C for 10k NTC; B=3380) 4.3 5 5.7 kΩ Thermistor high temperature detection resistance (equals 50°C for 10k NTC; B=3380) 3.5 4.1 4.8 kΩ Thermistor high temperature detection resistance (equals 55°C for 10k NTC; B=3380 ) 2.9 3.5 4.2 kΩ 2.4 3 3.5 kΩ BATTERY-PACK NTC MONITOR Thermistor high temperature detection resistance (equals 60°C for 10k NTC; B=3380) RNTCHOT Thermistor high temperature detection resistance (equals 45°C for 100k NTC) 43 50 57 kΩ Thermistor high temperature detection resistance (equals 50°C for 100k NTC) 35 41 48 kΩ Thermistor high temperature detection resistance (equals 55°C for 100k NTC) 29 35 42 kΩ Thermistor high temperature detection resistance (equals 60°C for 100k NTC) 24 30 35 kΩ Thermistor low temperature detection resistance (equals 0°C for 10k NTC; B=3380) 25 27 30 kΩ Thermistor low temperature detection resistance (equals 5°C for 10k NTC; B=3380) 20 22 24 kΩ Thermistor low temperature detection resistance (equals 10°C for 10k NTC; B=3380 ) 16 18 20 kΩ 13 15 16 kΩ 250 270 300 kΩ Thermistor low temperature detection resistance (equals 5°C for 100k NTC) 200 220 240 kΩ Thermistor low temperature detection resistance (equals 10°C for 100k NTC) 160 180 200 kΩ 130 150 160 kΩ kΩ Thermistor low temperature detection resistance (equals 15°C for 10k NTC; B=3380) RNTCCOLD Hot temperature detected and charging suspended when the resistance of the battery-NTC is lower than RNTCHOT Thermistor low temperature detection resistance (equals 0°C for 100k NTC) Cold temperature detected and charging suspended when the resistance of the battery-NTC is higher than RNTCCOLD Thermistor low temperature detection resistance (equals 15°C for 100k NTC) VHYS(COLD) Low temperature trip point hysteresis For 10k NTC; B=3380 Thermistor not detected for 10k NTC RNOSENSOR tDGL(TS) 5 Hot temperature detected and charging suspended when the resistance of the battery-NTC is higher than RNOSENSOR Thermistor not detected for 100k NTC Deglitch time, pack temperature fault detection °C 260 340 620 2500 3400 6200 kΩ 50 ms THERMAL REGULATION TJ(REG) Lower Temperature regulation limit 115 °C TJ(REG) Upper Temperature regulation limit 135 °C TJ(OFF) Thermal shutdown temperature 155 °C TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 DEVICE INFORMATION Chip scale version (YFF package): PIN ASSIGNMENT (bottom view) AC ISET RESET SDAT SCLK A5 SYS SYS PB_IN GPIO0 GPIO1 A4 BAT BAT GPIO2 INT GPIO3 A3 HOLD_ DCDC1 L1 TS HOLD_ LDO1 GND A2 FB_ DCDC1 PGND E1 AGND D1 VINLDO1 C1 VLDO1 B1 A1 FUNCTIONAL BLOCK DIAGRAM TPS65720 BAT AC BAT 1uF charger / power path NTC SYS ISET set charge current LiIon TS SYS 4.7uF R5 L1 HOLD_DCDC1 DCDC1 200mA 2.2uH 22pF Vout 1 R1 4.7uF FB_DCDC1 R2 VINLDO1 2.2uF HOLD_LDO1 VLDO1 LDO 1 200mA Vout 2 2.2uF SYS R6 PB_IN ON / OFF reset generator / startup logic RESET INT SCLK PGND I2C interface SDAT GPIO0 AGND GPIO or 5mA current sink GPIO1 GPIO2 GPIO3 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 9 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com PIN FUNCTIONS for CHIP SCALE VERSION (YFF package) PIN NAME NO. I/O DESCRIPTION AC E5 I Input power for power manager, connect to external DC supply. SYS E4, D4 O System voltage; output of the power path manager. Power input for step-down converter DCDC1 BAT E3, D3 I/O Connect to battery + terminal ISET D5 I Connect a resistor from this pin to GND to set fast charge current TS C2 I Connect a thermistor from this pin to GND for battery temperature AGND C1 Analog ground PGND E1 Power ground GND B2 L1 E2 O Switch output of step-down converter FB_DCDC1 D1 I Feedback input of step-down converter HOLD_DCDC1 D2 I Power-On input for DCDC1 converter. When pulled HIGH, the DCDC converter is kept enabled after PB_IN was released HIGH. VINLDO1 B1 I Input voltage for LDO1 VLDO1 A1 O Output voltage of LDO1 HOLD_LDO1 A2 I Power-On input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released HIGH. SDAT B5 I/O SCLK A5 I Clock input for the I2C interface PB_IN C4 I Push button input; Turns on DCDC1 and LDO1 if pulled to GND. INT C3 O Open drain interrupt output RESET C5 O Open drain output of the reset generator; This output goes active LOW when the output voltage of LDO1 falls 8% below its target voltage. GPIO0 B4 I/O General purpose I/O GPIO1 A4 I/O General purpose I/O GPIO2 B3 I/O General purpose I/O or 5mA current sink GPIO3 A3 I/O General purpose I/O or 5mA current sink Connect to AGND and PGND Data line for the I2C interface AC AC SYS SY S BAT BAT L1 P GN D QFN version (RSN package): PIN ASSIGNMENT (top view) 24 23 22 21 20 19 18 17 HOLD_DCDC1 FB_DCDC1 TS AGND GND VINLDO1 VLDO1 NC 25 26 27 28 29 30 31 32 TPS65721 16 15 14 13 12 11 10 9 ISET PB_IN RESET INT SDAT MODE NC NC FB_LDO1 10 HOLD_LDO1 THRESHOLD GPIO3 GPIO2 GPIO1 GPIO0 SCLK 1 2 3 4 5 6 7 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 FUNCTIONAL BLOCK DIAGRAM TPS65721 AC BAT AC BAT 1uF NTC SYS ISET set charge current LiIon TS charger / power path SYS 4.7uF R5 L1 MODE DCDC 1 200mA HOLD_DCDC1 2.2uH 4.7uF Vout1 R1 FB_DCDC1 22pF R2 VINLDO1 VLDO1 LDO1 200 mA HOLD_LDO1 Vout2 R3 2.2uF FB_LDO1 R4 SYS R6 THRESHOLD PB_IN ON / OFF reset generator / startup logic RESET INT SCLK PGND I2C interface SDAT GPIO0 AGND GPIO or 5mA current sink GPIO1 GPIO2 GPIO3 PIN FUNCTIONS for QFN VERSION (RSN package) PIN NAME NO. I/O DESCRIPTION AC 17, 18 I Input power for power manager, connect to external DC supply. SYS BAT 19, 20 O System voltage; output of the power path manager. Power input for step-down converter DCDC1 21, 22 I/O ISET 16 I Connect to battery + terminal Connect a resistor from this pin to GND to set fast charge current TS 27 I Connect a thermistor from this pin to GND for battery temperature AGND 28 PGND 24 L1 23 O Switch output of step-down converter FB_DCDC1 26 I Feedback input of step-down converter HOLD_DCDC1 25 I Power-On input for DCDC1 converter. When pulled HIGH, the DCDC converter is kept enabled after PB_IN was released HIGH. VINLDO1 30 I Input voltage for LDO1 VLDO1 31 O Output voltage from LDO1 FB_LDO1 1 I Feedback input for LDO1 HOLD_LDO1 2 I Power-On input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released HIGH. SDAT 12 I/O SCLK 8 I Clock input for the I2C interface PB_IN 15 I Push button input; Turns on DCDC1 and LDO1 if pulled to GND. INT 13 O Open drain interrupt output Analog ground Power ground Data line for the I2C interface Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 11 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com PIN FUNCTIONS for QFN VERSION (RSN package) (continued) PIN NAME NO. I/O DESCRIPTION RESET 14 O Open drain output of the reset generator; This output goes active LOW when the input voltage at pin THRESHOLD falls below the threshold voltage. THRESHOLD 3 I Input voltage to the reset comparator. When the input voltage falls below the threshold, the RESET output is actively pulled LOW. GPIO0 7 I/O General purpose I/O GPIO1 6 I/O General purpose I/O GPIO2 5 I/O General purpose I/O or 5mA current source GPIO3 4 I/O General purpose I/O or 5mA current source MODE 11 I Pull HIGH to force the DCDC1 converter to PWM mode. GND 29 – Connect to AGND and PGND PowerPad – Connect to GND PARAMETER MEASUREMENT INFORMATION Setup The graphs have been generated on the TPS65720YFF EVM with the inductors as mentioned in the graphs. See the TPS65720 EVM users guide (SLVU324) for details on the layout. TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE 12 TPS65720: Efficiency DCDC1 vs Load current / PWM mode 200mA; L= Murata LQM21P 3.3 μH Vo = 2.05V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 1 TPS65720: Efficiency DCDC1 vs Load current / PFM mode 200mA; L= Murata LQM21P 3.3 μH Vo = 2.05V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 2 TPS65720: Efficiency DCDC1 vs Load current / PWM mode 200mA; L= FDK MIPSA2520 2.2 μH Vo = 2.05V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 3 TPS65720: Efficiency DCDC1 vs Load current / PFM mode 200mA; L= FDK MIPSA2520 2.2 μH Vo = 2.05V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 4 TPS65721: Efficiency DCDC1 vs Load current / PWM mode; L= FDK MIPSA2520 2.2 μH Vo = 3.3V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 5 TPS65721: Efficiency DCDC1 vs Load current / PFM mode 500mA; L= FDK MIPSA2520 2.2 μH Vo = 3.3V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 6 TPS65721: Efficiency DCDC1 vs Load current / PWM mode; L= FDK MIPSA2520 2.2 μH Vo = 1.8V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 7 TPS65721: Efficiency DCDC1 vs Load current / PFM mode 500mA; L= FDK MIPSA2520 2.2 μH Vo = 1.8V; Vi = 3.0V, 3.6V, 4.2V, 5.0V Figure 8 Load transient response DCDC1; L= FDK MIPSA2520 2.2 μH, PFM mode Scope plot Io = 20mA to 180mA; Vo = 2.05V; Vi = 3.6V Figure 9 Load transient response DCDC1; L =FDK MIPSA2520 2.2 μH, PWM mode Scope plot Io = 50 μA to 60mA; Vo = 2.05V; Vi = 3.6V Figure 10 Load transient response DCDC1; L= FDK MIPSA2520 2.2 μH, PWM mode Scope plot Io = 40mA to 360mA; Vo = 3.3V; Vi = 3.6V Figure 11 Line transient response DCDC1; L= FDK MIPSA2520 2.2 μH, PWM mode Scope plot; Vo = 2.05V Vi = 3.6V to 5V to 3.6V; Io = 60mA Figure 12 Output voltage ripple in PFM mode; DCDC1 Scope plot: Vi = 3.6V Vo = 2.05V; Io = 50μA (PFM); Io = 60mA (PWM) Figure 13 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) FIGURE Output voltage ripple in PWM mode; DCDC1 Scope plot: Vi = 3.6V Vo = 2.05V; Io = 60mA (PWM) Figure 14 Startup DCDC1 and LDO1 Scope plot using TPS65720 (battery powered) for /PB_IN; Vo_DCDC1; Vo_LDO1 Figure 15 Load transient response LDO1 Scope plot; V = 1.85V; Vi = 2.05V I = 50 μA to 60mA to 50 μA Figure 16 Line transient response LDO1 Scope plot; Vo = 1.85V; Vi = 5V to 3.6V to 5V Figure 17 Kset vs Riset Figure 18–Figure 21 Efficiency vs Lout for DCDC1=2.05V, LDO1=1.85V, VinLDO=VDCDC1 Figure 22 TPS65720 Efficiency of DCDC1 vs Load Current; PWM Mode; inductor: LQM21P 3.3uH TPS65720 Efficiency of DCDC1 vs Load Current; PFM Mode; inductor: LQM21P 3.3uH 100 100 VO = 2.05 V VO = 2.05 V VI = 2.5 V 90 90 VI = 2.5 V VI = 3 V 80 80 VI = 3.6 V 60 70 Efficiency - % 70 Efficiency - % VI = 3 V VI = 4.2 V 50 VI = 5 V 40 VI = 3.6 V 60 VI = 4.2 V 50 30 30 20 20 10 10 0 0.00001 0.0001 0.01 0.001 IO - Output Current - A 0.1 VI = 5 V 40 0 0.00001 1 0.0001 0.01 0.001 IO - Output Current - A 0.1 Figure 1. Figure 2. TPS65720 Efficiency of DCDC1 vs Load Current; PWM Mode; inductor: MIPSA2520 2.2uH TPS65720 Efficiency of DCDC1 vs Load Current; PFM Mode; inductor: MIPSA2520 2.2uH 100 1 100 VO = 2.05 V VO = 2.05 V 90 90 VI = 2.5 V VI = 2.5 V 80 80 VI = 3 V 70 VI = 3.6 V 60 50 Efficiency - % Efficiency - % 70 VI = 4.5 V 40 VI = 5 V 40 20 20 10 10 0.01 0.001 IO - Output Current - A 0.1 1 VI = 4.2 V 50 30 0.0001 VI = 3.6 V 60 30 0 0.00001 VI = 3 V 0 0.00001 VI = 5 V 0.0001 Figure 3. 0.01 0.001 IO - Output Current - A 0.1 1 Figure 4. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 13 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com TPS65721 Efficiency of DCDC1 vs Load Current; PWM Mode; inductor: MIPSA2520 2.2uH TPS65721 Efficiency of DCDC1 vs Load Current; PFM Mode; inductor: MIPSA2520 2.2uH 100 100 VO = 3.3 V VO = 3.3 V 90 90 80 VI = 3.4 V 80 VI = 3.4 V VI = 3.6 V 70 Efficiency - % Efficiency - % 70 VI = 3.6 V 60 50 VI = 4.2 V 40 VI = 5 V 50 30 20 20 10 10 0.0001 0.01 0.001 IO - Output Current - A 0.1 VI = 5 V 40 30 0 0.00001 VI = 4.2 V 60 0 0.00001 1 0.0001 0.01 0.001 IO - Output Current - A 0.1 Figure 5. Figure 6. TPS65721 Efficiency of DCDC1 vs Load Current; PWM Mode; inductor: MIPSA2520 2.2uH TPS65721 Efficiency of DCDC1 vs Load Current; PFM mode; inductor: MIPSA2520 2.2uH 100 100 VO = 1.8 V VO = 1.8 V 80 70 VI = 3.6 V 60 VI = 4.2 V 50 VI = 5 V 40 VI = 5 V 20 10 10 0.1 1 VI = 4.2 V 40 20 0.01 0.001 IO - Output Current - A VI = 3.6 V 50 30 0.0001 VI = 3 V 60 30 0 0.00001 VI = 2.5 V 80 VI = 3 V 70 Efficiency - % 90 VI = 2.5 V Efficiency - % 90 1 0 0.00001 0.0001 0.01 0.001 IO - Output Current - A 0.1 Figure 7. Figure 8. Load Transent Response PFM Mode Load Transient Response PWM Mode 1 VI = 3.6 V VI = 3.6 V IO = 20 mA to 180 mA IO = 50 mA to 60 mA VO = 2.05 V VO = 2.05 V Time - 100 ms/div Time - 100 ms/div Figure 9. 14 Figure 10. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 Load Transient Response PWM Mode VI = 3.6 V Line Transient Response PWM Mode IO = 60 mA VI = 3.6 V to 5 V to 3.6 V IO = 40 mA to 360 mA VO = 3.3 V VO = 2.05 V Time - 100 ms/div Time - 100 ms/div Figure 11. Figure 12. Output Voltage Ripple on DCDC1 PFM Mode Output Voltage Ripple on DCDC1 PWM Mode VI = 3.6 V, PWM IO = 60 mA VI = 3.6 V, PFM IO = 50 mA VO = 2.05 V VO = 2.05 V 20 mV/div 20 mV/div Time - 1 ms/div Time - 2 ms/div Figure 13. Figure 14. Startup DCDC1 and LDO1 Load Transient Response LDO1 VILDO = VODCDC, VI = 2.05 V IODCDC = 200 mA VIbat = 3.6 V IO = 50 mA to 60 mA to 50 mA 1 V/div VODCDC = 2.05 V 1 V/div VO = 1.85 V VOLDO = 1.85 V 1 V/div Time - 40 ms/div Time - 200 ms/div Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 15 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com Kset vs Riset Line Transient Response LDO1 150 IO = 60 mA 145 TA = 25°C VI = 5 V to 3.6 V to 5 V 140 KISET - AW 135 TA = -40°C TA = 85°C 130 125 VO = 1.85 V 120 115 110 Time - 100 ms/div 0 4000 8000 12000 RISET - W 16000 Figure 17. Figure 18. ICH_SCL[1,0]=00 Kset vs Riset Kset vs Riset 260 20000 24000 20000 24000 395 TA = 25°C 390 255 TA = -40°C 385 380 TA = 25°C TA = -40°C KISET - AW KISET - AW 250 245 TA = 85°C 375 TA = 85°C 370 365 240 360 355 235 350 230 345 0 4000 8000 12000 RISET - W 16000 Figure 19. ICH_SCL[1,0]=01 16 20000 24000 0 4000 8000 12000 RISET - W 16000 Figure 20. ICH_SCL[1,0]=10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 Kset vs Riset Efficiency vs output current for the complete system; LDO1 powered by DCDC1 with VDCDC1=2.05V; VLDO1= 1.85V 505 100 500 90 TA = -40°C 495 VI = 3 V VI = 3.6 V 80 70 485 Efficiency - % KISET - AW VI = 4.2 V TA = 25°C 490 TA = 85°C 480 VI = 2.5 V 60 VI = 5 V 50 40 475 30 470 20 465 10 460 0 4000 8000 12000 RISET - W 16000 20000 24000 0 0.00001 0.0001 Figure 21. ICH_SCL[1,0]=11 0.01 0.001 IO - Output Current - A 0.1 1 Figure 22. DETAILED DESCRIPTION BATTERY CHARGER AND POWER PATH The TPS65720 integrates a Li-Ion linear charger and system power path management targeted at space-limited portable applications. The TPS65720 powers the system while simultaneously and independently charging the battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge termination and enables the system to run with a defective or absent battery pack. It also allows instant system turn-on even with a totally discharged battery. The input power source for charging the battery and running the system can be an AC adapter or an USB port. The power-path management feature automatically reduces the charging current if the system load increases. The power-path architecture also permits the battery to supplement the system current requirements when the adapter cannot deliver the peak system currents. POWER DOWN The charger remains in power-down mode when the input voltage at the AC pin is below the under-voltage lockout threshold (UVLO). During the power-down mode, the host commands through the I2C interface are ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that connects BAT to SYS is ON. (If <SYSOFF>=1, Q2 is off). During power-down mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on SYS. SLEEP MODE The charger enters sleep mode when VAC is greater than UVLO, but below VBAT + VIN(DT). In sleep mode, the host commands are ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that connects BAT to SYS is ON. (If <SYSOFF>=1, Q2 is off). During sleep mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on SYS. STANDBY MODE When VAC is greater than UVLO and VIN is greater than VBAT + VIN(DT), the device is in standby mode. <CH_PGOOD> =1 to indicate the valid power status and the host commands are read. The device enters standby mode whenever <AC input current1, AC input current0> = (0,0) or if an input overvoltage condition occurs. In standby mode, Q1 is OFF and Q2 is ON. (If <SYSOFF>=1, Q2 is off). During standby mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on SYS. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 17 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com POWER-ON RESET MODE The charger enters power-on reset mode when the input voltage at AC is within the valid range: VAC > UVLO and VAC > VBAT + VIN(DT) and VAC < VOVP, and the Bits <AC input current1, AC input current0> indicate that the USB suspend mode is not enabled [<AC input current1, AC input current0>≠ (0,0)]. During power-on reset mode, all internal timers and other circuit blocks are activated. The device checks for short-circuits at the ISET pin. If no short conditions exists, the device switches on the input FET Q1 with a 100-mA current limit to check for a short circuit at SYS. If VOUT rises above VSC, the FET Q1 switches to the current-limit threshold set by <AC input current1, AC input current0>, and the device enters into the Idle mode. IDLE MODE In the Idle mode, the system is powered by the input source (Q1 is on), and the device continuously monitors the status of the host commands. It also continuously monitors the input voltage conditions. Q2 is turned on whenever the input source cannot deliver the required load current (supplement mode). The device also enters Idle mode whenever <CH_EN> =0 while the input voltage is in the valid range of operation. POWER-PATH MANAGEMENT The current at the input pin AC of the power path manager is shared between charging the battery and powering the system load on the SYS pin. Priority is given to the system load. The input current is monitored continuously. If the sum of the charging and system load currents exceeds the preset maximum input current (programmed internally by I2C), the charging current is reduced automatically. The default value for the current limit is 500mA for the AC pin. 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 250mV V BAT OUT -SC1 <VOUT_0> <VOUT_1> V O(SC1 ) Q1 AC < I_PR_CH0> < I_PR_CH1> V REF ISET V IPRECHG V ICHG < I_CH_SCL0 > T J < I_CH_SCL1 > T J(REG ) <TH_LOOP> V IN -LOW USB 100 USB 500 USB- susp - ILIM Short Detect <V_ DPM> V DPPM V O(REG) Q2 VSYS <CH_VLT0> V BAT(REG <CH_VLT1> <IN_CUR_LIM> <USB_SUSP> ) V OUT I BIAS IBAT(SC 40mV - ITERM Supplement V LOWV V REF- ITERM T3L: ITERM ~3V ) BAT V RCH <I_TERM0> <I_TERM1> V BAT(SC) ITERM floating tD G L(RC H) ) ) t D G L2 (L O W V t D G L1 (L O W V I BAT (DET) tDG L (T E R M ) V AC V BAT + V OUT-SC2 SYS EN2 Short Detect t DGL(SC2) BAT -SC AC -DT t DGL(NO <TS_ON> <TS_HOT> <TS_COLD> INTC <E_I_TS> V HOT - IN ) t DGL(PGOOD V UVLO Charge Control V COL ) V OVP D t BLK(OVP ) V DIS(TS) <USB_SUSP> <TERM_DIS> <CH_EN> T3L: /CE Halt timers Reset timers <DYN_TMR> V IPRECHG V ICHG V ISET Dynamical ly Controlled Oscillator <CH_DONE > <PGOOD > Fast - Charge Timer Pre -Charge Timer ~100mV TS t DGL(T S ) Timers disabled T3L : TD T3L: /GHG T3L: /PGOOD Timer fault <SFTY_TMR_0> <SFTY_TMR1> <PR_ CH_TMR> <TMR_F> Figure 23. Charger Block Diagram BATTERY CHARGING When <CH_EN>=1, battery charging begins. First, the device checks for a short circuit on the BAT pin by sourcing IBAT(SC) to the battery and monitoring the voltage. When the BAT voltage exceeds VBAT(SC), the battery charging continues. The battery is charged in three phases: conditioning precharge, constant-current fast charge (current regulation) and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is exceeded. Figure 24 shows what happens in each of the three phases: Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 19 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com CC FAST CHARGE PRECHARGE CV TAPER DONE VBAT(REG) IO(CHG) Battery Current Battery Voltage VLOWV TERM CURRENT = 1 I(PRECHG) I(TERM) Figure 24. Battery Charge In the precharge phase, the battery is charged with the precharge current (IPRECHG). Once the battery voltage crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off as the battery approaches full charge. When the battery current reaches ITERM, the CHG pin indicates charging done by going high impedance. Note that termination detection is disabled whenever the charge rate is reduced from the set point because of the actions of the thermal loop, the DPM loop, or the VIN(LOW) loop. The value of the fast-charge current is set by the resistor connected from the ISET pin to GND, and is given by the equation: ICHG = KISET/RISET The charge current limit is adjustable up to 300mA. The valid resistor range is 1500Ω to 11.25kΩ. Note that if ICHG is programmed as greater than the input current limit, the battery does not charge at the rate of ICHG, but at the slower rate of IACmax (minus the load current on the OUT pin, if any). In this case, the charger timers are proportionately slowed down. I-PRECHARGE The value for the pre-charge current is defined with Bits <I_PRE1, I_PRE0> based on the charge current defined with pin ISET and Bits <CH_SCL1, ICH_SCL0> in register CHCONFIG1. Pre-charge current is scaled to lower currents in DPPM mode or when the charger is in thermal regulation. ITERM The value for the termination current threshold can be set in register CHGCONFIG1 using Bits <I_TERM1, I_TERM0> based on the charge current defined with pin ISET and Bits <CH_SCL1, ICH_SCL0>. Termination current is not scaled in DPPM mode or when the charger is in thermal regulation. BATTERY DETECTION AND RECHARGE The charger automatically detects if a battery is connected or removed. Once a charge cycle is complete, the battery voltage is monitored. When the battery voltage falls below VRCH, the device determines if the battery has been removed. A current, IBAT(DET), is pulled from the battery for a duration tDET. If the voltage on the BAT pin remains above VLOWV, it indicates that the battery is still connected, but has discharged. If <CH_EN>=1, the charger is turned on again to top off the battery. During this recharge cycle, the CHG output remains high-impedance. Recharge cycles are not indicated by the <CH_ACTIVE> Bit. 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 If the BAT voltage falls below VLOWV during the battery detection test, it indicates that the battery has been removed. The device then checks for battery insertion. The FET Q2 is turned on and sources IPRECHG out of BAT for the duration of tDET. If the battery voltage does not rise above VRCH, it indicates that a battery has been inserted, and a new charge cycle begins. If the voltage rises above VRCH, it is possible that a fully charged battery has been inserted. To check for this, IBAT(DET) is pulled from the battery for tDET. If the voltage falls below VLOWV, a battery is not present. The device continuously checks for the presence of a battery. CHARGE TERMINATION ON/OFF Charge termination can be disabled by setting the Bit <TERM_EN>=0. When termination is disabled, the device goes through the pre-charge, fast-charge, and CV phases, then remains in the CV phase. During the CV phase, the charger behaves like an LDO with an output voltage equal to VBAT(REG) and is able to source currents up to ICHG or IINmax, whichever is less. Battery detection is not performed. The Bit <CH_ACTIVE>=0 once the current falls below ITERM and does not go t o1 until the input power is toggled. When termination is disabled, the pre-charge and fast-charge safety timers are also disabled. Battery pack temperature sensing (TS pin functionality) is also disabled if Bit <TERM_EN>=0 and the TS pin is unconnected. TIMERS The charger in TPS65720 has internal safety timers for the pre-charge and fast-charge phases to prevent potential damage to either the battery or the system. The default values for the timers can be changed in register CHGCONFIG2. The pre-charge timer and fast charge timer will run with their nominal speed defined in register CHCONFIG2 if ICH_SCL[1,0]=01, which equals a charge current of 50% defined with the ISET resistor. If ICH_SCL[1,0] are set to higher or lower fast- charge current, the fast charge timers and pre-charge timers are scaled automatically. For instance, with ICH_SCL[1,0]=11, which equals 100% of fast charge current, the safety timers will time out in half the time defined in register CHCONFIG2. Changing the pre-charge current with I_PRE[1,0] will not change the pre-charge or fast-charge timers. DYNAMIC TIMER FUNCTION During the fast-charge phase, several events increase the timer durations. 1. The system load current activates the DPM loop which reduces the available charging current 2. The input current is reduced because the input voltage has fallen to VIN(LOW) 3. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG) During each of these events, the internal timers are slowed down proportionately to the reduction in charging current. For example, if the charging current is reduced by half, the fast-charge timer is twice as long as programmed. A modified charge cycle with the thermal loop active is shown in Figure 25 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 21 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com PRECHARGE THERMAL REGULATION CC FAST CHARGE CV TAPER DONE VO(REG) IO(CHG) Battery Voltage Battery Current V(LOWV) TERM CURRENT = 1 I(PRECHG) I(TERM) IC junction temperature, Tj TJ(REG) Figure 25. Thermal Loop TIMER FAULT If the pre-charge timer expires before the battery voltage reaches VLOWV, the charger indicates a fault condition. Additionally, if the battery current does not fall to ITERM before the fast-charge timer expires, a fault is indicated by setting Bit <TIMER_FAULT>=1. THERMAL REGULATION AND THERMAL SHUTDOWN The charger contains a thermal regulation loop that monitors the die temperature. If the temperature exceeds TJ(REG), the device automatically reduces the charging current to prevent the die temperature from increasing further. In some cases, the die temperature continues to rise despite the operation of the thermal loop, particularly under high VAC and heavy system load conditions. Under these conditions, if the die temperature increases to TJ(OFF), the input FET Q1 is turned OFF. FET Q2 is turned ON to ensure that the battery still powers the load on SYS. Once the device die temperature cools by TJ(OFF-HYS), the input FET Q1 is turned on and the device returns to thermal regulation. Continuous over-temperature conditions result in the pulsing of the Q1 FET. Note that this feature monitors the die temperature of the charger. This is not synonymous with ambient temperature. Self-heating exists due to the power dissipated in the IC because of the linear nature of the battery charging algorithm and the LDO mode for SYS. BATTERY PACK TEMPERATURE MONITORING The TPS65720 features an external battery pack temperature monitoring input. The TS input connects to the NTC resistor in the battery pack to monitor battery temperature and prevent dangerous over-temperature conditions. During charging, INTC is sourced to TS and the voltage at TS is continuously monitored. If, at any time, the voltage at TS is outside of the operating range (VCOLD to VHOT), charging is suspended. The timers maintain their values but suspend counting. When the voltage measured at TS returns to within the operation 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 window, charging is resumed and the timers continue counting. When charging is suspended due to a battery pack temperature fault, the CH_ACTIVE Bit remains 1 and continues to indicate charging. Battery pack temperature sensing is disabled when termination is disabled (<TERM_EN=0>) and the voltage at TS is greater than VDIS(TS). The battery pack temperature monitoring is disabled by connecting a 10-kΩ resistor from TS to GND. TPS65720 contains a feature to shift the termination temperature to higher levels by setting Bits <TMP_SHIFT1, TMP_SHIFT0>. DCDC1 CONVERTER The TPS65720 step down converter operates with typically 2.25 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converter can automatically enter Power Save Mode and operates then in PFM mode. During PWM operation the converter use a unique fast response voltage mode control scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the High Side MOSFET switch is exceeded. After a dead time preventing shoot through current, the Low Side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET rectifier. The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on the on the High Side MOSFET switch. The DCDC1 converters output voltage is externally adjustable using a resistor divider at FB_DCDC1. POWER SAVE MODE The Power Save Mode is enabled automatically with <F_PWM>=0 which is the default setting. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. The High Side MOSFET switch will turn on, and the inductor current ramps up. After the On-time expires, the switch is turned off and the Low Side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 15μA current consumption. If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode is entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be disabled by setting <F_PWM>=1. The converter will then operate in fixed frequency PWM mode. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 23 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. Soft Start The step-down converter in TPS65720 has an internal soft start circuit that controls the ramp up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250μs. This limits the inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high impedance power source is used. EN 95% 5% VOUT tStart tRAMP Figure 26. Soft Start 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output voltage. In order to maintain the output voltage, the High Side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the High Side MOSFET switch is turned on completely. In this case the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOmax + IOmax × ®DS(on)max + RL) With: IOmax = maximum output current plus inductor ripple current RDS(on)max = maximum high side switch RDSon. RL = DC resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 Under-Voltage Lockout The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters and LDOs. The under-voltage lockout threshold is typically 2.2V. SHORT-CIRCUIT PROTECTION All outputs are short circuit protected with a maximum output current as defined in the electrical specifications. THERMAL SHUTDOWN There are two thermal sensors in TPS6572x located at the main sources of power dissipation - the charger and the LDO. The maximum temperature of the charger is regulated by reducing its charge current. If the temperature increases further, the charger is disabled - see details in the charger description. The second sensor is enabled as soon as the LDO is enabled. As soon as the junction temperature, TJ, exceeds typically 150°C, the device goes into thermal shutdown. In this mode, the low side and high side MOSFETs are turned-off. A thermal shutdown for the LDO will disable both, LDO and the DCDC converter simultaneously. LDO1 The low dropout voltage regulator is designed to operate well with low value ceramic input and output capacitors. It operates with input voltages down to 1.8V. The LDOs offer a maximum dropout voltage of 160mV at rated output current. LDO1 supports a current limit feature. Its output voltage is adjustable using a resistor divider at FB_LDO1 for TPS65721. The LDO1 voltage is fixed to 1.85V for TPS65720. Default Voltage Setting for LDOs and DCDC1 In TPS65721, both DCDC1 and LDO1 are externally adjustable. For TPS65720, the output voltage of the DCDC1 converter is externally adjustable and for LDO1 it is fixed to 1.85V per default. The I2C registers do allow changing the default voltage for LDO1 in a range of 0.8V to 3.3V. For DCDC1, the register also allows setting any voltage in the range from 0.8V to 3.3V, however for the adjustable version of DCDC1, the change in the I2C register has no effect on the output voltage. The registers will be set to the default value when the voltage at SYS drops below the undervoltage lockout threshold or by a reset event (RESET output is actively pulled low). See the register description for more details. GPIOs, LED Drivers TPS65720 contains 4 standard input/output pins (GPIOs) named GPIO0 to GPIO3. The output driver/input buffer is available in register GPIO_SSC while register GPIODIR selects the data direction and additional features. After RESET, GPIO0 and GPIO1 are pre-defined as general purpose inputs while GPIO2 and GPIO3 are configured as LED driver outputs which are high impedance. The LED driver outputs are designed to be constant current sinks to GND, sinking a constant current of 5mA when enabled. The GPIOs do not have internal pull-up resistors. External pull-up resistors might be required if configured as inputs or outputs. RESET output Actively low, open drain reset output. Connect external pull-up resistor. The reset pin will go high impedance 100ms after the reset condition is left. For TPS65720, reset is generated, depending on the power-good signal of LDO1, when the output voltage is below the threshold or LDO1 is disabled. For TPS65721, reset is generated depending on the voltage at pin THRESHOLD. THRESHOLD INPUT (TPS65721 only) This is an input to the comparator driving the Reset output. If the voltage applied at THRESHOLD is below the threshold, Reset is pulled actively LOW. If the voltage rises above the threshold + hysteresis, the Reset output is released after a delay time of 100ms (typically). ENABLE for DCDC1 and LDO1 The DCDC1 converter and LDO1 are enabled as soon as PB_IN is pulled LOW OR input voltage at pin AC is detected (<CH_PGOOD>=1). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 25 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com There is a power-hold pin for DCDC1 (HOLD_DCDC1) and one for LDO1 (HOLD_LDO1). When HOLD_DCDC1 is pulled HIGH, DCDC1 is kept enabled after PB_IN was released HIGH. HOLD_LDO1 serves the same function and keeps LDO1 enabled after PB_IN was released HIGH. After first power-up by pulling PB_IN = LOW or applying voltage at AC, the HOLD pins HOLD_DCDC1 and HOLD_LDO1 can also be used as enable pins, such that they turn on LDO1 or DCDC1, respectively when they are pulled HIGH. This function is available as long as there is a voltage at the battery. After the battery was removed or was discharged, first power-on needs to be done by pulling PB_IN=LOW. Disabling the DCDC converter or LDO, forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the low and high side MOSFETs are turned-off and the entire internal control circuitry is switched-off. For proper operation the PB_IN, HOLD_DCDC1, EN_DLO1 pins must be terminated and must not be left floating. PB_IN Input Enables DCDC1 and LDO1 if pulled to GND. Disables DCDC1 and LDO1 if pulled high. There is no internal pull-up resistor, so a resistor is needed externally to SYS. SYS is preferred over BAT because it is powered by either AC or BAT (whichever is higher). If BAT is used, the device may not get a valid HIGH signal if the battery is deeply discharged even when there is voltage at AC. The input signal is debounced internally by 50ms. When PB_IN is pulled low, the DCDC1 converter and LDO1 will power-up simultaneously. When PB_IN is de-asserted, both converters are turned off. To leave the converters on, the HOLD_DCDC1 and HOLD_LDO1 pin need to be asserted high. The HOLD register Bit <CONTROL1:B5> will keep both, DCDC1 and LDO1 enabled if set to 1. For proper operation the PB_IN, HOLD_DCDC1 and HOLD_LDO1 pins must be terminated and must not be left floating. PB_IN PB_IN (internally after debounce) HOLD_DCDC1 set HIGH by I2C write to register (optional) HOLD_DCDC1 Bit <DEFDCDC1:B7> VDCDC1 HOLD_LDO1 set HIGH by I2C write to register (optional) HOLD_LDO1 Bit <LDO_CTRL:B7> VLDO1 Figure 27. PB_IN Timing HOLD_DCDC1 Input Actively high hold input for DCDC1. Logically OR´d with the DCDC1 hold Bit <DEFDCDC1:B7>. If the input is driven HIGH after PB_IN was pulled LOW, the DCDC1 converter stays on after PB_IN was released. HOLD_LDO1 Input Actively high hold input for LDO1. Logically OR´d with the LDO1 hold Bit <LDO_CTRL:B7>. If the input is driven HIGH after PB_IN was pulled LOW, LDO1 stays on after PB_IN was released. 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 INT Output Actively low, open drain interrupt output. Connect external pull-up resistor. Interrupts are flagged in the registers IR0, IR1 and IR2 if the interrupt is not masked by registers IRMASK0, IRMASK1 and IRMASK2. Per default, all interrupts are masked. Interrupts which are unmasked will set the Bit in either on the rising edge or on both edges. Details can be found in the register description for IR0, IR1 and IR2. Any Bit in IR0, IR1 and IR2, set to “1” will drive the reset pin INT actively LOW. The reset pin will go high impedance after the Bit, generating the reset is read. Serial Interface The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above the UVLO threshold. The TPS65720 has a 7bit address: ‘100 1000’, other addresses are available upon contact with the factory. Attempting to read data from register addresses not listed in this section will result in 00h being read out. For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65720 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65720 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65720 device must leave the data line high to enable the master to generate the stop condition. For the QFN version, the voltage the pull-up resistors for the I2C interface at SCLK and SDAT are connected to, should be monitored by the reset circuitry. This is done by connecting THRESHOLD with a voltage divider to the voltage the SDAT and SCLK pins are pulled-up to. This is needed to ensure a falling supply voltage will cause a reset to the I2C interface. Otherwise a START condition may be detected and the first access to the I2C interface may return NO ACK (no acknowledge). SDAT SCLK Data line stable; data valid Change of data allowed Figure 28. Bit Transfer on the Serial Interface SDAT SCLK STOP condition START condition Figure 29. START and STOP Conditions Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 27 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com ... SCLK SDAT A6 A5 ... A4 ... A0 R/W ACK 0 Start R7 R6 ... ... R5 R0 ACK 0 D7 D6 D5 ... D0 ACK 0 Slave Address 0 Register Address Stop Data NOTE: SLAVE =TPS65720 Figure 30. Serial I/f WRITE to TPS65720 Device ... SCLK SDAT A6 .. ... R/W ACK A0 0 .. R7 ... ... R0 ACK 0 .. A6 R/W ACK A0 0 1 D7 Register Address D0 Slave Drives the Data Slave Address Stop Master Drives ACK and Stop Repeated Start NOTE: SLAVE =TPS65720 ACK 0 Start Slave Address .. Figure 31. Serial I/f READ From TPS65720: Protocol A SCLK ... SDAT A6 .. ... A0 R7 .. R/W ACK 0 Start ... .. A6 .. R0 ACK 0 0 R/W ACK D7 .. 1 Stop Start Register Address Slave Address A0 D0 0 Slave Address NOTE: SLAVE=TPS65720 Slave Drives the Data ACK Stop Master Drives ACK and Stop Figure 32. Serial I/f READ From TPS65720: Protocol B DATA t(BUF) th(STA) t(LOW) tr tf CLK th(STA) t(HIGH) th(DATA) STO STA tsu(STA) tsu(DATA) tsu(STO) STA STO Figure 33. Serial I/f Timing Diagram 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 MIN MAX UNIT 400 kHz fMAX Clock frequency twH(HIGH) Clock high time 600 twL(LOW) Clock low time 1300 tR DATA and CLK rise time tF DATA and CLK fall time th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns th(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 0 ns tsu(DATA) Data input setup time 100 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns ns ns 300 ns 300 ns All registers are set to their default value by one of the following events: • Voltage at the SYS pin is below the undervoltage lockout voltage (UVLO) • RESET is active; RESET output is pulled LOW and goes high with a 100ms delay Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 29 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com CHGSTATUS Register Address: 01h (read only) CHGSTATUS Bit name and function Default B7 B6 B5 TS_HOT TS_COLD OVP x x x R R R B4 B3 B2 B1 CH_ACTIVE CH_PGOOD CH_THLOOP BO 0 x x x 0 R R R R R Default value loaded by: Read/write Bit 7 TS_HOT: 0 = battery temperature is below high temperature threshold (45°C/50°C/55°C/60°C). 1 = battery temperature is above high temperature threshold (45°C/50°C/55°C/60°C). Bit 6 TS_COLD: 0 = battery temperature is above low temperature threshold (0°C/5°C/10°C/15°C) 1 = battery temperature is below low temperature threshold (0°C/5°C/10°C/15°C) Bit 5 OVP: 0 = Input overvoltage protection is not active (VAC<6.6V) 1 = Input overvoltage protection is active (VAC>6.6V) Bit 3 CH_ACTIVE: 0 = charger is not active 1 = charger is charging the battery Bit 2 CH_PGOOD: 0 = no input voltage at pin AC or voltage not inside the voltage range for changing 1 = power source is present and in the range valid for charging Bit 1 CH_THLOOP: 0 = thermal loop not active 1 = thermal loop active 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 CHGCONFIG0 Register Address: 02h (read/write) CHGCONFIG0 Bit name and function B7 B6 B5 B4 B3 B2 B1 BO VSYS1 VSYS0 AC input current1 AC input current0 TH_LOOP DYN_TMR TERM_EN CH_EN 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W R/W R/W Default For TPS65720 For TPS65721 Default value loaded by: Read/write Bit 7..6 VSYS1..VSYS0: 00 = the output voltage of the power path at pin SYS tracks the battery voltage; VSYS=VBAT+200mV (Vbat>3.3V); VSYS=3.4V (VBAT</=3.3V); V_DPPM=1 is forced in this case 01 = the output voltage of the power path at pin SYS is regulated to 4.4V 10 = the output voltage of the power path at pin SYS is regulated to 5.0V 11 = the output voltage of the power path at pin SYS is regulated to 5.5V Bit 5..4 AC input current1.. AC input current0: 00 = 100mA, input voltage DPPM enabled 01 = 500mA, input voltage DPPM enabled 10 = 500mA, input voltage DPPM disabled 11 = USB suspend mode; standby Bit 3 TH_LOOP: 0 = the thermal loop is disabled 1 = the thermal loop is enabled and the charge current is reduced if the temperature exceeds 125°C Bit 2 DYN_TMR (dynamic timer function): 0 = safety timers run with their normal clock speed 1 = clock speed for the safety timers is reduced based on the actual charge current if DPPM or thermal loop is active Bit 1 TERM_EN (charge termination enable): 0 = charge termination will not occur and the charger will always be on 1 = charge termination enabled based on timers and termination current Bit 0 CH_EN: 0 = the charger is disabled 1 = the charger is enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 31 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com CHGCONFIG1 Register Address: 03h (read/write) CHGCONFIG1 Bit name and function Default For TPS65720 For TPS65721 Default value loaded by: Read/write B7 B6 B5 B4 B3 B2 I_PRE1 I_PRE0 ICH_SCL1 ICH_SCL0 I_TERM1 I_TERM0 0 0 1 1 0 1 1 1 0 0 1 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W B1 BO 0 1 0 1 R R Bit 7..6 I_PRE1..I_PRE0 (Pre-charge current factor): 00 = 5% of value defined with ICH_SCL1, ICH_SCL0 01 = 10% of value defined with ICH_SCL1, ICH_SCL0 10 = 15% of value defined with ICH_SCL1, ICH_SCL0 11 = 20% of value defined with ICH_SCL1, ICH_SCL0 Bit 5..4 ICH_SCL1..ICH_SCL0 (charge current scaling factor): 00 = 25% of value defined with ISET resistor; safety timer will time out at 2x SFTY_TMR[0,1] 01 = 50% of value defined with ISET resistor; safety timer runs at its nominal time defined in SFTY_TMR[0,1] 10 = 75% of value defined with ISET resistor; safety timer will time out at 0.66x SFTY_TMR[0,1] 11 = 100% of value defined with ISET resistor; safety timer will time out at 0.5x SFTY_TMR[0,1] Bit 3..2 I_TERM1..I_TERM0 (termination current scaling factor): 00 = 5% of value defined with ICH_SCL1, ICH_SCL0 01 = 10% of value defined with ICH_SCL1, ICH_SCL0 10 = 15% of value defined with ICH_SCL1, ICH_SCL0 11 = 20% of value defined with ICH_SCL1, ICH_SCL0 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 CHGCONFIG2 Register Address: 04h (read/write) CHGCONFIG2 Bit name and function Default Default value loaded by: Read/write B7 B6 B5 SFTY_TMR1 0 SFTY_TMR PRE_TMR 0 1 0 UVLO/R UVLO/R UVLO/R R/W R/W R/W B4 0 R B3 B2 B1 NTC V_DPPM VBAT_COMP_EN 1 1 0 UVLO/R UVLO/R UVLO/R R/W R/W R/W Bit 7..6 SFTY_TMR1..SFTY_TMR0 (charge safety timer value): 00 = 4h 01 = 5h 10 = 6h 11 = 8h Bit 5 PRE_TMR (pre-charge timer value): 0 = 30min 1 = 60min Bit 3 NTC (sensor resistance): 0 = 100k NTC (I=7.5uA) 1 = 10k NTC (I=75uA) Bit 2 V_DPPM (dynamic power path threshold): 0 = VBAT+100mV 1 = 4.3V Bit 1 VBAT_COMP_EN (battery voltage comparator enable): 0 = battery voltage comparator for Li-primary cells disabled; VBAT_COMP interrupt disabled 1 = battery voltage comparator for Li-primary cells enabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 BO 0 R 33 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com CHGCONFIG3 Register Address: 05h (read/write) CHGCONFIG3 Bit name and function Default Default value loaded by: Read/write B7 B6 B5 B4 B3 B2 B1 BO CH_VLTG2 CH_VLTG1 CH_VLTG0 TMP_SHIFT1 TMP_SHIFT0 VBAT1 VBAT0 VBAT_COMP 0 1 0 0 0 0 0 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W R/W R Bit 7..5 CH_VLTG2..CH_VLTG0 (charge voltage selection): 000 = 4.15V 001 = 4.175V 010 = 4.20V 011 = 4.225V 100 = 4.25V 101 = 4.275V 110 = 4.30V 111 = 4.325V Bit 4..3 TMP_SHIFT1..TMP_SHIFT0 (battery temperature shift): 00 = the temperature for TS_COLD and TS_HOT is at 0°C/45°C 01 = the temperature window is shifted by 5°C to TS_COLD/TS_HOT = 5°C/50°C 10 = the temperature window is shifted by 10°C to TS_COLD/TS_HOT = 10°C/55°C 11 = the temperature window is shifted by 15°C to TS_COLD/TS_HOT = 15°C/60°C Bit 2..1 VBAT1..VBAT0 (battery voltage comparator threshold; for Li primary cells): 00 = 2.2V 01 = 2.3V 10 = 2.4V 11 = 2.5V Bit 0 VBAT_COMP (battery voltage comparator output): 0 = voltage above the threshold 1 = voltage below the threshold or comparator disabled 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 CHGSTATE Register Address: 06h (read only) CHGSTATE Bit name and function B7 B6 B5 B4 B3 B2 B1 BO CH_SLEEP CH_RESET CH_IDLE CH_PRECH CH_CC CH_LDO CH_FAULT CH_SUSP Default X X X X X X X X Read/write R R R R R R R R Bit 7 CH_SLEEP: 0 = charger is not in sleep state 1 = charger is in sleep state Bit 6 CH_RESET: 0 = charger is not in reset state 1 = charger is in reset state Bit 5 CH_IDLE: 0 = charger is not in idle state 1 = charger is in idle state Bit 4 CH_PRECH: 0 = charger is not in pre-charge state 1 = charger is in pre-charge state Bit 3 CH_CC: 0 = charger is not in constant current mode 1 = charger is in constant current mode Bit 2 CH_LDO: 0 = charger is not in LDO mode 1 = charger is in LDO mode Bit 1 CH_FAULT: 0 = charger is not in fault state 1 = charger is in fault state Bit 0 CH_SUSP: 0 = charger is not in suspend state 1 = charger is in suspend state Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 35 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com DEFDCDC1 Register Address: 07h (read/write) DEFDCDC1 B7 B6 B5 B4 B3 B2 B1 BO Bit name and function HOLD_ DCDC1 DCDC_DISCH DCDC1[5] DCDC1[4] DCDC1[3] DCDC1[2] DCDC1[1] DCDC1[0] Default Default value loaded by: Read/write 0 0 1 0 1 0 0 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 HOLD_DCDC1: 0 = DCDC1 is disabled when HOLD_DCDC1 pin is pulled LOW and PB_IN is released HIGH 1 = DCDC1 stays enabled when HOLD_DCDC1 pin is pulled LOW and PB_IN is released HIGH Bit 6 DCDC_DISCH: 0 = DCDC1 output is not discharged when DCDC1 is disabled 1 = DCDC1 output is discharged when DCDC1 is disabled Bit 5..0 Output voltage setting for DCDC1: For reference only: A voltage change in the register will not have an effect on the output voltage for TPS65720 and TPS65721 as the voltage is set by an external resistor divider. Contact TI in case a fixed voltage version is needed. A Voltage change during operation must not exceed 8% of the value set in the register for each I2C write access as this may trigger the internal power good comparator and will trigger the Reset of the device. This limitation is only for a voltage step to higher voltages. There is no limitation for programming lower voltages by I2C. 36 OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0 0 0.800 0 0 0 0 0 0 1 0.825 0 0 0 0 0 1 2 0.850 0 0 0 0 1 0 3 0.875 0 0 0 0 1 1 4 0.900 0 0 0 1 0 0 5 0.925 0 0 0 1 0 1 6 0.950 0 0 0 1 1 0 7 0.975 0 0 0 1 1 1 8 1.000 0 0 1 0 0 0 9 1.025 0 0 1 0 0 1 10 1.050 0 0 1 0 1 0 11 1.075 0 0 1 0 1 1 12 1.100 0 0 1 1 0 0 13 1.125 0 0 1 1 0 1 14 1.150 0 0 1 1 1 0 15 1.175 0 0 1 1 1 1 16 1.200 0 1 0 0 0 0 17 1.225 0 1 0 0 0 1 18 1.250 0 1 0 0 1 0 19 1.275 0 1 0 0 1 1 20 1.300 0 1 0 1 0 0 21 1.325 0 1 0 1 0 1 22 1.350 0 1 0 1 1 0 23 1.375 0 1 0 1 1 1 24 1.400 0 1 1 0 0 0 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0 25 1.425 0 1 1 0 0 1 26 1.450 0 1 1 0 1 0 27 1.475 0 1 1 0 1 1 28 1.500 0 1 1 1 0 0 29 1.525 0 1 1 1 0 1 30 1.550 0 1 1 1 1 0 31 1.575 0 1 1 1 1 1 32 1.600 1 0 0 0 0 0 33 1.650 1 0 0 0 0 1 34 1.700 1 0 0 0 1 0 35 1.750 1 0 0 0 1 1 36 1.800 1 0 0 1 0 0 37 1.850 1 0 0 1 0 1 38 1.900 1 0 0 1 1 0 39 1.950 1 0 0 1 1 1 40 2.000 1 0 1 0 0 0 41 2.050 1 0 1 0 0 1 42 2.100 1 0 1 0 1 0 43 2.150 1 0 1 0 1 1 44 2.200 1 0 1 1 0 0 45 2.250 1 0 1 1 0 1 46 2.300 1 0 1 1 1 0 47 2.350 1 0 1 1 1 1 48 2.400 1 1 0 0 0 0 49 2.450 1 1 0 0 0 1 50 2.500 1 1 0 0 1 0 51 2.550 1 1 0 0 1 1 52 2.600 1 1 0 1 0 0 53 2.650 1 1 0 1 0 1 54 2.700 1 1 0 1 1 0 55 2.750 1 1 0 1 1 1 56 2.800 1 1 1 0 0 0 57 2.850 1 1 1 0 0 1 58 2.900 1 1 1 0 1 0 59 2.950 1 1 1 0 1 1 60 3.000 1 1 1 1 0 0 61 3.100 1 1 1 1 0 1 62 3.200 1 1 1 1 1 0 63 3.300 1 1 1 1 1 1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 37 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com LDO_CTRL Register Address: 08h (read/write) LDO_CTRL Bit name and function Default Default value loaded by: Read/write B7 B6 B5 B4 B3 B2 B1 BO HOLD_LDO1 LDO1_DISCH LDO1[5] LDO1[4] LDO1[3] LDO1[2] LDO1[1] LDO1[0] 0 1 1 0 0 1 0 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 HOLD_LDO1: 0 = LDO1 is disabled when HOLD_LDO1 pin is pulled LOW and PB_IN is released HIGH 1 = LDO1 stays enabled when HOLD_LDO1 pin is pulled LOW and PB_IN is released HIGH Bit 6 LDO1_DISCH: 0 = LDO1 output is not discharged when LDO1 is disabled 1 = LDO1 output is discharged when LDO1 is disabled Bit 5..0 LDO1 output voltage setting according to the table listed for DCDC1: The voltage setting is only valid for TPS65720. For TPS65721, the LDO1 voltage is set by an external resistor divider. The voltage setting is according to the same table given for DEFDCDC1. CONTROL0 Register Address: 09h (read/write) CONTROL0 Bit name and function Default Default value loaded by: Read/write B7 B6 B5 F_PWM PGOODZ_DCDC1 PGOODZ_LDO1 B4 B3 B2 B1 BO 0 PGOODDCDC1 PGOODLDO1 0 0 0 0 0 R R R R R R R UVLO/R R/W Bit 7 F_PWM: 0 = DCDC converter is in PWM/PFM mode 1 = DCDC converter is in forced PWM mode Bit 6 PGOODZ_DCDC1: 0 = indicates that the DCDC converters output voltage is within its nominal range 1 = range indicates that the DCDC converters output voltage is below the target regulation voltage or disabled Bit 5 PGOODZ_LDO1: 0 = indicates that the LDO1 output voltage is within its nominal range 1 = indicates that the LDO1 output voltage is below the target regulation voltage or disabled 38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 CONTROL1 Register Address: 0Ah (read/write) CONTROL1 B7 B6 Bit name and function Default 0 R B4 PB_STAT 0 B3 0 UVLO/R UVLO/R R R/W R B2 Bit 5 HOLD (ORed with PB_IN): 0 = DCDC1 and LDO1 switched off 1 = DCDC1 and LDO1 enabled Bit 4 PB_STAT (push-button status, after debounce): 0 = push-button not pressed 1 = push-button pressed Bit 0 RESET_DELAY: 0 = 11ms 1 = 90ms B1 BO RESET_DELAY 0 Default value loaded by: Read/write B5 HOLD 1 0 1 UVLO/R R R R R/W GPIO_SSC Register Address: 0Bh (read/write) GPIO_SSC B7 B6 B5 B4 0 0 0 0 B3 B2 B1 BO GPIO3 GPIO2 GPIO1 GPIO0 1 1 1 1 UVLO/R UVLO/R UVLO/R UVLO/R R R R R/W Bit name and function Default Default value loaded by: Read/write R R R R/W Bit 3 GPIO3: 0 = data in input buffer / actively pulled low when configured as an output or LED driver enabled 1 = data in input buffer / high impedance when configured as an output or LED driver Bit 2 GPIO2: 0 = data in input buffer / actively pulled low when configured as an output or LED driver enabled 1 = data in input buffer / high impedance when configured as an output or LED driver Bit 1 GPIO1: 0 = data in input buffer / actively pulled low when configured as an output 1 = data in input buffer / high impedance when configured as an output Bit 0 GPIO0: 0 = data in input buffer / actively pulled low when configured as an output 1 = data in input buffer / high impedance when configured as an output Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 39 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com GPIODIR Register Address: 0Ch (read/write) GPIODIR Bit name and function Default Default value loaded by: Read/write B7 B6 GPIO3_LED GPIO2_LED 1 1 UVLO/R UVLO/R R/W R/W B5 B4 1 B3 B2 B1 BO GPIO3_DIR GPIO2_DIR GPIO1_DIR GPIO0_DIR 1 R R Bit 7 GPIO3_LED: 0 = GPIO3 is configured as a standard GPIO 1 = GPIO3 is configured as 5mA LED driver Bit 6 GPIO2_LED: 0 = GPIO2 is configured as a standard GPIO 1 = GPIO2 is configured as 5mA LED driver Bit 3 GPIO3_DIR: 0 = GPIO3 is configured as an output / LED driver 1 = GPIO3 is configured as an input Bit 2 GPIO2_DIR: 0 = GPIO2 is configured as an output / LED driver 1 = GPIO2 is configured as an input Bit 1 GPIO1_DIR: 0 = GPIO1 is configured as an output 1 = GPIO1 is configured as an input Bit 0 GPIO0_DIR: 0 = GPIO0 is configured as an output 1 = GPIO0 is configured as an input 0 0 1 1 UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W IRMASK0 Register Address: 0Dh (read/write) IRMASK0 Bit name and function Default Default value loaded by: Read/write Bit 7..0 40 B7 B6 B5 B4 B3 B2 B1 BO M_TS_HOT M_TS_COLD M_OVP M_TIMER_ FAULT M_CH_ ACTIVE M_CH_ PGOOD M_VBAT_ COMP M_THLOOP 1 1 1 1 1 1 1 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W R/W R/W charger interrupt mask register: 0 = Interrupt not masked 1 = Interrupt masked (no interrupt based on the event) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 IRMASK1 Register Address: 0Eh (read/write) IRMASK1 Bit name and function B7 B6 B5 B4 B3 B2 B1 BO M_CH_ SLEEP M_CH_ RESET M_CH_IDLE M_CH_PRECH M_CH_ CC M_CH_ LDO M_CH_ FAULT M_CH_ SUSP Default Default value loaded by: Read/write Bit 7..0 1 1 1 1 1 1 1 1 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R R/W R/W R/W R/W R/W R/W R/W R/W charger state interrupt mask register: 0 = Interrupt not masked 1 = Interrupt masked (no interrupt based on the event) IRMASK2 Register Address: 0Fh (read/write) IRMASK2 Bit name and function Default B7 B6 B5 B4 B3 B2 B1 M_GPIO3 M_GPIO2 M_GPIO1 M_GPIO0 M_PGOODZ_ DCDC1 M_PGOODZ_ LDO1 M_PB_ STAT 1 1 1 1 1 1 1 Default value loaded by: UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R Read/write R/W R/W R/W R/W R/W R/W R/W Bit 7..0 charger state interrupt mask register: 0 = Interrupt not masked 1 = Interrupt masked (no interrupt based on the event) BO 1 R IR0 Register Address: 10h (read only) IR0 Bit name and function Default Default value loaded by: Set by: Read/write Bit 7..2 B7 B6 B5 B4 B3 B2 B1 BO TS_HOT TS_COLD OVP TIMER_FAULT CH_ACTIVE CH_PGOOD VBAT_COMP TH_LOOP 0 0 0 0 0 0 0 0 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R Rising edge of TS_HOT Rising edge of TS_COLD Rising edge of OVP Rising edge of TIMER_FAULT Rising edge of VBAT_COMP* Rising edge of TH_LOOP R R R R R R Rising edge Rising edge and falling edge and falling edge of CH_ACTIVE of CH_PGOOD R R interrupt register: 0 = no interrupt 1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK0 The VBAT_COMP interrupt is automatically disabled when the battery voltage comparator is disabled by clearing Bit 1 in register 04h (VBAT_COMP_EN) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 41 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com IR1 Register Address: 11h (read) IR1 Bit name and function Default Default value loaded by: Set by: Read/write Bit 7..0 B7 B6 B5 B4 B3 B2 B1 BO CH_SLEEP CH_RESET CH_IDLE CH_PRECH CH_CC CH_LDO CH_FAULT CH_SUSP 0 0 0 0 0 0 0 0 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R Rising edge of CH_SLEEP Rising edge of CH_RESET Rising edge of CH_IDLE Rising edge of CH_PRECH Rising edge of CH_CC Rising edge of CH_LDO Rising edge of VBAT_FAULT* Rising edge of TH_SUSP R R R R R R R R interrupt register: 0 = no interrupt 1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK1 IR2 Register Address: 12h (read) IR2 Bit name and function Default Default value loaded by: Set by: Read/write B7 B6 B5 B4 B3 B2 B1 GPIO3 GPIO2 GPIO1 GPIO0 PGOODZ_ DCDC1 PGOODZ_ LDO1 PB_STAT 0 0 0 0 0 0 0 UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R Rising and falling edge of GPIO3 Rising and falling edge of GPIO2 Rising and falling edge of GPIO1 Rising and falling edge of GPIO0 Rising edge of PGOODZ_ DCDC1 Rising edge of PGOODZ_ LDO1 Rising and falling edge of PB_ STAT R R R R R R R BO Bit 7..4 GPIO interrupt register: 0 = GPIO status did not change 1 = GPIO status changed; cleared when read; interrupt not masked in register IRMASK2 Bit 3..2 power good interrupt register: 0 = no interrupt (power good) 1 = interrupt occurred (output voltage of DCDC converter or LDO too low); cleared when read Bit 1 PB_STAT interrupt register: 0 = no interrupt 1 = interrupt occurred; cleared when read; interrupt not masked in register IRMASK2 42 Submit Documentation Feedback 0 R Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 APPLICATION INFORMATION OUTPUT VOLTAGE SETTING DCDC1 The output voltage of the DCDC converter can be set with external resistor network on Pin FB_DCDC1. The feedback voltage is 0.6V. It is recommended to set the total resistance of R1 + R2 to less than 1MΩ. Route the FB_DCDC1 trace separate from noise sources, such as the inductor trace (L1). VFB-DCDC1 = 0.6V VO UT = V FB_DCDC1 ´ R1 + R2 R2 æ VOUT ö R1 = R2 ´ ç ÷ - R2 è V FB_DCDC1 ø (1) Typical resistor values: OUTPUT VOLTAGE R1 R2 NOMINAL VOLTAGE 3.3V 680k 150k 3.32V 3.0V 510k 130k 2.95V 2.85V 560k 150k 2.84V 2.5V 510k 160k 2.51V 2.05V 360k 150k 2.04V 2.0V 470k 200k 2.01V 1.8V 300k 150k 1.80V 1.6V 200k 120K 1.60V 1.5V 300k 200k 1.50V 1.2V 330k 330k 1.20V A feed-forward capacitor in parallel to the resistor from Vout to FB_DCDC1 is required. It´s value should be based on transient performance and will be in the range from 4.7pF to 22pF. LDO1 For TPS65720, the output voltage of LDO1 is set by register LDO_CTRL with the I2C compatible interface. The default output voltage is programmed to 1.85V. The programmable voltage range is 0.8V to 3.3V. For the TPS65721, the output voltage for LDO1 is externally adjustable using a resistor divider at pin FB_LDO1. The feedback voltage is 0.8V and the total resistance of the voltage divider should be kept in the 100kΩ to 1MΩ range. A feed-forward capacitor in parallel to the resistor from Vout to FB_LDO1 is required. It´s value should be based on transient performance and will be in the range from 4.7pF to 22pF. The output voltage with an internal reference voltage VFB-LDO1 =0.8V is: VOUT = VFB_LDOx ´ R3 + R4 R4 æ V OUT ö R3 = R4 ´ ç ÷ - R4 è VFB_LDO1 ø (2) Typical resistor values: OUTPUT VOLTAGE R3 R4 NOMINAL VOLTAGE 3.3V 470k 150k 3.31V 1.85V 200k 150k 1.86V 1.8V 300k 240k 1.80V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 43 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) Inductor Selection The converter operates typically with 3.3μH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency. Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is recommended because during heavy load transient the inductor current will rise above the calculated value Vout 1DI Vin ILmax = Ioutm ax + L DIL = Vout ´ L ´ ¦ 2 (3) With: f = Switching Frequency (2.25MHz typical) L = Inductor Value ΔIL = Peak to Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current will occur at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies. Refer to Table 1 and the typical applications for possible inductors. Table 1. Tested Inductors INDUCTOR TYPE INDUCTOR VALUE SUPPLIER Comments LQM21P 3.3uH Murata For TPS65720 BRC1608T2R2M 2.2uH Taiyo Yuden For TPS65720; Smallest solution size; up to 150 mA of output current VLS201610ET-2R2M 2.2uH TDK For TPS65720, TPS65721 GLFR1608T2R2M-LR 2.2uH TDK For TPS65720; Smallest solution size; up to 150 mA of output current MIPSA2520 2.2uH FDK For TPS65721; highest efficiency Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the step-down converter allows the use of small ceramic capacitors with a typical value of 10μF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended. For an inductor value of 3.3μH, an output capacitor with 4.7μF can be used. Refer to recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Just for completeness the RMS ripple current is calculated as: Vout 11 Vin ´ IRMSCout = Vout ´ L ´ ¦ 2 ´ 3 (4) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: 44 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 Vout ö 1 Vin ´ æ + ESR ÷ ç L ´ ¦ è 8 ´ Cout ´ ¦ ø 1DVout = Vout ´ (5) Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 4.7μF. The input capacitor can be increased without any limit for better input voltage filtering. Table 2. Tested Capacitors TYPE VALUE VOLTAGE RATING SIZE SUPPLIER MATERIAL GRM155R60G475ME47D GRM155R60J225ME15D 4.7 μF 4V 0402 Murata Ceramic X5R 2.2 μF 6.3 V 0402 Murata Ceramic X5R GRM188R60J475K 4.7 μF 6.3 V 0603 Murata Ceramic X5R GMK107BJ105K 1 μF 35 V 0603 Taiyo Yuden Ceramic X5R CHARGER/POWER PATH Charger Stability In order to ensure stable operation of the charger including the power path, a list of components and their recommended value is given below. Note that these values represent the capacitance or inductance value in the application under the given operating conditions. For example, ceramic capacitors will typically show a drop in capacitance when a dc voltage is applied. Due to this dc bias effect, the capacitance in the applications when voltage is applied is much less than the nominal capacitor value. See the manufacturers data sheet on this. At pin AC, a series inductance of may be used with a values as stated below. Pins AC, SYS and BAT have been tested to be stable with the values given in the table: PIN NAME Cmin (μF) Cmax (μF) Lmin (μH) lmax (μH) AC 0.1 1 0 2 SYS 1 10 – – BAT 0.1 4.7 – – Setting the Charge Current The charge current is set with an external resistor connected form ISET to GND. The resulting charge current is: KSET ICHARGE = R SET RSET = K SET ISET (6) Additionally, the charge current can be scaled to 100%, 75%, 50% or 25% of the value set by Rset by software in register CHCONFIG1 using Bits ICH_SCL[1,0]. Pre-charge current and termination current is scaled accordingly. Dynamic Power Path Management (DPPM) The charger/power path in TPS6572x contains two different features to ensure there is sufficient power at the load and the input voltage supplying the charger/power path does not collapse. First there is output voltage DPPM, which is a control loop to keep the voltage at the output of the power path Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 45 TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com above a certain limit. In TPS6572x, the voltage at the output of the power path (SYS) is regulated to what is defined with VSYS[1,0] in register CHCONFIG0. When the current needed for the load and for charging the battery exceeds the input current limit, the voltage at SYS will collapse. The DPPM loop will reduce the charge current, such that the total current for the load and the charge current equals the input current limit. This is done as soon as the voltage at SYS drops 100mV below the target voltage. Second there is input voltage DPPM. For this, the input voltage to the charger/power path at pin AC is sensed to avoid the voltage from a USB port or dedicated charger to drop below a certain limit. This control loop will reduce the input current limit for pin AC as soon as the voltage at AC drops below 4.5V (typically). With Bits ACinputcurrent[1,0] set to 00 or 01, input voltage DPPM is enabled, with ACinputcurrent=10, input voltage DPPM is disabled. Layout Considerations As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation, and additional stability issues as well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitors should be placed as close as possible to the IC pins as well as the inductor and output capacitor. For TPS65721, connect the PGND pin of the device to the PowerPAD™ land of the PCB and connect the analog ground connection (GND) to the PGND at the PowerPAD™. Keep the common path to the GND pin, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The FB line should be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1 line). See the EVM users guide for details about the layout. 46 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 TPS65720 TPS65721 www.ti.com SLVS979 – OCTOBER 2009 APPLICATION CIRCUITS TPS65720 BAT AC BAT 1uF charger / power path LiIon NTC SYS ISET 3k for a charge current of 150mA 10k TS SYS 4.7uF / 6.3V R5 L1 DCDC 1 200 mA 2.2uH VDCDC 1=2.05 V R1 360 k 4.7uF 22pF FB_DCDC1 R2 150k bluetooth chip VINLDO1 2.2uF LDO1 200 mA VLDO 1 = 1.85V VLDO1 4.7uF / 4V 2 x 3.3k Vin 2 x 100k reset generator / startup logic SYS RESET Reset INT INT HOLD_LDO1 R6 GPIO HOLD_DCDC1 PB_IN ON / OFF SCLK PGND I2C interface SDAT GPIO or 5mA current sink GPIO1 SCLK SDAT GPIO0 AGND GPIO2 GPIO3 to SYS or VDCDC1 depending on LED forward voltage indication LEDs Figure 34. Typical Bluetooth Application Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 47 PACKAGE OPTION ADDENDUM www.ti.com 13-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS65720YFFR ACTIVE DSBGA YFF 25 3000 TBD Call TI Call TI TPS65720YFFT ACTIVE DSBGA YFF 25 250 TBD Call TI Call TI TPS65721RSNR ACTIVE QFN RSN 32 3000 TBD Call TI Call TI TPS65721RSNT ACTIVE QFN RSN 32 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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