E98930G53

6
3
4
2
8
1
7
V1
V2
V3
V4
VL
VM
SUB
SHD 30
SHP 31
GATE
9
10
11
13
12
DECODE
SELECTOR
COUNTER
IRIS/SHUTTER
CK GEN
14
UP/DOWN ADDER
16
VSS1
32
VSS2
GATE
TEST CIRCUIT
25 26 23 24 15 17 18
EIA
IVD
VDD2
43
5
TG/SSG
CBLK
RG 48
CLP1
AVDD 44
CLP2
H2 46
IHD
1/525
1/625
19
VH
BLC
H1 45
1/606
1/910
1/908
RESET
GEN
35 36 27
SYNC
BLCW1
AVSS 47
1/2
HV-PLL SELECTOR
HD
33
BLCW2
CCD 28
VD
EXT
34
HVDET
CVSS
CKI 42
HV-PLL SELECTOR
SYNC
SEP
SYNC
DISCRIMINATION
CIRCUIT
VD
SPDNV/ED2
LCOUT 41
COMP
VD DETECTION
CIRCUIT
EHD/SYNC
38
HD
IRIN/ED1
LCIN 40
37
NO SIGNAL
DETECTION
CIRCUIT
EVD
39
EIA
SPUPV/ED0
V DRIVER
VDD1
Vreg
–2–
CVDD
22
TEST
DECODER
Block Diagram
20 ESHUT2
21 ESHUT1
29 RST
CXD2463R
CXD2463R
HD
VD
EXT
HVDET
VSS2
SHP
SHD
RST
CCD
EIA
CBLK
SYNC
Pin Configuration (Top View)
36
35
34
33
32
31
30
29
28
27
26
25
LCOUT
41
20 ESHUT2
CKI
42
19 VDD1
VDD2
43
18 BLCW2
AVDD
44
17 BLCW1
H1
45
16 VSS1
H2
46
15 BLC
AVSS
47
14 CVSS
RG
48
13 IRIN/ED1
1
2
3
4
5
6
7
8
9
10
11
12
SPDNV/ED2
21 ESHUT1
SPUPV/ED0
40
Vreg
LCIN
CVDD
22 TEST
VL
39
SUB
COMP
V1
23 CLP1
VH
38
V3
EHD/SYNC
V2
24 CLP2
V4
37
VM
EVD
Pin Description
Pin
No.
Symbol
I/O
Description
1
VM
—
Power supply (GND for V driver)
2
V4
O
Pulse output for CCD vertical register drive
3
V2
O
Pulse output for CCD vertical register drive
4
V3
O
Pulse output for CCD vertical register drive
5
VH
—
Power supply (positive power supply for V driver)
6
V1
O
Pulse output for CCD vertical register drive
7
SUB
O
CCD discharge pulse output
8
VL
—
Power supply (negative power supply for V driver)
9
CVDD
—
Power supply (for comparator)
10
Vreg
—
Bias current supply for comparator
11
SPUPV/ED0
I
Shutter speed up reference voltage/shutter speed setting
12
SPDNV/ED2
I
Shutter speed down reference voltage/shutter speed setting
13
IRIN/ED1
I
Iris signal input/shutter speed setting
14
CVSS
—
GND (for comparator)
–3–
CXD2463R
Pin
No.
Symbol
I/O
Description
15
BLC
O
Window pulse output for backlight compensation
16
VSS1
—
GND
17
BLCW1
I
Window select 1 for backlight compensation (with pull-down resistor)
18
BLCW2
I
Window select 2 for backlight compensation (with pull-down resistor)
19
VDD1
20
ESHUT2
I
Sub pulse control (with pull-down resistor)
21
ESHUT1
I
Sub pulse control (with pull-down resistor)
22
TEST
I
Fixed low (with pull-down resistor)
23
CLP1
O
Clamp pulse output
24
CLP2
O
Clamp pulse output
25
SYNC
O
Composite sync output
26
CBLK
O
Composite blanking output
27
EIA
I
Low: EIA, High: CCIR (with pull-down resistor)
28
CCD
I
Low: 510H, High: 760H (with pull-down resistor)
29
RST
I
Reset (low reset). Always input reset pulse after power-on.
30
SHD
O
Data sample-and-hold pulse
31
SHP
O
Precharge level sample-and-hold pulse
32
VSS2
—
GND
33
HVDET
O
Horizontal PLL/Vertical PLL discrimination signal
High: Vertical PLL, Low: Horizontal PLL
34
EXT
O
External sync/internal sync discrimination signal
High: External sync, Low: Internal sync
35
VD
O
Vertical drive output
36
HD
O
Horizontal drive output
37
EVD
I
Vertical drive signal input (with pull-up resistor)
38
EHD/SYNC
I
Horizontal drive signal input/Composite sync input (with pull-up resistor)
39
COMP
O
Comparator output
40
LCIN
I
Inverter input for oscillation
41
LCOUT
O
Inverter output for oscillation
42
CKI
I
2MCK input
43
VDD2
—
Power supply
44
AVDD
—
Power supply (for H1, H2, and RG)
45
H1
O
H1 clock output for CCD horizontal register drive
46
H2
O
H2 clock output for CCD horizontal register drive
47
AVSS
—
GND (for H1, H2, and RG)
48
RG
O
Reset gate pulse output
—
Power supply
–4–
CXD2463R
Electrical Characteristics
(VDD = 5V ± 0.25V, Topr = –20 to +75°C)
1) DC Characteristics
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
5.0
5.25
V
Supply voltage
VDD
4.75
Input voltage 1
(For input pins not listed below)
VIH1
0.7VDD
Input voltage 2
(Pin 29)
VIH2
V
0.3VDD
VIL1
V
V
0.8VDD
VIL2
0.2VDD
V
Input voltage 3
(Pins 11 and 12 in electronic iris
mode)
VIN3
2.0
VDD
V
Input voltage 4
(Pin 13 in electronic iris mode)
VIN4
VSS
VDD
V
VOH1
Output voltage 1
(Pins 15, 23, 24, 25, 26, 33, 34, 35 and 36) VOL1
IOH = –4.0mA
VDD – 0.8
V
IOL = 8.0mA
0.4
Output voltage 2
(Pins 30, 31 and 48)
VOH2
IOH = –6.9mA
VOL2
IOL = 3.0mA
Output voltage 3
(Pins 45 and 46)
VOH3
IOH = –17.4mA
VOL3
IOL = 12.0mA
Output voltage 4
(Pin 39)
VOH4
IOH = –6.0mA
VOL4
IOL = 4.0mA
Output voltage 5
(Pins 2, 3, 4 and 6)
VOH5
IOH = –5.0mA
VOL5
IOL = 10.0mA
Output voltage 6
(Pins 4 and 6 (SG))
VOH6
IOH = –7.2mA
VOL6
IOL = 5.0mA
Output voltage 7
(Pin 7)
VOH7
IOH = –4.0mA
VOL7
IOL = 5.4mA
Feedback resistor 1
(Pin 42)
RFE1
VIN = VDD or VSS
250k
Feedback resistor 2
(Resistor between Pins 40 and 41)
RFE2
VIN = VDD or VSS
Pull-up resistor
RPU
Pull-down resistor
V
V
VDD – 0.8
0.4
V
V
VDD – 0.8
0.4
V
V
VDD – 0.8
0.4
VM – 0.25
V
V
VL + 0.25
VH – 0.25
V
V
VM + 0.25
VH – 0.25
V
V
VL + 0.25
V
1M
2.5M
Ω
250k
1M
2.5M
Ω
VIL = 0V
20k
50k
125k
Ω
RRD
VIH = VDD
20k
50k
125k
Ω
IVM
AVDD = 5V
CVDD = 5V
VDD1 = 5V
VDD2 = 5V
24
mA
IVL
VL = –8.5V
1.9
mA
IVH
VH = 15V
0.8
mA
Current consumption
∗ The typical power consumption is 148mW with the ICX054BL load (in the normal operating state).
–5–
CXD2463R
2) Input/Output Capacitance
Symbol
Item
(VDD = VI = 0V, fM = 1MHz)
Min.
Typ.
Max.
Unit
Input pin capacitance
CIN
9
pF
Output pin capacitance
COUT
11
pF
I/O pin capacitance
CI/O
11
pF
3) Comparator Characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Item
Symbol
Indefinite region
Min.
Typ.
Vf
Max.
Unit
±70
mV
Note 1) Input offset voltage and indefinite region
The input offset voltage and indefinite region (region in which the comparator output is not set to high
or low) shown in the figure below exist in the built-in comparator in this IC, so be careful when
designing the external circuit.
Note 2) Pins 11 and 12 in electronic iris mode
Make sure of Pin 11 (SPUPV) < Pin 12 (SPDNV).
5.0V
70mV
Pins 11 and 12
(SPUPV, SPDNV)
70mV
Indefinite region
GND
4) Power-on Reset Condition
4.75V
VDD
RST
0.2VDD
tWRST
(Within the recommended operating condition)
Item
Power-on reset period
Symbol
tWRST
Min.
Typ.
35
Max.
Unit
ns
–6–
CXD2463R
1. Electronic Iris/Electronic Shutter Function
The electronic iris or electronic shutter can be selected by setting the following pins to different combinations of
high and low.
ESHUT1
Pin 21
ESHUT2
Pin 20
L
L
Electronic iris without limiter
H
L
Electronic iris with limiter EIA: 1/100 (s), CCIR: 1/120 (s)
L
H
Electronic shutter mode
H
H
Sub pulse stopped
Operating Mode
1) Electronic Iris Mode
Symbol
Pin No.
Function
IRIN/ED1
13
Iris signal input
SPDNV/ED2
12
Shutter speed down reference voltage
SPUPV/ED0
11
Shutter speed up reference voltage
2) Electronic Shutter Mode
Symbol
Mode
Pin No.
SPUPV/ED0
11
H
L
H
L
H
L
H
L
IRIN/ED1
13
H
H
L
L
H
H
L
L
SPDNV/ED2
12
H
H
H
H
L
L
L
L
EIA:
1/100
CCIR:
1/120
1/250
1/500
1/1000
1/2000
Shutter speed
–7–
1/5000 1/10000 1/100000
CXD2463R
2. Backlighting Correction Function
The CXD2463R has a function to output the window pulse for backlight compensation.
The backlight compensation pulse is output from BLC (Pin 15) in the following range according to the high/low
combination of BLCW1 (Pin 17) and BLCW2 (Pin 18).
Window Type for Different Pin Combinations
Window type
BLCW1 (Pin 17) BLCW2 (Pin 18)
Full-screen photometry
L
L
Bottom emphasis photometry
H
L
Center emphasis photometry
L
H
Bottom + center emphasis photometry
H
H
Example of Basic Circuit Configuration
+5V
Iris comparator
Iris
window switch
39k
10k
10µ
27 IRIS
13
IRIN/ED1
3.9k
10k
10k
100k
10µ
19 OP+
13 DETOUT
BLC 15
AGC
window switch
10k
1k
100k
CXD2463R
CXA1310AQ
Full-screen photometry
Bottom emphasis photometry
Center emphasis photometry
Bottom + center emphasis photometry
–8–
CXD2463R
1) Window Pulse Timing Charts
• EIA Mode/Vertical Direction Timing
(1) Full-screen photometry
VD
HD
0.5HD
BLC
20HD
20.5HD
(2) Center emphasis photometry
VD
HD
101.5HD
181.5HD
101HD
181HD
BLC
(3) Bottom emphasis photometry
VD
HD
0.5HD
BLC
181HD
181.5HD
–9–
CXD2463R
• EIA Mode/Horizontal Direction Timing
(1) Bottom emphasis photometry and full-screen photometry
HD
MCK
BLC
X1
X2
X1
X2
510H
104MCK
760H
154MCK
510H
3MCK
760H
22MCK
510H
272MCK
760H
407MCK
510H
167MCK
760H
252MCK
(2) Center emphasis photometry
HD
MCK
BLC
X1
X2
X1
X2
– 10 –
CXD2463R
• CCIR Mode/Vertical Direction Timing
(1) Full-screen photometry
VD
HD
0.5HD
BLC
25HD
25.5HD
(2) Center emphasis photometry
VD
HD
121.5HD
216.5HD
121HD
216HD
BLC
(3) Bottom emphasis photometry
VD
HD
0.5HD
BLC
216HD
216.5HD
– 11 –
CXD2463R
• CCIR Mode/Horizontal Direction Timing
(1) Bottom emphasis photometry and full-screen photometry
HD
MCK
BLC
X1
X2
X1
X2
510H
114MCK
760H
169MCK
510H
3MCK
760H
22MCK
510H
279MCK
760H
416MCK
510H
164MCK
760H
246MCK
(2) Center emphasis photometry
HD
MCK
BLC
X1
X2
X1
X2
– 12 –
CXD2463R
3. External Sync Function
The CXD2463R supports the three modes of Line-Lock, VReset + HPLL (VD and HD inputs), and VReset +
HPLL (Sync input) as the external sync functions. Each mode is automatically switched according to the
combination of signals input to EHD/SYNC (Pin 38) and EVD (Pin 37).
1) Automatic External Sync Discrimination
I/O
Symbol
Pin
No.
EHD/SYNC and EVD pins signal input state
and HVDET and EXT pins discrimination results
I
EHD/SYNC
38
HD
No signal
HD
SYNC
No signal
I
EVD
37
No signal
VD
VD
HD after SYNC
separation
No signal
O
HVDET
33
L
H
L
L
L
O
EXT
34
L
H
H
H
L
INT
LL
VReset
+ HPLL
VReset
+ HPLL
INT
Mode
• If unspecified signals are input for the external signals given above, there may be recognition errors.
2) LL (Line-Lock) Mode
When the V sync clock is externally input to EVD (Pin 37), the result of comparing the falling edge of the clock
and the falling edge of the internal VD is output from COMP (Pin 39). The output polarity is compatible with the
active filter.
EXT-VD
(Pin 37)
INT-VD
(Pin 35)
COMP
(Pin 39)
High impedance state
– 13 –
CXD2463R
3) VReset + HPLL (VD and HD Inputs) Mode
When the HD cycle clock is externally input to EHD/SYNC (Pin 38) and the V cycle clock is externally input to
the EVD (Pin 37), the CXD2463R sync signal is output as shown below based on the phase difference
between these signals.
Similar to Line-Lock mode, the result of comparing the phase of the falling edges of the HD cycle clock input to
Pin 38 and the CXD2463R internal HD is output from COMP (Pin 39). The PLL is applied using this signal.
Similar to Line-Lock mode, the polarity of the COMP (Pin 39) output is compatible with the active filter. The
phase of the HD falling edge can be shifted up to ±1/4H with respect to the falling edge of the master VD (EXTVD).
• EIA/ODD
(1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD
(Pin 37 input)
EXT-HD
(Pin 38 input)
VD
(Pin 35 output)
HD
(Pin 36 output)
SYNC
(Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
(3) EXT-VD and EXT-HD have the –1/4H to the same phase.
EXT-VD
EXT-HD
VD
HD
SYNC
– 14 –
CXD2463R
• EIA/EVEN
(1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD
(Pin 37 input)
EXT-HD
(Pin 38 input)
VD
(Pin 35 output)
HD
(Pin 36 output)
SYNC
(Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
(3) EXT-VD and EXT-HD have the same phase to –1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
– 15 –
CXD2463R
• CCIR/ODD
(1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD
(Pin 37 input)
EXT-HD
(Pin 38 input)
VD
(Pin 35 output)
HD
(Pin 36 output)
SYNC
(Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
(3) EXT-VD and EXT-HD have the same phase to –1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
– 16 –
CXD2463R
• CCIR/EVEN
(1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD
(Pin 37 input)
EXT-HD
(Pin 38 input)
VD
(Pin 35 output)
HD
(Pin 36 output)
SYNC
(Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
(3) EXT-VD and EXT-HD have the same phase to –1/4H.
EXT-VD
EXT-HD
VD
HD
SYNC
– 17 –
CXD2463R
4) VReset + HPLL (SYNC Input) Mode
When the specified sync signal is externally input to EHD/SYNC (Pin 38), the EXT-HD separated from this
sync signal is output from HD (Pin 36). This signal is input through the shifter to EVD (Pin 37). At this time, the
CXD2463R sync signal is output as shown below based on the amount by which EXT-HD is shifted. (The
phase can be shifted up to ±1/2H with respect to the falling edge of EXT-HD.)
COMP (Pin 39) outputs the result of comparing the phase of the falling edge of the shifted EXT-HD (signal
input to Pin 37) and the falling edge of the CXD2463R internal HD. The polarity is compatible with the active
filter.
• EIA/ODD
1/2H 1/2H
EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)
(1) Same phase
SFT-HD (1)
(Pin 37 input)
VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)
(2) Delayed phase
SFT-HD (2)
VD
HD
SYNC
(3) Advanced phase
SFT-HD (3)
VD
HD
SYNC
∗ SFT-HD (1) to (3) are the signals after shifting EXT-HD.
– 18 –
CXD2463R
• EIA/EVEN
1/2H 1/2H
EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)
(1) Same phase
SFT-HD (1)
(Pin 37 input)
VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)
(2) Delayed phase
SFT-HD (2)
VD
HD
SYNC
(3) Advanced phase
SFT-HD (3)
VD
HD
SYNC
– 19 –
CXD2463R
• CCIR/ODD
1/2H 1/2H
EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)
(1) Same phase
SFT-HD (1)
(Pin 37 input)
VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)
(2) Delayed phase
SFT-HD (2)
VD
HD
SYNC
(3) Advanced phase
SFT-HD (3)
VD
HD
SYNC
– 20 –
CXD2463R
• CCIR/EVEN
1/2H 1/2H
EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)
(1) Same phase
SFT-HD (1)
(Pin 37 input)
VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)
(2) Delayed phase
SFT-HD (2)
VD
HD
SYNC
(3) Advanced phase
SFT-HD (3)
VD
HD
SYNC
– 21 –
– 22 –
CLP2
CLP1
760H
CCD OUT
510H
CCD OUT
V4
V3
V2
V1
BLK
SYNC
VD
HD
CLP2
CLP1
760H
CCD OUT
510H
CCD OUT
V4
V3
V2
V1
BLK
SYNC
VD
HD
494
493
493
4
2
493
3
4
3
3
1
2
1
3
2
1
2
493
492 494
20H
20H
1
9H
FIELD.E
9H
FIELD.O
492
FIELD.O
492
491
FIELD.E
Timing Generator + Sync Generator Block Timing Chart
Vertical Direction EIA (during 510H/760H CCD drive)
CXD2463R
– 23 –
CLP2
CLP1
510H
CCD OUT
V4
V3
V2
V1
BLK
SYNC
VD
HD
CLP2
CLP1
510H
CCD OUT
V4
V3
V2
V1
BLK
SYNC
VD
HD
583
7.5H
FIELD.O
4
2
583
3
3
1
2
1
25H
25H
582
7.5H
FIELD.O FIELD.E
582
581
FIELD.E
Timing Generator + Sync Generator Block Timing Chart
Vertical Direction CCIR (during 510H CCD drive)
CXD2463R
– 24 –
CLP2
CLP1
760H
CCD OUT
V4
V3
V2
V1
BLK
SYNC
VD
HD
CLP2
CLP1
760H
CCD OUT
V4
V3
V2
V1
BLK
SYNC
VD
HD
7.5H
FIELD.O
2
583
1
1
25H
25H
582
7.5H
FIELD.O FIELD.E
582
581 583
FIELD.E
Timing Generator + Sync Generator Block Timing Chart
Vertical Direction CCIR (during 760H CCD drive)
3
2
CXD2463R
– 25 –
14
14
EQ
VSYNC
VD
14
7
10
HSYNC
SUB
V4
V3
V2
V1
CLP2
CLP1
SHD
SHP
RG
H2
H1
MCK
(Internal clock)
HD/BLK
0
20
23
26
26
32
30
Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction EIA (during 510H CCD drive)
36
38
40
44
50
50
55
56
59
59
62
60
68
72
70
79
80
80
90
94
104
100
110
MCK = 104.88ns
CXD2463R
– 26 –
14
14
EQ
VSYNC
VD
14
7
10
HSYNC
SUB
V4
V3
V2
V1
CLP2
CLP1
SHD
SHP
RG
H2
H1
MCK
(Internal clock)
HD/BLK
0
20
23
30
31
31
37
36
Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction CCIR (during 510H CCD drive)
40
43
49
50
55
59
60
59
60
61
67
73
70
77
80
85
84
90
99
100
110
MCK = 105.61ns
114
CXD2463R
– 27 –
22
VSYNC
VD
22
EQ
20
22
12
10
HSYNC
SUB
V4
V3
V2
V1
CLP2
CLP1
SHD
SHP
RG
H2
H1
MCK
(Internal clock)
HD/BLK
0
30
36
40
40
40
49
50
Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction EIA (during 760H CCD drive)
56
58
60
67
70
76
80
85
85
90
90
94
90
103
100
108
110
119
118
120
130
140
140
154
150
160
MCK = 69.84ns
170
CXD2463R
– 28 –
22
VSYNC
VD
22
EQ
20
22
12
10
HSYNC
SUB
V4
V3
V2
V1
CLP2
CLP1
SHD
SHP
RG
H2
H1
MCK
(Internal clock)
HD/BLK
0
30
36
40
40
40
51
50
Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction CCIR (during 760H CCD drive)
56
62
60
73
70
84
80
90
90
90
95
95
100
106
110
117
122
120
133
132
130
140
154
150
160
170
169
MCK = 70.48ns
CXD2463R
– 29 –
V4
V3
V2
V1
EVEN
V4
V3
V2
V1
ODD
HD
E: 38.38µs
(366CK)
C: 38.65µs
Timing Generator + Sync Generator Block Timing Chart
Charge Readout Timing
Field Accumulation (during 510H CCD drive)
(3CK)
E: 0.32µs
C: 0.32µs
(12CK)
E: 1.26µs
C: 1.27µs
E: 2.51µs
(24CK)
C: 2.53µs
E: 1.99µs
(19CK)
C: 2.00µs
E: 1.57µs
(15CK)
C: 1.58µs
E: EIA 1CK = 104.88ns
C: CCIR 1CK = 105.61ns
CXD2463R
– 30 –
V4
V3
V2
V1
EVEN
V4
V3
V2
V1
ODD
HD
E: 40.56µs
(581CK)
C: 40.95µs
Timing Generator + Sync Generator Block Timing Chart
Charge Readout Timing
Field Accumulation (during 760H CCD drive)
(3CK)
E: 0.21µs
C: 0.21µs
(23CK)
E: 1.61µs
C: 1.62µs
E: 2.51µs
(36CK)
C: 2.54µs
E: 2.51µs
(36CK)
C: 2.54µs
E: 2.51µs
(36CK)
C: 2.54µs
E: EIA 1CK = 69.84ns
C: CCIR 1CK = 70.48ns
CXD2463R
BLK (HD)
HD
– 31 –
VSYNC
EQ
HSYNC
VD (EVEN)
VD (ODD)
BLK (EVEN)
BLK (ODD)
EIA
1.47µs (14CK)
4.72µs (45CK)
2.30µs (22CK)
4.72µs (45CK)
10.90µs (104CK)
6.19µs (59CK)
31.78µs (303CK)
Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 510H CCD drive)
1.47µs (14CK)
1/2H
4.72µs (45CK)
2.30µs (22CK)
1CK = 104.88ns
CXD2463R
BLK (HD)
HD
– 32 –
VSYNC
EQ
HSYNC
VD (EVEN)
VD (ODD)
BLK (EVEN)
BLK (ODD)
CCIR
1.48µs (14CK)
4.75µs (45CK)
2.30µs (22CK)
4.75µs (45CK)
12.04µs (114CK)
6.23µs (59CK)
32.00µs (303CK)
Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 510H CCD drive)
1.48µs (14CK)
1/2H
4.75µs (45CK)
2.30µs (22CK)
1CK = 105.61ns
CXD2463R
BLK (HD)
HD
– 33 –
VSYNC
EQ
HSYNC
VD (EVEN)
VD (ODD)
BLK (EVEN)
BLK (ODD)
EIA
1.54µs (22CK)
4.75µs (68CK)
2.37µs (34CK)
4.75µs (68CK)
10.76µs (154CK)
6.29µs (90CK)
31.78µs (455CK)
Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 760H CCD drive)
1.54µs (22CK)
1/2H
4.75µs (68CK)
2.37µs (34CK)
1CK = 69.84ns
CXD2463R
BLK (HD)
HD
– 34 –
VSYNC
EQ
HSYNC
VD (EVEN)
VD (ODD)
BLK (EVEN)
BLK (ODD)
CCIR
1.55µs (22CK)
4.79µs (68CK)
2.40µs (34CK)
4.79µs (68CK)
11.91µs (169CK)
6.34µs (90CK)
32.00µs (454CK)
Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 760H CCD drive)
1.55µs (22CK)
1/2H
4.79µs (68CK)
2.40µs (34CK)
1CK = 70.48ns
CXD2463R
CXD2463R
High-Speed Phase Timing Chart for the Timing Generator Block
MCK
(Internal clock)
H1
H2
RG
CCD OUT
SHP
SHD
– 35 –
1M
1000p
100k
10k
0.1µ
1M
10k
+5V
RG ADJ
1000p
1p
10p
0.01µ 10k
SYNC IN
• SYNC input external synchronization
• Electronic iris mode
Application Circuit
1
2
3
4
8
9 10 11 12
– 36 –
50k
50k
3.9k
39k
10µ
10k 10k 100k
+14.55 to +15.45V
–9.0 to –8.0V
100
100
VIDEO OUT
CXA1310AQ
CCD OUT
10µ
10k
27
30
25
4 29 21 20 24
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
510H/760H black-and-white CCD
VSUB ADJ
36k
13
48
7
14
47
6
15
46
5
16
17
18
19
45
44
43
42
20
21
40
41
22
23
38
39
24
37
CXD2463R
36 35 34 33 32 31 30 29 28 27 26 25
H shifter
Reset circuit
CXD2463R
CXD2463 R
Pckage Outline
Unit：mm
ASE Assy
Marking
- 39ー
Sony C o 巾orat旧n