CXD2401R Electronic Iris Control IC Description The CXD2401R is an IC which performs electronic iris control by applying a CCD electronic shutter. 48 pin LQFP (Plastic) Features • Electronic iris control drive • Generates system clocks in response to the CXA1390AR series • Generates timing pulses to drive the 510H system CCD image sensor • H driver for CCD (5V direct drive for Type 1/3 CCD) Applications CCD monitoring cameras Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5V • Output voltage VO VSS – 0.5 to VDD + 0.5V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 • Operating temperature Topr –20 to +75 Structure Silicon gate CMOS IC Applicable CCD Image Sensors 510H system SONY CCD • ICX054BK (Type 1/3 NTSC CCD) • ICX055BK (Type 1/3 PAL CCD) V °C GM VDD3 RG H2 H1 VSS3 XSUB XV4 XSG2 XV3 XSG1 XV1 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 VSS4 37 24 XV2 SPUPV 38 23 XDL2 IRIN 39 22 XDL1 SPDNV 40 21 XSP2 Vreg 41 20 XSP1 VDD4 42 19 XSHP ENB 43 18 VSS2 IRENB 44 17 XSHD PS 45 16 VDD2 LIMIT1 46 15 CLP2 LIMIT2 47 14 BFG NTSC 48 13 ID 4 5 6 7 8 9 OSCO CK TEST CL VSS1 VD HD VDD1 10 11 12 PBLK 3 CLP1 2 CLP4 1 OSCI CXD2401R Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94620D9X CXD2401R Pin Description Pin No. Symbol I/O Description 1 OSCI I Inverter input for oscillation. (NTSC: 1820fH, PAL: 1816fH) 2 OSCO O Inverter output for oscillation. (NTSC: 1820fH, PAL: 1816fH) 3 CK I Input for main clock in IC. (NTSC: 1820fH, PAL: 1816fH) 4 TEST I IC test input. Fixed at GND in normal operation. (With pull-down resistor) 5 CL O CK/2 clock output. NTSC: 910fH = 4fsc, PAL: 908fH 6 VSS1 — GND 7 VD I Vertical sync signal input. 8 HD I Horizontal sync signal input. 9 VDD1 — 5V power supply. 10 CLP4 O Clamping pulse for CCD dummy output. 11 CLP1 O Clamping pulse for CCD optical black. 12 PBLK O Cleaning pulse for vertical/horizontal blanking. 13 ID O Vertical direction line identification signal. 14 BFG O Burst flag gate pulse. 15 CLP2 O Clamping pulse in horizontal blanking. 16 VDD2 — 5V power supply. 17 XSHD O CCD data level sample-and-hold pulse output. 18 VSS2 — GND 19 XSHP O CCD precharge level sample-and-hold pulse output. 20 XSP1 O Color separation sample-and-hold pulse output. 21 XSP2 O Color separation sample-and-hold pulse output. 22 XDL1 O Clock output for CCD DL (Delay Line). 23 XDL2 O Clock output for CCD DL (Delay Line). 24 XV2 O CCD vertical clock output. 25 XV1 O CCD vertical clock output. 26 XSG1 O Clock output for CCD sensor readout. 27 XV3 O CCD vertical clock output. 28 XSG2 O Clock output for CCD sensor readout. 29 XV4 O CCD vertical clock output. 30 XSUB O Clock output for CCD electronic shutter. 31 VSS3 — GND 32 H1 O CCD horizontal clock output. 33 H2 O CCD horizontal clock output. 34 RG O CCD reset gate pulse output. –2– CXD2401R Pin No. Symbol I/O — Description 35 VDD3 36 GM I 37 VSS4 — 38 SPUPV I When set in electronic iris mode: Shutter speedup reference voltage input When set in serial mode of electronic shutter: Strobe input 39 IRIN I When set in electronic iris mode: Iris signal input When set in serial mode of electronic shutter: Clock input 40 SPDNV I When set in electronic iris mode: Shutter speed-down reference voltage input When set in serial mode of electronic shutter: Data input 41 Vreg — Current source for comparator. Connected to 5V power supply via 33kΩ resistor. 42 VDD4 — 5V power supply. 43 ENB I Generation/halt switching of electronic shutter pulse (Pin 30). (With pull-up resistor) 44 IRENB I Electronic iris/electronic shutter switching. (With pull-up resistor) 45 PS I Parallel/serial input switching of electronic shutter speed data. (With pull-up resistor) 46 LIMIT1 I Selecting limit value of max. shutter speed. (With pull-down resistor) 47 LIMIT2 I Selecting limit value of max. shutter speed. (With pull-down resistor) 48 NTSC I NTSC/PAL switching. (With pull-down resistor) 5V power supply. Used for GND connection. GND Electrical Characteristics DC Characteristics Item (Within recommended operating range) Pin No. Min. Typ. Max. Unit VDD 4.75 5.0 5.25 V Input voltage 1 38, 40 (Electronic iris mode) VIN1 1.9 VDD V Input voltage 2 39 (Electronic iris mode) VIN2 VSS VDD V Input voltage 3∗ 4, 7, 8, 36, 38, 39, 40, 43, 44, 45, 46, 47, 48 (Pins 38, 39 and 40 are when set in electronic shutter mode) VIH3 0.7VDD Supply voltage 1 9, 16, 35, 42 Output voltage 1 5, 10, 11 Output voltage 2 15, 17, 19, 20, 21, 22, 23, 34 Output voltage 3 32, 33 Symbol Conditions V VIL3 0.3VDD VOH1 IOH = –4mA VOL1 IOL = 8mA VOH2 IOH = –8mA VOL2 IOL = 8mA VOH3 IOH = –20mA VOL3 IOL = 20mA VDD – 0.8 VDD – 0.8 VDD – 0.8 IOH = –2mA VOL4 IOL = 4mA Pull-up resistance value 43, 44, 45 RPU VIL = 0V 25 Pull-down resistance value 4, 36, 46, 47, 48 RPD VIH = VDD 25 –3– V V 0.4 VOH4 V V 0.4 12, 13, 14, 24, 25, 26, 27, 28, 29, 30 ∗ Pins 7 and 8 do not have a protective diode at the power supply side. V 0.4 Output voltage 4 V VDD – 0.8 V V 0.4 V 50 75 kΩ 50 75 kΩ CXD2401R Comparator Characteristics Item (Within recommended operating range) Pin No. Symbol Input offset voltage Vos Response Rise time Fall tpd + tpd – Current consumption 38, 39, 40 Conditions Min. Response time when a step input of 100mV amplitude/ 5mV overdrive is applied. Typ. Max. Unit 1.1 50 mV 140 ns 190 ns IDD 98 In-phase input voltage range VICR 1.9 to 5 Indefinite region Vf 140 µA V ±10 mW Bias current source for comparator. Pin No.: 41. Connected to power supply via 33kΩ resistor. Note) 1. Input offset voltage and indefinite region Input offset voltage and indefintie region are existed in the comparator which builds in this IC as shown right figure. Note that this when designing external circuit. 2. Pins 40 and 38 for electronic iris mode Use it in this state of Pin 40 (SPDNV) > Pin 38 (SPUPV). 5.0V Indefinite region 50mV Input offset voltage 50mV Input offset voltage Indefinite region GND Oscillating Inverter I/O Characteristics Item Pin No. 1 Input voltage Feedback resistor (Within recommended operating range) Conditions Typ. 2 1 to 2 VIH V 0.3VDD VOH IOH = –12mA VOL IOL = 12mA RFE VIN = VDD or Vss VDD/2 250k Symbol Conditions 3 V 2.5M Ω 30 MHz Min. Typ. Max. VDD/2 VIH Input voltage 1M VDD/2 (Within recommended operating range) LVth Logical Vth V V 20 Duty Control Inverter Input Characteristics Unit V 0.7VDD f Pin No. Max. VDD/2 VIL Oscillator frequency Item Min. LVth Logical Vth Output voltage Symbol 10mV 10mV Pins 40 and 38 (SPDNV and SPUPV) 10mV 10mV V 0.7VDD V VIL 0.3VDD Input amplification VIN fmax = 50MHz sine wave Feedback resistor RFE VIN = VDD or Vss 0.5 250k Unit V Vpp 1M 2.5M Ω Note) The input voltage is the input voltage characteristics for an external direct power input, and input amplification is the input amplification characteristics for input through capacitor. –4– CXD2401R Electrical Characteristics AC Characteristics 1) AC characteristics among serial communication clocks (SPDNV (ED2), IRIN (ED1), SPUPV (ED0)) 0.7VDD 0.3VDD SPDNV (ED2) 0.7VDD 0.7VDD IRIN (ED1) ts2 SPUPV (ED0) th2 0.7VDD 0.3VDD tw0 ts1 ts0 (Within recommended operating range) Definition Symbol ts2 th2 Min. SPDNV (ED2) set-up time, activated by the rising edge of IRIN (ED1) 20ns SPDNV (ED2) hold time, activated by the rising edge of IRIN (ED1) 20ns ts1 IRIN (ED1) rising set-up time, activated by the rising edge of SPUPV (ED0) 20ns tw0 SPUPV (ED0) pulse width 20ns ts0 SPUPV (ED0) rising set-up time, activated by the rising edge of IRIN (ED1) 20ns Typ. Max. 50µs 2) Microcomputer communication clock → IC take-in characteristics Example: NTSC/ODD field VD HD XSG1 Magnification HD 0.3VDD 0.3VDD XSG1 NTSC mode: 63.5µs, PAL mode: 63.9µs SEN logic level is to be High for this period. Note) During the 1H period for generating XSG1, the phase against AVD differs according to each mode. Please always maintain the SEN logic level at High for "the 1H period when XSG1 varies." –5– CXD2401R 3) HD/VD take-in characteristics HD VD 0.3VDD 0.3VDD 0.7VDD CL ts4 th4 (Within recommended operating range, Load capacity of CL = 30pF) Symbol ts4 th4 Definition Min. Typ. Max. Unit HD/VD set-up time, activated by CL 5 ns HD/VD hold time, activated by CL 7 ns 4) Phase discrimination characteristics by VD/HD input NTSC: ODD field PAL: EVEN field VD NTSC: EVEN field PAL: ODD field VD 0.3VDD 0.3VDD tpd2 tpd2 HD HD When the HD logic level is Low tpd2 after VD falls, the phase is discriminated as an ODD field (NTSC). When the HD logic level is High tpd2 after VD falls, the phase is discriminated as an EVEN field (NTSC). (Within recommended operating range) Symbol tpd2 Definition Min. Field discriminating clock phase, activated by the falling edge of VD –6– 700 Typ. Max. Unit 1000 ns CXD2401R 5) Phase characteristics of H1, RG, XSHP, XSHD, XSP1, XSP2, XDL1, XDL2, and CL tCK Vpp/2 CK H1 tpd3 tpd5 0.7VDD tpd4 0.3VDD tpd6 RG 0.7VDD 0.3VDD tpd8 0.7VDD tpd7 XSHP tpd10 tpd9 0.3VDD XSHD XSP1 XSP2 tpd11 tpd12 0.7VDD 0.3VDD 0.7VDD tpd13 0.3VDD tpd14 0.7VDD tpd16 tpd15 0.3VDD XDL1 0.7VDD 0.3VDD XDL2 tpd17 0.7VDD tpd18 0.3VDD tpd20 CL tpd19 0.3VDD 0.7VDD (Within recommended operating range) CK-duty = within 50 ± 4%, Load capacity of H1 = 150pF, Load capacity of CL = 30pF, Load capacity of RG, XSHP, XSHD, XSP1, XSP2, XDL1, and XDL2 = 10pF Symbol tCK tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 tpd15 tpd16 tpd17 tpd18 tpd19 tpd20 Definition Min. Typ. Max. 35 CK cycle Unit ns H1 falling delay, activated by the falling edge of CK 16.22 29 56.9 ns H1 rising delay, activated by the rising edge of CK 17.25 31 60.38 ns RG falling delay, activated by the falling edge of CK 20.18 36 70.58 ns RG rising delay, activated by the rising edge of CK 18.61 33 65.32 ns XSHP falling delay, activated by the rising edge of CK 15.86 28 55.59 ns XSHP rising delay, activated by the falling edge of CK 15.76 28 55.32 ns XSHD falling delay, activated by the falling edge of CK 14.92 27 52.26 ns XSHD rising delay, activated by the rising edge of CK 14.76 26 51.62 ns XSP1 falling delay, activated by the rising edge of CK 14.79 26 51.74 ns XSP1 rising delay, activated by the rising edge of CK 15.05 27 52.58 ns XSP2 falling delay, activated by the rising edge of CK 15.09 27 52.82 ns XSP2 rising delay, activated by the rising edge of CK 15.29 27 53.54 ns XDL1 rising delay, activated by the rising edge of CK 14.49 26 50.79 ns XDL1 falling delay, activated by the falling edge of CK 15.05 27 52.67 ns XDL2 rising delay, activated by the rising edge of CK 14.46 26 50.65 ns XDL2 falling delay, activated by the falling edge of CK 14.92 27 52.47 ns CL falling delay, activated by the falling edge of CK 15.33 27 53.01 ns CL rising delay, activated by the falling edge of CK 14.71 26 51.58 ns –7– CXD2401R 6) Waveform characteristics of H1 and RG 0.9VDD H1 0.1VDD trH1 tfH1 0.9VDD RG 0.1VDD tfRG trRG VDD = 5.0V, Topr = 25°C, Load capacity of H1 = 150pF, Load capacity of RG = 10pF Definition Symbol trH1 tfH1 trRG tfRG Min. Typ. Max. Unit H1 rise time 7 ns H1 fall time 7 ns RG rise time 3 ns RG fall time 3 ns I/O Pin Capacitances Item Symbol Min. Typ. Max. Unit Input pin capacitance CIN 9 pF Output pin capacitance COUT 11 pF I/O pin capacitance CI/O 11 pF –8– CXD2401R Description of Operation The operations of the CXD2401R are described below. Control pin Detailed description NTSC (Pin 48) Low: The CXD2401R performs control drive in accordance with NTSC. In this case, the CXD2401R operates by assuming the signals input to Pin 7 (VD) and Pin 8 (HD) are NTSC sync signals. High: The CXD2401R performs control drive in accordance with PAL. In this case, the CXD2401R operates by assuming the signals input to Pin 7 (VD) and Pin 8 (HD) are PAL sync signals. Refer to the "Timing Chart" for the control drive pulse for either NTSC or PAL. ENB (Pin 43) Low: Pin 30 (XSUB) is always High. That is, the electronic iris and electronic shutter to which XSUB pulses are applied suspend operation (electronic iris and electronic shutter OFF). High: Pin 30 (XSUB) outputs control pulses for the electronic iris and electronic shutter. (electronic iris and electronic shutter ON). IRENB (Pin 44) Low: Realizes the electronic shutter control. High: Realizes the electronic iris control. The control pins (SPUPV, IRIN, and SPDNV) are used in common for both electronic shutter control and electronic iris control. The operations of these pins differ depending on the state of IRENB pin. PS (Pin 45) This pin is valid when the operation of electronic shutter is assigned (IRENB = Low). Low: Electronic shutter speed can be controlled by inputting serial data into SPUPV, IRIN, and SPDNV pins. High: Electronic shutter speed can be controlled by inputting parallel data into SPUPV, IRIN, and SPDNV pins. Note) The PS pin is invalid when IRENB = High, and the CXD2401R does not accept data, whether PS is Low or High. –9– CXD2401R Control pin Detailed description The operations of SPUPV, IRIN, and SPDNV pins differ according to the mode (IRENB control) of the electronic iris and electronic shutter. The operations are described below for each case. IRENB = Low: When the operation of electronic shutter is assigned SPUPV : Strobe input pin IRIN : Clock input pin SPDNV : Data input pin PS = Low: When inputting serial data is assigned SPUPV (Pin 38) IRIN (Pin 39) SPDNV (Pin 40) SPDNV (ED2) D7 D6 D5 D4 D3 D2 D1 D0 IRIN (ED1) SPUPV (ED0) MSB Ld : Shutter speed data Ex.: Ld = 100 [decimal] LSB D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 1 0 0 <Shutter speed calculation formula> Shutter speed = 1/n [s] PAL: NTSC (Pin 48) = H NTSC: NTSC (Pin 48) = L Ld (decimal) Ld (decimal) n = 1/m × 106 n = 1/m × 106 m m 255 to 248 [261 – {(255 – Ld) × 7 + 2}] × 63.56 + 31 255 to 251 [311 – {(255 – Ld) × 10 + 2}] × 64 + 30.77 247 to 241 [261 – {(247 – Ld) × 5 + 58}] × 63.56 + 31 250 to 243 [311 – {(250 – Ld) × 7 + 52}] × 64 + 30.77 240 to 232 [261 – {(240 – Ld0 × 4 + 93}] × 63.56 + 31 242 to 236 [311 – {(242 – Ld) × 5 + 108}] × 64 + 30.77 231 to 220 [261 – {(231 – Ld) × 3 + 129}] × 63.56 + 31 235 to 227 [311 – {(235 – Ld) × 4 + 143}] × 64 + 30.77 219 to 202 [261 – {(219 – Ld) × 2 + 165}] × 63.56 + 31 226 to 215 [311 – {(226 – Ld) × 3 + 179}] × 64 + 30.77 201 to 151 [261 – {(201 – Ld) × 1 + 201}] × 63.56 + 31 214 to 197 [311 – {(214 – Ld) × 2 + 215}] × 64 + 30.77 150 to 114 [875 – {(150 – Ld) × 11 + 253}] × 0.978 + 0.047 196 to 146 [311 – {(196 – Ld) × 1 + 251}] × 64 + 30.77 113 to 107 [875 – {(113 – Ld) × 5 + 660}] × 0.978 + 0.047 145 to 109 [923 – {(145 – Ld) × 11 + 303}] × 0.987 + 0.721 106 to 98 [875 – {(106 – Ld) × 4 + 695}] × 0.978 + 0.047 108 to 102 [923 – {(108 – Ld) × 5 + 710}] × 0.987 + 0.721 97 to 86 [875 – {(97 – Ld) × 3 + 731}] × 0.978 + 0.047 101 to 93 [923 – {(101 – Ld) × 4 + 745}] × 0.987 + 0.721 85 to 69 [875 – {(85 – Ld) × 2 + 767}] × 0.978 + 0.047 92 to 81 [923 – {(92 – Ld) × 3 + 781}] × 0.987 + 0.721 68 to 0 [875 – {(68 – Ld) × 1 + 801}] × 0.978 + 0.047 80 to 64 [923 – {(80 – Ld) × 2 + 817}] × 0.987 + 0.721 63 to 0 [923 – {(63 – Ld) × 1 + 851}] × 0.987 + 0.721 – 10 – CXD2401R Control pin Detailed description IRENB = Low: When the operation of electronic shutter is assigned PS = High: When inputting parallel data is assigned Shutter Speed Compatibility Chart SPUPV (Pin 38) IRIN (Pin 39) SPDNV (40Pin) Shutter speed (s) SPUPV IRIN SPDNV H H H 1/100 1/120 L H H 1/250 1/250 H L H 1/500 1/500 L L H 1/1000 1/1000 H H L 1/2000 1/2000 L H L 1/5000 1/5000 H L L 1/10000 1/10000 L L L 1/100000 1/110000 NTSC(Pin 48) = L NTSC(Pin 48) = H IRENB = High: When the operation of electronic iris is assigned AAA AAA AAA AAA CXD2401R Comp1 SPDNV Shutter Speed Cont IRIN DECODE Comp2 SPUPV Comp 1 Truth Table DECODE Truth Table SPDNV IRIN Comp1 Comp1 Comp2 Shutter Speed Cont L H H L L Shutter speed; Faster H L L L H Shutter speed; Hold H L Shutter speed; Hold H H Shutter speed; Slower Comp 2 Truth Table IRIN SPUPV Comp2 L H L H L H In the electronic iris control operation, the electronic shutter speed is controlled according to the logic above. The variations of shutter speed by each control are the same as those shown in <Shutter speed calculation formula> for "electronic shutter; inputting serial data". – 11 – CXD2401R Control pin Detailed description LIMIT1 and LIMIT2 pins function only when IRENB = High (when the operation of electronic iris is assigned). (Inputs from LIMIT1 and LIMIT2 are not accepted when IRENB = Low: when the operation of electronic shutter is assigned.) Maximum Electronic Shutter Speed LIMIT1 (Pin 46) LIMIT2 (Pin 47) Max. shutter speed (s) LIMIT1 LIMIT2 L L 1/200 1/200 Reduces flickers caused by an indoor fluorescent lamp. L H 1/2000 1/2000 Intermediate mode between indoor and outdoor applications. H L 1/20000 1/20000 Reduces CCD smear outdoors. H H 1/90000 1/100000 Secures dynamic range of iris. NTSC (Pin 48) = L NTSC (Pin 48) = H Purpose Electronic iris control of the CXD2401R is realized by applying functions of the electronic shutter. The electronic shutter has a dynamic range from 1/60s when Pin 48 (NTSC) = Low or from 1/50s when Pin 48 (NTSC) = High up to the maximum shutter speed in the table above. Select one of the four dynamic ranges of the electronic iris, according to the application conditions of the CXD2401R. The dynamic range is also determined by also taking into consideration the influence of the electronic shutter on image quality, as shown in the table above. – 12 – – 13 – BFG CLP4 CLP2 CLP1 PBLK CCD XV4 XV3 XV2 XV1 ID XSG2 XSG1 HD BLK/VD FLD 491 492 NTSC Vertical Direction Timing Chart 2 4 6 1 3 5 7 491 490 492 2 4 6 8 1 3 5 7 CXD2401R – 14 – BFG CLP4 CLP2 CLP1 PBLK CCD XV4 XV3 XV2 XV1 ID XSG2 XSG1 HD BLK/VD FLD 581 582 PAL Vertical Direction Timing Chart 2 4 6 8 1 3 5 7 9 582 2 4 6 8 10 1 3 5 7 9 CXD2401R – 15 – BFG ID PBLK CLP4 CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 XDL2 XDL1 XSP2 XSP1 XSHD XSHP RG H1 CL BLK/HD 2 8 NTSC Horizontal Direction Timing Chart 18 18 21 24 27 33 39 45 50 51 56 57 67 75 89 94 64 94 94 BLK HD 63 102 (63) CXD2401R – 16 – BFG ID PBLK CLP4 CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 XDL2 XDL1 XSP2 XSP1 XSHD XSHP RG H1 CL BLK/HD 2 8 PAL Horizontal Direction Timing Chart 18 23 24 26 32 38 44 55 50 56 61 62 69 72 80 94 103 103 103 BLK HD 68 112 (64) CXD2401R EVEN FIELD ODD – 17 – XSG2 XSG1 XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 HD H1 Readout Timing Chart 1 2 3 4 10 289 290 [285] [286] 3 24 14 24 19 1 clock: 104.76ns (NTSC) 105.73ns (PAL) Unit: Number of clocks (common to NTSC and PAL) Numerals in brackets are for PAL. CXD2401R – 18 – XDL2 XDL1 XSP2 XSP1 XSHD XSHP RG H2 H1 CL CK HD 1 2 NTSC High-speed Phase Timing Chart 3 Reset phase 93 112 Start of H1 and H2 CXD2401R – 19 – XDL2 XDL1 XSP2 XSP1 XSHD XSHP RG H2 H1 CL CK HD 1 2 PAL High-speed Phase Timing Chart 3 100 Rset phase AA AA AA AA 118 Start of H1 and H2 CXD2401R CXD2401R AAAAAAA AAAAAAA AAAAAAAAAAAAA AAAAA AAA AAAAAA AAAA AAAAA AAA AAAAAA AAAA AAAAA AAA AAAAAA AAAA AAAAA AAA Application Circuit ICX055AK ICX054AK CXL1518N IRIS GC = 4.1V IRIS LEVEL = 3.0V DET LEVEL = 5.0V ICX027CK ICX026CK CXA1391R/Q CXA1390AQ/AR CCD CXA1392R/Q XDL2 XDL1 CLP2 XSP2 CLP1 PBLK XSHP 3.9K XV2, XV3, XV4 XSG1, XSG2 XSHD XSP1 CXD1267N BFG XV1 ID CLP4 AAA AA A A A AAAAA A A AA A AAAAAA A AAAAAA AAAAAAAA AAAAAA A AAAA A AAAA A H1 CXD2401R H2 RG 30P OSCI IRIS/SHUTTER CK GEN OSCO Timing Generator 1000P WND CXD1159Q CK COUNTER D CL VD SELECTOR HD SUBTRACTION AA AA AA AA AA AA AA AA AA AAA GATE CK 27P XSUB SELECTOR DECODE DECODE ED2 ED1 UP/DOWN ADDER ENB IRENB PS ED0 NTSC VSS4 VSS3 6.8K 3.9K 33µ/16V AA AA AAA A LIMIT1 LIMIT2 2.3V 2.2K 33K IRIN SPUPV SPDNV Vreg VSS2 VSS1 GM VDD1 VDD2 VDD3 VDD4 2.8V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 20 – CXD2401R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 25 A 13 48 (0.22) 0.5 ± 0.2 (8.0) 24 37 12 1 + 0.05 0.127 – 0.02 0.5 ± 0.08 + 0.2 1.5 – 0.1 + 0.08 0.18 – 0.03 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 21 –