SP10T High Linearity Switch with MIPI I/F for Qualcomm chipset CXM3632ER Description The CXM3632ER is SP10T middle power switch for wireless communication system. The CXM3632ER has a 1.8 V CMOS compatible decoder with MIPI function for Qualcomm chipset. The SONY GaAs junction gate pHEMT(JPHEMT) MMIC process is used for low insertion loss and high linearity. Features ◆Low Insertion loss : 0.38 dB(typ.) at GSM Low Band, UMTS BAND 5 0.46 dB(typ.) at GSM High Band, UMTS BAND 1 ◆Low Voltage Operation : VDD = 2.5 V ◆No DC Blocking Capacitors (except sourcing DC bias) ◆Supports CMOS control for serial interface(MIPI I/F for Qualcomm chipset) ◆Small package Size : VQFN-20pin (2.4 mm × 2.4 mm × 0.725 mm Typ.) ◆Lead-Free and RoHS compliant Structure GaAs Junction Gate pHEMT(JPHEMT) MMIC switch, CMOS decoder This IC is ESD sensitive device. Special handling precautions are required. 1 CXM3632ER Block Diagram of SP10T Diversity Switch with MIPI 2 CXM3632ER Block Diagram of SP10T Switch ANT F22 F9 F1 F20 F19 F2 F11 F12 RF10 F18 F17 F10 RF9 F16 F8 RF7 RF3 F7 RF6 F15 F14 RF2 RF1 F13 F6 F5 RF5 F4 RF4 F3 F23 RF8 F21 Truth Table D3 D2 D1 D0 ANT - RF1 ON Path 0 0 1 0 OFF OFF ON OFF OFF OFF OFF OFF OFF OFF ON F1 F2 F3 F4 F5 F6 F7 F8 F9 ON OFF ON ON ON ON ON ON ON ON OFF OFF ANT - RF2 1 0 1 0 OFF OFF OFF ON OFF OFF OFF OFF OFF OFF ON ON ON OFF ON ON ON ON ON ON ON OFF OFF ANT - RF3 1 1 1 0 OFF OFF OFF OFF ON OFF OFF OFF OFF OFF ON ON ON ON OFF ON ON ON ON ON ON OFF OFF ANT - RF4 1 0 1 1 OFF OFF OFF OFF OFF ON OFF OFF OFF OFF ON ON ON ON ON OFF ON ON ON ON OFF ON OFF ANT - RF5 0 0 0 1 OFF OFF OFF OFF OFF OFF ON OFF OFF OFF ON ON ON ON ON ON OFF ON ON ON OFF ON OFF ANT - RF6 1 0 0 1 OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON ON ON ON ON OFF ON ON OFF ON OFF ANT - RF7 0 1 1 0 OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON ON ON ON ON ON ON ON OFF ON OFF OFF ON ANT - RF8 0 1 0 0 OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON OFF OFF OFF ON ANT - RF9 1 1 0 0 ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON OFF OFF ON ANT - RF10 1 0 0 0 OFF ON OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON ON ON ON ON ON ON ON OFF OFF ON Isolation 0 0 0 0 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON OFF OFF OFF 3 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 ON ON ON CXM3632ER Pin Configuration VQFN-20P PKG (2.4mm × 2.4mm × 0.775mm Max.) Top View Absolute Maximum Ratings ◆ Supply voltage VDD ◆ Control voltage for MIPI VIO, SDATA, SCLK ◆ Maximum input 6 V (Ta = 25 °C) 2.5 V (Ta = 25 °C) 32 dBm (Ta = 25 °C) ◆ Operating temperature Topr –35 to +90 °C ◆ Storage temperature Tstg –65 to +150 °C 4 CXM3632ER Electrical Characteristics (VDD = 2.5 V, Ta = 25 ℃) Param eter Insertion Loss Sym bol IL Path ANT-RF1 ANT-RF2 ANT-RF3 ANT-RF4 ANT-RF5 ANT-RF6 ANT-RF7 ANT-RF8 ANT-RF9 ANT-RF10 VSWR Harmonics VSWR 2fo All ports in active paths ANT-RF1 -10 Input IP3 IMD2 ANT-RF1 -10 Control Current Ic Idd Supply Current Ivio Max. 0.44 0.56 *3,*4,*7 - 0.49 0.64 *5 - 0.52 0.67 *1,*2,*6 - 0.44 0.56 *3,*4,*7 - 0.50 0.65 *5 - 0.54 0.69 *1,*2,*6 - 0.43 0.55 *3,*4,*7 - 0.49 0.64 *5 - 0.53 0.68 *1,*2,*6 - 0.38 0.50 *3,*4,*7 - 0.46 0.61 *5 - 0.56 0.71 *1,*2,*6 - 0.38 0.50 *3,*4,*7 - 0.46 0.61 *5 - 0.57 0.72 *1,*2,*6 - 0.40 0.52 *3,*4,*7 - 0.47 0.62 *5 - 0.56 0.71 *1,*2,*6 - 0.42 0.54 *3,*4,*7 - 0.50 0.65 *5 - 0.61 0.76 *1,*2,*6 - 0.42 0.54 *3,*4,*7 - 0.50 0.65 *5 - 0.58 0.73 *1,*2,*6 - 0.42 0.54 *3,*4,*7 - 0.52 0.67 *5 - 0.62 0.77 *1,*2,*6 - 0.43 0.55 *3,*4,*7 - 0.50 0.65 *5 - 0.59 0.74 600 to 2170 MHz - 1.2 - 2500 to 2700 MHz - 1.4 - - - -40 - - -40 Unit dB dBm *8,*9,*10,*13,*14,*17,*18 - - -105 - - -105 *8,*21 65 70 - *8,*22 65 70 - 50% Ctl to 90% RF - 3 5 µs SDATA,SCLK Vc = 1.8 V - 2.5 10 µA Active Mode V DD = 2.8 V - 230 400 µA Idle Mode V DD = 2.8 V - - 10 µA Active w rite Vio = 1.8 V - 200 400 µA Idle Mode Vio = 1.8 V - - 10 µA IIP3 Ts Typ. - *8,*11,*12,*15,*16,*19,*20 IMD3 Sw itching Speed Min. *1,*2,*6 *2,*3,*5 3fo Inter Modulation Distortion in Rx Band Condition Electrical characteristics are measured with all RF ports terminated in 50 . 5 dBm dBm CXM3632ER (VDD = 2.5 V, Ta = 25 ℃) Param eter Isolation Sym bol ISO. Condition Min. Typ. Max. ANT – RF1 (Active Ports RF4/5/6/7/8/9/10) Path *1,*2,*6 40 45 - *3,*4,*7 28 33 - *5 26 31 - ANT – RF2 (Active Ports RF4/5/6/7/8/9/10) *1,*2,*6 36 41 - *3,*4,*7 27 32 - *5 25 30 - ANT – RF3 (Active Ports RF4/5/6/7/8/9/10) *1,*2,*6 26 31 - *3,*4,*7 22 25 - *5 21 24 - ANT – RF4 (Active Ports RF1/2/3/7/8/9/10) *1,*2,*6 27 32 - *3,*4,*7 22 25 - *5 21 24 - ANT – RF5 (Active Ports RF1/2/3/7/8/9/10) *1,*2,*6 31 36 - *3,*4,*7 24 27 - *5 21 24 - ANT – RF6 (Active Ports RF1/2/3/7/8/9/10) *1,*2,*6 28 33 - *3,*4,*7 21 24 - *5 19 22 - ANT – RF7 (Active Ports RF1/2/3/4/5/6) *1,*2,*6 25 30 - *3,*4,*7 21 24 - *5 20 23 - ANT – RF8 (Active Ports RF1/2/3/4/5/6) *1,*2,*6 33 38 - *3,*4,*7 27 32 - *5 25 30 - ANT – RF9 (Active Ports RF1/2/3/4/5/6) *1,*2,*6 40 45 - *3,*4,*7 31 36 - *5 28 33 - ANT – RF10 (Active Ports RF1/2/3/4/5/6) *1,*2,*6 42 47 - *3,*4,*7 31 36 - *5 28 33 - Electrical characteristics are measured with all RF ports terminated in 50 . 6 Unit dB CXM3632ER ANT to RF Isolation Matrix Active Condition Isolation (dB) Min. RF1 *1,*2,*6 RF1 *3,*4,*7 N/A *5 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF9 RF10 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF9 RF10 24 34 38 32 34 38 42 46 48 19 26 27 25 26 30 33 35 35 18 26 26 22 26 28 31 33 33 25 36 32 34 38 41 45 48 22 26 24 26 30 33 35 35 20 25 22 26 28 31 33 33 27 34 34 38 41 45 47 22 24 27 30 33 35 35 21 21 26 28 31 33 33 30 33 38 41 44 45 22 25 30 33 34 34 19 25 27 31 32 32 34 39 42 44 45 25 30 33 34 34 25 28 31 32 32 25 33 40 42 21 27 31 31 20 25 28 28 26 36 38 22 26 26 21 25 25 26 35 22 27 21 24 *1,*2,*6 25 *3,*4,*7 20 *5 19 *1,*2,*6 35 26 *3,*4,*7 25 22 N/A N/A *5 24 21 *1,*2,*6 40 36 26 *3,*4,*7 28 27 22 N/A *5 26 25 21 *1,*2,*6 42 40 34 26 *3,*4,*7 30 30 27 22 *5 28 27 27 20 *1,*2,*6 44 42 40 34 31 *3,*4,*7 33 33 31 26 25 N/A N/A *5 30 30 29 26 22 *1,*2,*6 45 42 39 35 32 28 *3,*4,*7 35 34 31 28 26 21 N/A *5 32 32 29 26 24 19 *1,*2,*6 45 43 39 35 31 35 27 *3,*4,*7 35 34 31 28 26 25 22 *5 33 32 29 26 24 22 21 *1,*2,*6 46 43 39 35 31 34 36 25 *3,*4,*7 35 34 31 28 26 25 25 21 *5 33 32 29 26 24 23 25 21 *1,*2,*6 48 44 39 35 31 34 38 33 24 *3,*4,*7 35 34 31 28 26 26 26 26 19 *5 33 32 29 26 24 24 26 26 18 Electrical characteristics are measured with all RF ports terminated in 50 . * 1 Pin = 25 dBm, 704 to 787MHz (Band13, Band17) * 2 Pin = 26 dBm, 824 to 960MHz (Band5, Band8) * 3 Pin = 26 dBm, 1710 to 1990 MHz (Band1 Tx, Band 2 Tx, Band 3 Tx, Band 4 Tx) * 4 Pin = 10 dBm, 2110 to 2170 MHz (Band1 Rx, Band4 Rx) * 5 Pin = 26 dBm, 2500 to 2690 MHz (Band7) * 6 Pin = 10 dBm, 869 to 960 MHz (GSM850/900 Rx) * 7 Pin = 10 dBm, 1805 to 1990 MHz (GSM1800/1900 Rx) * 8 Measured with the recommended circuit. 7 N/A 25 N/A 20 19 N/A CXM3632ER IMD Condition Band fRx on RF [MHz] fBlocker -15dBm on ANT [MHz] IMD2(fRx - fTx) IMD2(fRx + fTx) IMD3(2fTx - fRx) IMD3(2fTx + fRx) IMD2(fRx - fTx) IMD2(fRx + fTx) IMD3(2fTx - fRx) IMD3(2fTx + fRx) IMD2(fRx - fTx) IMD2(fRx + fTx) IMD3(2fTx - fRx) IMD3(2fTx + fRx) fTx +20dBm on RF [MHz] Band 1 2140 1950 Band 2 1960 1880 Band 5 880 835 IMD Condition 190 4090 1760 6040 80 3840 1800 5720 45 1715 790 2550 *9 *10 *11 *12 *13 *14 *15 *16 *17 *18 *19 *20 IIP3 Condition Band Band 1 Band 5 f1 +27dBm on RF [MHz] 1950 835 f2 +27dBm on RF [MHz] 1951 836 8 IIP3 Condition IIP3=(3*Pout-IMD3) / 2 [dBm] *21 *22 CXM3632ER MIPI Specification Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 2.5 2.8 5.0 V IDD - 230 400 µA IDD - - 10 µA VIO 1.65 1.8 1.95 V 230 400 µA 10 µA Supply current (ACTIVE) *VDD=2.8V Supply current Low Power(disable) *VDD=2.8V Interface Supply Voltage Supply current (ACTIVE) *VIO=1.8V Supply current Low Power(disable) *VIO=1.8V Ivio Ivio Signal level low Vcl 0 - 0.2xVIO V Signal level high Vch 0.8xVIO - VIO V SCLK write Frequency fSCLKw 0.032 19.2 26 MHz SCLK read Frequency fSCLr 0.032 9.6 13 MHz SDATA/SCLK input capacitance Vcl 2 3 pF Data setup time Ts 2 ns Data hold time Th 5 ns Switching Time * Tsw - - 5 µs Turn on Time ** Ton - - 100 µs * Switching Time: Timing for switching from an arbitrary state to the next state. **Turn on time: Time to guarantee RF performance after switch activation. 9 CXM3632ER Explanation of Register Features PM_TRIG with three triggers Software reset and debug using the RFFE_STATUS register Register 0 write Full speed write, half speed read GSID Programmable USID Slave Address : 1010. Register Address Register Name Data Bits Notes Read Write 0x0000 0x001A 0x001B 0x001C 6:0 Antenna sw itch states (see Truth Table) Register 0 Write command sequence use. Trigger Support. W 7:0 Antenna sw itch states (see Truth Table) Read/Write command sequence use. Trigger Support. R/W REGISTER_0 (Table A or B) RFFE_STATUS (Table C) GROUP_ID (Table D) PM_TRIG (Table E) 7 SOFTWARE RESET 6 COMMAND_FRAME_PARITY_ERR 5 COMMAND_LENGTH_ERR 4 ADDRESS_FRAME_PARITY_ERR 3 DATA_FRAME_PARITY_ERR 2 READ_UNUSED_REG 1 WRITE_UNUSED_REG 0 BID_GID_ERR 7:4 RESERVED 3:0 GROUP_SID 7:6 Pow er mode 5:3 Trigger_Mask_[2:0] 2:0 Trigger_[2:0] R/W R/W R/W 0x001D PRODUCT_ID (Table F) 7:0 PRODUCT_ID R 0x001E MANUFACTURER_ID (Table G) 7:0 MANUFACTURER_ID[7:0] R 7:6 SPARE R 0x001F SPARE MANUFACTURER_ID USID (Table H) 5:4 MANUFACTURER_ID[9:8] R 3:0 USID MANUFACTURER_ID[9:0] is defined by SONY ID (0x01B0). 10 R/W CXM3632ER Write and Read Command sequence REGISTER_0 Write command sequence SCLK SDATA SSC SA3 SA2 SA1 SA0 1 D6 D5 D4 D3 D2 D1 D0 Slave Address P 0 Parity Bit Bus Park Write command sequence SCLK SDATA SSC SA3 SA2 SA1 SA0 0 Slave Address 1 0 A4 Write Command A3 A2 A1 A0 P D7 D6 D5 D4 D3 D2 D1 Parity Bit Register Address D0 P 0 Parity Bit Bus Park Read command sequence Data frame from ANT Switch needs Half Speed function. ① SCLK SDATA SSC SA3 SA2 SA1 SA0 Slave Address SCLK SDATA 0 1 1 A4 Read Command A3 A2 A1 A0 P 0 Parity Bit Register Address Bus Park ① 0 Bus Park D7 D6 D5 D4 D3 D2 Data frame from ANT Sw itch (Read Half Speed) 11 D1 D0 P Bus Park CXM3632ER Register Map Register 0 Write command sequence use. 24 Sta te 1 2 3 4 5 6 7 8 9 10 11 Path RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF9 RF10 Isolation 23 22 21 20 19 18 17 16 15 14 13 12 11 10 A4 A3 A2 A1 A0 Parity Bit P 1/0 0 0 0 0 0 1/0 1 1/0 0 0 0 0 0 1/0 0 1 1/0 0 0 0 0 0 1/0 0 0 1 1/0 0 0 0 0 0 1/0 0 0 1 1/0 0 0 0 0 0 1/0 1 0 0 1 1/0 0 0 0 0 0 1/0 0 1 0 0 1 1/0 0 0 0 0 0 1/0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 21 20 19 18 17 16 15 14 13 12 11 10 Slave Address Write/ Read Com m and Write:010 Read:011 C2 C1 C0 SSC - - - SA3 SA2 SA1 SA0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 1 Register Address Read/Write command sequence use. 24 Sta te 1 2 3 4 5 6 7 8 9 10 11 Path RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF9 RF10 Isolation Sta te Path 1 2 3 4 5 6 7 8 9 10 12 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF9 RF10 Isolation 23 22 A4 A3 A2 A1 A0 Parity Bit P 1/0 0 0 0 0 0 1/0 1 1/0 0 0 0 0 0 1/0 0 1 1/0 0 0 0 0 0 1/0 0 0 1 1/0 0 0 0 0 0 1/0 0 0 1 1/0 0 0 0 0 0 1/0 1 0 0 1 1/0 0 0 0 0 0 1/0 0 1 0 0 1 1/0 0 0 0 0 0 1/0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 1 0 1 0 1 0 0 1 1/0 0 0 0 0 0 1/0 9 8 7 6 5 4 3 2 1 0 Bu s P ar k - Slave Address Write/ Read Com m and Write:010 Read:011 C2 C1 C0 SSC - - - SA3 SA2 SA1 SA0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 Register Address D7 D6 D5 D4 D3 D2 D1 D0 Parity Bit P 0 0 0 0 0 0 1 0 1/0 0 0 0 0 0 1 0 1 0 1/0 0 0 0 0 0 1 1 1 0 1/0 0 0 0 0 0 1 0 1 1 1/0 0 0 0 0 0 0 0 0 1 1/0 0 0 0 0 0 1 0 0 1 1/0 0 0 0 0 0 0 1 1 0 1/0 0 0 0 0 0 0 1 0 0 1/0 0 0 0 0 0 1 1 0 0 1/0 0 0 0 0 0 1 0 0 0 1/0 0 0 0 0 0 0 0 0 0 1/0 0 Data *Parity Bit A Frame shall end with a single parity bit. The parity bit shall be driven such that the total number of bits in the Frame that are driven to logic level one, including the parity bit, is odd. 12 CXM3632ER Table A REGISTER_0 for ANT Switch State (0x0000) Bit 1 0 1 0 1 0 0 0 0/1 0/1 0/1 0/1 0/1 Description Items Slave Address Address of Diversity Switch REGISTER_0 Write : 1 Switch State See the truth table Trigger Supprt. Initial value : [D6:D0] =000 0000 Command Frame SA3 Slave SA2 Address SA1 SA0 C0 D6 D5 D4 Data D3 D2 D1 D0 Parity Bit P Parity bit for Frame Read Write Register Address Parity Bit Data Frame Command Frame Items Table B REGISTER_0 for ANT Switch State (0x0000) Data Parity Bit SA3 SA2 SA1 SA0 C2 C1 C0 A4 A3 A2 A1 A0 P D7 D6 D5 D4 D3 D2 D1 D0 P Bit 1 0 1 0 0 1 0/1 0 0 0 0 0 0/1 0 0 0 0 0/1 0/1 0/1 0/1 0/1 Description Address of Diversity Switch Write : 010 Read: 011 Register Address: 0x0000 Parity bit for Command Frame Switch State See the truth table Initial value : [D7:D0] =0000 0000 Trigger Supprt. Parity bit for Data Frame Table C RFFE_STATUS (0x001A) Items Command Frame Slave Address Read Write Register Address Data Frame Parity Bit Data Parity Bit Description Bit SA3 1 SA2 0 Address of Diversity Switch SA1 1 SA0 0 C2 0 Write : 010 C1 1 Read: 011 C0 0/1 A4 1 A3 1 A2 0 Register Address: 0x001A A1 1 A0 0 P 0/1 Parity bit for Command Frame 0: Normal operation D7 0/1 1: Software reset (reset of all configurable registers to default values, except for USID、PM_TRIG、GSID) D6 0/1 Command sequence received with parity error – discard D5 0/1 Command length error D4 0/1 Address frame parity error = 1 D3 0/1 Data frame with parity error D2 0/1 Read command to an invalid address D1 0/1 Write command to an invalid address D0 0/1 Read command with a Broadcast_ID or GROUP_ID P 0/1 Parity bit for Data Frame All Data bits become 0 after Read Command Sequence is sent. 13 Initial value : [D7:D0] =0000 0000 CXM3632ER Table D GROUP_ID (0x001B) Command Frame Slave Address Read Write Register Address Parity Bit Bit Description SA3 1 SA2 0 Address of Diversity Switch SA1 1 SA0 0 C2 0 Write : 010 C1 1 Read: 011 C0 0/1 A4 1 A3 1 A2 0 Register Address: 0x001B A1 1 A0 1 P 0/1 Parity bit for Command Frame Data Frame D7 D6 D5 Data D4 D3 D2 D1 D0 Parity Bit P 0 0 0 0 0/1 0/1 Group slave ID 0/1 0/1 0/1 Parity bit for Data Frame Initial value : [D3:D0] =0000 Table E Power Mode & Trigger Mode (0x001C) Command Frame Slave Address Read Write Register Address Data Frame Parity Bit Data Parity Bit Description Bit SA3 1 SA2 0 Address of Diversity Switch SA1 1 SA0 0 C2 0 Write : 010 C1 1 Read: 011 C0 0/1 A4 1 A3 1 A2 1 Register Address: 0x001C A1 0 A0 0 P 0/1 Parity bit for Command Frame 00: Normal operation (ACTIVE) D7 0/1 01: Default settings (STARTUP) 10: Low power (LOW POWER) D6 0/1 11: Reserved D5 0/1 Trigger_Mask_[2:0] D4 0/1 111: valid D3 0/1 other: Invalid D2 0/1 Trigger_[2:0] D1 0/1 000: Invalid D0 0/1 other: valid P 0/1 Parity bit for Data Frame Items Slave Address Command Frame Items Table F Product ID (0x001D) Read Write Register Address Parity Bit Initial value : [D7:D6] =10 Initial value : [D5:D3] =000 Initial value : [D5:D3] =000 14 Data Frame Items SA3 SA2 SA1 SA0 C2 C1 C0 A4 A3 A2 A1 A0 P Bit 1 0 1 0 0 1 1 1 1 1 0 1 1 D7 0 D6 0 D5 Data D4 D3 D2 D1 D0 Parity Bit P Description Address of Diversity Switch Read Only Register Address: 0x001D Parity bit for Command Frame 0 Product ID : 07h 0 0 1 1 1 0 Parity bit for Data Frame CXM3632ER Table G Manufacturer ID (0x001E) Items Read Write Register Address Parity Bit Description Items Description Bit SA3 1 SA2 0 Address of Diversity Switch SA1 1 SA0 0 C2 0 Write : 010 C1 1 Read : 011 C0 0/1 A4 1 A3 1 A2 1 Register Address: 0x001F A1 1 A0 1 P 0/1 Parity bit for Command Frame SA3 SA2 SA1 SA0 C2 C1 C0 A4 A3 A2 A1 A0 P Bit 1 0 1 0 0 1 1 1 1 1 1 0 1 D7 1 D7 0 D6 0 D6 0 Slave Address Address of Diversity Switch Command Frame Command Frame Slave Address Table H Manufacturer ID and USID (0x001F) Read Only Register Address: 0x001E Parity bit for Command Frame Read Write Register Address Parity Bit D5 D4 D3 D2 D1 D0 Parity Bit P Data Data Frame Data Frame SPARE 1 Manufacturer ID [7:0]:B0h (SONY ID) 1 0 0 0 0 0 Parity bit for Data Frame D5 D4 D3 D2 D1 D0 Parity Bit P Data 0 Manufacturer ID [9:8]:01h (SONY ID) 1 0/1 Initial 0/1 Programmable USID value:[D3:D0] 0/1 =1010 0/1 0/1 Parity bit for Data Frame For Programmable USID The PRODUCT_ID and the MANUFACTURER_ID match, then a new USID is programmed 15 CXM3632ER Recommended Circuit VQFN-20P PKG (2.4mm × 2.4mm × 0.775mm Max.) Top View *1: No DC blocking capacitors are required on all RF ports. *2: DC levels of all RF ports are GND. *3: L1 (27 nH) and C1 (15 pF) are recommended for ESD protection. *4: C2 (100 pF) and C3 (0.1 µF) are recommended. 16 CXM3632ER PCB Layout Foot Pattern (Unit: mm) Recommended PCB Design 17 CXM3632ER Package Outline (Unit: mm) 18 CXM3632ER Marking 19 CXM3632ER Tape and Reel Size (Unit: mm) 20 CXM3632ER Moisture Sensitivity Moisture Sensitivity Level for this part is MSL = 2 21 CXM3632ER Note Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits 22