Si1004-C Ultra-Low Power 64 kB, 10-bit ADC MCU with Integrated 240–960 MHz Transceiver Transceiver Features Supply Voltage: 0.9 to 1.8 V - Built-in dc-dc converter with 1.8 to 3.6 V output - Typical sleep mode current < 0.1 µA; retains state and RAM contents over full supply range; fast wakeup of < 2 µs - Two built-in brown-out detectors cover sleep and active modes 10-Bit Analog to Digital Converter - Up to 300 ksps - Up to 15 external inputs - External pin or internal VREF (no external capacitor required) - Built-in temperature sensor (±3 °C); no calibration required - External conversion start input option - Autonomous burst mode with 16-bit automatic averaging accumulator Dual Comparators - Programmable hysteresis and response time - Configurable as interrupt or reset source - Low current (< 0.5 µA) in 1 or 2 system clocks - 25 MIPS peak throughput with 25 MHz clock Development Kit: Si1000DK-915, Si1000DK-470, Si1002DK-868 Power On Reset/PMU Wake Reset XTAL1 XTAL3 XTAL4 Antenna diversity and transmit/receive switch control Programmable packet handler TX and RX 64 byte FIFOs Frequency hopping capability On-chip crystal tuning Ordering Part Number - Si1004-E-GM, 42-pin LGA (5 mm x 7 mm) PA Internal External VREF VREF TX A M U X VDD VREF Temp Sensor CP1, CP1A SFR Bus AGC RXp RXn LNA Mixer GND CP0, CP0A SYSCLK Low Power 20 MHz Oscillator IREF0 10-bit 300ksps ADC CRC Engine Digital Power RF XCVR (240-960 MHz) 4096 Byte XRAM VREG - Low power 20 MHz internal oscillator - External oscillator: crystal, RC, C, CMOS clock - smaRTClock oscillator: 32.768 kHz crystal or self-oscillate 6-bit IREF + - PGA ADC + - Comparators Digital Peripherals Transceiver Control Interface Digital Modem Delta Sigma Modulator Digital Logic UART External Oscillator Circuit Timers 0, 1, 2, 3 smaRTClock Oscillator PCA/ WDT System Clock Configuration Wireless MCU Auto-frequency calibration (AFC) 64k Byte ISP Flash Program Memory Precision 24.5 MHz Oscillator XTAL2 Data rate = 0.123 to 256 kbps Analog Peripherals C2D GND - CIP-51 8051 Controller Core 256 Byte SRAM Debug / Programming Hardware DC/DC Converter - 18.5 mA receive - 30 mA @ +13 dBm transmit - 18 mA @ +1 dBm transmit ports UART operation; spread-spectrum mode for reduced EMI High-Speed 8051 µC Core - Pipe-lined instruction architecture; executes 70% of instructions VBAT RF power consumption programmable counter array (PCA) system debug (no emulator required) GND/DC- Max output power = +13 dBm Clock Sources - Precision internal oscillators: 24.5 MHz with ±2% accuracy sup- On-Chip Debug - On-chip debug circuitry facilitates full speed, non-intrusive in- Analog Power FSK, GFSK, and OOK modulation concurrently - 4352 bytes internal data RAM (256 + 4K) VDD/DC+ Sensitivity = –121 dBm - Low power 32-bit smaRTClock - Four general purpose 16-bit counter/timers; six channel sectors; full read/write/erase functionality over the entire supply range Power Net Frequency range = 240–960 MHz Digital Peripherals - 19 port I/O - Hardware enhanced UART, SPI and I2C serial ports available Memory - 64 kB flash; in-system programmable in 1024-byte C2CK/RST - XIN XOUT OSC Priority Crossbar Decoder SMBus SPI 0 Copyright © 2010 by Silicon Laboratories Port I/O Config 19 ANALOG & DIGITAL I/O 1.15.10 Smart. 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