® RT9628A High Voltage Synchronous Rectified Triple Channel Buck MOSFET Driver for Notebook Computer General Description Features The RT9628A is a high frequency, triple Channel driver specifically designed to drive two power N-MOSFETs in each channel of a synchronous-rectified Buck converter topology. It is especially suited for mobile computing applications that require high efficiency and excellent thermal performance. This driver, combined with Richtek's series of multi-phase Buck PWM controllers, provides a complete core voltage regulator solution for advanced microprocessors. The drivers are capable of driving a 3nF load with fast rising/falling time and fast propagation delay. This device implements bootstrapping on the upper gates with only a single external capacitor. This reduces implementation complexity and allows the use of higher performance, cost effective, N-MOSFETs. Adaptive shoot through protection is integrated to prevent both MOSFETs from conducting simultaneously. Triple Channel Driver Each Channel Drives Two N-MOSFETs Adaptive Shoot-Through Protection 0.5Ω Ω On-Resistance, 4A Sink Current Capability Supports High Switching Frequency Tri-State PWM Input for Power Stage Shutdown Output Disable Function Integrated Boost Switch Low Bias Supply Current VCC POR Feature Integrated Applications Core Voltage Supplies for Intel ® / AMD ® Mobile Microprocessors High Frequency Low Profile DC/DC Converters High Current Low Output Voltage DC/DC Converters High Input Voltage DC/DC Converters Marking Information 00= : Product Code 00=YM DNN YMDNN : Date Code Simplified Application Circuit 12V VIN VCCx RT9628A L1 PHASE1 PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 Enable EN VOUT L2 PHASE2 L3 PHASE3 GND Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9628A-00 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9628A Ordering Information Pin Configurations (TOP VIEW) RT9628A Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. LGATE2 VCC LGATE1 PHASE1 UGATE1 BOOT1 Package Type QW : WQFN-24L 4x4 (W-Type) (Exposed Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) 24 23 22 21 20 19 PHASE2 NC UGATE2 BOOT2 NC NC 1 18 2 17 3 16 GND 4 15 25 5 6 14 13 8 9 10 11 12 NC PWM2 PWM1 EN PWM3 NC 7 LGATE3 PHASE3 UGATE3 BOOT3 NC NC WQFN-24L 4x4 Functional Pin Description Pin No. Pin Name Pin Function 1, 17, 21 PHASE2, PHASE3, PHASE1 Switch Nodes. Connect these pins to the Sources of the high side MOSFETs and the Drains of the low side MOSFETs. These pins provide return paths for the high side gate drivers. 3, 16, 20 UGATE2, UGATE3, UGATE1 High Side Gate Drive Outputs. Connect to the gates of high side power NMOSFETs. 4, 15, 19 BOOT2, BOOT3, BOOT1 Bootstrap Supply for High Side Gate Drives. Connect the bootstrap capacitors between these pins and the PHASEx pins. The bootstrap capacitors provide the charge to turn on the high side MOSFETs. 8, 9, 11 PWM2, PWM1, PWM3 Control Inputs for Drivers. The PWM signal can enter three distinct states during operation. Connect these pins to the PWM outputs of the controller. The PWM signal must be driving after EN signal then 60s. EN Enable Control Input. When pulling low, both UGATEx and LGATEx are driven low and the normal operation is disabled. LGATE3, LGATE1, LGATE2 Low Side Gate Drive Outputs. Connect to the Gates of the low side power NMOSFETs. VCC Supply Voltage Input. Connect this pin to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND. 25 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 10 18, 22, 24 23 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9628A-00 October 2014 RT9628A Function Block Diagram VCC BOOT1 POR UGATE1 EN Control Logic VCC Shoot-Through Protection PHASE1 VCC R LGATE1 Tri-State Detect PWM1 GND R BOOT2 UGATE2 VCC Control Logic R Shoot-Through Protection PWM2 PHASE2 VCC Tri-State Detect R LGATE2 BOOT3 UGATE3 VCC Control Logic R Shoot-Through Protection PWM3 PHASE3 VCC Tri-State Detect R LGATE3 Operation POR (Power On Reset) POR block detects the voltage at the VCC pin. When the VCC pin voltage is higher than POR rising threshold, POR pin output voltage (POR output) is high. The POR output is low when VCC is not higher than POR rising threshold. When the POR pin voltage is high, UGATEx and LGATEx can be controlled by PWMx input voltage. If the POR pin voltage is low, both UGATEx and LGATEx will be pulled to low. Control Logic Control logic block detects whether high side MOSFET is turned off by monitoring (UGATEx − PHASEx) voltages below 1.1V or phase voltage below 2V. To prevent the overlap of the gate drives during the UGATEx pull low and the LGATEx pull high, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection Tri-State Detect When both POR output and ENx pin voltages are high, UGATEx and LGATEx can be controlled by PWMx input. There are three PWMx input modes which are high, low, and shutdown state. If PWMx input is within the shutdown window, both UGATEx and LGATEx outputs are low. When PWMx input is higher than its rising threshold, UGATEx is high and LGATEx is low. When PWMx input is lower than its falling threshold, UGATEx is low and LGATEx is high. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9628A-00 October 2014 Shoot-through protection block implements the dead-time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFETs are never turned on simultaneously. Thus, shoot-through between high side and low side MOSFETs is prevented. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9628A Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -----------------------------------------------------------------------------------------------------BOOTx to PHASEx ------------------------------------------------------------------------------------------------------- PHASEx to GND DC -----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------- UGATEx to PHASEx DC -----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------- LGATEx to GND DC -----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------- PWMx, EN to GND ------------------------------------------------------------------------------------------------------ Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 ------------------------------------------------------------------------------------------------------------ Package Thermal Resistance (Note 2) WQFN-24L 4x4, θJA ------------------------------------------------------------------------------------------------------WQFN-24L 4x4, θJC ------------------------------------------------------------------------------------------------------ Junction Temperature ----------------------------------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- Storage Temperature Range -------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------- Recommended Operating Conditions −0.3V to 6V −0.3V to 6V −0.3V to 32V −8V to 38V −0.3V to 6V −5V to 7.5V −0.3V to 6V −2.5V to 7.5V −0.3V to 6V 3.57W 28°C/W 7°C/W 150°C 260°C −65°C to 150°C 2kV (Note 4) Input Voltage, VIN ---------------------------------------------------------------------------------------------------------Supply Voltage, VCC -----------------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------------------------- 4.5V to 26V 4.5V to 5.5V −40°C to 85°C −40°C to 125°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VCC Supply Current Quiescent Current IQ PWM Pin Floating, VEN = 3.3V -- 150 -- A Shutdown Current ISHDN VEN = 0V, PWM = 0V -- 0 5 A V PORH VCC POR Rising -- 3.85 4.1 V V PORL VCC POR Falling 3.4 3.65 -- V V PORHYS Hysteresis -- 200 -- mV R BOOT VCC to BOOT, 10mA -- -- 80 VCC Power On Reset (POR) Internal BOOT Switch Internal Boot Switch On Resistance Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9628A-00 October 2014 RT9628A Parameter Symbol Test Conditions Min Typ Max Unit A PWMx Input V PWM = 5V -- 174 -- V PWM = 0V -- 174 -- V PWMH 3.5 3.8 4.1 V V PWML 0.7 1 1.3 V tSHD_Tri 100 175 250 ns Input Current IPWM PWMx Tri-State Rising Threshold PWMx Tri-State Falling Threshold Tri-State Shutdown Hold-off Time EN Input EN Input Voltage Logic-High VENH 2 -- -- Logic-Low VENL -- -- 0.5 V Switching Time UGATEx Rise Time tUGATEr 3nF load -- 8 -- ns UGATEx Fall Time tUGATEf 3nF load -- 8 -- ns LGATEx Rise Time tLGATEr 3nF load -- 8 -- ns LGATEx Fall Time UGATEx Turn-Off Propagation Delay LGATEx Turn-Off Propagation Delay UGATEx Turn-On Propagation Delay LGATEx Turn-On Propagation Delay UGATEx/LGATEx Tri-State Propagation Delay Output tLGATEf 3nF load -- 4 -- ns tPDLU Outputs Unloaded -- 35 -- ns tPDLL Outputs Unloaded -- 35 -- ns tPDHU Outputs Unloaded -- 20 -- ns tPDHL Outputs Unloaded -- 20 -- ns tPTS Outputs Unloaded -- 35 -- ns UGATEx Driver Source Resistance RUGATEsr 100mA Source Current -- 1 -- UGATEx Driver Source Current IUGATEsr VUGATE VPHASE = 2.5V -- 2 -- A UGATEx Driver Sink Resistance RUGATEsk 100mA Sink Current -- 1 -- UGATEx Driver Sink Current IUGATEsk VUGATE VPHASE = 2.5V -- 2 -- A LGATEx Driver Source Resistance RLGATEsr 100mA Source Current -- 1 -- LGATEx Driver Source Current ILGATEsr VLGATE = 2.5V -- 2 -- A LGATEx Driver Sink Resistance LGATEx Driver Sink Current RLGATEsk ILGATEsk 100mA Sink Current VLGATE = 2.5V --- 0.5 4 --- A Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution recommended. The human body mode is a 100pF capacitor is charged through a 1.5kΩ resistor into each pin. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9628A-00 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9628A Typical Application Circuit L1 2.2µH VIN VBAT C8 C9 C10 C11 C12 C13 C2 1µF R2 19 BOOT1 R1 R3 20 23 UGATE1 VCC C1 RT9628A 1µF 21 PHASE1 VCC Enable PWM1 PWM2 PWM3 10 EN 9 8 11 25 (Exposed Pad) LGATE1 C14 22 R4 3 R6 QUG1 PWM3 C3 3.3nF QLG1 VCORE C4 C5 C6 C7 R5 2.2 PWM1 PWM2 L2 1µH VIN UGATE2 BOOT2 4 1 PHASE2 QUG2 R5 C15 1µF L3 1µH GND LGATE2 24 R7 16 R10 C16 3.3nF QLG2 R8 2.2 VIN UGATE3 R9 BOOT3 15 17 PHASE3 LGATE3 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 18 QUG3 C17 1µF L4 1µH R11 QLG3 C18 3.3nF R8 2.2 is a registered trademark of Richtek Technology Corporation. DS9628A-00 October 2014 RT9628A Typical Operating Characteristics Driver Enable Driver Disable UGATE (20V/Div) UGATE (20V/Div) PHASE (20V/Div) PHASE (20V/Div) LGATE (10V/Div) EN (10V/Div) LGATE (10V/Div) VIN = 19V, No Load EN (10V/Div) VIN = 19V, No Load Time (10μs/Div) Time (2μs/Div) PWM Rising Edge PWM Falling Edge PWM (10V/Div) PWM (10V/Div) UGATE (20V/Div) UGATE (20V/Div) PHASE (20V/Div) PHASE (20V/Div) LGATE (5V/Div) LGATE (5V/Div) Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE LGATE (5V/Div) (5V/Div) No Load Time (20ns/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9628A-00 October 2014 No Load Time (20ns/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9628A Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE (5V/Div) LGATE (5V/Div) Full Load Full Load Time (20ns/Div) Time (20ns/Div) Short Pulse UGATE PHASE LGATE (5V/Div) UGATE-PHASE No Load Time (20ns/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9628A-00 October 2014 RT9628A Application Information Supply Voltage and Power On Reset The RT9628A is designed to drive three sets of both high side and low side N-MOSFETs through three externally input PWMx control signals. Connect 5V to VCC to power on the RT9628A. A minimum 1μF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor physically near the IC. The Power On Reset (POR) circuit monitors the supply voltage at the VCC pin. If VCC exceeds the POR rising threshold voltage, the controller resets and prepares for operation. UGATEx and LGATEx are held low before VCC is above the POR rising threshold. Enable and Disable The RT9628A includes an EN pin for sequence control. When the EN pin rises above the VENH trip point, the RT9628A begins a new initialization and follows the PWMx command to control the UGATEx and LGATEx. When the EN pin falls below the VENL trip point, the RT9628A shuts down and keeps UGATEx and LGATEx low. fall below the threshold, LGATEx begins to turn high. By waiting for the voltages of the PHASEx pin and high side gate drive to fall below their threshold, the non-overlap protection circuit ensures that UGATEx is low before LGATEx pulls high. Also to prevent the overlap of the gate drives during LGATEx pull low and UGATEx pull high, the non-overlap circuit monitors the LGATEx voltage. When LGATEx go below 1.1V, UGATEx is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. The gate draws the current only for few nano-amperes. Thus, once the gate has been driven up to “ON” level, the current could be negligible. However, the capacitance at the Gate to Source terminal should be considered. It requires relatively large currents to drive the Gate up and down rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. D1 Three State PWM Input After initialization, the PWMx signal takes over the control. The rising PWMx signal first forces the LGATEx signal low and then allows the UGATEx signal to go high right after a non-overlapping time to avoid shoot-through current. In contrast, the falling PWMx signal first forces UGATEx to go low. When the UGATEx or PHASEx signal reach a predetermined low level, LGATEx signal is then allowed to go high. The PWM signal must be driving after EN signal then 60μs. d1 s1 PHASEx VIN L VOUT Cgs1 Cgd1 Cgd2 Igs1 Igd1 Ig1 g1 d2 Ig2 Igd2 g2 D2 Igs2 Cgs2 s2 GND Vg1 Non-overlap Control To prevent the overlap of the gate drives during the UGATEx pull low and the LGATEx pull high, the non-overlap circuit monitors the voltages at the PHASEx node and high side gate drive (UGATEx − PHASEx). When the PWMx input signal goes low, UGATEx begins to pull low (after propagation delay). Before LGATEx can pull high, the nonoverlap protection circuit ensures that the monitored (UGATEx − PHASEx) voltages have gone below 1.1V or phase voltage is below 2V. Once the monitored voltages Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9628A-00 October 2014 VPHASEx +5V t Vg2 5V t Figure1. Equivalent Circuit and Associated Waveforms is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9628A In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 5V. The operation consists of charging Cgd1, Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from Gate to Source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs1 and C gs2 are referred as “Ciss” which are the input capacitors. Cgd1 and Cgd2 are the capacitors from Gate to Drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as “Crss” the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are shown as below : Igs1 Cgs1 Igs2 Cgs1 dVg1 dt dVg2 dt Cgs1 x 5 Igd1 Igd2 380 x 10-12 x 5 14 x 10-9 0.136 (A) 500 x 10-12 x 12 + 5 30 x 10-9 (7) 0.283 (A) (8) the total current required from the gate driving source can be calculated as following equations : Ig1 Igs1 Igd1 0.593 0.136 0.729 (A) (9) Ig2 Igs2 Igd2 0.367 0.283 0.65 (A) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. (1) tr1 Select the Bootstrap Capacitor Cgs1 x 5 (2) tr2 Before driving the Gate of the high side MOSFET up to 5V, the low side MOSFET has to be off; the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode “D2” had been turned on before high side MOSFETs turned on. Igd1 Cgd1 from equation. (3) and (4) dV 5 Cgd1 dt tr1 Figure 2 shows part of the bootstrap circuit of the RT9628A. The VCB (the voltage difference between BOOTx and PHASEx on RT9628A) provides a voltage to the Gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance C B has to be selected properly. It is determined by following constraints. VIN (3) BOOTx UGATEx Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 5V, the required current is : PHASEx CB + VCB - VCC dV Vi 5 Igd2 Cgd2 Cgd2 dt tr2 (4) GND It is helpful to calculate these currents in a typical case. Assume a synchronous rectified Buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 5V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain : Igs1 Igs2 1660 x 10-12 x 5 14 x 10-9 2200 x 10-12 x 5 30 x 10 -9 0.593 (A) (5) 0.367 (A) (6) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 LGATEx Figure 2. Part of Bootstrap Circuit of RT9628A In practice, a low value capacitor CB will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. is a registered trademark of Richtek Technology Corporation. DS9628A-00 October 2014 RT9628A Thermal Considerations Layout Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Figure 4 shows the schematic circuit of a synchronous Buck converter to implement the RT9628A. VBAT L1 + CIN1 CIN2 5V VIN R1 BOOTx CB QUGx PD(MAX) = (TJ(MAX) − TA) / θJA VCC RT9628A UGATEx Lx For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-24L 4x4 package, the thermal resistance, θJA, is 28°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : P D(MAX) = (125°C − 25°C) / (28°C/W) = 3.57W for WQFN-24L 4x4 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. VCORE PHB83N03LT + where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. PWMx PHASEx EN COUT QLGx PHB95N03LT C1 PWM Signal 5V GND LGATEx Figure 4. Synchronous Buck Converter Circuit When layout the PCB, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of QUGx, QLGx, Lx should be very close. Next, the trace from UGATEx, and LGATEx should also be short to decrease the noise of the driver output signals. PHASEx signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C1 should be connected to GND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. Maximum Power Dissipation (W)1 4.0 Four-Layer PCB 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curve of Maximum Power Dissipation Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9628A-00 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9628A Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b A3 Symbol D2 E2 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 E 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 12 DS9628A-00 October 2014