® RT9610A/B High Voltage Synchronous Rectified Buck MOSFET Driver for Notebook Computer General Description Features The RT9610A/B is a high frequency, dual MOSFET driver specifically designed to drive two power N-MOSFETS in a synchronous-rectified buck converter topology. It is especially suited for mobile computing applications that require high efficiency and excellent thermal performance. This driver, combined with Richtek's series of multi-phase Buck PWM controllers, provides a complete core voltage regulator solution for advanced microprocessors. The drivers are capable of driving a 3nF load with fast rising/falling time and fast propagation delay. This device implements bootstrapping on the upper gates with only a single external capacitor. This reduces implementation complexity and allows the use of higher performance, cost effective, N-MOSFETs. Adaptive shoot through protection is integrated to prevent both MOSFETs from conducting simultaneously. The RT9610A/B is available in WQFN-8L 3x3 and WDFN-8L 2x2 Packages. Drives Two N-MOSFETs Adaptive Shoot-Through Protection 0.5Ω Ω On-Resistance, 4A Sink Current Capability Supports High Switching Frequency Tri-State PWM Input for Power Stage Shutdown Output Disable Function Integrated Boost Switch Low Bias Supply Current VCC POR Feature Integrated Small 8-Lead WQFN and WDFN Packages RoHS Compliant and Halogen Free Applications Core Voltage Supplies for Intel ® / AMD ® Mobile Microprocessors High Frequency Low Profile DC/DC Converters High Current Low Output Voltage DC/DC Converters High Input Voltage DC/DC Converters Simplified Application Circuit VIN RT9610A/B VCC VCC UGATE BOOT Chip Enable PWM EN PHASE PWM LGATE GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 September 2015 VCORE is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9610A/B Ordering Information Pin Configurations RT9610A/B BOOT 1 PWM 2 PHASE 8 7 3 4 LGATE 9 A : WQFN-8L 3x3 B : WDFN-8L 2x2 Note : 5 VCC EN PHASE UGATE BOOT Suitable for use in SnPb or Pb-free soldering processes. 1 2 3 4 GND RT9610A RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. EN WQFN-8L 3x3 Richtek products are : 6 GND GND Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) UGATE (TOP VIEW) Package Type QW : WQFN-8L 3x3 (W-Type) QW : WDFN-8L 2x2 (W-Type) 9 8 7 6 5 VCC LGATE GND PWM WDFN-8L 2x2 RT9610B Marking Information RT9610AGQW RT9610BGQW 26= : Product Code 26=YM DNN YMDNN : Date Code 20 : Product Code 20W RT9610BZQW RT9610AZQW 26 : Product Code 26 YM DNN YMDNN : Date Code Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 W : Date Code 20 : Product Code 20W W : Date Code is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 RT9610A/B Functional Pin Description Pin No. WQFN-8L 3x3 WDFN 8L 2x2 Pin Name Pin Function 1 4 BOOT Floating Bootstrap Supply Pin for Upper Gate Drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. 2 5 PWM Control Input for Driver. The PWM signal can enter three distinct states during operation. Connect this pin to the PWM output of the controller. 3, 6, GND 9 (Exposed Pad) 9 (Exposed Pad) Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 4 7 LGATE Lower Gate Drive Output. Connect to the gate of the low side power N-MOSFET. 5 8 VCC Input Supply Pin. Connect this pin to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND. 6 1 EN Enable Pin. When low, both UGATE and LGATE are driven low and the normal operation is disabled. 7 2 PHASE Switch Node. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver. 8 3 UGATE Upper Gate Drive Output. Connect to the gate of high side power N-MOSFET. Function Block Diagram VCC BOOT POR UGATE Control Logic EN Shoot-Through Protection PHASE VCC VCC LGATE R Tri-State Detect PWM GND R Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 September 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9610A/B Operation POR (Power On Reset) POR block detects the voltage at the VCC pin. When the VCC pin voltage is higher than POR rising threshold, the POR pin output voltage (POR output) is high. POR output is low when VCC is not higher than POR rising threshold. When the POR pin voltage is high, UGATE and LGATE can be controlled by PWM input voltage. If the POR pin voltage is low, both UGATE and LGATE will be pulled to low. Tri-State Detect When both POR output and EN pin voltages are high, UGATE and LGATE can be controlled by PWM input. There are three PWM input modes which are high, low, and shutdown state. If PWM input is within the shutdown window, both UGATE and LGATE outputs are low. When PWM input is higher than its rising threshold, UGATE is high and LGATE is low. When PWM input is lower than its falling threshold, UGATE is low and LGATE is high. Control Logic Control logic block detects whether high side MOSFET is turned off by monitoring (UGATE - PHASE) voltages below 1.1V or PHASE voltage below 2V. To prevent the overlap of the gate drives during the UGATE pulls low and the LGATE pulls high, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection Shoot-through protection block implements the dead-time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFETs are never turned on simultaneously. Thus, shoot-through between high side and low side MOSFETs is prevented. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 RT9610A/B Absolute Maximum Ratings (Note 1) Supply Voltage, VCC ------------------------------------------------------------------------------------------------------- −0.3V to 6V BOOT to PHASE ------------------------------------------------------------------------------------------------------------ −0.3V to 6V PHASE to GND DC ------------------------------------------------------------------------------------------------------------------------------- −0.3V to 32V < 20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V UGATE to PHASE DC ------------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V LGATE to GND DC ------------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V PWM, EN to GND ---------------------------------------------------------------------------------------------------------- −0.3V to 6V Power Dissipation, PD @ TA = 25°C WQFN-8L 3x3 ---------------------------------------------------------------------------------------------------------------- 1.258W WDFN-8L 2x2 ---------------------------------------------------------------------------------------------------------------- 0.833W Package Thermal Resistance (Note 2) WQFN-8L 3x3, θJA ---------------------------------------------------------------------------------------------------------- 79.5°C/W WQFN-8L 3x3, θJC ---------------------------------------------------------------------------------------------------------- 8°C/W WDFN-8L 2x2, θJA ----------------------------------------------------------------------------------------------------------- 120°C/W WDFN-8L 2x2, θJC ---------------------------------------------------------------------------------------------------------- 8.2°C/W Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------------------------------ 2kV MM (Machine Model) ------------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4) Input Voltage, VIN ----------------------------------------------------------------------------------------------------------- 4.5V to 26V Control Voltage, VCC ------------------------------------------------------------------------------------------------------- 4.5V to 5.5V Ambient Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 85°C Junction Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 125°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Min Typ Max Unit PWM Pin Floating, VEN = 3.3V -- 80 -- A ISHDN VEN = 0V, PWM = 0V, VCC = 5V -- 0 5 A VPORH VCC POR Rising -- 4.2 4.5 V VCC Power On Reset (POR) VPORL VCC POR Falling 3.5 3.84 -- V -- 360 -- mV VCC Supply Current Quiescent Current Shutdown Current Symbol IQ VPORHYS Test Conditions Hysteresis Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 September 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9610A/B Parameter Internal BOOT Switch Symbol Internal Boost Switch On RBOOT Resistance Test Conditions Min Typ Max Unit VCC to BOOT, 10mA -- -- 80 VPWM = 5V -- 174 -- VPWM = 0V -- 174 -- PWM Input Input Current IPWM A PWM Tri-State Rising Threshold VPWMH VCC = 5V 3.5 3.8 4.1 V PWM Tri-State Falling Threshold VPWML VCC = 5V 0.7 1 1.3 V Tri-State Shutdown Hold-off Time tSHD_Tri VCC = 5V 100 175 250 ns Logic-High VENH VCC = 5V 2 -- -- Logic-Low VENL VCC = 5V -- -- 0.48 tUGATEr VCC = 5V, 3nF Load -- 8 -- ns 8 -- ns EN Input EN Input Voltage V Switching Time UGATE Rise Time UGATE Fall Time tUGATEf VCC = 5V, 3nF Load -- LGATE Rise Time tLGATEr VCC = 5V, 3nF Load -- 8 -- ns LGATE Fall Time tLGATEf VCC = 5V, 3nF Load -- 4 -- ns tPDLU VCC = 5V, Outputs Unloaded -- 35 -- ns tPDLL VCC = 5V, Outputs Unloaded -- 35 -- ns tPDHU VCC = 5V, Outputs Unloaded -- 20 -- ns tPDHL VCC = 5V, Outputs Unloaded -- 20 -- ns tPTS VCC = 5V, Outputs Unloaded -- 35 -- ns RUGATEsr 100mA Source Current -- 1 -- UGATE Driver Source Current IUGATEsr VUGATE VPHASE = 2.5V -- 2 -- A UGATE Driver Sink Resistance RUGATEsk 100mA Sink Current -- 1 -- UGATE Driver Sink Current IUGATEsk VUGATE VPHASE = 2.5V -- 2 -- A RLGATEsr 100mA Source Current -- 1 -- LGATE Driver Source Current ILGATEsr VLGATE = 2.5V -- 2 -- A LGATE Driver Sink Resistance RLGATEsk 100mA Sink Current -- 0.5 -- LGATE Driver Sink Current ILGATEsk VLGATE = 2.5V -- 4 -- A UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay UGATE/LGATE Tri-State Propagation Delay Output UGATE Driver Source Resistance LGATE Driver Source Resistance Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 ® RT9610A/B Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution recommended. The human body mode is a 100pF capacitor is charged through a 1.5kΩ resistor into each pin. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 September 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9610A/B Typical Application Circuit L1 2.2µH VIN VBAT C8 C9 C10 C12 C11 R2 BOOT R1 VCC VCC C13 C14 C2 1µF R3 Q1 UGATE C1 1µF L2 1µH RT9610A/B Chip Enable PHASE EN C3 3.3nF R4 PWM PWM LGATE GND Q2 VCORE C4 C5 R5 2.2 C6 C7 Timing Diagram PWM tPDLL 90% tPDLU LGATE 1.5V 1.5V 90% UGATE 1.5V tPDHU Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 1.5V tPDHL is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 ® RT9610A/B Typical Operating Characteristics Driver Enable Driver Disable UGATE (20V/Div) PHASE (20V/Div) UGATE (20V/Div) PHASE (20V/Div) LGATE (5V/Div) LGATE (5V/Div) EN (5V/Div) EN (5V/Div) VIN = 19V, No Load VIN = 19V, No Load Time (1μs/Div) Time (1μs/Div) PWM Rising Edge PWM Falling Edge VIN = 19V, No Load UGATE (20V/Div) UGATE (20V/Div) PHASE (20V/Div) LGATE (5V/Div) PHASE (20V/Div) LGATE (5V/Div) PWM (5V/Div) PWM (5V/Div) VIN = 19V, No Load Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE UGATE - PHASE (5V/Div) (5V/Div) LGATE VIN = 19V, PWM Rising, No Load Time (20ns/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 UGATE - PHASE September 2015 LGATE VIN = 19V, PWM Falling, No Load Time (20ns/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9610A/B Dead Time Dead Time UGATE UGATE PHASE PHASE UGATE - PHASE (5V/Div) LGATE VIN = 19V, PWM Rising, Full Load Time (20ns/Div) UGATE - PHASE (5V/Div) LGATE VIN = 19V, PWM Falling, Full Load Time (20ns/Div) Short Pulse UGATE PHASE UGATE - PHASE (5V/Div) LGATE VIN = 19V, Start Up Time (20ns/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 RT9610A/B Application Information Supply Voltage and Power On Reset The RT9610A/B is designed to drive both high side and low side N-MOSFETs through an externally input PWM control signal. Connect 5V to VCC to power on the RT9610A/B. A minimum 1μF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor physically near the IC. The power on reset (POR) circuit monitors the supply voltage at the VCC pin. If VCC exceeds the POR rising threshold voltage, the controller resets and prepares for operation. UGATE and LGATE are held low before VCC is above the POR rising threshold. Enable and Disable The RT9610A/B includes an EN pin for sequence control. When the EN pin rises above the VENH trip point, the RT9610A/B begins a new initialization and follows the PWM command to control the UGATE and LGATE. When the EN pin falls below the VENL trip point, the RT9610A/B shuts down and keeps UGATE and LGATE low. voltages of the PHASE pin and high side gate drive to fall below their threshold, the non-overlap protection circuit ensures that UGATE is low before LGATE pulls high. Also to prevent the overlap of the gate drives during LGATE pull low and UGATE pull high, the non-overlap circuit monitors the LGATE voltage. When LGATE go below 1.1V, UGATE is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. The gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ON” level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. D1 d1 Three State PWM Input After initialization, the PWM signal takes over the control. The rising PWM signal first forces the LGATE signal low and then allows the UGATE signal to go high right after a non-overlapping time to avoid shoot through current. In contrast, the falling PWM signal first forces UGATE to go low. When the UGATE or PHASE signal reach a predetermined low level, LGATE signal is then allowed to go high. VOUT Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 September 2015 Cgs1 Cgd1 Cgd2 Igs1 Igd1 Ig1 g1 d2 Ig2 Igd2 g2 D2 Igs2 Cgs2 s2 GND Vg1 VPHASE +5V Non-overlap Control To prevent the overlap of the gate drives during the UGATE pull low and the LGATE pull high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to pull low (after propagation delay). Before LGATE can pull high, the non-overlap protection circuit ensures that the monitored (UGATEPHASE) voltages have gone below 1.1V or phase voltage is below 2V. Once the monitored voltages fall below the threshold, LGATE begins to turn high. By waiting for the L s1 VIN t Vg2 5V t Figure1. Equivalent Circuit and Associated Waveforms is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9610A/B In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 5V. The operation consists of charging Cgd1, Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs1 and C gs2 are referred as “Ciss” which are the input capacitors. Cgd1 and Cgd2 are the capacitors from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as “Crss” the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are shown as below : dVg1 Cgs1 x 5 (1) Igs1 Cgs1 dt tr1 Igs2 Cgs1 dVg2 dt Cgs1 x 5 (2) tr2 Before driving the gate of the high side MOSFET up to 5V, the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode “D2” had been turned on before high side MOSFETs turned on. dV 5 Igd1 Cgd1 Cgd1 (3) dt tr1 Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 5V, the required current is : dV Vi 5 Igd2 Cgd2 Cgd2 (4) dt tr2 It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 5V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain : Igs1 Igs2 1660 x 10-12 x 5 14 x 10-9 2200 x 10-12 x 5 30 x 10 -9 0.593 (A) (5) 0.367 (A) (6) from equation. (3) and (4) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 Igd1 Igd2 380 x 10-12 x 5 14 x 10-9 0.136 (A) 500 x 10-12 x 12+5 30 x 10-9 (7) 0.283 (A) (8) the total current required from the gate driving source can be calculated as following equations : Ig1 Igs1 Igd1 0.593 0.136 0.729 (A) (9) Ig2 Igs2 Igd2 0.367 0.283 0.65 (A) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of the RT9610A/B. The VCB (the voltage difference between BOOT and PHASE on RT9610A/B) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. VIN BOOT UGATE CB PHASE + VCB - VCC LGATE GND Figure 2. Part of Bootstrap Circuit of RT9610A/B In practice, a low value capacitor CB will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 RT9610A/B For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA 1.3 Maximum Power Dissipation (W)1 Thermal Considerations 1.1 1.0 0.9 0.8 0.6 0.4 0.3 0.2 0.1 PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for WDFN-8L 2X2 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curves in Figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curve of Maximum Power Dissipation Layout Considerations Figure 4 shows the schematic circuit of a synchronous buck converter to implement the RT9610A/B. L1 VIN 12V 5V C1 C2 1 BOOT 8 Q1 L2 7 VCORE PHB83N03LT UGATE PWM PHASE EN C3 Q2 R1 VCC RT9610A/B CB + PD(MAX) = (125°C − 25°C) / (79.5°C/W) = 1.258W for WQFN-8L 3x3 package WDFN-8L 2x2 0.5 + 79.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-8L 2x2 packages, the thermal resistance, θJA, is 120°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : WQFN-8L 3x3 0.7 where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-8L 3x3 packages, the thermal resistance, θJA, is Four-Layer PCB 1.2 PHB95N03LT 4 LGATE GND 5 C4 2 6 PWM 5V 3 Figure 4. Synchronous Buck Converter Circuit When layout the PCB, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from UGATE, and LGATE should also be short to decrease the noise of the driver output signals. PHASE signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to GND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS9610A/B-06 September 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9610A/B Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 2.900 3.100 0.114 0.122 D2 1.050 1.150 0.041 0.045 E 2.900 3.100 0.114 0.122 E2 1.050 1.150 0.041 0.045 0.650 e L 0.550 0.026 0.650 0.022 0.026 W-Type 8L QFN 3x3 Package Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS9610A/B-06 September 2015 RT9610A/B D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.950 2.050 0.077 0.081 D2 1.000 1.250 0.039 0.049 E 1.950 2.050 0.077 0.081 E2 0.400 0.650 0.016 0.026 e L 0.500 0.300 0.020 0.400 0.012 0.016 W-Type 8L DFN 2x2 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9610A/B-06 September 2015 www.richtek.com 15