SiA414DJ-DS

SPICE Device Model SiA414DJ
Vishay Siliconix
Dual N-Channel 8-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 4.5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 69167
S-71632Rev. A, 06-Aug-07
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SPICE Device Model SiA414DJ
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = 250 µA
0.57
ID(on)
VDS ≤ 5 V, VGS = 4.5 V
423
VGS = 4.5 V, ID = 9.7 A
0.009
0.009
VGS = 2.5 V, ID = 9 A
0.011
0.011
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
Forward Transconductancea
Forward Voltage
a
rDS(on)
V
A
Ω
VGS = 1.8 V, ID = 8.1 A
0.013
0.013
gfs
VDS = 6 V, ID = 9.7A
49
50
S
VSD
IS = 10 A
0.84
0.80
V
1872
1800
608
650
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 4 V, VGS = 0 V, f = 1 MHz
447
VDS = 4 V, VGS = 5 V, ID = 10 A
VDS = 4 V, VGS = 4.5 V, ID = 10 A
pF
450
17
21
16
19
2.5
2.5
6.5
6.5
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 69167
S-71632Rev. A, 06-Aug-07
SPICE Device Model SiA414DJ
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 69167
S-71632Rev. A, 06-Aug-07
www.vishay.com
3
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Document Number: 91000
Revision: 18-Jul-08
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