Si1012R-DS

SPICE Device Model Si1012R
Vishay Siliconix
N-Channel 1.8-V (G-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72854
S-51298⎯Rev. C, 27-Jul-05
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SPICE Device Model Si1012R
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
VGS(th)
VDS = VGS, ID = 250 μA
0.60
Measured
Data
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
ID(on)
rDS(on)
V
VDS = 5 V, VGS = 4.5 V
5.5
VGS = 4.5 V, ID = 600 mA
0.49
0.41
A
VGS = 2.5 V, ID = 500 mA
0.60
0.53
0.70
Ω
VGS = 1.8 V, ID = 350 mA
0.73
Forward Transconductancea
gfs
VDS = 10 V, ID = 400 mA
1
1
S
Diode Forward Voltagea
VSD
IS = 150 mA, VGS = 0 V
0.70
0.80
V
0.68
0.75
Dynamicb
Total Gate Charge
Qg
VDS = 10 V, VGS = 4.5 V, ID = 250 mA
Gate-Source Charge
Qgs
0.075
0.075
Gate-Drain Charge
Qgd
0.225
0.225
Turn-On Delay Time
td(on)
5
5
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
tf
VDD = 10 V, RL = 47 Ω
ID ≅ 200 mA, VGEN = 4.5 V, RG = 10 Ω
6
5
19
25
21
11
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 72854
S-51298⎯Rev. C, 27-Jul-05
SPICE Device Model Si1012R
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72854
S-51298⎯Rev. C, 27-Jul-05
www.vishay.com
3
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Document Number: 91000
Revision: 18-Jul-08
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