16-Bit, 65 MSPS, 1.8 V Analog-to-Digital Converter AD9266-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 77.6 dBFS at 9.7 MHz input 76.4 dBFS at 70 MHz input SFDR 94 dBc at 9.7 MHz input 93 dBc at 70 MHz input Low power 111 mW at 65 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = −0.5/+1.0 LSB Interleaved data output for reduced pin-count interface Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1 to 8 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock output (DCO) with programmable clock and data alignment AVDD Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline Enhanced product change notification Qualification data available on request APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imaging Rev. B RBIAS SPI AD9266-EP PROGRAMMING DATA VIN+ ADC CORE VIN– DRVDD CMOS OUTPUT BUFFER VCM OR D15_D14 8 VREF D1_D0 DCO SENSE REF SELECT DUTY CYCLE STABILIZER MODE CONTROLS PDWN DFS MODE CLK+ CLK– 10476-001 DIVIDE 1 TO 8 Figure 1. PRODUCT HIGHLIGHTS 1. 2. 3. ENHANCED PRODUCT FEATURES SDIO SCLK CSB AGND 4. The AD9266-EP operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The sample-and-hold circuit maintains excellent performance at high input frequencies and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D15_D14 to D1_D0) timing and offset adjustments, and voltage reference modes. The AD9266-EP is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9609 10-bit ADC, the AD9629 12-bit ADC, and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling at 65 MSPS. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9266-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Digital Specifications ....................................................................6 Enhanced Product Features ............................................................ 1 Switching Specifications ...............................................................7 Applications ....................................................................................... 1 Timing Specifications ...................................................................8 Functional Block Diagram .............................................................. 1 Absolute Maximum Ratings ............................................................9 Product Highlights ........................................................................... 1 Thermal Characteristics ...............................................................9 Revision History ............................................................................... 2 ESD Caution...................................................................................9 General Description ......................................................................... 3 Pin Configuration and Function Descriptions........................... 10 Specifications..................................................................................... 4 Outline Dimensions ....................................................................... 11 DC Specifications ......................................................................... 4 Ordering Guide .......................................................................... 11 AC Specifications.......................................................................... 5 REVISION HISTORY 3/16—Rev. A to Rev. B Change to Product Highlights ........................................................ 1 Changes to General Description .................................................... 3 Change to Pipeline Delay (Latency) Parameter, Table 4 ............. 7 Changes to Figure 3 and Table 8 ................................................... 10 1/12—Revision 0: Initial Version 7/12—Rev. 0 to Rev. A Changes to Resolution Parameter, Table 1 and Note 3, Table 1 ........ 4 Rev. B | Page 2 of 12 Enhanced Product AD9266-EP GENERAL DESCRIPTION The AD9266-EP is a monolithic, single-channel 1.8 V supply, 16-bit, 65 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. A differential clock input with a selectable internal 1-to-8 divide ratio controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 65 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The interleaved digital output data is presented in offset binary, gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper latch timing with receiving logic. CMOS levels from 1.8 V through 3.3 V are supported. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9266-EP is available in a 32-lead RoHS compliant LFCSP and is specified over the −55°C to +125°C temperature range. Additional application and technical information can be found in the AD9266 data sheet. Rev. B | Page 3 of 12 AD9266-EP Enhanced Product SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 3 Input Common-Mode Voltage Input Common-Mode Range REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD2 IDRVDD2 (1.8 V) IDRVDD2 (3.3 V) POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power Temp Full Typ Max Unit Bits Full Full 25°C Full 25°C Full 25°C Guaranteed +0.05 −1.3 ±0.30 ±2.6 % FSR % FSR LSB LSB LSB LSB Full ±2 ppm/°C Full 25°C Min 16 −0.9/+1.7 −0.5/+1.0 ±6.5 0.983 0.995 2 1.007 V mV 25°C 2.8 LSB rms 25°C 25°C 25°C Full Full 2 6.5 0.9 V p-p pF V V kΩ Full Full 0.5 1.3 7.5 1.7 1.7 1.8 1.9 3.6 V V Full 25°C 25°C 56.3 5.2 9.3 62.2 mA mA mA 25°C Full 25°C 25°C 25°C 107 111 132 44 0.5 122 Measured with 1.0 V external reference. Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between the differential inputs. 4 Standby power is measured with a dc input and the CLK active. 1 2 Rev. B | Page 4 of 12 mW mW mW mW mW Enhanced Product AD9266-EP AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz TWO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) ANALOG INPUT BANDWIDTH 1 Temp 25°C 25°C Full 25°C 25°C 25°C Full 25°C 25°C 25°C Full 25°C Min Typ Max 77.6 77.4 dBFS dBFS dBFS dBFS 76.5 76.4 77.4 77.2 dBFS dBFS dBFS dBFS 76.0 76.3 12.6 12.5 Bits Bits Bits Bits 12.3 12.4 25°C 25°C Full 25°C −94 −93 25°C 25°C Full 25°C 94 93 Unit −80 −93 dBc dBc dBc dBc dBc dBc dBc dBc 80 93 25°C 25°C Full 25°C −92 −101 −98 dBc dBc dBc dBc 25°C 25°C 90 700 dBc MHz −88 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. B | Page 5 of 12 AD9266-EP Enhanced Product DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (CSB) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 µA High Level Output Voltage, IOH = 0.5 mA Low Level Output Voltage, IOL = 1.6 mA Low Level Output Voltage, IOL = 50 µA DRVDD = 1.8 V High Level Output Voltage, IOH = 50 µA High Level Output Voltage, IOH = 0.5 mA Low Level Output Voltage, IOL = 1.6 mA Low Level Output Voltage, IOL = 50 µA 1 2 Temp Full Full Full Full Full Full Full Min Typ Max Unit 3.6 AVDD + 0.2 +10 +10 12 V V p-p V µA µA kΩ pF CMOS/LVDS/LVPECL 0.9 0.2 GND − 0.3 −10 −10 8 Full Full Full Full Full Full 1.2 0 −50 −10 Full Full Full Full Full Full 1.2 0 −10 40 Full Full Full Full 3.29 3.25 Full Full Full Full 1.79 1.75 10 4 DRVDD + 0.3 0.8 −75 +10 V V µA µA kΩ pF DRVDD + 0.3 0.8 +10 135 V V µA µA kΩ pF 30 2 26 2 Internal 30 kΩ pull-down. Internal 30 kΩ pull-up. Rev. B | Page 6 of 12 0.2 0.05 V V V V 0.2 0.05 V V V V Enhanced Product AD9266-EP SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 CLK Period—Divide by 1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) Wake-Up Time2 Standby OUT-OF-RANGE RECOVERY TIME 2 Min Full Full Full 3 15.38 Typ Max Unit 520 65 Full Full 7.69 1.0 0.1 MHz MSPS ns ns ns ps rms Full Full Full Full Full Full Full 3 3 0.1 8 350 300 2 ns ns ns Cycles μs ns Cycles Conversion rate is the clock rate after the CLK divider. Wake-up time is dependent on the value of the decoupling capacitors. tA N–1 N N+6 N+1 N+7 N+5 VIN N+8 N+2 tCLK N+3 CLK+ CLK– tDCO DCO tSKEW tSKEW D1_D0 D1N–9 D0N–9 D1N–8 D0N–8 D1N–7 D0N–7 D1N–6 D0N–6 D15N–9 D14N–9 D15N–8 D14N–8 D15N–7 D14N–7 D15N–6 D14N–6 D1N–5 D0N–5 D1N–4 D0N–4 tPD D15_D14 D15N–5 D14N–5 Figure 2. CMOS Output Data Timing Rev. B | Page 7 of 12 D15N–4 D14N–4 10476-002 1 Temp AD9266-EP Enhanced Product TIMING SPECIFICATIONS Table 5. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Test Conditions/Comments Min Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Rev. B | Page 8 of 12 Typ Max Unit Enhanced Product AD9266-EP ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/PDWN to AGND MODE/OR to AGND D1_D0 Through D15_D14 to AGND DCO to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −55°C to +125°C The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the circuit board. Soldering the exposed paddle to the board also increases the reliability of the solder joints and maximizes the thermal capability of the package. 150°C Typical θJA is specified for a 4-layer printed circuit board (PCB) with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 7. Thermal Resistance Package Type 32-Lead LFCSP 5 mm × 5 mm Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 37.1 32.4 29.1 θJC1, 3 3.1 θJB1, 4 ΨJT1, 2 20.7 0.3 0.5 0.8 Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 1 2 ESD CAUTION Rev. B | Page 9 of 12 AD9266-EP Enhanced Product 32 31 30 29 28 27 26 25 AVDD VIN+ VIN– AVDD RBIAS VCM SENSE VREF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9266-EP TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AVDD MODE/OR DCO (MSB) D15_D14 D13_D12 D11_D10 D9_D8 D7_D6 NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION ON THE DEVICE. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY, HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH. 10476-003 DNC DNC DNC DNC DRVDD D1_D0 (LSB) D3_D2 D5_D4 9 10 11 12 13 14 15 16 CLK+ CLK– AVDD CSB SCLK/DFS SDIO/PDWN DNC DNC Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 0 Mnemonic EPAD 1, 2 3, 24, 29, 32 4 5 CLK+, CLK− AVDD CSB SCLK/DFS 6 SDIO/PDWN 7 to 12 13 14 to 21 22 23 DNC DRVDD D1_D0 (LSB) to (MSB) D15_D14 DCO MODE/OR 25 26 27 28 30, 31 VREF SENSE VCM RBIAS VIN−, VIN+ Description Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and mechanical strength. Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 1.8 V Supply Pin for ADC Core Domain. SPI Chip Select. Active low enable, 30 kΩ internal pull-up. SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down. Do Not Connect. 1.8 V to 3.3 V Supply Pin for Output Driver Domain. ADC Digital Outputs. Data Clock Digital Output. Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip standby (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode. 1.0 V Voltage Reference Input/Output. Reference Mode Selection. Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. ADC Analog Inputs. Rev. B | Page 10 of 12 Enhanced Product AD9266-EP OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 3.60 SQ 3.55 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 08-16-2010-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 4. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9266TCPZ-65EP AD9266TCPZRL7-65EP 1 Temperature Range −55°C to +125°C −55°C to +125°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. B | Page 11 of 12 Package Option CP-32-12 CP-32-12 AD9266-EP Enhanced Product NOTES ©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10476-0-3/16(B) Rev. B | Page 12 of 12