REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 13-01-10 4 A REV 5 6 7 8 9 10 11 12 13 14 15 16 17 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, DIGITAL-LINEAR, 16 BIT, 65 MSPS, 1.8 V ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE AMSC N/A 3 CODE IDENT. NO. DWG NO. V62/12660 16236 PAGE 1 OF 17 5962-V001-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16 bit, 65 million samples per second (MSPS), 1.8 V analog to digital converter microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12660 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function AD9266 16 bit, 65 MSPS, 1.8 V analog to digital converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 32 JEDEC PUB 95 Package style MO-220-WHHD-5 Thin quad chip carrier 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 2 1.3 Absolute maximum ratings. 1/ Analog voltage 1.8 V (AVDD) to analog ground (AGND) .......................................................... -0.3 V to +2.0 V Voltage supply for driver domain (DRVDD) to AGND ............................................................... -0.3 V to +3.9 V Positive analog input (+VIN), negative analog input (-VIN) to AGND ........................................ -0.3 V to AVDD + 0.2 V Clock input (+CLK), clock input (-CLK) to AGND ..................................................................... -0.3 V to AVDD + 0.2 V Reference voltage (VREF) to AGND ......................................................................................... -0.3 V to AVDD + 0.2 V Reference selection (SENSE) to AGND ................................................................................... -0.3 V to AVDD + 0.2 V Analog output voltage (VCM) to AGND .................................................................................... -0.3 V to AVDD + 0.2 V Set analog current bias (RBIAS) to AGND ............................................................................... -0.3 V to AVDD + 0.2 V Serial port interface (SPI) chip select (CSB) to AGND ............................................................. -0.3 V to DRVDD + 0.3 V SPI clock input (SCLK) / data format selection (DFS) to AGND ............................................... -0.3 V to DRVDD + 0.3 V SPI data input/output (SDIO) / non-SPI mode power down (PDWN) to AGND ........................ -0.3 V to DRVDD + o.3 V Chip mode select input (MODE) / out of range digital output in SPI mode (OR) to AGND ....... -0.3 V to DRVDD + 0.3 V ADC digital outputs (D1_D0 through D15_D14) to AGND ....................................................... -0.3 V to DRVDD + 0.3 V Data clock digital output (DCO) to AGND ................................................................................ -0.3 V to DRVDD + 0.3 V Maximum junction temperature under bias (TJ) ....................................................................... 150°C Storage temperature range (TSTG) .......................................................................................... -65°C to +150°C 1.4 Recommended operating conditions. 2/ Operating free-air temperature range (TA) ............................................................................... -55°C to +125°C 1.5 Thermal characteristics. Thermal metric Symbol Airflow velocity 1/ 2/ 3/ 4/ 5/ 6/ Case X Unit 0 1.0 2.5 m/sec Thermal resistance, junction-to-ambient 3/ 4/ θJA 37.1 32.4 29.1 °C/W Thermal resistance, junction-to-case 3/ 5/ θJC 3.1 --- --- °C/W Thermal resistance, junction-to-board 3/ 6/ θJB 20.7 --- --- °C/W Characterization parameter, junction-to-top 3/ 4/ ψJT 0.3 0.5 0.8 °C/W Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Per JEDEC JESD51-7 plus JEDEC JESD 51-5 test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD 51-6 (moving air). Per MIL-STD-883, method 1021, thermal characteristics. Per JEDEC JESD 51-8 (still air). DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 EIA/JEDEC 51-5 - EIA/JEDEC 51-6 EIA/JEDEC 51-7 EIA/JEDEC 51-8 - Registered and Standard Outlines for Semiconductor Devices Extension of Thermal Conductivity Test Board Standards for Packages with Direct Thermal Attachment Mechanisms Integrated Circuit Thermal Test Method Environmental Conditions – Forced Convection (Moving Air) High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. (Copies of these documents are available online at https://assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 CMOS output data timing waveforms. The CMOS output data timing waveforms shall be as shown in figure 3. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max DC specifications. Resolution -55°C to +125°C 01 16 Bits No missing codes -55°C to +125°C 01 Guaranteed Offset error -55°C to +125°C 01 +25°C 01 -1.3 typical %FSR +25°C 01 -0.5/+1.0 typical LSB Accuracy. Gain error 3/ Differential 4/ nonlinearity error DNL ±0.30 -0.9/ +1.7 -55°C to +125°C Integral nonlinearity 4/ INL +25°C error ±2.6 typical 01 LSB ±6.5 -55°C to +125°C Offset error temperature drift %FSR ±2 typical -55°C to +125°C 01 ppm/ °C -55°C to +125°C 01 +25°C 01 2 typical mV +25°C 01 2.8 typical LSB rms +25°C 01 2 typical VPP +25°C 01 6.5 typical pF Input common mode voltage +25°C 01 0.9 typical V Input common mode range -55°C to +125°C 01 Internal voltage reference. Output voltage 1 V mode Load regulation error at 1.0 mA 0.983 1.007 V Input referred noise Input referred noise VREF = 1.0 V Analog input. Input span, VREF = 1.0 V Input capacitance 5/ CIN 0.5 1.3 V See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Reference input resistance -55°C to +125°C 01 Unit Max 7.5 typical kΩ Power supplies. Supply voltage for ADC core domain AVDD -55°C to +125°C 01 1.7 1.9 V Supply voltage for output driver domain DRVDD -55°C to +125°C 01 1.7 3.6 V Supply current for 4/ ADC core domain IAVDD -55°C to +125°C 01 62.2 mA Supply current for 4/ for output driver domain IDRVDD At 1.8 V +25°C 01 5.2 typical mA Supply current for 4/ for output driver domain IDRVDD At 3.3 V +25°C 01 9.3 typical mA +25°C 01 107 typical mW DRVDD = 1.8 V -55°C to +125°C 01 DRVDD = 3.3 V +25°C Power consumption. DC input Sine wave input 4/ 122 mW 132 typical Standby power 6/ +25°C 01 44 typical mW Power down power. +25°C 01 0.5 typical mW fIN = 9.7 MHz +25°C 01 77.6 typical dBFS fIN = 30.5 MHz +25°C AC specification Signal to noise ratio SNR 77.4 typical 76.5 -55°C to +125°C Signal to noise and distortion SINAD fIN = 70 MHz +25°C fIN = 9.7 MHz +25°C fIN = 30.5 MHz +25°C 76.4 typical 01 -55°C to +125°C +25°C fIN = 70 MHz 77.4 typical dBFS 77.2 typical 76.0 76.3 typical See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max AC specification – continued. Effective number of bits ENOB fIN = 9.7 MHz +25°C fIN = 30.5 MHz +25°C 01 Worst second or third harmonic +25°C fIN = 9.7 MHz +25°C fIN = 30.5 MHz +25°C 12.3 12.4 typical 01 -94 typical Spurious free dynamic range SFDR +25°C fIN = 9.7 MHz +25°C fIN = 30.5 MHz +25°C -80 -93 typical 01 Worst other (harmonic or spur) +25°C fIN = 9.7 MHz +25°C fIN = 30.5 MHz +25°C Two tone SFDR +25°C fIN = 30.5 MHz (-7 dBFS) +25°C dBc 80 93 typical 01 -92 typical dBFS -101 typical -88 -55°C to +125°C fIN = 70 MHz 94 typical 93 typical -55°C to +125°C fIN = 70 MHz dBc -93 typical -55°C to +125°C fIN = 70 MHz Bits 12.5 typical -55°C to +125°C fIN = 70 MHz 12.6 typical -98 typical 01 90 typical dBc 90 typical fIN = 32.5 MHz (-7 dBFS) Analog input bandwidth +25°C 01 700 typical MHz See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Digital specifications. Differential clock inputs (+CLK, -CLK) Logic compliance CMOS / LVDS / LVPECL Internal common mode bias -55°C to +125°C 01 0.9 typical V Differential input voltage -55°C to +125°C 01 0.2 3.6 VPP Input voltage range -55°C to +125°C 01 GND – 0.3 AVDD + 0.2 V High level input current IIL -55°C to +125°C 01 -10 +10 µA Low level input current IIH -55°C to +125°C 01 -10 +10 µA Input resistance RIN -55°C to +125°C 01 8 12 kΩ Input capacitance CIN +25°C 01 4 typical pF Logic inputs (SCLK/DFS, MODE, SDIO/PDWN). 7/ High level input voltage VIH -55°C to +125°C 01 1.2 DRVDD + 0.3 V Low level input voltage VIL -55°C to +125°C 01 0 0.8 V High level input current IIH -55°C to +125°C 01 -50 -75 µA Low level input current IIL -55°C to +125°C 01 -10 +10 µA Input resistance RIN -55°C to +125°C 01 30 typical kΩ Input capacitance CIN -55°C to +125°C 01 2 typical pF See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Uni t Min Max Digital specifications – continued. Logic inputs (CSB) 8/ High level input voltage VIH -55°C to +125°C 01 1.2 DRVDD + 0.3 V Low level input voltage VIL -55°C to +125°C 01 0 0.8 V High level input current IIH -55°C to +125°C 01 -10 +10 µA Low level input current IIL -55°C to +125°C 01 40 135 µA Input resistance RIN -55°C to +125°C 01 26 typical kΩ Input capacitance CIN -55°C to +125°C 01 2 typical pF -55°C to +125°C 01 Digital outputs High level output voltage VOH DRVDD = 3.3 V, IOH = 50 µA VOL -55°C to +125°C DRVDD = 3.3 V, IOL = 1.6 mA 01 0.2 VOH DRVDD = 1.8 V, IOH = 50 µA -55°C to +125°C 01 VOL 1.79 V 1.75 DRVDD = 1.8 V, IOH = 0.5 mA Low level output voltage V 0.05 DRVDD = 3.3 V, IOL = 50 µA High level output voltage V 3.25 DRVDD = 3.3 V, IOH = 0.5 mA Low level output voltage 3.29 -55°C to +125°C DRVDD = 1.8 V, IOL = 1.6 mA 01 0.2 V 0.05 DRVDD = 1.8 V, IOL = 50 µA See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 9 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Switching specifications. Clock input parameters. Input clock rate -55°C to +125°C 01 Conversion rate 9/ -55°C to +125°C 01 3 15.38 520 MHz 65 MSPS CLK period divide by 1 mode tCLK -55°C to +125°C 01 ns CLK pulse width high tCH +25°C 01 7.69 typical ns Aperture delay tA -55°C to +125°C 01 1.0 typical ns Aperture uncertainty jitter tJ -55°C to +125°C 01 0.1 typical ps rms Data propagation delay tPD -55°C to +125°C 01 3 typical ns DCO propagation delay tDCO -55°C to +125°C 01 3 typical ns DCO to data skew tSKEW -55°C to +125°C 01 0.1 typical ns Pipeline delay Latency -55°C to +125°C 01 9 typical Cycles Wake up time 10/ -55°C to +125°C 01 350 typical µs Standby -55°C to +125°C 01 300 typical ns Out of range recovery time -55°C to +125°C 01 2 typical Cycles Data output parameters Timing specifications. SPI timing requirements. Setup time between the data and the rising edge of SCLK tDS -55°C to +125°C 01 2 ns Hold time between the data and the rising edge of SCLK tDH -55°C to +125°C 01 2 ns Period of the SCLK tCLK -55°C to +125°C 01 40 ns See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 10 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Timing specifications - continued. SPI timing requirements - continued. Setup time between CSB and SCLK tS -55°C to +125°C 01 2 ns Hold time between CSB and SCLK tH -55°C to +125°C 01 2 ns SCLK pulse width high tHIGH -55°C to +125°C 01 10 ns SCLK pulse width low tLOW -55°C to +125°C 01 10 ns Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge tEN_SDIO -55°C to +125°C 01 10 ns Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge tDIS_SDIO -55°C to +125°C 01 10 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 VPP differential input, 1.0 V internal reference, AIN = -1.0 dBFS, 50 % duty cycle clock, and DCS disabled. 3/ Measured with 1.0 V external reference. 4/ Measured with a 10 MHz input frequency at rated sample rate, full scale sine wave, with approximately 5 pF loading on each output bit. 5/ Input capacitance refers to the effective capacitance between the differential inputs. 6/ Standby power is measured with a dc input and the CLK active. 7/ Internal 30 kΩ pull down. 8/ Internal 30 kΩ pull up. 9/ Conversion rate is the clock rate after the CLK divider. 10/ Wake up time is dependent on the value of the decoupling capacitors. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 11 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 12 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A .027 .031 0.70 0.80 A1 .0007 .001 0.02 0.05 A2 .007 REF 0.20 REF b .007 .011 0.18 0.30 D/E .192 .200 4.90 5.10 D1/E1 .139 .147 3.55 3.75 L .011 .019 0.30 0.50 L1 .009 --- 0.25 --- NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. For proper connection of the exposed pad, refer to the pin configuration and function descriptions section of the manufacturer’s datasheet. 3. Falls within reference to JEDEC MO-220-WHHD-5. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 13 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 +CLK 17 D7_D6 2 -CLK 18 D9_D8 3 AVDD 19 D11_D10 4 CSB 20 D13_D12 5 SCLK/DFS 21 (MSB) D15_D14 6 SDIO/PDWN 22 DCO 7 NC 23 MODE/OR 8 NC 24 AVDD 9 NC 25 VREF 10 NC 26 SENSE 11 NC 27 VCM 12 NC 28 RBIAS 13 DRVDD 29 AVDD 14 D1_D0 (LSB) 30 -VIN 15 D3_D2 31 +VIN 16 D5_D4 32 AVDD NOTES: 1. NC = no connect. Do not connect to this pin. 2. The exposed paddle (pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 14 Terminal symbol Description Exposed pad AGND. The exposed paddle is the only ground connection on the chip. It must be soldered to the analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. +CLK, -CLK Differential encode clock for PECL, LVDS, or 1.8 V CMOS inputs. AVDD 1.8 V supply pin for ADC core domain. CSB SPI chip select. Active low enable, 30 kΩ internal pull up. SCLK/DFS SDIO/PDWN NC D1_D0 (LSB) to (MSB) D15_D14 DRVDD DCO MODE/OR VREF SENSE VCM RBIAS -VIN, +VIN SPI clock input in SPI mode (SCLK). 30 kΩ internal pull down. Data format select in non-SPI mode (DFS). Static control of data output format. 30 kΩ internal pull down. DFS high = twos complement output; DFS low = offset binary output. SPI data input/output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull down. Non-SPI mode power down (PDWN). Static control chip power down with 30 kΩ internal pull down. No connect. Do not connect to this pin. ADC digital outputs. 1.8 V to 3.3 V supply pin for output driver domain. Data clock digital output. Chip mode select input (MODE)/out of range digital output in SPI mode (OR). Default = out of range (OR) digital output (SPI register 0x2A, bit 0 = 1). Option = chip mode select input (SPI register 0x2A, bit 0 = 0). Chip power down (SPI register 0x08, bits[7:5] = 100b). Chip standby (SPI register 0x08, bits[7:5] = 101b). Normal operation, output disabled (SPI register 0x08, bits[7:5] = 110b). Normal operation, output enabled (SPI register 0x08, bits[7:5} = 111b). Out of range (OR) digital output only in non-SPI mode. 1.0 V voltage reference input/output. Reference mode selection. Analog output voltage at mid AVDD supply. Sets common mode of the analog inputs. Set analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground. ADC analog inputs. FIGURE 2. Terminal connections - continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 15 FIGURE 3. CMOS output data timing waveforms. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 16 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12660-01XE 24355 AD9266TCPZ-65-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices Route 1 Industrial Park P.O. Box 9106 Norwood, MA 02062 Point of contact: Raheen Business Park Limerick, Ireland SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12660 PAGE 17