UG 386

Evaluation Board User Guide
UG-386
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the AD9642/AD9634/AD6672 Analog-to-Digital Converters
FEATURES
DOCUMENTS NEEDED
Full featured evaluation board for the
AD9642/AD9634/AD6672
SPI interface for setup and control
External or AD9523 clocking option
Balun/transformer or amplifier input drive option
LDO regulator power supply
VisualAnalog and SPI controller software interfaces
AD9642, AD9634, or AD6672 data sheet
HSC-ADC-EVALCZ data sheet
AN-905 Application Note, VisualAnalog Converter Evaluation
Tool Version 1.0 User Manual
AN-878 Application Note, High Speed ADC SPI Control Software
AN-877 Application Note, Interfacing to High Speed ADCs via SPI
AN-835 Application Note, Understanding ADC Testing and
Evaluation
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
Sample clock source (if not using the on-board oscillator)
2 switching power supplies (6.0 V, 2.5 A), CUI
EPS060250UH-PHP-SZ, provided
PC running Windows® 98 (2nd ed.), Windows 2000,
Windows ME, or Windows XP
USB 2.0 port recommended (USB 1.1 compatible)
AD9642, AD9634, or AD6672 evaluation board
HSC-ADC-EVALCZ FPGA-based data capture kit
SOFTWARE NEEDED
VisualAnalog
SPI controller
GENERAL DESCRIPTION
This user guide describes the AD9642, AD9634, and AD6672
evaluation board, which provides all of the support circuitry
required to operate the AD9642, AD9634, and AD6672 in their
various modes and configurations. The application software
used to interface with the devices is also described.
The AD9642, AD9634, and AD6672 data sheets provide
additional information and should be consulted when using the
evaluation board. All documents and software tools are available at
http://www.analog.com/fifo. For additional information or
questions, send an email to [email protected].
10593-001
TYPICAL MEASUREMENT SETUP
Figure 1. AD9642, AD9634, or AD6672 Evaluation Board (on Left) and HSC-ADC-EVALCZ Data Capture Board (on Right)
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 28
UG-386
Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Signals ...............................................................................4
Equipment Needed ........................................................................... 1
Default Operation and Jumper Selection Settings ....................4
Software Needed ............................................................................... 1
Evaluation Board Software Quick Start Procedures .....................6
Documents Needed .......................................................................... 1
Configuring the Board .................................................................6
General Description ......................................................................... 1
Using the Software for Testing.....................................................6
Typical Measurement Setup ............................................................ 1
Evaluation Board Schematics and Artwork ................................ 14
Revision History ............................................................................... 2
Ordering Information .................................................................... 23
Evaluation Board Hardware ............................................................ 3
Bill of Materials ........................................................................... 23
Power Supplies .............................................................................. 3
Related Links ................................................................................... 25
Input Signals .................................................................................. 3
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Evaluation Board User Guide
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EVALUATION BOARD HARDWARE
The evaluation board can be powered in a nondefault condition
using external bench power supplies. To do this, remove the
jumpers on the P104, P107, P108, and P105 header pins to
disconnect the outputs from the on-board LDOs. This enables the
user to bias each section of the board individually. Use P202
and P203 to connect a different supply for each section. A 1.8 V
supply is needed with a 1 A current capability for DUT_AVDD and
DRVDD; however, it is recommended that separate supplies be
used for both analog and digital domains. An additional supply
is also required to supply 1.8 V for digital support circuitry on
the board, DVDD. This should also have a 1 A current capability
and can be combined with DRVDD with little or no degradation
in performance. To operate the evaluation board using the SPI
and alternate clock options, a separate 3.3 V analog supply is
needed in addition to the other supplies. This 3.3 V supply, or
3P3V_ANALOG, should have a 1 A current capability. This
3.3 V supply is also used to support the optional input path
amplifier (ADL5201) on Channel A and Channel B.
The AD9642, AD9634, and AD6672 evaluation board provides
all of the support circuitry required to operate these parts in
their various modes and configurations. Figure 2 shows the
typical bench characterization setup used to evaluate the ac
performance of the AD9642, AD9634, or AD6672. It is critical
that the signal sources used for the analog input and the clock
have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the
analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve
the specified noise performance.
See the Evaluation Board Software Quick Start Procedures section
to get started, and see Figure 19 to Figure 30 for the complete
schematics and layout diagrams. These diagrams demonstrate
the routing and grounding techniques that should be applied at
the system level when designing application boards using these
converters.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2.5 A maximum output. Connect
the supply to a rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output from the supply is provided through a
2.1 mm inner diameter jack that connects to the printed circuit
board (PCB) at P201. The 6 V supply is fused and conditioned
on the PCB before connecting to the low dropout linear regulators
(default configuration) that supply the proper bias to each of the
various sections on the board.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA or HP 8644B signal generators or an equivalent. Use a 1 m
shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired frequency and amplitude (see the
Specifications section in the data sheet of the respective part).
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
SWITCHING
POWER
SUPPLY
6V DC
2.5A MAX
SIGNAL
SYNTHESIZER
6V DC
2.5A MAX
ANALOG
FILTER
OPTIONAL CLOCK SOURCE
Figure 2. Evaluation Board Connection
Rev. 0 | Page 3 of 28
10593-002
SIGNAL
SYNTHESIZER
PC
RUNNING ADC
ANALYZER
OR VISUAL ANALOG
USER SOFTWARE
UG-386
Evaluation Board User Guide
When connecting the analog input source, use of a multipole,
narrow-band, band-pass filter with 50 Ω terminations is recommended. Analog Devices, Inc., uses TTE and K&L Microwave,
Inc., band-pass filters. The filters should be connected directly
to the evaluation board.
If an external clock source is used, it should also be supplied
with a clean signal generator as previously specified. Typically,
most Analog Devices evaluation boards can accept ~2.8 V p-p or
13 dBm sine wave input for the clock.
included on the evaluation board at U401. However, the path into
and out of the ADL5201 can be configured in many different
ways depending on the application; therefore, the parts in the
input and output path are left unpopulated. See the ADL5201
data sheet for additional information on this part and for
configuring the inputs and outputs. The ADL5201, by default,
is held in power-down mode but can be enabled by adding 1 kΩ
resistors at R427 and R428 to enable Channel A and Channel B,
respectively.
Clock Circuitry
OUTPUT SIGNALS
The default setup uses the Analog Devices high speed converter
evaluation platform (HSC-ADC-EVALCZ) for data capture. The
output signals from Channel A and Channel B for the AD9642,
AD9634, and AD6672 are routed through P601 and P602,
respectively, to the FPGA on the data capture board.
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
This section explains the default and optional settings or modes
allowed on the AD9642/AD9634/AD6672 evaluation board.
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P201.
Analog Input
The A and B channel inputs on the evaluation board are set up for a
double balun-coupled analog input with a 50 Ω impedance. This
input network is optimized to support a wide frequency band. See
the AD9642, AD9634, and AD6672 data sheets for additional
information on the recommended networks for different input
frequency ranges. The nominal input drive level is 10 dBm to
achieve 2 V p-p full scale into 50 Ω. At higher input frequencies,
slightly higher input drive levels are required due to losses in the
front-end network.
The default clock input circuit that is populated on the AD9642/
AD9634/AD6672 evaluation board uses a simple transformercoupled circuit with a high bandwidth 1:1 impedance ratio
transformer (T503) that adds a very low amount of jitter to the
clock path. The clock input is 50 Ω terminated and ac-coupled
to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal
that is clipped by CR503 before entering the ADC clock inputs.
The board is set by default to use an external clock generator. An
external clock source capable of driving a 50 Ω terminated input
should be connected to J506.
A differential LVPECL clock driver output can also be used to
clock the ADC input using the AD9523 (U501). To place the
AD9523 into the clock path, populate R541 and R542 with 0 Ω
resistors and remove C532 and C533 to disconnect the default
clock path inputs. In addition, populate R533 and R534 with
0 Ω resistors, remove R522 and R523 to disconnect the default
clock path outputs, and insert AD9523 LVPECL Output 2. The
AD9523 must be configured through the SPI controller software to
set up the PLL and other operation modes. Consult the AD9523
data sheet for more information about these and other options.
PDWN
To enable the power-down feature, Bits[1:0] of Register 0x08 must
be written for the desired power-down mode.
OEB
Optionally, Channel A and Channel B inputs on the board can
be configured to use the ADL5201 digitally controlled, variable
gain wide bandwidth amplifier. The ADL5201 component is
To disable the digital output pins and place them in a high impedance state, Bit 4 of Register 0x14 must be written.
3.9pF
2V p-p
15Ω
0.1µF
49.9Ω
VIN+
36Ω
PA
S
S
P
3.9pF
0.1µF
36Ω
0.1µF
AD9642/AD9634/
AD6672
15Ω
VIN–
VCM
Figure 3. Default Analog Input Configuration of the AD9642/AD9634/AD6672
Rev. 0 | Page 4 of 28
10593-003
49.9Ω
3.9pF
Evaluation Board User Guide
UG-386
Switching Power Supply
Optionally, the ADC on the board can be configured to use the
ADP2114 dual switching power supply to provide power to the
DRVDD and AVDD rails of the ADC. To configure the board
to operate from the ADP2114, the following changes must be
incorporated (see the Evaluation Board Schematics and Artwork
and the Bill of Materials sections for specific recommendations
for part values):
1.
2.
Install R204 and R221 to enable the ADP2114.
Install R216 and R218.
3.
4.
5.
6.
Install L201 and L202.
Remove JP201 and JP203.
Remove jumpers from across Pin 1 and Pin 2 on P107 and
P108, respectively.
Place jumpers across Pin 1 and Pin 2 of P106 and P109,
respectively.
Making these changes enables the switching converter to power
the ADC. Using the switching converter as the ADC power
source is more efficient than using the default LDOs.
Rev. 0 | Page 5 of 28
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Evaluation Board User Guide
EVALUATION BOARD SOFTWARE QUICK START PROCEDURES
This section provides quick start procedures for using the AD9642/
AD9634/AD6672 evaluation board. Both the default and
optional settings are described.
CONFIGURING THE BOARD
3.
4.
5.
6.
7.
Figure 4. VisualAnalog, New Canvas Window
2.
USING THE SOFTWARE FOR TESTING
Figure 5. VisualAnalog Default Configuration Message
Setting Up the ADC Data Capture
After configuring the board, set up the ADC data capture using
the following steps:
1.
After the template is selected, a message appears asking if
the default configuration can be used to program the FPGA
(see Figure 5). Click Yes, and the window closes.
10593-005
2.
Connect the evaluation board to the data capture board, as
shown in Figure 1 and Figure 2.
Connect one 6 V, 2.5 A switching power supply (such as
the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to
the AD9642/AD9634/AD6672 board.
Connect another 6 V, 2.5 A switching power supply (such
as the CUI EPS060250UH-PHP-SZ that is supplied) to the
HSC-ADC-EVALCZ board.
Connect the HSC-ADC-EVALCZ board (J6) to the PC
with a USB cable.
On the ADC evaluation board, confirm that jumpers are
installed on the P105, P108, P104, P107, and P110 headers.
Connect a low jitter sample clock to Connector J506.
Use a clean signal generator with low phase noise to provide
an input signal to the desired channel(s) at Connector J301
(Channel A) and/or Connector J303 (Channel B). Use a
1 m, shielded, RG-58, 50 Ω coaxial cable to connect the
signal generator. For best results, use a narrow-band bandpass filter with 50 Ω terminations and an appropriate
center frequency. (Analog Devices uses TTE, Allen Avionics,
and K&L band-pass filters.)
3.
Open VisualAnalog® on the connected PC. The appropriate part type should be listed in the status bar of the
VisualAnalog – New Canvas window. Select the template
that corresponds to the type of testing to be performed
(see Figure 4 where the AD9642 is shown as an example).
The AD9642 is given as an example in this user guide.
Similar settings are used for the AD9634. For the AD6672,
the differences are noted where necessary in the steps
that follow.
To change features to settings other than the default settings,
click the Expand Display button, located on the bottom
right corner of the window (see Figure 6) to see what is
shown in Figure 7.
Detailed instructions for changing the features and capture
settings can be found in the AN-905 Application Note,
VisualAnalog™ Converter Evaluation Tool Version 1.0 User
Manual. After the changes are made to the capture settings,
click the Collapse Display button.
EXPAND DISPLAY BUTTON
Figure 6. VisualAnalog Window Toolbar, Collapsed Display
Rev. 0 | Page 6 of 28
10593-006
1.
10593-004
Before using the software for testing, configure the evaluation
board as follows:
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10593-007
Evaluation Board User Guide
Figure 7. VisualAnalog, Main Window
Setting Up the SPI Controller Software
After the ADC data capture board setup is complete, set up the
SPI controller software using the following procedure:
Open the SPI controller software by going to the Start menu
or by double-clicking the SPIController software desktop
icon. If prompted for a configuration file, select the appropriate
one. If not, check the title bar of the window to determine
which configuration is loaded. If necessary, choose Cfg
Open from the File menu and select the appropriate file
based on your part type. Note that the CHIP ID(1) section
should be filled to indicate whether the correct SPI
controller configuration file is loaded (see Figure 8).
10593-008
1.
Figure 8. SPI Controller, CHIP ID(1) Section
Rev. 0 | Page 7 of 28
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2.
Evaluation Board User Guide
4.
Click the New DUT button in the SPIController window
(see Figure 9).
10593-009
NEW DUT BUTTON
In the ADCBase 0 tab of the SPIController window, find the
OUTPUT DELAY(17) box. Select the DCO Clk Delay
Enable checkbox to enable this feature. In the drop-down box,
select 600 ps additional delay on DCO pin. These settings
align the output timing with the input timing on the
capture FPGA.
Note that other settings can be changed on the ADCBase 0
tab (see Figure 11). See the appropriate part data sheet; the
AN-878 Application Note, High Speed ADC SPI Control
Software; and the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, for additional information on
the available settings.
Figure 9. SPI Controller, New DUT Button
In the ADCBase 0 tab of the SPIController window, find the
CLK DIV(B) section (see Figure 11). If using the clock
divider, use the drop-down box to select the correct clock
divide ratio, if necessary. See the appropriate part data sheet;
the AN-878 Application Note, High Speed ADC SPI Control
Software; and the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, for additional information.
10593-010
3.
Figure 10. SPI Controller, Example ADCBase 0 Tab
Rev. 0 | Page 8 of 28
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10593-011
Evaluation Board User Guide
Figure 11. SPI Controller, CLK DIV(B) Section
Rev. 0 | Page 9 of 28
Evaluation Board User Guide
10593-012
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Figure 12. SPI Controller, Example ADCBase 0 Tab—NSR Settings for the AD6672
If using the noise shaping requantizer (NSR) feature of the
AD6672, the settings in the ADCBase 0 tab must be
changed (see Figure 12). The NSR Enable checkbox must
be selected under the NOISE SHAPED REQUANTIZER
1(3C) section. This enables the circuitry in the AD6672.
To select the bandwidth mode, use the NSR Mode dropdown box in the NOISE SHAPED REQUANTIZER 1(3C)
section. Upon selecting the bandwidth mode, select the
desired tuning word in the NSR Tuning drop-down menu
under the NOISE SHAPED REQUANTIZER TUNING(3E)
section.
6.
Rev. 0 | Page 10 of 28
Click the Run button in the VisualAnalog toolbar (see
Figure 13).
10593-013
5.
Figure 13. Run Button (Encircled in Red) in VisualAnalog Toolbar,
Collapsed Display
Evaluation Board User Guide
UG-386
Adjusting the Amplitude of the Input Signal
0
250MSPS
90.1MHz @ –1dBFS
–20 SNR = 71dB (72dBFS)
SFDR = 89dBc
–40
THIRD HARMONIC
–60
SECOND HARMONIC
–80
–100
–120
–140
0
25
50
75
100
125
FREQUENCY (MHz)
Figure 14. Typical FFT, AD9642
Figure 15. Graph Window of VisualAnalog (AD9642)
Rev. 0 | Page 11 of 28
10593-014
2.
3.
Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading
in the left panel of the VisualAnalog Graph window.) See
Figure 15.
Repeat this procedure for Channel B if desired.
Click the Save disk icon within the Graph window to save
the performance plot data as a .csv formatted file. See
Figure 14 for an example.
10593-015
1.
AMPLITUDE (dBFS)
The next step is to adjust the amplitude of the input signal for
each channel as follows:
UG-386
If operating the AD6672 with NSR enabled, certain options
in VisualAnalog must be enabled. Click the button circled
in the FFT Analysis box (see Figure 16) in VisualAnalog to
bring up the options for setting the NSR.
10593-016
4.
Evaluation Board User Guide
Figure 16. VisualAnalog, Main Window—Showing FFT Analysis for AD6672
Rev. 0 | Page 12 of 28
Evaluation Board User Guide
5.
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Troubleshooting Tips
Configure the settings in the FFT analysis to match the
settings selected for the NSR in the SPI controller (see
Figure 17).
If the FFT plot appears abnormal, do the following:
•
•
If you see a normal noise floor when you disconnect the
signal generator from the analog input, be sure that you
are not overdriving the ADC. Reduce the input level if
necessary.
In VisualAnalog, click the Settings button in the Input
Formatter block (see Figure 7). Check that Number
Format in the settings of the Input Formatter block is set
to the correct encoding (offset binary by default). Repeat
for the other channel.
If the FFT appears normal but the performance is poor, check
the following:
10593-017
•
Figure 17. VisualAnalog, FFT Analysis Settings for AD6672
6.
•
•
The result should show an FFT plot that looks similar to
Figure 18.
•
Make sure that an appropriate filter is used on the
analog input.
Make sure that the signal generators for the clock and the
analog input are clean (low phase noise).
Change the analog input frequency slightly if noncoherent
sampling is being used.
Make sure that the SPI configuration file matches the
product being evaluated.
If the FFT window remains blank after Run (see Figure 13) is
clicked, do the following:
•
•
10593-018
•
Figure 18. Graph Window of VisualAnalog, NSR Enabled, AD6672
7.
8.
The amplitude shows approximately 0.6 dB lower than
when the NSR is disabled. The NSR circuitry introduces
this loss. An amplitude of −1.6 dBFS with NSR enabled
is analogous to an amplitude of −1.0 dBFS with NSR
disabled.
Make sure that the evaluation board is securely connected
to the HSC-ADC-EVALCZ board.
Make sure that the FPGA has been programmed by
verifying that the DONE LED is illuminated on the HSCADC-EVALCZ board. If this LED is not illuminated, make
sure that the U4 switch on the board is in the correct
position for USB CONFIG.
Make sure that the correct FPGA program was installed by
clicking the Settings button in the ADC Data Capture
block in VisualAnalog. Then select the FPGA tab and
verify that the proper FPGA bin file is selected for the part.
If VisualAnalog indicates that the data capture timed out, do the
following:
•
•
Repeat Step 3 to save the graph in a .csv file format.
Rev. 0 | Page 13 of 28
Make sure that all power and USB connections are secure.
Probe the DCO signal at the ADC on the evaluation board
and confirm that a clock signal is present at the ADC
sampling rate.
DRVDD
D2/D3+
D2/D3-
D0/D1+
D0/D1-
D4/D5-
CLK-
D4/D5+
AVDD
AVDD
D6/D7-
1
2
3
4
5
6
7
8
VIN+
D6/D7+
CLK+
VIN-
D8/D9-
C105
0.1UF
D8/D9+
VCM
AVDD
DRVDD
D12/D13-
D12/D13+
DCO-
DCO+
DUT_SDIO
DUT_SCLK
DUT_CSB
SG-MLF32A-7004
24
23
22
21
20
19
18
17
U1010
KP_VDDIO
1
TP_KPIBIAS
THE FOOTPRINT FOR THIS SOCKED NEEDS TO BE CHECKED AGAINST THE DRAWING
DUT
AD9642/AD9634 ENG (SOCKET)
VCM
PAD
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
D10/D11-
Rev. 0 | Page 14 of 28
D10/D11+
Figure 19. Device Under Test and Related Circuits
TP103
1
TP102
1
TP101
1
C109
0.1UF
1
TP104
C110
0.1UF
AVDD
C111
0.1UF
1
TP105
C112
0.1UF
C107
1UF
C103
0.1UF
C113
0.1UF
C122
1UF
ADD 1UF AT DUT PIN #3
C101
0.1UF
DRVDD
C117
1UF
C121
1UF
C118
1UF
LAYOUT: DECOUPLING QUANTITY MAY VARY LAYOUT DEPENDI
10593-019
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Evaluation Board User Guide
EVALUATION BOARD SCHEMATICS AND ARTWORK
VIN
R209
27K
VIN
DNI
0
R204
DNI
0
R221
R211
15K
R210
4.64K
VIN
CR204
A
C
C210
22UF
EN2
R212
15K
P
VOUTB
EN2
VOUTA
EN1
SW_FREQ
EN1
C201
C211
22UF
C204
C207
F201
1
2
1.1A
SCFG
FREQ
SYNC_CLKOUT
OPCFG
EN1
V1SET
FB1
SS1
EN2
V2SET
FB2
SS2
GND
VDD
0.01UF
0.01UF
S2A-TP
0.01UF
4
EN
NC
2
4
PAD
PGOOD2
COMP2
SW3
SW4
PGOOD1
COMP1
SW1
SW2
2
4.7UF
4
6
5
2
CR202 VIN
A
C
100MHZ
E204
1
2
100MHZ
E202
1
2
13K
R213
R208
100K
C213
100PF
1500PF
C216
C215
100PF
C214
2200PF
261
P104
SK33A-TP
CR203
OPTIONAL
SWITCHING
SUPPLY
ADP2114_PRELIM
U206
R207
100K
GND
U203
ADP150AUJZ-3.3-R7
1
VIN
5
3
VOUT
GND
EN
NC
U202
ADP150AUJZ-3.3-R7
1
VIN
5
VOUT
3
3
1
C206
C209
P105
DNI
R220
TBD0603
DNI
R215
TBD0603
LNJ314G8TRA (GREEN)
DNI
3P3V_ANALOG
R218
0
DNI
DNI
C222
TBD0603
DNI
2.2UH
L202
DNI
C219
TBD0603
DNI
2.2UH
L201
DNI
R216
0
100MHZ
C223
22UF
E211
1
2
C220
22UF
100MHZ
E210
1
2
S2A-TP
S2A-TP
VOUTA
CR206
A
C
E203
1
2
CR205
A
C
3P3V_DIGITAL
C224
22UF
R219
0
VOUTB
C221
22UF
R217
0
C241
JP203
1
2
0
JP201
1
2
0
POWER
2
GND
100MHZ
E208
1
2
C243
2 PAD
EN
SENSE
IN
OUT
IN2
OUT2
SS
GND1 PAD
5
6
4.7UF
1
7
3
4
8
100MHZ
E209
1
2
2 PAD
EN
SENSE
OUT
IN
IN2
OUT2
SS
GND1 PAD
5
6
U205
ADP1706ARDZ-1.8-R7
1
7
3
4
8
U204
ADP1706ARDZ-1.8-R7
4
EN
NC
U207
ADP150AUJZ-1.8-R7
1
VIN
5
3
VOUT
P106
100MHZ
P109
100MHZ
E207
1
2
100MHZ
E205
1
2
E217
1
2
Z5.531.3625.0
P202
1
2
3
4
5
6
P107
P203
P108
1
2
3
4
10UF
P
DRVDD
TO EVALUATE SHARING OF AVDD AND DVDD
100MHZ
E216
1
2
Z5.531.3425.0
AVDD
1P8V_CLOCK
100MHZ
E214
1
2
100MHZ
E213
1
2
C231
C233
C235
PJ-202A
R205
C217
R222
1.00K
1.00K
P110
R201
1
2
1
2
DNI
DNI
10
100MHZ
1
2
3
DNI
4.7UF
C205
4.7UF
C208
R206
1
2
1
2
4.7UF
R214
10.5K
4.7UF
C242
DNI
C225
C228
N
C212
C218
C227
C230
1
2
4.7UF
4.7UF
0.01UF
4.7UF
C226
4.7UF
C229
10UF
1UF
0.01UF
E206
1
2
CR201
A
C
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
PGND1
PGND2
PGND3
PGND4
0.01UF
0.01UF
Figure 20. Board Power Input and Supply
1
2
Rev. 0 | Page 15 of 28
1
2
C239
0.1UF
0.1UF
C232
0.1UF
C234
N
P
N
C236
100MHZ
3P3V_ANALOG
AVDD
DRVDD
3P3V_DIGITAL
10UF
P201
100MHZ
P
N
0.1UF
C240
10UF
10UF
P
N
FL201
BNX016-01
10593-020
E212
1
2
Evaluation Board User Guide
UG-386
Rev. 0 | Page 16 of 28
AIN
1
2 3 4 5
DNI
J302
2 3 4 5
DNI
0
Figure 21. Passive Analog Input Circuits
R309
0
0
DNI
AMP_IN-
R310
0
3
1
T301
DNI
6
2
4
0.1UF
C314
DNI
ADT1-1WT+
4
T302
3
1
SEC
MABA-007159-000000
5
PRI
T303
MABA-007159-000000
SHARE PADS
0.1UF
C306
0.1UF
C305
SHARE PADS
AMP_OUT-
R312
0
DNI
0.1UF
R314
36
VCM
R313
36
C301
R311
0
DNI
AMP_OUT+
R317
49.9
33
R316
R318
49.9
0
R320
0
DNI
R319
L301
33
C302
R315
82NH
LAYOUT: SMA'S SHOULD BE PLACED 540 MILS CENTER TO CENTER
0
R306
DNI
0
DNI
DNI
R305
DNI
R304
49.9
DNI
R301
49.9
R303
0
0
R302
R308
R307
J301
5
1
1
4
3
C303
8.2PF
C304
ANALOG INPUT
PASSIVE PATH
PRI
SEC
8.2PF
8.2PF
AMP_IN+
VIN-
VIN+
UG-386
Evaluation Board User Guide
10593-021
SEC
3
4
T401
PRI
1
MABA-007159-000000
AMP_IN-
AMP_IN+
5
C402
R402
40.2
0.1UF
R401
40.2
0.1UF
R404
DNI
Figure 22. Optional Active Input Circuits
Rev. 0 | Page 17 of 28
PD_N_A
R407
1.1K
1
2
3P3V_ANALOG
0
DNI
R406
0
R405
0
0
R403
12
P401
ADL5562_PRELIM
PD_N_A
ENBL
VIN2
1
VIP2
2
VIP1
3
VIN1
4
GND
VCC
PAD
VCOM
VOP
VON
9
11
10
U401
C404
0.1UF
5
6
7
8
13
14
15
16
PAD
C401
3P3V_ANALOG
C403
0.1UF
DNI
JPR0402
JP401
1
2
N
P
VCM
0 DNI
0 DNI
R409
R408
C405
10UF
DNI
0.1UF
C407
DNI
0.1UF
C406
C408
DNI
120NH
DNI
L404
DNI
C410
5PF
DNI
DNI
DNI
C409
5PF
L403
120NH
120NH
0.1UF
R411
DNI
1.00K
DNI L402
DNI
R410
1.00K
120NH
L401
DNI
0
R412
DNI
AMP_OUT-
82NH
L406
DNI
82NH
L405
AMP_OUT+
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
VCM
10593-022
ACTIVE PATH
Evaluation Board User Guide
UG-386
3
0.1UF
C506
0
R506
49.9
49.9
0.33UF
R505
TBD0402
R507
49.9
0.1UF
C502
0.1UF
C504
PASSIVE CLOCK
DNI
0
R508
0.1UF
C507
0.1UF
2 3 4 5
J506
1
CLK
2 3 4 5
J505
1
DNI
DNI
390PF
C523
390PF
C522
1
DNI
4 0.1UF
T502
ADT1-1WT+
3
6
C529
2
DNI
0
CLK_IN+
0
R523
3 MABA-007159-000000
SEC
PRI
4
1
5
3.3V_REF
R540
33
0
R528
1
3
CR503
2
1
390PF
C533
390PF
1
100
C515
0.1UF
LDO_PLL1
VDD3_PLL1
REFA
REFA_N
REFB
REFB_N
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN_N
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
PD_N
REF_SEL
SYNC_N
VDD3_REF
RESETB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SI04
TP501
CLK-
CLK_OUT-
C516
C518
0.1UF
J503
1
2 3 4 5
DNI
100
R511
MABA-007159-000000
R543
100
DNI
CLK+
CLK_OUT+
TP505
C532
R515
3.3V_OUT_4-13
10K
3.3V_REF
SYNCB
PDB
3.3V_PLL1
3.3V_REF
3.3V_OUT_4-13
10K
TP504
R509
R539
33
3.3V_PLL2
0.47UF
R522
CLK_IN-
0.47UF
T503
C512
C513
0.33UF
0.47UF
C508
49.9
C511
R501
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S
60-800MHZ
Y501
DNI
4
5
R503
R604
C509
1
0.001UF
VC
OUT+
OUTGND
C510
VCXO_CTRL
0.001UF
CLK_IN-
10K
C501
1
R516
VCC
DNI R529
10K
C505
0.1UF 6
49.9
R530
R519
3.3V_PLL1
DNI
R537
R538
R541
C503
49.9
OUT2_N
C517
0.1UF
DNI
5 4 3 2
J502
1
T501
100
CLK_IN+
0
0
0
100
R502
1K
0
DNI
R533DNI
R534
R544
ACTIVE CLOCK PATH
PECL/CML/LVDS CLK CIRCUITRY
DNI
OUT13_N
3
49.9
0 DNI
0 DNI
0.1UF
USB_CSB2
CYP_SCLK
CYP_SDI
CYP_SDO
DNI R520
R545
4
R542
OUT13
3.3V_OUT_4-13
1
SEC
DNI R521
100
AD9523
E502
45OHMS
2
45OHMS
E501
1
2
3P3V_DIGITAL1
3P3V_ANALOG
1P8V_CLOCK
OUT9
OUT9_N
OUT8
OUT8_N
VDD3_OUT8_9
OUT7
OUT7_N
VDD_1_8_OUT8_9
OUT6
OUT6_N
VDD3_OUT6_7
TP503
5
2
Y2
3 A2
4
6
U300
GND
NC7WZ16P6X
Y1
VCC
1 A1
1UH
1UH
L505 3.3V_OUT_4-13
L504 3.3V_OUT_0-3
1UH
1UH
L503 3.3V_PLL1
1UH
L502 3.3V_PLL2
1UH
L501 3.3V_REF
L506 1.8V_OUT_0-13
CR502
3.3V_OUT_0-3
LNJ314G8TRA (GREEN)
200
10K
R518
LNJ314G8TRA (GREEN)
R514
200
R513
10K
R517
CR501
CLK_OUT-
CLK_OUT+
EEPROM_SEL
1.8V_OUT_0-13
54
R546
53
52
100
51 3.3V_OUT_4-13
R526
50
49
100
48
R527
47
3.3V_OUT_4-13
46
100
45
R531
44
43
100
42
R532
41
40
100
39
R535
38
1.8V_OUT_0-13
37
100
DNI
U501
1
1
3.3V_OUT_4-13
C531
12PF
C519 3.3V_OUT_0-3
3.9NH
L507
0.1UF
TP502
0.1UF
C521
STATUS0/SP0
STATUS1/SP1
DNI
VDD_1_8_OUT4_5
OUT4
OUT4_N
VDD3_OUT4_5
OUT5
OUT5_N
VDD_1_8_OUT6_7
R512
C520
C540
R510
100
C535
0.1UF
C541
C514
PAD
0.1UF
72
71
70
69 1.8V_OUT_0-13
68 OUT0
67 OUT0_N
66
65 R524
64 100
63
62
61
60
59 R525
58 100
57
56
55
R536
0.1UF
C536
PAD
PLL1_OUT
ZD_IN_N
ZD_IN
VDD_1_8_OUT0_1
OUT0
OUT0_N
VDD3_OUT0_1
OUT1
OUT1_N
VDD_1_8_OUT2_3
OUT2
OUT2_N
VDD3_OUT2_3
OUT3
OUT3_N
EEPROM_SEL
STATUS0_SP0
STATUS1_SP1
RESET_N
CS_N
SCLK_SCL
SDIO_SDA
SDO
REF_TEST
OUT13_N
OUT13
VDD3_OUT12_13
OUT12_N
OUT12
VDD_1_8_OUT12_13
OUT11_N
OUT11
VDD3_OUT10_11
OUT10_N
OUT10
VDD_1_8_OUT10_11
1.8V_OUT_0-13
0.1UF
C537
0.1UF
C543
C526
0.1UF
10UF
C547
OUT2
10UF
0.1UF
C538
C534
0.1UF
C544
0.1UF
C548
10UF
C527
0.1UF
C539
0.1UF
C545
0.1UF
0.1UF
0.1UF
C546
10UF
C530
0.1UF
C542
C524
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
5
PRI
49.9
0.1UF
10UF
Rev. 0 | Page 18 of 28
10593-023
3.3V_OUT_0-3
Figure 23. Default and Optional Clock Input Circuits
10UF
C525
UG-386
Evaluation Board User Guide
Evaluation Board User Guide
UG-386
FAST_SPI_EN
R603
1.1K
3P3V_DIGITAL
DNI
10K
R629
DRVDD
R626
1.1K
5
CYP_SDI
3 A2
Y1
6
Y2
4
1
DNI
TP_DUT_SDIO
U603
ADG734BRUZ
1
FPGA_SDIO
DUT_SDIO
10
SB
9
7
D
8
3P3V_DIGITAL
IN
CYP_SDO
R606
GND
100K
R602
10K
R601
1 A1
R605
1.1K
U601
NC7WZ07P6X
VCC
IN
DRVDD
C601
0.1UF
3 D
U603
ADG734BRUZ
2
4 SB
DRVDD
2
DNI
R608
TP_CYP_SDIO
KP_VDDIO
0
DNI
0
C602
0.1UF
LAYOUT: PLACE C602 NEAR DUT
DNI
DNI
1
CYP_SDIO
A1
Y1
U603
ADG734BRUZ
IN
11
20
IN
13 D
DUT_CSB
3P3V_DIGITAL
TP_DUT_SCLK
1
DUT_SCLK
C603
0.1UF
FPGA_SCLK
VCC
1
CYP_SCLK
SPI & FPGA CONN.
DNI
DNI
1
12
14 SB
FPGA_CSB
DNI
NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC
TP_DUT_CSB
18 D
U603
U602
R615
10K
DNI
19
17 SB
R611
5
100K
C604
0.1UF
10K
R609
DRVDD
ADG734BRUZ
FAST_SPI_EN
6
16
VDD
NC7WZ16P6X 2
R613
R616
0
0
15 NC15
6 GND
5 VSS
4
100K
Y2
GND
10K
R610
A2
R612
3
CYP_CSB
DCO+
D2/D3+
D6/D7+
D10/D11+
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
1
PLUG HEADER
DNI
DNI
TP612
1
DNI
TP611
DNI
TP610
DNI
TP609
TP607
1
R633
100
P602
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DCOD2/D3D6/D7D10/D11-
D0/D1+
R643
D2/D3+
100
R635
D4/D5+
100
D6/D7+
DCODNI
D0/D1DNI
D2/D3-
100 DNI
R644
100
D4/D5-
DNI
R636
D0/D1+
D4/D5+
D8/D9+
D12/D13+
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D8/D9+
D0/D1D4/D5D8/D9D12/D13-
D6/D7DNI
R645
D8/D9-
100 DNI
D10/D11+
R637
100
D12/D13+
D10/D11DNI
R646
100
D12/D13DNI
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
10593-024
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
PLUG HEADER
P602 P602
P601 P601
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
ADG734BRUZ
P602 P602
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
PLUG HEADER
PLUG HEADER
P601
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PLUG HEADER
0
CYP_CSB2
PLUG HEADER
R628
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
PLUG HEADER
USB_CSB2
10K
R627
P601
DNI
1
PLUG HEADER
3P3V_DIGITAL
1
DCO+
P602
PLUG HEADER
CYP_CSB2
CYP_CSB
1
TP608
DNI
DNI
TP606
1
PLUG HEADER
TP605
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
DNI
DNI
DNI
USING FIFO5
(UNUSED PINS REMOVED)
LAYOUT: ROUTE ALL TRACES TO THE
TYCO CONN ON TOP OF BOARD
P601 P601
1
B1
B2
B3 FAST_SPI_EN
B4
CYP_SDO
B5
CYP_SDI
B6
CYP_SCLK
B7
FPGA_SCLK
FPGA_CSB
B8
B9
FPGA_SDIO
B10
U603
6469169-1
Figure 24. SPI Configuration Circuit and FIFO Board Connector Circuit
Rev. 0 | Page 19 of 28
Evaluation Board User Guide
10593-025
UG-386
10593-026
Figure 25. Top Side
Figure 26. Ground Plane (Layer 2)
Rev. 0 | Page 20 of 28
UG-386
10593-027
Evaluation Board User Guide
10593-028
Figure 27. Power Plane (Layer 3)
Figure 28. Power Plane (Layer 4)
Rev. 0 | Page 21 of 28
Evaluation Board User Guide
10593-029
UG-386
10593-030
Figure 29. Ground Plane (Layer 5)
Figure 30. Bottom Side
Rev. 0 | Page 22 of 28
Evaluation Board User Guide
UG-386
ORDERING INFORMATION
BILL OF MATERIALS
Table 1. AD9642/AD9634/AD6672 Bill of Materials
Item
1
Qty
1
Reference Designator
N/A
2
13
3
4
5
6
6
10
6
7
6
1
C101, C103, C105, C109 to C113,
C514 to C516, C520, C521
C107, C117, C118, C121, C122, C212
C201, C232, C234, C236, C240, C405
C204, C206, C207, C209, C225,
C227, C228, C230, C241, C243
C210, C211, C220, C221, C223, C224
C213
8
2
C214, C216
9
10
11
1
4
36
12
13
14
15
16
17
18
19
20
21
3
2
2
3
3
6
1
1
1
3
C215
C217, C218, C226, C229
C231, C233, C235, C239, C301,
C305, C306, C401 to C404, C501,
C502, C504 to C507, C517 to C519,
C535 to C548, C601, C604
C302 to C304
C503, C508
C509, C510
C511 to C513
C523, C532, C533
C524 to C527, C530, C534
C531
CR201
CR202
CR204 to CR206
22
2
CR501, CR502
23
24
1
13
25
26
27
2
1
1
CR503
E202, E204, E205, E207 to E214,
E216, E217
E501, E502
F201
FL201
28
2
J301, J506
29
30
31
32
2
6
1
8
JP201, JP203
L501 to L506
L507
P104 to P110, P401
33
34
1
1
P201
P202
35
1
P203
Description
Printed circuit board, AD9642 engineering
board
0.1 µF capacitor ceramic X5R 0201
Murata GRM033R60J104KE19D
1 µF capacitor mono ceramic 0402
10 µF capacitor tantalum
4.7 µF capacitor monolithic ceramic X5R
Murata GRM155R60J105KE19D
AVX TAJA106K010RNJ
Murata GRM188R60J475KE19
22 µF capacitor ceramic chip
2200 pF capacitor ceramic X7R 0402
Murata GRM21BR60J226ME39L
Phycomp (YAGEO)
CC0402KRX7R9BB222
Murata GRM1555C1H101JD01D
100 pF capacitor chip mono ceramic C0G
0402
1500 pF capacitor ceramic X7R 0402
0.01 µF capacitor ceramic X7R 0402
0.1 µF capacitor ceramic X7R 0402
3.9 pF capacitor ceramic NP0 0402
0.33 µF capacitor ceramic X5R
0.001 µF capacitor ceramic monolithic
0.47 µF capacitor chip CER X7R 0603
390 pF capacitor ceramic C0G 0402
10 µF capacitor ceramic monolithic
12 pF capacitor ceramic C0G 0402
S1AB-13 diode rectifier GPP SMD
SK33A-TP diode Schottky 3-amp rectifier
S2A-TP diode recovery rectifier
LNJ314G8TRA (green) LED green surface
mount
HSMS-2812BLK diode Schottky dual series
100 MHZ inductor ferrite bead
45 Ω chip bead core
1.1 A fuse poly-switch PTC device 1812
BNX016-01 FLTR noise suppression LC
combined type
SMA-J-P-X-ST-EM1 CONN-PCB SMA ST edge
mount
0 Ω resistor JMPR SMD 0805 (SHRT)
1 µH inductor SMT power
3.9 nH inductor SM
TSW-102-08-G-S CONN-PCB header
2 POS
PJ-202A CONN-PCB DC power jack SM
Z5.531.3625.0 CONN-PCB header
6-position
Z5.531.3425.0 CONN-PCB, pluggable
header
Rev. 0 | Page 23 of 28
Manufacturer/Part No.
AD9642EE01A
Murata GRM155R71H152KA01D
Murata GRM155R71H103KA01D
Murata GRM155R71C104KA88D
Murata GRM1555C1H3R9CZ01D
Murata GRM155R61A334KE15D
Murata GRM155R71H102KA01D
Murata GCM188R71C474KA55D
Murata GRM1555C1H391JA01D
Murata GRM21BR61C106KE15L
Murata GRM1555C1H120JZ01D
Diode Incorp S1AB-13
MCC SK33A-TP
MICRO Commercial Components CORP
S2A-TP
Panasonic LNJ314G8TRA
Avago HSMS-2812BLK
Panasonic EXC-ML20A390U
Panasonic EXCCL3225U1
TYCO Electronics NANOSMDC110F-2
Murata BNX016-01
Samtec SMA-J-P-X-ST-EM1
Panasonic ERJ-6GEYJ0.0
Coil-Craft ME3220-102MLB
Murata LQG15HN3N9S02D
Samtec TSW-102-08-G-S
CUI Stack PJ-202A
Wieland Z5.531.3625.0
Wieland Z5.531.3425.0
UG-386
Evaluation Board User Guide
Item
36
37
38
Qty
2
1
2
Reference Designator
P601, P602
R201
R205, R222
39
40
1
5
R206
R207, R208, R602, R611, R612
41
42
1
1
R209
R210
43
44
45
2
1
1
R211, R212
R213
R214
46
14
47
48
49
2
2
6
R217, R219, R302, R303, R307, R319,
R320, R404, R405, R506, R522, R523,
R528, R537
R313, R314
R315, R316
R317, R318, R501, R503, R505, R604
50
2
R401, R402
51
52
53
4
1
10
54
13
55
2
R407, R603, R605, R626
R507
R509, R515 to R519, R601, R609,
R610, R615
R510, R511, R524 to R527, R531,
R532, R535, R536, R544 to R546
R513, R514
56
57
58
4
5
1
R606, R613, R616, R628
T302, T303, T401, T501, T503
U1010
59
2
U202, U203
60
2
U204, U205
61
1
U206
62
1
U207
63
64
2
1
U300, U602
U401
65
66
67
1
1
1
U601
C602
CR203
68
1
R502
69
70
711
721
2
1
R539, R540
U501
C205, C208, C242
C219, C222
Description
6469169-1 CONN_PCB 60PIN RA connector
261 resistor film chip thick
1.00 kΩ resistor precision thick film chip
R0402
10 Ω resistor precision thick film chip R0402
100 kΩ resistor precision thick film chip
R0402
27 kΩ resistor chip SMD 0402
4.64 Ω resistor precision thick film chip
R0402
15 kΩ resistor chip SMD 0402
13 kΩ resistor film SMD 0402
10.5 kΩ resistor precision thick film chip
R0402
0 Ω resistor film SMD 0402
Manufacturer/Part No.
TYCO 6469169-1
NIC COMP CORP NRC06F2610TRF
Panasonic ERJ-2RKF1001X
36 Ω resistor film SMD 0402
15 Ω resistor film SMD 0402
49.9 Ω resistor precision thick film chip
R0402
40.2 Ω resistor precision thick film chip
R0402
1.1 kΩ resistor film SMD 0402
TBD0402 do not install (TBD_R0402)
10 kΩ resistor precision thick film chip
R0402
100 Ω resistor precision thick film chip
R0201
200 Ω resistor precision thick film chip
R0402
0 Ω resistor thick film chip
MABA-007159-000000 XFMR RF 1:1
SG-MLF32A-7004 socket 32P MLF direct
mount
ADP150AUJZ-3.3-R7 IC CMOS linear
regulator LDO 3.3 V
ADP1706ARDZ-1.8-R7 IC low dropout CMOS
linear regulator
ADP2114 IC dual configurable synchronous
PWM step-down regulator
ADP150AUJZ-1.8-R7 IC CMOS linear
regulator LDO 1.8 V
NC7WZ16P6X IC tiny logic UHS dual buffer
ADL5562 IC 2.6 GHZ ultralow distortion
DIFF IF/RF amp
NC7WZ07P6X IC tiny logic UHS dual buffer
0.1 μF capacitor ceramic X7R 0402
LNJ314G8TRA (green) LED green surface
mount
1 kΩ resistor ultraprecision ultrareliability
MF chip
33 Ω resistor high PRES, high stability
AD9523 IC
0.01 μF capacitor ceramic X7R 0402
TBD0603 do not install (TBD_C0603)
Panasonic ERJ-2GEJ360X
Panasonic ERJ-2RFK15R0X
Panasonic ERJ-2RKF49R9X
Rev. 0 | Page 24 of 28
Panasonic ERJ-2RKF10R0X
Panasonic ERJ-2RKF1003X
Panasonic ERJ-2RKF2702X
Panasonic ERJ-2RKF4641X
Panasonic ERJ-2RKF1502X
Yageo 9C04021A1302FLHF3
Panasonic ERJ-2RKF1052X
Panasonic ERJ-2GE0R00X
Panasonic ERJ-2RKF40R2X
Panasonic ERJ-2GEJ112X
TBD0402
Panasonic ERJ-2RKF1002X
Panasonic ERJ-1GEF1000C
Panasonic ERJ-2RKF2000X
Multicomp 0402WGF0000TCE
MACOM MABA-007159-000000
Ironwood Electronics SG-MLF32A-7004
Analog Devices ADP150AUJZ-3.3-R7
Analog Devices ADP1706ARDZ-1.8-R7
Analog Devices ADP2114
Analog Devices ADP150AUJZ-1.8-R7
Fairchild NC7WZ16P6X
Analog Devices ADL5562
Fairchild NC7WZ07P6X
Murata GRM155R71C104KA88D
Panasonic LNJ314G8TRA
SUSUMU RG1005P-102-B-T5
Yageo RT0402DRE0733RL
Analog Devices AD9523
Murata GRM155R71H103KA01D
TBD0603
Evaluation Board User Guide
Item
731
741
751
761
771
Qty
781
791
801
811
821
831
841
851
861
871
881
891
901
1
Reference Designator
C314, C406 to C408, C529, C603
C409, C410
C522
E203, E206
J302, J502, J503, J505
L201, L202
L301, L405, L406
L401 to L404
R204, R216, R218, R221, R305, R306,
R308 to R312, R403, R406, R408,
R409, R412, R508, R533, R534, R538,
R541, R542, R608
R215, R220
R301, R304, R520, R521, R529, R530
R410, R411
R512, R633, R635 to R637, R643 to
R646
R543
R627, R629
T301, T502
U603
Y501
UG-386
Description
0.1 µF capacitor ceramic X7R 0402
5 pF capacitor
390 pF capacitor ceramic C0G 0402
100 MHZ inductor ferrite bead
SMA-J-P-X-ST-EM1 CONN-PCB SMA ST edge
mount
2.2 µH inductor SM
82 nH inductor SM
120 nH inductor SM
0 Ω resistor film SMD 0402
Manufacturer/Part No.
Murata GRM155R71C104KA88D
Panasonic ECU-E1H050CCQ
Murata GRM1555C1H391JA01D
Panasonic EXC-ML20A390U
Samtec SMA-J-P-X-ST-EM1
Toko FDV0630-2R2M
Murata LQW18AN82NG00D
Panasonic ELJ-RER12JF3
Panasonic ERJ-2GE0R00X
TBD0603 do not install (TBD_R0603)
49.9 Ω resistor PREC thick film chip R0402
1.00 kΩ resistor PREC thick film chip R0402
100 Ω resistor PREC thick film chip R0201
TBD0603
Panasonic ERJ-2RKF49R9X
Panasonic ERJ-2RKF1001X
Panasonic ERJ-1GEF1000C
100 Ω resistor film SMD 0402
10 kΩ resistor PREC thick film chip R0402
ADT1-1WT+ XFMR RF
Quad SPDT switches IC CMOS
60 MHz to 800 MHz IC oscillator voltage
controlled OSC
Venkel CR0402-16W-1000FPT
Panasonic ERJ-2RKF1002X
Mini Circuits ADT1-1WT+
Analog Devices ADG734BRUZ
Epson Toyocom TCO-2111
Do not install.
RELATED LINKS
Resource
AD6672
AD9634
AD9642
ADP2114
AD9523
ADG734
AN-878
AN-877
AN-835
AN-905
Description
Product Page, 11-Bit, 250 MSPS, 1.8 V IF Diversity Receiver
Product Page, 12-bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
Product Page, 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
Product Page, Configurable, Dual 2 A/Single 4 A, Synchronous Step-Down DC-to-DC Regulator
Product Page, 14-Output, Low Jitter Clock generator
Product Page, CMOS, 2.5 Ω Low Voltage, Quad SPDT Switch
Application Note, High Speed ADC SPI Control Software
Application Note, Interfacing to High Speed ADCs via SPI
Application Note, Understanding High Speed ADC Testing and Evaluation
Application Note, VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual
Rev. 0 | Page 25 of 28
UG-386
Evaluation Board User Guide
NOTES
Rev. 0 | Page 26 of 28
Evaluation Board User Guide
UG-386
NOTES
Rev. 0 | Page 27 of 28
UG-386
Evaluation Board User Guide
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF
THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG10593-0-4/12(0)
Rev. 0 | Page 28 of 28