Dual, 14-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter AD9645 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Handheld scope meters Portable medical imaging and ultrasound Radar/LIDAR GENERAL DESCRIPTION The AD9645 is a dual, 14-bit, 80 MSPS/125 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Rev. B AVDD DRVDD AGND AD9645 VINA+ VINA– D0A+ D0A– 14 PLL, SERIALIZER AND DDR LVDS DRIVERS 14-BIT PIPELINE ADC 14 VCM 14 VINB+ VINB– 14-BIT PIPELINE ADC 14 REFERENCE D1A+ D1A– D0B+ D0B– D1B+ D1B– DCO+ DCO– FCO+ FCO– SERIAL PORT INTERFACE 1 TO 8 CLOCK DIVIDER SCLK/ SDIO/ CSB DFS PDWN CLK+ CLK– 10537-001 1.8 V supply operation Low power: 122 mW per channel at 125 MSPS with scalable power options SNR = 74 dBFS (to Nyquist) SFDR = 91 dBc at 70 MHz DNL = ±0.65 LSB (typical); INL = ±1.5 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Programmable output resolution Standby mode Figure 1. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported; the AD9645 typically consumes less than 2 mW in the full power-down state. The ADC provides several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9645 is available in a RoHS-compliant, 32-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Small Footprint. Two ADCs are contained in a small, spacesaving package. Low Power. The AD9645 uses 122 mW/channel at 125 MSPS with scalable power options. Pin Compatibility with the AD9635, a 12-Bit Dual ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. 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Technical Support www.analog.com AD9645 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Power-Down Mode ........................... 22 Applications ....................................................................................... 1 Digital Outputs and Timing ..................................................... 23 General Description ......................................................................... 1 Output Test Modes ..................................................................... 26 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) .............................................................. 27 Product Highlights ........................................................................... 1 Configuration Using the SPI ..................................................... 27 Revision History ............................................................................... 2 Hardware Interface ..................................................................... 28 Specifications..................................................................................... 3 Configuration Without the SPI ................................................ 28 DC Specifications ......................................................................... 3 SPI Accessible Features .............................................................. 28 AC Specifications.......................................................................... 4 Memory Map .................................................................................. 29 Digital Specifications ................................................................... 5 Reading the Memory Map Register Table............................... 29 Switching Specifications .............................................................. 6 Memory Map Register Table ..................................................... 30 Timing Specifications .................................................................. 6 Memory Map Register Descriptions ........................................ 33 Absolute Maximum Ratings .......................................................... 10 Applications Information .............................................................. 35 Thermal Resistance .................................................................... 10 Design Guidelines ...................................................................... 35 ESD Caution ................................................................................ 10 Power and Ground Guidelines ................................................. 35 Pin Configuration and Function Descriptions ........................... 11 Clock Stability Considerations ................................................. 35 Typical Performance Characteristics ........................................... 12 Exposed Pad Thermal Heat Slug Recommendations ............ 35 AD9645-80 .................................................................................. 12 VCM ............................................................................................. 35 AD9645-125 ................................................................................ 15 Reference Decoupling ................................................................ 35 Equivalent Circuits ......................................................................... 18 SPI Port ........................................................................................ 35 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 36 Analog Input Considerations.................................................... 19 Ordering Guide .......................................................................... 36 Voltage Reference ....................................................................... 20 Clock Input Considerations ...................................................... 21 REVISION HISTORY 10/15—Rev. A to Rev. B Changed AD9516 to AD9516-0/AD9516-1/AD9516-2/ AD9516-3/AD9516-4/AD9516-5, and AD9517 to AD9517-0/ AD9517-1/AD9517-2/AD9517-3/AD9517-4 ............ Throughout Changes to General Description .................................................... 1 Added Endnote 4, Table 4................................................................ 6 Changes to Digital Outputs and Timing Section ....................... 24 8/14—Rev. 0 to Rev. A Added Propagation Delay Parameters of 1.5 ns (min) and 3.1 ns (max), Table 4 ................................................................. 6 Changes to Figure 3 .......................................................................... 7 Changes to Figure 5 .......................................................................... 8 Changes to Pin 21 Description ..................................................... 11 Changes to Voltage Reference Section......................................... 20 Changes to Table 10 and Table 11 ................................................ 25 Changes to First Paragraph of Serial Port Interface (SPI) Section .............................................................................................. 27 Changes to SPI Accessible Features Section ............................... 28 Changes to Output Phase (Register 0x16) Bits[6:4]—Input Clock Phase Adjust Section........................................................... 33 Changes to Resolution/Sample Rate Override (Register 0x100) Section and User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down Section ..................................................................... 34 Added Clock Stability Considerations Section........................... 35 6/12—Revision 0: Initial Version Rev. B | Page 2 of 36 Data Sheet AD9645 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Common-Mode Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD2 IDRVDD (ANSI-644 Mode)2 IDRVDD (Reduced Range Mode)2 TOTAL POWER CONSUMPTION DC Input Sine Wave Input (Two Channels; Includes Output Drivers in ANSI-644 Mode) Sine Wave Input (Two Channels; Includes Output Drivers in Reduced Range Mode) Power-Down Standby3 Temp Full Full Full Full Full Full 25°C Full 25°C Min 14 Min 14 AD9645-125 Typ Max Guaranteed −0.2 +0.1 +0.1 +0.4 −1.0 +2.2 0.5 2.2 −0.6 +1.3 ±0.65 −2.6 +2.8 ±1.1 Guaranteed −0.2 +0.2 +0.1 +0.4 −1.5 +2.3 0.6 2.6 −0.6 +1.3 ±0.65 −3.6 +3.4 ±1.5 2.7 3.3 −0.6 −0.2 −4.3 Full Full 25°C 25°C AD9645-80 Typ Max 0.98 1.0 2 7.5 1.02 −0.6 −0.2 −5.1 0.98 1.0 2 7.5 Unit Bits % FSR % FSR % FSR % FSR LSB LSB LSB LSB ppm/°C 1.02 V mV kΩ 25°C 0.95 1.0 LSB rms Full Full 25°C 25°C 25°C 2 0.9 2 0.9 V p-p V V kΩ pF Full Full Full Full 25°C 0.5 1.3 0.5 5.2 3.5 1.7 1.7 1.8 1.8 56 48 39 1.9 1.9 61 50 Full Full 178 187 191 200 25°C 171 25°C Full 2 92 1 1.3 5.2 3.5 1.7 1.7 1.8 1.8 78 57 48 1.9 1.9 83 60 V V mA mA mA 227 243 244 257 mW mW 227 101 2 115 mW 126 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured with a low input frequency, full-scale sine wave on both channels. 3 Can be controlled via the SPI. 2 Rev. B | Page 3 of 36 mW mW AD9645 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2. AD9645-80 Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 139.5 MHz fIN = 200.5 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 139.5 MHz fIN = 200.5 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 139.5 MHz fIN = 200.5 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 139.5 MHz fIN = 200.5 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 139.5 MHz fIN = 200.5 MHz WORST OTHER HARMONIC OR SPUR fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 139.5 MHz fIN = 200.5 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz CROSSTALK2 CROSSTALK (OVERRANGE CONDITION)3 POWER SUPPLY REJECTION RATIO (PSRR)4 AVDD DRVDD ANALOG INPUT BANDWIDTH, FULL POWER Temp 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C Min Typ 73.1 75.6 75.4 74.5 72.1 70.0 72.7 75.6 75.2 74.4 71.7 69.7 11.8 12.3 12.2 12.1 11.6 11.3 82 96 91 96 82 82 Max AD9645-125 Min Typ Max Unit 72.8 75.2 75.0 74.3 72.5 70.3 dBFS dBFS dBFS dBFS dBFS 72.4 75.1 75.0 74.2 72.4 70.0 dBFS dBFS dBFS dBFS dBFS 11.7 12.2 12.2 12.0 11.7 11.3 Bits Bits Bits Bits Bits 82 93 97 91 91 81 dBc dBc dBc dBc dBc −83 −93 −97 −91 −93 −81 −82 dBc dBc dBc dBc dBc −82 −96 −99 −96 −91 −87 −84 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C −96 −91 −96 −82 −82 25°C 25°C Full 25°C 25°C −99 −97 −99 −93 −91 25°C 25°C 25°C −93 −97 −97 −93 −97 −97 dBc dB dB 25°C 25°C 25°C 42 67 650 42 67 650 dB dB MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is specified with 3 dB of the full-scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitude of the spur voltage over the amplitude of the pin voltage, expressed in decibels (dB). 2 Rev. B | Page 4 of 36 Data Sheet AD9645 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 3. Parameter1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUT (SCLK/DFS) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/PDWN) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/PDWN)3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D0x±, D1x±), ANSI-644 Logic Compliance Differential Output Voltage Magnitude (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D0x±, D1x±), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance Differential Output Voltage Magnitude (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temp Min Full Full Full 25°C 25°C 0.2 AGND − 0.2 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Typ Max Unit 3.6 AVDD + 0.2 V p-p V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF CMOS/LVDS/LVPECL 0.9 15 4 30 2 26 2 26 5 Full Full 1.79 0.05 V V Full Full 290 1.15 LVDS 345 400 1.25 1.35 Twos complement mV V Full Full 160 1.15 LVDS 200 230 1.25 1.35 Twos complement mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Specified for LVDS and LVPECL only. Specified for 13 SDIO/PDWN pins sharing the same connection. Rev. B | Page 5 of 36 AD9645 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. Parameter1, 2 CLOCK3 Input Clock Rate Conversion Rate4 Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)5 DCO to Data Delay (tDATA)5 DCO to FCO Delay (tFRAME)5 Lane Delay (tLD) Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down)6 Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time Temp Min Full Full Full Full 10 10 Full Full Full Full Full Full Full 1.5 Typ Max Unit 1000 80/125 MHz MSPS ns ns 3.1 ns ps ps ns ns ps ps ps ps ns μs Clock cycles 6.25/4.00 6.25/4.00 Full 25°C 25°C Full 2.3 300 300 2.3 tFCO + (tSAMPLE/16) tSAMPLE/16 tSAMPLE/16 90 ±50 250 375 16 25°C 25°C 25°C 1 174 1 1.5 (tSAMPLE/16) − 300 (tSAMPLE/16) − 300 3.1 (tSAMPLE/16) + 300 (tSAMPLE/16) + 300 ±200 ns fs rms Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured on standard FR-4 material. Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. 2 3 TIMING SPECIFICATIONS Table 5. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description See Figure 68 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 68) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 68) Rev. B | Page 6 of 36 Limit Unit 2 2 40 2 2 10 10 10 ns min ns min ns min ns min ns min ns min ns min ns min 10 ns min Data Sheet AD9645 Timing Diagrams Refer to the Memory Map Register Descriptions section and Table 20 for SPI register settings. N–1 VINx± N tA tEH CLK– N+1 tEL CLK+ tCPD DCO– DDR DCO+ DCO– SDR DCO+ tFCO FCO– tFRAME FCO+ tPD D0A– BITWISE MODE tDATA D0A+ D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 0 N – 17 MSB N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 0 N – 17 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 0 N – 17 MSB N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D12 N – 16 D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 0 N – 16 MSB N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 0 N – 16 0 N – 17 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 0 N – 16 0 N – 16 D06 N – 17 MSB N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 tLD D1A– D1A+ FCO– FCO+ D0A– D1A– D1A+ Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default) N–1 VINx± N+1 tA N tEL tEH CLK– CLK+ DCO+ DDR DCO– DCO+ SDR DCO– tFCO FCO– FCO+ BITWISE MODE tDATA tPD D0A– D0A+ tFRAME D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D10 N – 16 D08 N – 16 D06 N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D09 N – 16 D07 N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 D05 N – 16 D04 N – 16 MSB N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 MSB N – 16 D10 N – 16 D02 N – 16 LSB N – 16 D05 N – 16 D03 N – 16 D01 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 D04 N – 16 tLD D1A– D1A+ FCO– FCO+ D0A– BYTEWISE MODE D0A+ D1A– D1A+ Figure 3. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode Rev. B | Page 7 of 36 10537-002 D0A+ 10537-003 BYTEWISE MODE AD9645 Data Sheet N–1 VINx± N tA tEL tEH CLK– N+1 CLK+ tCPD DCO– DDR DCO+ DCO– SDR DCO+ tFRAME tFCO FCO– FCO+ tPD D0A– BITWISE MODE tDATA D0A+ D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 0 N – 16 MSB N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 0 N – 16 0 N – 17 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 0 N – 16 0 N – 16 D06 N – 17 MSB N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 0 N – 17 MSB N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 0 N – 17 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 0 N – 17 MSB N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D12 N – 16 tLD D1A– D1A+ FCO– FCO+ D0A– D1A– D1A+ Figure 4. 16-Bit DDR/SDR, Two-Lane, 2× Frame Mode N–1 VINx± N+1 tA N tEL tEH CLK– CLK+ tCPD DCO+ DDR DCO– DCO+ SDR DCO– tFCO FCO– FCO+ BITWISE MODE tDATA tPD D0A– D0A+ tFRAME D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D10 N – 16 D08 N – 16 D06 N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D09 N – 16 D07 N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 D05 N – 16 D04 N – 16 MSB N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 MSB N – 16 D10 N – 16 D02 N – 16 LSB N – 16 D05 N – 16 D03 N – 16 D01 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 D04 N – 16 tLD D1A– D1A+ FCO– FCO+ BYTEWISE MODE D0A– D0A+ D1A– D1A+ Figure 5. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode Rev. B | Page 8 of 36 10537-004 D0A+ 10537-005 BYTEWISE MODE Data Sheet AD9645 N–1 VINx± tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFCO FCO– tFRAME FCO+ MSB N – 17 D0x+ D14 MSB D13 0 0 LSB D1 D2 D12 D3 D4 D11 D10 D9 D8 D7 D6 D5 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 Figure 6. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode N–1 VINx± tA N tEH CLK– tEL CLK+ DCO– tCPD DCO+ FCO– tFCO tFRAME FCO+ D0x+ tDATA tPD MSB N – 17 D2 D10 D9 D8 D7 D6 D5 D4 D3 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 Figure 7. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode Rev. B | Page 9 of 36 D1 N – 17 D0 MSB N – 17 N – 16 D10 N – 16 10537-007 D0x– 10537-006 tDATA tPD D0x– AD9645 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs to AGND (D0x±, D1x±, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− to AGND VINx+, VINx− to AGND SCLK/DFS, SDIO/PDWN, CSB to AGND RBIAS to AGND VREF to AGND VCM to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) THERMAL RESISTANCE Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V The exposed paddle is the only ground connection on the chip. The exposed paddle must be soldered to the AGND plane of the user’s circuit board. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Package Type 32-Lead LFCSP, 5 mm × 5 mm Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 37.1 32.4 29.1 θJC1, 3 3.1 θJB1, 4 20.7 ΨJT1, 2 0.3 0.5 0.8 Unit °C/W °C/W °C/W 1 −40°C to +85°C 150°C 300°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. ESD CAUTION Rev. B | Page 10 of 36 Data Sheet AD9645 32 31 30 29 28 27 26 25 AVDD VINB– VINB+ AVDD AVDD VINA+ VINA– AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9645 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AVDD RBIAS VCM VREF CSB DRVDD D0A+ D0A– NOTES 1. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 10537-008 D0B– D0B+ DCO– DCO+ FCO– FCO+ D1A– D1A+ 9 10 11 12 13 14 15 16 AVDD CLK+ CLK– SDIO/PDWN SCLK/DFS DRVDD D1B– D1B+ Figure 8. Pin Configuration, Top View Table 8. Pin Function Descriptions Pin No. 0 Mnemonic AGND, Exposed Pad 1, 24, 25, 28, 29, 32 2, 3 4 AVDD CLK+, CLK− SDIO/PDWN 5 SCLK/DFS 6, 19 7, 8 9, 10 11, 12 13, 14 15, 16 17, 18 20 21 22 23 26, 27 30, 31 DRVDD D1B−, D1B+ D0B−, D0B+ DCO−, DCO+ FCO−, FCO+ D1A−, D1A+ D0A−, D0A+ CSB VREF VCM RBIAS VINA−, VINA+ VINB+, VINB− Description The exposed paddle is the only ground connection on the chip. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1.8 V Supply Pins for ADC Analog Core Domain. Differential Encode Clock for LVPECL, LVDS, or 1.8 V CMOS Inputs. Data Input/Output in SPI Mode (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Power-Down in Non-SPI Mode (PDWN). Static control of chip power-down with 30 kΩ internal pull-down. SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non-SPI Mode (DFS). Static control of data output format with 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 1.8 V Supply Pins for Output Driver Domain. Channel B Digital Outputs. Channel B Digital Outputs. Data Clock Outputs. Frame Clock Outputs. Channel A Digital Outputs. Channel A Digital Outputs. SPI Chip Select. Active low enable with 15 kΩ internal pull-up. 1.0 V Voltage Reference Output. Analog Output Voltage at Mid AVDD Supply. Sets the common-mode voltage of the analog inputs. Sets the analog current bias. Connect this pin to a 10 kΩ (1% tolerance) resistor to ground. Channel A ADC Analog Inputs. Channel B ADC Analog Inputs. Rev. B | Page 11 of 36 AD9645 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9645-80 0 0 80MSPS 9.7MHz AT –1dBFS SNR = 74.6dB (75.6dBFS) SFDR = 95.2dBc –40 –60 –80 –100 –120 –60 –80 –100 20 30 40 FREQUENCY (MHz) –140 Figure 9. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 80 MSPS 0 10 20 30 40 FREQUENCY (MHz) 10537-012 10 10537-009 0 Figure 12. Single-Tone 16k FFT with fIN = 139.5 MHz, fSAMPLE = 80 MSPS 0 0 80MSPS 30.5MHz AT –1dBFS SNR = 74.3dB (75.3dBFS) SFDR = 90.9dBc –20 80MSPS 200.5MHz AT –1dBFS SNR = 68.9dB (69.9dBFS) SFDR = 81.7dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –40 –60 –80 –100 –120 0 10 20 30 40 FREQUENCY (MHz) –140 10537-010 –140 Figure 10. Single-Tone 16k FFT with fIN = 30.5 MHz, fSAMPLE = 80 MSPS 0 10 20 30 40 FREQUENCY (MHz) 10537-013 AMPLITUDE (dBFS) –40 –120 –140 Figure 13. Single-Tone 16k FFT with fIN = 200.5 MHz, fSAMPLE = 80 MSPS 0 0 80MSPS 70.2MHz AT –1dBFS SNR = 73.4dB (74.4dBFS) SFDR = 95.3dBc –20 80MSPS 200.5MHz AT –1dBFS SNR = 70.8dB (71.8dBFS) SFDR = 81.5dBc –15 –30 –40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 80MSPS 139.5MHz AT –1dBFS SNR = 71dB (72dBFS) SFDR = 80.8dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 –60 –80 –100 –45 –60 –75 –90 –105 –120 0 10 20 FREQUENCY (MHz) 30 40 –135 10537-011 –140 Figure 11. Single-Tone 16k FFT with fIN = 70.2 MHz, fSAMPLE = 80 MSPS 0 4 8 12 16 20 24 FREQUENCY (MHz) 28 32 36 40 10537-014 –120 Figure 14. Single-Tone 16k FFT with fIN = 200.5 MHz, fSAMPLE = 80 MSPS, Clock Divide = Divide-by-8 Rev. B | Page 12 of 36 Data Sheet AD9645 120 110 SFDRFS 100 SFDR 100 SNRFS 80 60 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 90 SFDR 40 SNR 20 80 SNR 70 60 50 40 30 20 0 –80 –70 –60 –50 –40 –30 –20 0 –10 INPUT AMPLITUDE (dBFS) 0 10537-015 –20 –90 0 40 60 80 100 120 140 160 180 200 220 240 260 INPUT FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Analog Input Level; fIN = 9.7 MHz, fSAMPLE = 80 MSPS Figure 18. SNR/SFDR vs. fIN; fSAMPLE = 80 MSPS 0 120 AIN1 AND AIN2 = –7dBFS SFDR = 90.8dBc IMD2 = –94.2dBc IMD3 = –92.7dBc –20 110 100 SFDR 90 –40 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) 20 10537-018 10 –60 –80 –100 SNR 80 70 60 50 40 30 20 –120 0 10 20 30 40 FREQUENCY (MHz) 0 –40 10537-016 –140 Figure 16. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 80 MSPS –20 0 40 20 10537-019 10 80 60 TEMPERATURE (°C) Figure 19. SNR/SFDR vs. Temperature; fIN = 9.7 MHz, fSAMPLE = 80 MSPS 0 1.0 0.8 –20 0.4 INL (LSB) IMD3 (dBc) –60 0.2 0 –0.2 –80 –0.4 SFDR (dBFS) –100 –0.6 IMD3 (dBFS) Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 80 MSPS Figure 20. INL; fIN = 9.7 MHz, fSAMPLE = 80 MSPS Rev. B | Page 13 of 36 16393 10537-020 OUTPUT CODE 15027 13661 12295 9563 10929 8197 6831 INPUT AMPLITUDE (dBFS) –0.8 5465 –10 4099 –30 2733 –50 1367 –70 1 –120 –90 10537-017 SFDR/IMD3 (dBc/dBFS) 0.6 SFDR (dBc) –40 AD9645 Data Sheet 110 0.6 SFDR 100 0.4 SNR/SFDR (dBFS/dBc) 90 DNL (LSB) 0.2 0 –0.2 SNRFS 80 70 60 50 40 30 20 –0.4 0 10 16393 OUTPUT CODE 10537-021 15027 13661 12295 9563 10929 8197 6831 5465 4099 2733 1367 1 –0.6 Figure 21. DNL; fIN = 9.7 MHz, fSAMPLE = 80 MSPS 30 50 70 90 SAMPLE RATE (MSPS) 10537-024 10 Figure 24. SNR/SFDR vs. Sample Rate; fIN = 9.7 MHz, fSAMPLE = 80 MSPS 110 900,000 100 0.95LSB rms 800,000 SFDR 90 SNR/SFDR (dBFS/dBc) NUMBER OF HITS 700,000 600,000 500,000 400,000 300,000 SNRFS 80 70 60 50 40 30 200,000 20 100,000 N–5N–4N–3N–2N–1 N 0 10 10537-022 0 N+1N+2N+3N+4N+5 CODE Figure 22. Input Referred Noise Histogram; fSAMPLE = 80 MSPS DRVDD 50 AVDD 40 30 20 10 10 FREQUENCY (MHz) 10537-023 PSRR (dB) 60 1 70 90 Figure 25. SNR/SFDR vs. Sample Rate; fIN = 70 MHz, fSAMPLE = 80 MSPS 70 0 50 SAMPLE RATE (MSPS) 90 80 30 10537-025 10 Figure 23. PSRR vs. Frequency; fCLK = 125 MHz, fSAMPLE = 80 MSPS Rev. B | Page 14 of 36 Data Sheet AD9645 AD9645-125 0 0 125MSPS 9.7MHz AT –1dBFS SNR = 74.2dB (75.2dBFS) SFDR = 93.7dBc –40 –60 –80 –100 –60 –80 –100 10 30 20 40 50 60 FREQUENCY (MHz) –140 Figure 26. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 125 MSPS 0 60 40 20 FREQUENCY (MHz) 10537-029 0 10537-026 –140 Figure 29. Single-Tone 16k FFT with fIN = 139.5 MHz, fSAMPLE = 125 MSPS 0 0 125MSPS 30.5MHz AT –1dBFS SNR = 73.9dB (74.9dBFS) SFDR = 96.8dBc –20 125MSPS 200.5MHz AT –1dBFS SNR = 69.4dB (70.4dBFS) SFDR = 81.5dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –40 –60 –80 –100 –120 0 20 40 60 FREQUENCY (MHz) –140 10537-027 –140 Figure 27. Single-Tone 16k FFT with fIN = 30.5 MHz, fSAMPLE = 125 MSPS 0 20 60 40 FREQUENCY (MHz) 10537-030 AMPLITUDE (dBFS) –40 –120 –120 Figure 30. Single-Tone 16k FFT with fIN = 200.5 MHz, fSAMPLE = 125 MSPS 0 0 125MSPS 70.2MHz AT –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 92.1dBc –20 125MSPS 200.5MHz AT –1dBFS SNR = 70.6dB (71.6dBFS) SFDR = 81.3dBc –15 –30 –40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 125MSPS 139.5MHz AT –1dBFS SNR = 71.2dB (72.2dBFS) SFDR = 90.7dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 –60 –80 –45 –60 –75 –90 –100 –105 –120 0 20 40 FREQUENCY (MHz) 60 –135 10537-028 –140 Figure 28. Single-Tone 16k FFT with fIN = 70.2 MHz, fSAMPLE = 125 MSPS 0 6 12 18 24 30 36 42 FREQUENCY (MHz) 48 54 60 10537-031 –120 Figure 31. Single-Tone 16k FFT with fIN = 200.5 MHz, fSAMPLE = 125 MSPS, Clock Divide = Divide-by-8 Rev. B | Page 15 of 36 AD9645 Data Sheet 120 110 SFDRFS 100 SFDR 100 SNRFS 80 60 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 90 SFDR 40 SNR 20 80 70 SNR 60 50 40 30 20 0 –70 –60 –50 –40 –30 –20 0 –10 INPUT AMPLITUDE (dBFS) 0 10537-032 –80 0 40 60 80 100 120 140 160 180 200 220 240 260 INPUT FREQUENCY (MHz) Figure 35. SNR/SFDR vs. fIN; fSAMPLE = 125 MSPS Figure 32. SNR/SFDR vs. Analog Input Level; fIN = 9.7 MHz, fSAMPLE = 125 MSPS 0 120 AIN1 AND AIN2 = –7dBFS SFDR = 89.6dBc IMD2 = –96.4dBc IMD3 = –90.8dBc –20 110 100 SFDR 90 –40 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) 20 10537-035 10 –20 –90 –60 –80 –100 80 70 SNR 60 50 40 30 20 –120 0 20 10 30 50 40 60 FREQUENCY (MHz) Figure 33. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS 0 –20 20 40 80 60 TEMPERATURE (°C) Figure 36. SNR/SFDR vs. Temperature; fIN = 9.7 MHz, fSAMPLE = 125 MSPS 0 1.5 –20 1.0 SFDR (dBc) 0.5 –40 INL (LSB) IMD3 (dBc) –60 0 –0.5 –80 SFDR (dBFS) –1.0 –100 IMD3 (dBFS) Figure 34. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS Figure 37. INL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS Rev. B | Page 16 of 36 16393 10537-072 OUTPUT CODE 15027 13661 12295 10929 9563 8197 6831 INPUT AMPLITUDE (dBFS) –1.5 5465 –10 4099 –30 2733 –50 1367 –70 1 –120 –90 10537-034 SFDR/IMD3 (dBc/dBFS) 0 –40 10537-033 –140 10537-071 10 Data Sheet AD9645 0.6 110 0.5 100 0.4 90 0.3 80 DNL (LSB) 0.2 0.1 0 –0.1 –0.2 70 60 50 40 30 –0.3 20 –0.4 10 16393 OUTPUT CODE 0 10 10537-073 15027 13661 12295 10929 9563 8197 6831 5465 4099 2733 1367 1 –0.5 SNRFS 30 50 70 90 110 130 SAMPLE RATE (MSPS) 10537-074 SNR/SFDR (dBFS/dBc) SFDR Figure 41. SNR/SFDR vs. Sample Rate; fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 38. DNL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS 110 900,000 100 1LSB rms 800,000 SFDR 90 SNR/SFDR (dBFS/dBc) 600,000 500,000 400,000 300,000 200,000 60 50 40 30 10 N–5N–4N–3N–2N–1 N 0 10 10537-076 0 N+1N+2N+3N+4N+5 CODE DRVDD 80 70 60 50 AVDD 40 30 20 10 10537-077 10 FREQUENCY (MHz) 50 70 90 SAMPLE RATE (MSPS) 90 0 30 110 130 Figure 42. SNR/SFDR vs. Sample Rate; fIN = 70 MHz, fSAMPLE = 125 MSPS Figure 39. Input Referred Noise Histogram; fSAMPLE = 125 MSPS PSRR (dB) SNRFS 70 20 100,000 1 80 10537-075 NUMBER OF HITS 700,000 Figure 40. PSRR vs. Frequency; fCLK = 125 MHz, fSAMPLE = 125 MSPS Rev. B | Page 17 of 36 AD9645 Data Sheet EQUIVALENT CIRCUITS DRVDD AVDD 400Ω SCLK/DFS VINx± 10537-036 10537-040 30kΩ Figure 43. Equivalent Analog Input Circuit Figure 47. Equivalent SCLK/DFS Input Circuit AVDD 10Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 10537-041 10537-037 CLK– 400Ω RBIAS AND VCM 10Ω Figure 48. Equivalent RBIAS and VCM Circuit Figure 44. Equivalent Clock Input Circuit DRVDD DRVDD 400Ω SDIO/PDWN 15kΩ 31kΩ 400Ω 10537-038 10537-042 CSB Figure 49. Equivalent CSB Input Circuit Figure 45. Equivalent SDIO/PDWN Input Circuit DRVDD AVDD V D0x–, D1x– V V D0x+, D1x+ V VREF 10Ω 400Ω 10537-039 10537-043 7.5kΩ Figure 50. Equivalent VREF Circuit Figure 46. Equivalent Digital Output Circuit Rev. B | Page 18 of 36 Data Sheet AD9645 THEORY OF OPERATION Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9645 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. H CPAR A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a differential capacitor or two singleended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9645 are not internally dc biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 52. 100 SFDR 90 80 SNR/SFDR (dBFS/dBc) The AD9645 is a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The serializer transmits this converted data in a 16-bit output. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. CSAMPLE S S S 30 20 0.5 CSAMPLE VINx– 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Figure 52. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 9.7 MHz, fSAMPLE = 125 MSPS 10537-044 H 0.6 INPUT COMMON MODE (V) H CPAR 50 10537-078 S 60 40 H VINx+ SNRFS 70 Figure 51. Switched-Capacitor Input Circuit The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 51). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. An on-chip, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 µF capacitor, as described in the Applications Information section. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9645, the largest input span available is 2 V p-p. Rev. B | Page 19 of 36 AD9645 Data Sheet Differential Input Configurations 0 –0.5 There are several ways to drive the AD9645 either actively or passively. However, optimum performance is achieved by driving the analog inputs differentially. Using a differential double balun configuration to drive the AD9645 provides excellent performance and a flexible interface to the ADC for baseband applications (see Figure 55). –1.0 INTERNAL VREF = 1V VREF ERROR (%) –1.5 For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 56) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9645. –2.0 –2.5 –3.0 –3.5 –4.0 –5.0 Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (mA) 10537-048 –4.5 Figure 53. VREF Error vs. Load Current It is not recommended to drive the AD9645 inputs single-ended. 4 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9645. The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. 2 VREF ERROR (mV) 0 Figure 53 shows how the internal reference voltage is affected by loading. Figure 54 shows the typical drift characteristics of the internal reference in 1.0 V mode. –2 –4 The internal buffer generates the positive and negative full-scale references for the ADC core. –8 –40 –15 10 35 TEMPERATURE (°C) Figure 54. Typical VREF Drift 0.1µF 0.1µF R C 33Ω 33Ω 2V p-p *C1 C VINx+ ADC 5pF 33Ω 0.1µF R VCM VINx– ET1-1-I3 33Ω C *C1 200Ω 0.1µF C 0.1µF *C1 IS OPTIONAL Figure 55. Differential Double Balun Input Configuration for Baseband Applications ADT1-1WT 1:1 Z RATIO R *C1 VINx+ 33Ω 2V p-p 49.9Ω C ADC 5pF R 33Ω VINx– VCM *C1 0.1µF 0.1μF *C1 IS OPTIONAL 10537-047 200Ω Figure 56. Differential Transformer-Coupled Configuration for Baseband Applications Rev. B | Page 20 of 36 10537-046 R 60 85 10537-049 –6 Data Sheet AD9645 For optimum performance, clock the AD9645 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 44) and require no external bias. Clock Input Options The AD9645 has a flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 57 and Figure 58 show two preferred methods for clocking the AD9645 (at clock rates up to 1 GHz prior to the internal clock divider). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer or an RF balun. Mini-Circuits® ADT1-1WT, 1:1 Z 0.1µF CLOCK INPUT XFMR 0.1µF CLK+ 100Ω 50Ω ADC 0.1µF If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 59. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516-0/AD9516-1/AD9516-2/ AD9516-3/AD9516-4/AD9516-5/AD9517-0/AD9517-1/ AD9517-2/AD9517-3/AD9517-4 clock drivers offer excellent jitter performance. 0.1µF 0.1µF CLOCK INPUT CLK+ 0.1µF CLOCK INPUT AD951x PECL DRIVER 100Ω ADC 0.1µF CLK– 50kΩ 240Ω 50kΩ 10537-053 CLOCK INPUT CONSIDERATIONS 240Ω Figure 59. Differential PECL Sample Clock (Up to 1 GHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 60. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-0/ AD9516-1/AD9516-2/AD9516-3/AD9516-4/AD9516-5/ AD9517-0/AD9517-1/AD9517-2/AD9517-3/AD9517-4 clock drivers offer excellent jitter performance. CLK– 0.1µF CLK+ Figure 57. Transformer-Coupled Differential Clock (Up to 200 MHz) 0.1µF CLOCK INPUT 100Ω ADC 0.1µF CLK– 50kΩ 50kΩ Figure 60. Differential LVDS Sample Clock (Up to 1 GHz) 0.1µF CLK+ ADC 0.1µF 0.1µF CLK– SCHOTTKY DIODES: HSMS2822 10537-051 50Ω AD951x LVDS DRIVER In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 61). Figure 58. Balun-Coupled Differential Clock (Up to 1 GHz) VCC The RF balun configuration is recommended for clock frequencies between 125 MHz and 1 GHz, and the RF transformer configuration is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary winding limit clock excursions into the AD9645 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9645 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. However, the diode capacitance comes into play at frequencies above 500 MHz. Care must be taken when choosing the appropriate signal limiting diode. 0.1µF CLOCK INPUT 50Ω1 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω 1kΩ CLK+ ADC CLK– 0.1µF 150Ω RESISTOR IS OPTIONAL. 10537-055 0.1µF CLOCK INPUT 0.1µF CLOCK INPUT 10537-054 10537-050 SCHOTTKY DIODES: HSMS2822 0.1µF Figure 61. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider The AD9645 contains an input clock divider that can divide the input clock by integer values from 1 to 8. To achieve a given sample rate, the frequency of the externally applied clock must be multiplied by the divide value. The increased rate of the external clock normally results in lower clock jitter, which is beneficial for IF undersampling applications. Rev. B | Page 21 of 36 AD9645 Data Sheet Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9645 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9645. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by the following equation: In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 62). 130 Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 63, the power dissipated by the AD9645 is proportional to its sample rate. The AD9645 is placed in powerdown mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9645 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. 240 125MSPS 200 105MSPS 180 80MSPS 65MSPS 160 50MSPS 140 40MSPS 120 20MSPS RMS CLOCK JITTER REQUIREMENT 100 10 120 30 50 70 90 110 130 SAMPLE RATE (MSPS) 110 100 16 BITS 90 14 BITS 80 Figure 63. Total Power Dissipation vs. fSAMPLE for fIN = 9.7 MHz 12 BITS 70 10 BITS 60 8 BITS 50 40 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 30 1 10 100 ANALOG INPUT FREQUENCY (MHz) Figure 62. Ideal SNR vs. Input Frequency and Jitter 1000 10537-056 SNR (dB) 220 10537-079 1 SNR Degradation = 20 log10 2π × f × t J A The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9645. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock as the last step. TOTAL POWER DISSIPATION (mW) Clock Duty Cycle Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when the part enters power-down mode and must then be recharged when the part returns to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in powerdown mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wakeup times are required. See the Memory Map section for more details on using these features. Rev. B | Page 22 of 36 Data Sheet AD9645 DIGITAL OUTPUTS AND TIMING The AD9645 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This default setting can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing (or 700 mV p-p differential) at the receiver. Figure 65 shows the LVDS output timing example in reduced range mode. The LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close as possible to the receiver. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, ensure that the trace length is less than 24 inches and that the differential output traces are close together and at equal lengths. Figure 64 shows an example of the FCO and data stream with proper trace length and position. 4ns/DIV D0 400mV/DIV D1 400mV/DIV DCO 400mV/DIV FCO 400mV/DIV 10537-059 When operating in reduced range mode, the output current is reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p differential) across a 100 Ω termination at the receiver. Figure 65. AD9645-125, LVDS Output Timing Example in Reduced Range Mode Figure 66 shows an example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on standard FR-4 material. 500 EYE: ALL BITS ULS: 7000/400354 EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 –400 –500 –0.8ns 0ns 0.4ns 0.8ns 7k 6k Figure 64. AD9645-125, LVDS Output Timing Example in ANSI-644 Mode (Default) TIE JITTER HISTOGRAM (Hits) 5k 4k 3k 2k 1k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps 10537-060 4ns/DIV 10537-058 D0 500mV/DIV D1 500mV/DIV DCO 500mV/DIV FCO 500mV/DIV –0.4ns Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only Rev. B | Page 23 of 36 AD9645 Data Sheet Figure 67 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Note that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. 500 EYE: ALL BITS Data from each ADC is serialized and provided on a separate channel in two lanes in DDR mode. The data rate for each serial stream is equal to (16 bits × the sample clock rate)/2 lanes, with a maximum of 1 Gbps/lane ((16 bits × 125 MSPS)/(2 lanes) = 1 Gbps/lane)). The maximum allowable output data rate is 1 Gbps/lane. If one-lane mode is used, the data rate doubles for a given sample rate. To stay within the maximum data rate of 1 Gbps/lane, the sample rate is limited to a maximum of 62.5 MSPS in one-lane output mode. ULS: 8000/414024 EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 The lowest typical conversion rate is 10 MSPS. For conversion rates of less than 20 MSPS, the SPI must be used to reconfigure the integrated PLL. See Register 0x21 in the Memory Map section for details on enabling this feature. –400 –500 –0.8ns –0.4ns 0ns 0.4ns 0.8ns Two output clocks are provided to assist in capturing data from the AD9645. The DCO is used to clock the output data and is equal to 4× the sample clock (CLK) rate for the default mode of operation. Data is clocked out of the AD9645 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate in 1× frame mode. See the Timing Diagrams section for more information. 12k 10k TIE JITTER HISTOGRAM (Hits) The format of the output data is twos complement by default. An example of the output coding format can be found in Table 9. To change the output data format to offset binary, see the Memory Map section. 8k 6k 4k 0 –800ps –600ps –400ps –200ps 0ps 200ps 400ps 600ps 10537-061 2k Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater Than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only It is the responsibility of the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of both outputs to drive longer trace lengths. This increase in current can be achieved by programming Register 0x15. Although an increase in current produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins, if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 180° relative to the output data edge. A 12-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower resolution systems. When changing the resolution to a 12-bit serial stream, the data stream is shortened. See Figure 3 for the 12-bit example. In the default option with the serial output number of bits at 16, the data stream stuffs two 0s at the end of the 14-bit serial data. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. This can be inverted by using the SPI so that the LSB is first in the data output serial stream. Table 9. Digital Output Coding Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) <−VREF − 0.5 LSB −VREF 0V +VREF − 1.0 LSB >+VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1100 1111 1111 1111 1100 Rev. B | Page 24 of 36 Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1100 0111 1111 1111 1100 Data Sheet AD9645 Table 10. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 PN sequence long1 Digital Output Word 1 Not applicable 1000 0000 0000 (12-bit) 1000 0000 0000 0000 (16-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 1100 (16-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 0000 (16-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 1000 (16-bit) Not applicable 0110 PN sequence short1 0111 1000 1001 One-/zero-word toggle User input 1-/0-bit toggle 1010 1× sync 1011 One bit high 1100 Mixed frequency 1 Digital Output Word 2 Not applicable Not applicable Subject to Data Format Select N/A Yes Not applicable Yes Not applicable Yes 0101 0101 0101 (12-bit) 0101 0101 0101 0100 (16-bit) Not applicable No Not applicable Not applicable Yes 1111 1111 1111 (12-bit) 111 1111 1111 1100 (16-bit) Register 0x19 and Register 0x1A 1010 1010 1010 (12-bit) 1010 1010 1010 1000 (16-bit) 0000 0011 1111 (12-bit) 0000 0001 1111 1100 (16-bit) 1000 0000 0000 (12-bit) 1000 0000 0000 0000 (16-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 0000 (16-bit) Register 0x1B and Register 0x1C Not applicable No Not applicable No Not applicable No 1010 0011 0011 (12-bit) 1010 0001 1001 1100 (16-bit) Not applicable No Yes Notes Offset binary code shown Offset binary code shown Offset binary code shown PN23 ITU 0.150 X23 + X18 + 1 PN9 ITU 0.150 X9 + X5 + 1 No No Pattern associated with the external pin All test mode options except PN sequence short and PN sequence long can support 12-bit to 16-bit word lengths to verify data capture to the receiver. There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 10 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 11 for the initial values). The output is a parallel representation of the serial PN9 sequence in MSB-first format. The first output word is the first 14 bits of the PN9 sequence in MSB aligned form. Table 11. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x1FE0 0x1FFF Next Three Output Samples (MSB First), Twos Complement 0x1DF1, 0x3CC8, 0x294E 0x1FE0, 0x2001, 0x1C00 The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 11 for the initial values) and the AD9645 inverts the bit stream with relation to the ITU standard. The output is a parallel representation of the serial PN23 sequence in MSB-first format. The first output word is the first 14 bits of the PN23 sequence in MSB aligned form. Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Rev. B | Page 25 of 36 AD9645 Data Sheet SDIO/PDWN Pin CSB Pin For applications that do not require SPI mode operation, the CSB pin is tied to DRVDD, and the SDIO/PDWN pin controls power-down mode according to Table 12. The CSB pin should be tied to DRVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. Table 12. Power-Down Mode Pin Settings Note that, in non-SPI mode (CSB tied to DRVDD), the power-up sequence described in the Power and Ground Guidelines section must be adhered to. Violating the power-up sequence necessitates a soft reset via SPI, which is not possible in non-SPI mode. PDWN Pin Voltage AGND (Default) DRVDD Device Mode Run device, normal operation Power down device Note that in non-SPI mode (CSB tied to DRVDD), the powerup sequence described in the Power and Ground Guidelines section must be adhered to. Violating the power-up sequence necessitates a soft reset via the SPI, which is not possible in non-SPI mode. SCLK/DFS Pin The SCLK/DFS pin is used for output format selection in applications that do not require SPI mode operation. This pin determines the digital output format when the CSB pin is held high during device power-up. When SCLK/DFS is tied to DRVDD, the ADC output format is twos complement; when SCLK/DFS is tied to AGND, the ADC output format is offset binary. Table 13. Digital Output Format DFS Voltage AGND DRVDD Output Format Offset binary Twos complement RBIAS Pin To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. OUTPUT TEST MODES The output test options are described in Table 10 and are controlled by the output test mode bits at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. B | Page 26 of 36 Data Sheet AD9645 SERIAL PORT INTERFACE (SPI) The AD9645 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For general operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of CSB, in conjunction with the rising edge of SCLK/DFS, determines the start of the framing. An example of the serial timing is shown in Figure 68. See Table 5 for definitions of the timing parameters. Other modes involving the CSB pin are available. CSB can be held low indefinitely, which permanently enables the device; this is called streaming. CSB can stall high between bytes to allow for additional external timing. When the CSB pin is tied high, SPI functions are placed in high impedance mode. This mode turns on the secondary functions of the SPI pins. CONFIGURATION USING THE SPI During the instruction phase of a SPI operation, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/PDWN pin, and the CSB pin (see Table 14). SCLK/DFS (a serial clock when CSB is low) is used to synchronize the read and write data presented from and to the ADC. SDIO/PDWN (serial data input/output when CSB is low) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. CSB (chip select bar) is an active low control that enables or disables the SPI read and write cycles. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Table 14. Serial Port Interface Pins Pin SCLK/DFS SDIO/PDWN CSB Function Serial clock when CSB is low. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output when CSB is low. A dualpurpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that enables the SPI mode read and write cycles. tHIGH tDS tS tDH All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB-first mode is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 68. Serial Port Interface Timing Diagram Rev. B | Page 27 of 36 D4 D3 D2 D1 D0 DON’T CARE 10537-062 SCLK DON’T CARE AD9645 Data Sheet HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9645. The SCLK/DFS pin and the CSB pin function as inputs when using the SPI interface. The SDIO/PDWN pin is bidirectional, functioning as an input during write phases and as an output during readback. In applications that do not interface to the SPI control registers, the SCLK/DFS pin and the SDIO/PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format and power-down feature control. In this mode, CSB should be connected to DRVDD, which disables the serial port interface. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK/DFS signal, the CSB signal, and the SDIO/PDWN signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9645 to prevent these signals from transitioning at the converter inputs during critical sampling periods. The SCLK/DFS and SDIO/PDWN pins serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. Table 12 and Table 13 describe the strappable functions supported on the AD9645. Note that, in non-SPI mode (CSB tied to DRVDD), the power-up sequence described in the Power and Ground Guidelines section must be adhered to. Violating the power-up sequence necessitates a soft reset via the SPI, which is not possible in non-SPI mode. SPI ACCESSIBLE FEATURES Table 15 provides a brief description of the general features that are accessible via the SPI. These features are described in general in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9645 part-specific features are described in detail in Table 16, the external memory map register table and the following text. Table 15. Features Accessible Using the SPI Feature Name Power Mode Clock Offset Test I/O Output Mode Output Phase ADC Resolution Rev. B | Page 28 of 36 Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS, set the clock divider, and set the clock divider phase Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode Allows the user to set the output clock polarity Allows for power consumption scaling with respect to sample rate Data Sheet AD9645 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each row in the memory map register table (see Table 16) has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); and the global ADC function registers, including setup, control, and test (Address 0x08 to Address 0x102). After the AD9645 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 16. The memory map register table lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x33. This means that in Address 0x05, Bits[7:6] = 00, Bits[5:4] = 11, Bits[3:2] = 00, and Bits[1:0] = 11 (in binary). This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers are documented in the Memory Map Register Descriptions section. Open Locations All address and bit locations that are not included in Table 16 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open or not listed in Table 16 (for example, Address 0x13), this address location should not be written. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Channel-Specific Registers Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 16 as local. These local registers and bits can be accessed by setting the appropriate data channel bits (A or B) and the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in Register 0x05. If all the bits are set, the subsequent write affects the registers of both channels and the DCO/FCO clock channels. In a read cycle, only one channel (A or B) should be set to read one of the two registers. If all the bits are set during a SPI read cycle, the part returns the value for Channel A. Registers and bits that are designated as global in Table 16 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. B | Page 29 of 36 AD9645 Data Sheet MEMORY MAP REGISTER TABLE The AD9645 uses a 3-wire interface and 16-bit addressing and, therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset, where all of the user registers revert to their default values and Bit 2 is automatically cleared. Table 16. Addr. Parameter Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 SPI port 0 = SDO configuration active 0x01 Chip ID (global) 0x02 Chip grade (global) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first Soft reset 1 = 16-bit address 1 = 16-bit address Soft reset LSB first Bit 0 (LSB) 0 = SDO active 8-bit chip ID, Bits[7:0] AD9645 0x8B = dual, 14-bit, 80 MSPS/125 MSPS, serial LVDS Open Speed grade ID, Bits[6:4] 100 = 80 MSPS 110 = 125 MSPS Default Value (Hex) 0x18 0x8B Open Open Open Open Device Index and Transfer Registers 0x05 Device index Open Open Clock Channel DCO Clock Channel FCO Open Open Data Channel B Data Channel A 0x33 0xFF Open Open Open Open Open Open Open Initiate override 0x00 Global ADC Function Registers 0x08 Power modes Open (global) Open Open Open Open Open 0x09 Clock (global) Open Open Open Open Open Open 0x0B Clock divide (global) Open Open Open Open Open 0x0C Enhancement control Open Open Open Open Open Transfer Rev. B | Page 30 of 36 Chop mode 0 = off 1 = on Power mode 00 = chip run 01 = full power-down 10 = standby 11 = reset Open Duty cycle stabilizer 0 = off 1 = on Clock divide ratio[2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Open Open Comments Nibbles are mirrored to allow a given register value to perform the same function for either MSBfirst or LSBfirst mode. Unique chip ID used to differentiate devices; read only. Unique speed grade ID used to differentiate graded devices; read only. Bits are set to determine which device on chip receives the next write command. Default is all devices on chip. Set resolution/ sample rate override. 0x00 Determines various generic modes of chip operation. 0x00 Turns duty cycle stabilizer on or off. 0x00 0x00 Enables/ disables chop mode. Data Sheet AD9645 Parameter Name Test mode (local except for PN sequence resets) 0x10 0x14 Offset adjust (local) Output mode Open 0x15 Output adjust Open 0x16 Output phase Open 0x18 VREF Open Open Open Open Open 0x19 USER_PATT1_LS B (global) USER_PATT1_MS B (global) USER_PATT2_LS B (global) USER_PATT2_MS B (global) B7 B6 B5 B4 B3 B2 B15 B14 B13 B12 B11 B10 B9 B8 0x00 B7 B6 B5 B4 B3 B2 B1 B0 0x00 B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x1A 0x1B 0x1C Bit 7 Bit 6 (MSB) User input test mode 00 = single 01 = alternate 10 = single once 11 = alternate once (affects user input test mode only, Bits[3:0] = 1000) Bit 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Reset PN Reset PN Output test mode, Bits[3:0] (local) short long gen 0000 = off (default) gen 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN23 sequence 0110 = PN9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 8-bit device offset adjustment, Bits[7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) LVDS-ANSI/ Open Open Open Output Open Output LVDS-IEEE format invert option 0 = offset (local) 0 = LVDS-ANSI binary 1 = LVDS-IEEE 1 = twos reduced range complelink (global); ment see Table 17 (global) Open Output driver Open Open Open Output drive termination, Bits[1:0] 0 = 1× 00 = none drive 01 = 200 Ω 1 = 2× 10 = 100 Ω drive 11 = 100 Ω Input clock phase adjust, Bits[6:4] Output clock phase adjust, Bits[3:0] (value is number of input clock cycles (0000 through 1011); see Table 19 of phase delay); see Table 18 Default Value (Hex) 0x00 Addr. (Hex) 0x0D Rev. B | Page 31 of 36 Internal VREF adjustment digital scheme, Bits[2:0] 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p B1 B0 0x00 0x01 Comments When set, the test data is placed on the output pins in place of normal data. Device offset trim. Configures the outputs and format of the data. 0x00 Determines LVDS or other output properties. 0x03 On devices using global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. Selects and/or adjusts VREF. 0x04 0x00 User Defined Pattern 1 LSB. User Defined Pattern 1 MSB. User Defined Pattern 2 LSB. User Defined Pattern 2 MSB. AD9645 Data Sheet Addr. (Hex) 0x21 Parameter Name Serial output data control (global) Bit 7 (MSB) LVDS output 0 = MSB first (default) 1 = LSB first 0x22 Serial channel status (local) 0x10 0 0x10 1 0x10 2 Bit 6 Bit 5 Bit 4 SDR/DDR one-lane/two-lane, bitwise/bytewise, Bits[6:4] 000 = SDR two-lane, bitwise 001 = SDR two-lane, bytewise 010 = DDR two-lane, bitwise 011 = DDR two-lane, bytewise (default) 100 = DDR one-lane, wordwise Open Open Open Resolution/ sample rate override Open Resolution/ sample rate override enable User I/O Control 2 User I/O Control 3 Open Open Open Open Open Open Open Open Open Open VCM powerdown Open Open Resolution 01 = 14 bits 10 = 12 bits Bit 3 Encode mode 0= normal encode rate mode (default) 1 = low encode mode for sample rate of <20 MSPS Open Bit 2 0 = 1× frame (default) 1 = 2× frame Open Open Rev. B | Page 32 of 36 Bit 0 Bit 1 (LSB) Serial output number of bits 00 = 16 bits (default) 10 = 12 bits Channel output reset Channel powerdown Sample rate 000 = 20 MSPS 001 = 40 MSPS 010 = 50 MSPS 011 = 65 MSPS 100 = 80 MSPS 101 = 105 MSPS 110 = 125 MSPS Open SDIO pull-down Open Open Default Value (Hex) 0x30 0x00 0x00 0x00 0x00 Comments Serial stream control. Sample rate of <20 MSPS requires that Bits[6:4] = 100 (DDR one-lane) and Bit 3 = 1 (low encode mode). Used to power down individual sections of a converter. Resolution/ sample rate override (requires writing to the transfer register, 0xFF). Disables SDIO pull-down. VCM control. Data Sheet AD9645 Table 17. LVDS-ANSI/LVDS-IEEE Options MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Output Mode, Bit 6 0 Device Index (Register 0x05) 1 There are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context), regardless of which is selected. Bits[1:0] in Register 0x05 can be used to select which individual data channel is affected. The output clock channels can be selected in Register 0x05, as well. A smaller subset of the independent feature list can be applied to those devices. Output Mode LVDS-ANSI Output Driver Termination User selectable LVDS-IEEE reduced range link User selectable Output Driver Current Automatically selected to give proper swing Automatically selected to give proper swing Bits[5:3]—Open Bit 2—Output Invert Setting this bit inverts the output bit stream. Bit 1—Open Transfer (Register 0xFF) Bit 0—Output Format All registers except Register 0x100 are updated the moment they are written. Setting Bit 0 of Register 0xFF high initializes the settings in the ADC sample rate override register (Address 0x100). By default, this bit is set to send the data output in twos complement format. Clearing this bit to 0 changes the output mode to offset binary. Power Modes (Register 0x08) Bits[7:2]—Open Output Adjust (Register 0x15) Bits[7:6]—Open Bits[1:0]—Power Mode Bits[5:4]—Output Driver Termination In normal operation (Bits[1:0] = 00), both ADC channels are active. These bits allow the user to select the internal termination resistor. In power-down mode (Bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. Outputs are disabled. Bit 0—Output Drive Bits[3:1]—Open During a digital reset (Bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except the SPI port. Note that the SPI is always left under control of the user; that is, it is never automatically disabled or in reset (except by power-on reset). Bit 0 of the output adjust register controls the drive strength on the LVDS driver of the FCO and DCO outputs only. The default values set the drive to 1×, or the drive can be increased to 2× by setting the appropriate channel bit in Register 0x05 and then setting Bit 0. These features cannot be used with the output driver termination select. The termination selection takes precedence over the 2× driver strength on FCO and DCO when both the output driver termination and output drive are selected. Enhancement Control (Register 0x0C) Bits[7:3]—Open Output Phase (Register 0x16) Bit 7—Open Bit 2—Chop Mode Bits[6:4]—Input Clock Phase Adjust For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9645 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2, where it can be filtered. When the clock divider (Register 0x0B) is used, the applied clock is at a higher frequency than the internal sampling clock. Bits[6:4] determine at which phase of the external clock sampling occurs. This is only applicable when the clock divider is used. Setting Bits[6:4] greater than Register 0x0B, Bits[2:0] is prohibited. In standby mode (Bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. Table 18. Input Clock Phase Adjust Options Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Setting this bit selects the LVDS-IEEE (reduced range) option. The default setting is LVDS-ANSI. When LVDS-ANSI or the LVDS-IEEE reduced range link is selected, the user can select the driver termination (see Table 17). The driver current is automatically selected to give the proper output swing. Input Clock Phase Adjust, Bits[6:4] 000 (Default) 001 010 011 100 101 110 111 Rev. B | Page 33 of 36 Number of Input Clock Cycles of Phase Delay 0 1 2 3 4 5 6 7 AD9645 Data Sheet Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) See Table 19 for details. This register allows the user to downgrade the resolution and/or the maximum sample rate (for lower power) in applications that do not require full resolution and/or sample rate. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is written high. Table 19. Output Clock Phase Adjust Options Output Clock (DCO), Phase Adjust, Bits[3:0] 0000 0001 0010 0011 (Default) 0100 0101 0110 0111 1000 1001 1010 1011 DCO Phase Adjustment (Degrees Relative to D0x±/D1x± Edge) 0 60 120 180 240 300 360 420 480 540 600 660 Bits[2:0] do not affect the sample rate; they affect the maximum sample rate capability of the ADC. User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. User I/O Control 3 (Register 0x102) Bits[7:4]—Open Serial Output Data Control (Register 0x21) Bit 3—VCM Power-Down The serial output data control register is used to program the AD9645 in various output data modes, depending on the data capture solution. Table 20 describes the various serialization options available in the AD9645. Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an input common mode voltage from an external source. Bits[2:0]—Open Table 20. SPI Register Options Register 0x21 Contents 0x30 0x20 0x10 0x00 0x34 0x24 0x14 0x04 0x40 0x32 0x22 0x12 0x02 0x36 0x26 0x16 0x06 0x42 Serialization Options Selected Serial Output Number of Bits (SONB) Frame Mode Serial Data Mode 16-bit 1× DDR two-lane bytewise 16-bit 1× DDR two-lane bitwise 16-bit 1× SDR two-lane bytewise 16-bit 1× SDR two-lane bitwise 16-bit 2× DDR two-lane bytewise 16-bit 2× DDR two-lane bitwise 16-bit 2× SDR two-lane bytewise 16-bit 2× SDR two-lane bitwise 16-bit 1× DDR one-lane wordwise 12-bit 1× DDR two-lane bytewise 12-bit 1× DDR two-lane bitwise 12-bit 1× SDR two-lane bytewise 12-bit 1× SDR two-lane bitwise 12-bit 2× DDR two-lane bytewise 12-bit 2× DDR two-lane bitwise 12-bit 2× SDR two-lane bytewise 12-bit 2× SDR two-lane bitwise 12-bit 1× DDR one-lane wordwise Rev. B | Page 34 of 36 DCO Multiplier 4 × fS 4 × fS 8 × fS 8 × fS 4 × fS 4 × fS 8 × fS 8 × fS 8 × fS 3 × fS 3 × fS 6 × fS 6 × fS 3 × fS 3 × fS 6 × fS 6 × fS 6 × fS Timing Diagram See Figure 2 (default setting) See Figure 2 See Figure 2 See Figure 2 See Figure 4 See Figure 4 See Figure 4 See Figure 4 See Figure 6 See Figure 3 See Figure 3 See Figure 3 See Figure 3 See Figure 5 See Figure 5 See Figure 5 See Figure 5 See Figure 7 Data Sheet AD9645 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9645 as a system, it is recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements that are needed for certain pins. POWER AND GROUND GUIDELINES When connecting power to the AD9645, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. If two supplies are used, AVDD must not power up before DRVDD. DRVDD must power up before, or simultaneously with, AVDD. If this sequence is violated, a soft reset via SPI Register 0x00 (Bits[7:0] = 0x3C), followed by a digital reset via SPI Register 0x08 (Bits[7:0] = 0x03, then Bits[7:0] = 0x00), restores the part to proper operation. EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9645. An exposed continuous copper plane on the PCB should mate to the AD9645 exposed pad, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 69 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. SILKSCREEN PARTITION PIN 1 INDICATOR In non-SPI mode, the supply sequence is mandatory; in this case, violating the supply sequence is nonrecoverable. CLOCK STABILITY CONSIDERATIONS When powered on, the AD9645 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. During the initialization process, the AD9645 needs a stable clock. If the ADC clock source is not present or not stable during ADC power-up, it disrupts the state machine and causes the ADC to start up in an unknown state. To correct this, reinvoke an initialization sequence after the ADC clock is stable by issuing a digital reset via Register 0x08. In the default configuration (internal VREF, accoupled input) where VREF and VCM are supplied by the ADC itself, a stable clock during power-up is sufficient. In the case where VCM is supplied by an external source, this, too, must be stable at power-up; otherwise, a subsequent digital reset via Register 0x08 is needed. The pseudo code sequence for a digital reset is as follows: SPI_Write (0x08, 0x03); # Digital Reset SPI_Write (0x08, 0x00); # Normal Operation 10537-063 A single PCB ground plane should be sufficient when using the AD9645. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Figure 69. Typical PCB Layout VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor. REFERENCE DECOUPLING The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI PORT The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9645 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Rev. B | Page 35 of 36 AD9645 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 EXPOSED PAD 3.60 SQ 3.55 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 08-16-2010-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 70. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9645BCPZ-80 AD9645BCPZRL7-80 AD9645BCPZ-125 AD9645BCPZRL7-125 AD9645-125EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) Evaluation Board Z = RoHS Compliant Part. ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10537-0-10/15(B) Rev. B | Page 36 of 36 Package Option CP-32-12 CP-32-12 CP-32-12 CP-32-12