Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com Report Title: Qualification Test Report Report Type: See Attached Date: See Attached QTR: 2013-00273 Wafer Process: PHEMT-G HMC599 HMC650 HMC651 HMC652 HMC653 HMC654 HMC655 HMC656 HMC657 HMC658 Rev: 01 QTR: 2013-00273 Wafer Process: PHEMT-G Rev: 01 Introduction The testing performed for this report is designed to accelerate the predominant failure mode, electro-migration (EM), for the devices under test. The devices are stressed at high temperature and DC biased to simulate a lifetime of use at typical operating temperatures. Using the Arrhenius equation, the acceleration factor (AF) is calculated for the stress testing based on the stress temperature and the typical use operating temperature. This report is intended to summarize all of the High Temperature Operating Life Test (HTOL) data for the PHEMT-G process. The FIT/MTTF data contained in this report includes all the stress testing performed on this process to date and will be updated periodically as additional data becomes available. Data sheets for the tested devices can be found at www.hittite.com. Glossary of Terms & Definitions: 1. HTOL: High Temperature Operating Life. This test is used to determine the effects of bias conditions and temperature on semiconductor devices over time. It simulates the devices’ operating condition in an accelerated way, through high temperature and/or bias voltage, and is primarily for device qualification and reliability monitoring. This test was performed in accordance with JEDEC JESD22-A108. 2. Operating Junction Temp (T oj ): Temperature of the die active circuitry during typical operation. 3. Stress Junction Temp (T sj ): Temperature of the die active circuitry during stress testing. QTR: 2013-00273 Wafer Process: PHEMT-G Rev: 01 Qualification Sample Selection: All qualification devices used were manufactured and tested on standard production processes and met pre-stress acceptance test requirements. Summary of Qualification Tests: HMC656 (QTR11011) QTY IN 12 QTY OUT 12 RF HTOL, 1000 hours 12 12 Complete Post HTOL Electrical Test 12 12 Pass TEST Initial Electrical PASS/FAIL Complete NOTES QTR: 2013-00273 Wafer Process: PHEMT-G Rev: 01 PHEMT-G Failure Rate Estimate Based on the HTOL test results, a failure rate estimation was determined using the following parameters: With Device Die Junction Temp, T j = 60°C HMC656 (QTR11011) Operating Junction Temp (T oj ) = 60°C(333°K) Stress Junction Temp (T sj ) = 125°C(398°K) Device hours: HMC656 (QTR11011) = (12 X 1000hrs) = 12,000 hours For PHEMT-G MMIC, Activation Energy = 1.3 eV Acceleration Factor (AF): HMC656 (QTR11011) Acceleration Factor = exp[1.3/8.6 e-5(1/333-1/398)] = 1658.4 Equivalent hours = Device hours x Acceleration Factor Equivalent hours = (12,000x1658.4) = 1.99x107 hours Since there was no failures and we used a time terminated test, F=0, and R = 2F+2 = 2 QTR: 2013-00273 Wafer Process: PHEMT-G Rev: 01 The failure rate was calculated using Chi Square Statistic: at 60% and 90% Confidence Level (CL), with 0 units out of spec and a 60°C device junction temp; Failure Rate λ 60 = [(χ2) 60 , 2 ]/(2X λ 90 = [(χ2) 90 , 2 ]/(2X 1.99x107 )] = 1.8/ 3.98x107 = 4.60x10-8 failures/hour or 46.0 FIT or MTTF = 2.17x107 Hours 1.99x107 )] = 4.6/ 3.98x107 = 1.16x10-7 failures/hour or 116 FIT or MTTF = 8.63x106 Hours