Balanced Modulator/Demodulator AD630 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Recovers signal from 100 dB noise 2 MHz channel bandwidth 45 V/µs slew rate Low crosstalk: −120 dB at 1 kHz, −100 dB at 10 kHz Pin programmable, closed-loop gains of ±1 and ±2 0.05% closed-loop gain accuracy and match 100 µV channel offset voltage (AD630) 350 kHz full power bandwidth Chips available RINA CM OFF ADJ DIFF OFF ADJ DIFF OFF ADJ BIAS 2.5kΩ AMP A CH A+ COMP CH A– RINB A +VS 2.5kΩ AMP B 10kΩ –V 10kΩ 5kΩ Balanced modulation and demodulation Synchronous detection Phase detection Quadrature detection Phase sensitive detection Lock in amplification Square wave multiplication +VS VOUT B CH B+ CH B– APPLICATIONS RB RF RA CHANNEL STATUS B/A COMP SEL B –VS 00784-001 SEL A Figure 1. GENERAL DESCRIPTION The AD630 is a high precision balanced modulator/demodulator that combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin film resistors. A network of on-board applications resistors provides precision closed-loop gains of ±1 and ±2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of 1, 2, 3, or 4. External feedback enables high gain or complex switched feedback topologies. The AD630 can be thought of as a precision op amp with two independent differential input stages and a precision comparator that is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. The AD630 is used in precision signal processing and instrumentation applications that require wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, the AD630 can recover a small signal from 100 dB of interfering noise (see the Lock-In Amplifier Applications section). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz. Rev. F CM OFF ADJ Other features of the AD630 include pin programmable frequency compensation; optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output that indicates which of the two differential inputs is active. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. The application flexibility of the AD630 makes it the best choice for applications that require precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high speed precision amplification. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. The op amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. The AD630 can be used as a 2-channel multiplexer with gains of 1, 2, 3, or 4. The channel separation of 100 dB at 10 kHz approaches the limit achievable with an empty IC package. Laser trimming of the comparator and amplifying channel offsets eliminate the need for external nulling in most cases. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD630 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description .................................................................... 13 Applications ....................................................................................... 1 Other Gain Configurations ....................................................... 14 Functional Block Diagram .............................................................. 1 Switched Input Impedance........................................................ 14 General Description ......................................................................... 1 Frequency Compensation ......................................................... 14 Product Highlights ........................................................................... 1 Offset Voltage Nulling ............................................................... 15 Revision History ............................................................................... 2 Channel Status Output .............................................................. 15 Specifications..................................................................................... 3 Applications Information .............................................................. 16 Absolute Maximum Ratings ............................................................ 4 Balanced Modulator ................................................................... 16 Thermal Resistance ...................................................................... 4 Balanced Demodulator .............................................................. 16 Chip Availability ........................................................................... 4 Precision Phase Comparator .................................................... 16 ESD Caution .................................................................................. 4 Precision Rectifier Absolute Value ........................................... 16 Pin Configurations and Function Descriptions ........................... 5 LVDT Signal Conditioner ......................................................... 17 Typical Performance Characteristics ............................................. 9 AC Bridge .................................................................................... 17 Test Circuits ..................................................................................... 11 Lock-In Amplifier Applications ............................................... 18 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 19 Two Ways To Look At The AD630 .......................................... 12 Ordering Guide .......................................................................... 20 How the AD630 Works .............................................................. 12 REVISION HISTORY 7/15—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Features Section, General Description Section, Product Highlights Section, and Figure 1 ..................................... 1 Added Applications Section ............................................................ 1 Changes to Table 3 ............................................................................ 4 Added Table 4; Renumbered Sequentially .................................... 5 Added Figure 4; Renumbered Sequentially and Table 5 ............. 6 Added Figure 5 and Table 6............................................................. 7 Added Table 7.................................................................................... 8 Changes to Figure 7, Figure 8, and Figure 9.................................. 9 Changes to Figure 13, Figure 14, and Figure 15 ......................... 10 Added Test Circuits Section and Figure 16 to Figure 19 ........... 11 Added Theory of Operation Section............................................ 12 Change to Figure 24 ....................................................................... 13 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 6/04—Rev. D to Rev. E Changes to Ordering Guide .............................................................3 Replaced Figure 12 ............................................................................9 Changes to AC Bridge Section.........................................................9 Replaced Figure 13 ......................................................................... 10 Changes to Lock-In Amplifier Applications ............................... 10 Updated Outline Dimensions ....................................................... 11 6/01—Rev. C to Rev. D Changes to Specification Table ........................................................2 Changes to Thermal Characteristics ...............................................3 Changes to Ordering Guide .............................................................3 Changes to Pin Configurations .......................................................3 Changes to Outline Dimensions .................................................. 11 Rev. F | Page 2 of 20 Data Sheet AD630 SPECIFICATIONS At 25°C and ±VS = ±15 V, unless otherwise noted. Table 1. Parameter GAIN Open-Loop Gain ±1, ±2 Closed-Loop Gain Error Closed-Loop Gain Match Closed-Loop Gain Drift CHANNEL INPUTS VIN Operational Limit1 Input Offset Voltage TMIN to TMAX Input Bias Current Input Offset Current Channel Separation at 10 kHz COMPARATOR VIN Operational Limit1 Switching Window TMIN to TMAX Input Bias Current Response Time (−5 mV to +5 mV Step) Channel Status ISINK at VOL = −VS + 0.4 V2 Pull-Up Voltage DYNAMIC PERFORMANCE Unity Gain Bandwidth Slew Rate3 Settling Time to 0.1% (20 V Step) OPERATING CHARACTERISTICS Common-Mode Rejection Power Supply Rejection Supply Voltage Range Supply Current OUTPUT VOLTAGE, AT RL = 2 kΩ TMIN to TMAX Output Short-Circuit Current TEMPERATURE RANGES N Package D Package Min 90 AD630J/AD630A Typ Max 110 0.1 0.1 2 Min AD630K/AD630B Typ Max 100 120 Min 90 0.05 0.05 2 AD630S Typ Max Unit 110 0.1 0.1 2 dB % % ppm/°C (−VS + 4) to (+VS − 1) 500 800 100 300 10 50 100 (−VS + 4) to (+VS − 1) 100 160 100 300 10 50 100 (−VS + 4) to (+VS − 1) 500 1000 100 300 10 50 100 V µV µV nA nA dB (−VS + 3) to (+VS − 1.5) ±1.5 ±2.0 100 300 200 (−VS + 3) to (+VS − 1.5) ±1.5 ±2.0 100 300 200 (−VS + 3) to (+VS − 1.3) ±1.5 ±2.5 100 300 200 V mV mV nA ns 1.6 1.6 1.6 (−VS + 33) (−VS + 33) 2 45 3 85 90 ±5 2 45 3 105 110 4 ±16.5 5 ±10 90 90 ±5 110 110 4 ±16.5 5 ±10 25 0 −25 (−VS + 33) 90 90 ±5 70 +85 0 −25 2 45 3 MHz V/µs µs 110 110 dB dB V mA 4 ±16.5 5 ±10 25 V mA 25 70 +85 −55 +125 If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. ISINK at VOL = (−VS + 1 V) is typically 4 mA. 3 Pin 12 open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/µs. 1 2 Rev. F | Page 3 of 20 mA V °C °C AD630 Data Sheet ABSOLUTE MAXIMUM RATINGS CHIP AVAILABILITY Table 2. The AD630 is available in laser trimmed, passivated chip form. Figure 2 shows the AD630 metallization pattern, bonding pads, and dimensions. AD630 chips are available; consult factory for details. Rating ±18 V 600 mW Indefinite 18 17 −65°C to +150°C −55°C to +125°C 300°C 150°C 0.99 (2.515) 15 19 14 20 13 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 0.089 (2.260) 12 11 10 9 3 4 THERMAL RESISTANCE 5 6 7 8 Figure 2. Chip Metallization and Pinout Dimensions shown in inches and (millimeters) Contact factory for latest dimensions Table 3. Thermal Resistance Package Type 20-Lead PDIP (N-20) 20-Lead SBDIP (D-20) 20-Lead LCC (E-20-4) 20-Lead SOIC_W (RW-20) 16 θJC 24 35 35 38 θJA 61 120 120 75 Unit °C/W °C/W °C/W °C/W ESD CAUTION Rev. F | Page 4 of 20 00784-002 Parameter Supply Voltage Internal Power Dissipation Output Short-Circuit to Ground Storage Temperature Ceramic Package Plastic Package Lead Temperature Range (Soldering, 10 sec) Maximum Junction Temperature Data Sheet AD630 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RINA 1 20 CH A– CH A+ 2 19 CH B– 18 CH B+ DIFF OFF ADJ 4 AD630 17 RINB CM OFF ADJ 6 TOP VIEW 16 RA (Not to Scale) 15 RF CHANNEL STATUS B/A 7 14 RB CM OFF ADJ 5 –VS 8 13 VOUT SEL B 9 12 COMP SEL A 10 11 +VS 00784-030 DIFF OFF ADJ 3 Figure 3. 20-Lead SOIC Pin Configuration Table 4. 20-Lead SOIC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic RINA CH A+ DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ CHANNEL STATUS B/A −VS SEL B SEL A +VS COMP VOUT RB RF RA RINB CH B+ CH B− CH A− Description 2.5 kΩ Resistor to Noninverting Input of Op Amp A Noninverting Input of Op Amp A Differential Offset Adjustment Differential Offset Adjustment Common-Mode Offset Adjustment Common-Mode Offset Adjustment B or A Channel Status Negative Supply B Channel Comparator Input A Channel Comparator Input Positive Supply Pin to Connect Internal Compensation Capacitor Output Voltage 10 kΩ Gain Setting Resistor 10 kΩ Feedback Resistor 5 kΩ Feedback Resistor 2.5 kΩ Resistor to Noninverting Input of Op Amp B Noninverting Input of Op Amp B Inverting Input of Op Amp B Inverting Input of Op Amp A Rev. F | Page 5 of 20 AD630 Data Sheet RINA 1 20 CH A– CH A+ 2 19 CH B– DIFF OFF ADJ 3 18 CH B+ RINB CM OFF ADJ 5 CM OFF ADJ 6 AD630 17 TOP VIEW 16 RA (Not to Scale) 15 RF CHANNEL STATUS B/A 7 –VS 8 14 RB 13 VOUT SEL B 9 12 SEL A 10 11 COMP +VS 00784-031 DIFF OFF ADJ 4 Figure 4. 20-Lead PDIP Pin Configuration Table 5. 20-Lead PDIP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic RINA CH A+ DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ CHANNEL STATUS B/A −VS SEL B SEL A +VS COMP VOUT RB RF RA RINB CH B+ CH B− CH A− Description 2.5 kΩ Resistor to Noninverting Input of Op Amp A Noninverting Input of Op Amp A Differential Offset Adjustment Differential Offset Adjustment Common-Mode Offset Adjustment Common-Mode Offset Adjustment B or A Channel Status Negative Supply B Channel Comparator Input A Channel Comparator Input Positive Supply Pin to Connect Internal Compensation Capacitor Output Voltage 10 kΩ Gain Setting Resistor 10 kΩ Feedback Resistor 5 kΩ Feedback Resistor 2.5 kΩ Resistor to Noninverting Input of Op Amp B Noninverting Input of Op Amp B Inverting Input of Op Amp B Inverting Input of Op Amp A Rev. F | Page 6 of 20 Data Sheet AD630 RINA 1 20 CH A– CH A+ 2 19 CH B– DIFF OFF ADJ 3 18 CH B+ DIFF OFF ADJ 4 CM OFF ADJ 5 17 RINB AD630 16 RA TOP VIEW CM OFF ADJ 6 (Not to Scale) 15 RF 14 RB CHANNEL STATUS B/A 7 13 VOUT 12 COMP SEL A 10 11 +VS 00784-003 –VS 8 SEL B 9 Figure 5. 20-Lead CERDIP Pin Configuration Table 6. 20-Lead CERDIP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic RINA CH A+ DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ CHANNEL STATUS B/A −VS SEL B SEL A +VS COMP VOUT RB RF RA RINB CH B+ CH B− CH A− Description 2.5 kΩ Resistor to Noninverting Input of Op Amp A Noninverting Input of Op Amp A Differential Offset Adjustment Differential Offset Adjustment Common-Mode Offset Adjustment Common-Mode Offset Adjustment B or A Channel Status Negative Supply B Channel Comparator Input A Channel Comparator Input Positive Supply Pin to Connect Internal Compensation Capacitor Output Voltage 10 kΩ Gain Setting Resistor 10 kΩ Feedback Resistor 5 kΩ Feedback Resistor 2.5 kΩ Resistor to Noninverting Input of Op Amp B Noninverting Input of Op Amp B Inverting Input of Op Amp B Inverting Input of Op Amp A Rev. F | Page 7 of 20 2 1 CH B– CH A+ 3 RIN A CH A– Data Sheet DIFF OFF ADJ AD630 20 19 18 CH B+ CM OFF ADJ 5 AD630 17 RINB CM OFF ADJ 6 TOP VIEW (Not to Scale) 16 RA 15 RF 14 RB CHANNEL STATUS B/A 7 10 11 12 13 SEL A +VS COMP VOUT 9 SEL B –VS 8 00784-004 DIFF OFF ADJ 4 Figure 6. 20-Terminal CLCC Pin Configuration Table 7. 20-Terminal CLCC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic RINA CH A+ DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ CHANNEL STATUS B/A −VS SEL B SEL A +VS COMP VOUT RB RF RA RINB CH B+ CH B− CH A− Description 2.5 kΩ Resistor to Noninverting Input of Op Amp A Noninverting Input of Op Amp A Differential Offset Adjustment Differential Offset Adjustment Common-Mode Offset Adjustment Common-Mode Offset Adjustment B or A Channel Status Negative Supply B Channel Comparator Input A Channel Comparator Input Positive Supply Pin to Connect Internal Compensation Capacitor Output Voltage 10 kΩ Gain Setting Resistor 10 kΩ Feedback Resistor 5 kΩ Feedback Resistor 2.5 kΩ Resistor to Noninverting Input of Op Amp B Noninverting Input of Op Amp B Inverting Input of Op Amp B Inverting Input of Op Amp A Rev. F | Page 8 of 20 Data Sheet AD630 TYPICAL PERFORMANCE CHARACTERISTICS 120 10 5 0 1k 10k 100k 1M FREQUENCY (Hz) 100 80 60 40 20 0 1 10 100 1k 10k 00784-008 COMMON-MODE REJECTION (dB) RL = 2kΩ CL = 100pF 00784-005 OUTPUT VOLTAGE (±V) 15 100k FREQUENCY (Hz) Figure 7. Output Voltage vs. Frequency (See Figure 16) Figure 10. Common-Mode Rejection vs. Frequency 60 15 CL = 100pF f = 1kHz UNCOMPENSATED 20 (V/µs) 10 COMPENSATED 0 dt dVO OUTPUT VOLTAGE (±V) 40 –20 5 –60 –5 1 10 100 1k 10k 100k RESISTIVE LOAD (Ω) –4 –3 –2 00784-006 0 1M –1 0 1 2 3 Figure 8. Output Voltage vs. Resistive Load (See Figure 16) Figure 11. 18 5 dVO vs. Input Voltage dt 120 f = 1kHz CL = 100pF 15 0 OPEN-LOOP GAIN (dB) 10 5 45 80 60 90 COMPENSATED 40 135 OPEN-LOOP PHASE (Degrees) 100 UNCOMPENSATED OUTPUT VOLTAGE (±V) 4 INPUT VOLTAGE (V) 00784-009 –40 0 5 10 15 20 SUPPLY VOLTAGE (±V) 0 00784-007 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Gain and Phase vs. Frequency Figure 9. Output Voltage Swing vs. Supply Voltage (See Figure 16) Rev. F | Page 9 of 20 180 10M 00784-010 20 AD630 Data Sheet 20mV 10V 100 ±10V 20kHz (Vi) 90 20mV/DIV (Vo) 1mV 5µs 100 90 1mV/DIV (B) 10V/DIV (Vo) 10 0% 500ns TOP TRACE: Vo BOTTOM TRACE: Vi 10V TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (B) BOTTOM TRACE: Vo Figure 13. Channel-to-Channel Switch-Settling Characteristic (See Figure 17) 50mV 50mV/DIV (Vi) Figure 15. Large Signal Inverting Step Response (See Figure 19) 1mV 100 90 1mV/DIV (A) 10 0% 100mV 500ns TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (A) BOTTOM TRACE: Vo 00784-013 100mV/DIV (Vo) 10 0% 00784-012 20mV 00784-011 20mV/DIV (Vi) Figure 14. Small Signal Noninverting Step Response (See Figure 18) Rev. F | Page 10 of 20 Data Sheet AD630 TEST CIRCUITS 10kΩ 5kΩ 5kΩ Vi TOP TRACE 100pF 00784-105 VO 2kΩ 1kΩ 13 10kΩ MIDDLE TRACE (A) 30pF VO BOTTOM TRACE 10kΩ TEKTRONIX 7A13 Figure 16. Test Circuit for Output Voltage vs. Frequecy, Resistive Load, and Supply Voltage (See Figure 7, Figure 8, and Figure 9) Figure 18. Test Circuit for Small Signal Noninverting Step Response (See Figure 14) 15 5kΩ 10kΩ 2 20 13 19 18 10kΩ Vi TOP TRACE CH A CH B VO 12 10kΩ 15 20 2 CH A 12 13 10kΩ 10kΩ HP5082-2811 9 10 00784-111 14 14 Figure 17. Test Circuit for Channel-to-Channel Switch-Settling Characteristic (See Figure 13) 10kΩ VO BOTTOM TRACE (B) MIDDLE TRACE 00784-112 16 Vi 2 CH A 12 00784-113 Vi 14 10kΩ 15 20 Figure 19. Test Circuit for Large Signal Noninverting Step Response (See Figure 15) Rev. F | Page 11 of 20 AD630 Data Sheet THEORY OF OPERATION TWO WAYS TO LOOK AT THE AD630 The functional block diagram of the AD630 (see Figure 1) shows the pin connections of the internal functions. An alternative architectural diagram is shown in Figure 20. In this diagram, the individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This amplifier has two differential input channels, only one of which is active at a time. +VS 11 14 RA 5kΩ RB 10kΩ 1 2 2.5kΩ A 20 The two closed-loop gain magnitudes are equal when RF/RA = 1 + RF/RB, which results from making RA equal to RFRB/(RF + RB) the parallel equivalent resistance of RF and RB. RF 10kΩ 13 19 18 17 B 12 2.5kΩ 7 CHANNEL STATUS B/A SEL B 9 00784-014 SEL A 10 8 –VS Figure 20. Architectural Block Diagram HOW THE AD630 WORKS The basic mode of operation of the AD630 may be easier to recognize as two fixed gain stages, which can be inserted into the signal path under the control of a sensitive voltage comparator. When the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. The AD630 is unique in that it includes laser wafer trimmed thin-film feedback resistors on the monolithic chip. The configuration shown in Figure 21 yields a gain of ±2 and can be easily changed to ±1 by shifting RB from its ground connection to the output. The 5 kΩ and the two 10 kΩ resistors on the AD630 chip can be used to make a gain of 2 as shown in Figure 22 and Figure 23. By paralleling the 10 kΩ resistors to make RF equal to 5 kΩ and omitting RB, the circuit can be programmed for a gain of ±1 (as shown in Figure 28). These and other configurations using the on-chip resistors present the inverting inputs with a 2.5 kΩ source impedance. The more complete AD630 diagrams show 2.5 kΩ resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents. The comparator selects one of the two input stages to complete an operational feedback connection around the AD630. The deselected input is off and has a negligible effect on operation. 16 2 20 A 19 RB 10kΩ 18 B 13 VO 14 9 10 Vi RB 10kΩ VO = – RF RA Figure 21. AD630 Symmetric Gain (±2) Rev. F | Page 12 of 20 Vi Figure 22. Inverting Gain Configuration Vi RA 5kΩ RB 10kΩ VO = (1+ RF RB RF 10kΩ Figure 23. Noninverting Gain Configuration RF 10kΩ 00784-015 Vi RA 5kΩ 15 RF 10kΩ RA 5kΩ 00784-016 16 ) Vi 00784-017 15 When Channel B is selected, the RA and RF resistors are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 22. The amplifier has sufficient loop gain to minimize the loading effect of RB at the virtual ground produced by the feedback connection. When the sign of the comparator input is reversed, Input B is deselected and Input A is selected. The new equivalent circuit is the noninverting gain configuration shown in Figure 23. In this case, RA appears across the op amp input terminals, but because the amplifier drives this difference voltage to zero, the closed-loop gain is unaffected. Data Sheet AD630 CIRCUIT DESCRIPTION Another feature of the input structure is that it enhances the slew rate of the circuit. The current output of the active stage follows a quasihyperbolic sine relationship to the differential input voltage. This means that the greater the input voltage, the harder this stage drives the output integrator, and the faster the output signal moves. This feature helps ensure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations. The simplified schematic of the AD630 is shown in Figure 24. It has been subdivided into three major sections, the comparator, the two input stages, and the output integrator. The comparator consists of a front end made up of Q52 and Q53, a flip-flop load formed by Q3 and Q4, and two current steering switching cells Q28, Q29 and Q30, Q31. This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude applied to the comparator inputs completely selects one of the switching cells. The sign of this input voltage determines which of the two switching cells is selected. The output section of the AD630 includes a current mirror load (Q24 and Q25), an integrator voltage gain stage (Q32), and a complementary output buffer (Q44 and Q74). The outputs of both transconductance stages are connected in parallel to the current mirror. Because the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. The current mirror translates the differential output current from the active input transconductance amplifier into single-ended form for the output integrator. The complementary output driver then buffers the integrator output to produce a low impedance output. The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i22 and i23 to the input stage it controls, causing it to become active. The deselected cell blocks the bias to its input stage, which, as a consequence, remains off. The structure of the transconductance stages is such that it presents a high impedance at its input terminals and draws no bias current when deselected. The deselected input does not interfere with the operation of the selected input ensuring maximum channel separation. CH A– CH A+ CH B– 2 20 CH B+ 18 19 +VS 11 Q33 Q35 Q34 Q36 i73 i55 Q44 SEL A 10 Q52 Q53 Q62 Q65 Q67 Q70 13 9 VOUT Q74 SEL B C121 Q30 12 Q31 Q28 C122 Q29 Q24 Q3 Q4 i22 COMP Q32 Q25 i23 3 4 5 6 DIFF OFF ADJ DIFF OFF ADJ CM OFF ADJ CM OFF ADJ Figure 24. AD630 Simplified Schematic Rev. F | Page 13 of 20 00784-018 –VS 8 AD630 Data Sheet OTHER GAIN CONFIGURATIONS SWITCHED INPUT IMPEDANCE Many applications require switched gains other than the ±1 and ±2, which the self-contained applications resistors provide. The AD630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and RB and RF to give the noninverting gain 1 + RF/RB and subsequent RA to give the desired inverting gain. Note that when the inverting magnitude equals the noninverting magnitude, the value of RA is found to be RBRF/(RB + RF). That is, RA equals the parallel combination of RB and RF to match positive and negative gain. The noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration. This means that the input impedance of the circuit undergoes an abrupt change as the gain is switched under control of the comparator. If the gain is switched when the input signal is not zero, as it is in many practical cases, a transient is delivered to the circuitry driving the AD630. In most applications, this requires the AD630 circuit to be driven by a low impedance source, which remains stiff at high frequencies. This is generally a wideband buffer amplifier. The feedback synthesis of the AD630 may also include reactive impedance. The gain magnitudes match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances. The same considerations apply to the AD630 as to conventional op amp feedback circuits. Virtually any function that can be realized with simple noninverting L network feedback can be used with the AD630. A common arrangement is shown in Figure 25. The low frequency gain of this circuit is 10. The response has a pole (−3 dB) at a frequency f 1/(2 π 100 kΩ × C) and a zero (3 dB from the high frequency asymptote) at about 10 times this frequency. The 2 kΩ resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stability problems, and has a minor effect on the pole-zero locations. FREQUENCY COMPENSATION As a result of the reactive feedback, the high frequency components of the switched input signal are transmitted at unity gain while the low frequency components are amplified. This arrangement is useful in demodulators and lock-in amplifiers. It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. The output signal contains the desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain. C 2kΩ 10kΩ 100kΩ C In gain of ±2 applications, the noise gain that must be addressed for stability purposes is actually 4. In this circumstance, the phase margin of the loop is on the order of 60° without the optional compensation. This condition provides the maximum bandwidth and slew rate for closed loop gains of |2| and above. When the AD630 is used as a multiplexer, or in other configurations where one or both inputs are connected for unity gain feedback, the phase margin is reduced to less than 20°. This may be acceptable in applications where fast slewing is a first priority, but the transient response is not optimum. For these applications, the self-contained compensation capacitor may be added by connecting Pin 12 to Pin 13. This connection reduces the closed-loop bandwidth somewhat and improves the phase margin. For intermediate conditions, such as a gain of ±1 where the loop attenuation is 2, determine the use of the compensation by whether bandwidth or settling response must be optimized. Also, use optional compensation when the AD630 is driving capacitive loads or whenever conservative frequency compensation is desired. 2 20 A 13 VO 19 11.11kΩ 18 B 12 7 SEL B SEL A CHANNEL STATUS B/A 9 10 8 –V S 00784-019 Vi 2kΩ The AD630 combines the convenience of internal frequency compensation with the flexibility of external compensation by means of an optional self-contained compensation capacitor. Figure 25. AD630 with External Feedback Rev. F | Page 14 of 20 Data Sheet AD630 +5V OFFSET VOLTAGE NULLING 1MΩ 100kΩ 100kΩ 9 7 10 8 100Ω –15V 00784-020 Figure 26. Comparator Hysteresis The channel status output may be interfaced with TTL inputs as shown in Figure 27. This circuit provides appropriate level shifting from the open-collector AD630 channel status output to TTL inputs. CHANNEL STATUS OUTPUT +5V +15V 6.8kΩ AD630 The channel status output, Pin 7, is an open collector output referenced to −VS that can be used to indicate which of the two input channels is active. The output is active (pulled low) when Channel A is selected. This output can also be used to supply positive feedback around the comparator. This produces hysteresis which serves to increase noise immunity. Figure 26 shows an example of how hysteresis may be implemented. Note that the feedback signal is applied to the inverting (−) terminal of the comparator to achieve positive feedback. This is because the open collector channel status output inverts the output sense of the internal comparator. Rev. F | Page 15 of 20 100kΩ 7 22kΩ IN914s 2N2222 TTL INPUT 8 –15V Figure 27. Channel Status—TTL Interface 00784-021 The offset voltages of both input stages and the comparator have been pretrimmed so that external trimming is only required in the most demanding applications. The offset adjustment of the two input channels is accomplished by means of a differential and common-mode scheme. This facilitates fine adjustment of system errors in switched gain applications. With the system input tied to 0 V, and a switching or carrier waveform applied to the comparator, a low level square wave appears at the output. The differential offset adjustment potentiometers can be used to null the amplitude of this square wave (Pin 3 and Pin 4). The common-mode offset adjustment can be used to zero the residual dc output voltage (Pin 5 and Pin 6). Implement these functions using 10 kΩ trim potentiometers with wipers connected directly to Pin 8 as shown in Figure 28 and Figure 29. AD630 Data Sheet APPLICATIONS INFORMATION BALANCED MODULATOR 5V These balanced modulator topologies accept two inputs, a signal (or modulation) input applied to the amplifying channels and a reference (or carrier) input applied to the comparator. 10kΩ 6 MODULATION INPUT 1 10kΩ CM OFF ADJ DIFF OFF ADJ 4 5 3 2.5kΩ AMP A 12 A 2 11 20 2.5kΩ B AMP B 17 10kΩ 10kΩ –V 18 19 AD630 CARRIER INPUT +VS 13 5kΩ 14 MODULATED OUTPUT SIGNAL 15 16 COMP 7 9 10 00784-022 8 –VS Figure 28. AD630 Configured as a Gain-of-One Balanced Modulator 10kΩ MODULATION INPUT 1 2.5kΩ 10kΩ CM OFF ADJ 6 5 DIFF OFF ADJ 4 3 AMP A 11 20 2.5kΩ 17 10kΩ –V 18 19 CARRIER INPUT 10kΩ AD630 COMP 5kΩ 14 MODULATED OUTPUT SIGNAL 15 16 7 9 CARRIER INPUT OUTPUT SIGNAL 10V Figure 30. Gain-of-Two Balanced Modulator Sample Waveforms BALANCED DEMODULATOR The balanced modulator topology described in the Balanced Modulator section also acts as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input. The output under these circumstances is the baseband modulation signal. Higher order carrier components that can be removed with a low-pass filter are also present. Other names for this function are synchronous demodulation and phasesensitive detection. PRECISION PHASE COMPARATOR The balanced modulator topologies of Figure 28 and Figure 29 can also be used as precision phase comparators. In this case, an ac waveform of a particular frequency is applied to the signal input and a waveform of the same frequency is applied to the reference input. The dc level of the output (obtained by lowpass filtering) is proportional to the signal amplitude and phase difference between the input signals. If the signal amplitude is held constant, the output can be used as a direct indication of the phase. When these input signals are 90° out of phase, they are said to be in quadrature and the AD630 dc output is zero. If the input signal is used as its own reference in the balanced modulator topologies, the AD630 acts as a precision rectifier. The high frequency performance is superior to that which can be achieved with diode feedback and op amps. There are no diode drops that the op amp must leap over with the commutating amplifier. +VS 13 B AMP B MODULATION INPUT PRECISION RECTIFIER ABSOLUTE VALUE 12 A 2 20µs 00784-024 Perhaps the most commonly used configuration of the AD630 is the balanced modulator. The application resistors provide precise symmetric gains of ±1 and ±2. The ±1 arrangement is shown in Figure 28 and the ±2 arrangement is shown in Figure 29. These cases differ only in the connection of the 10 kΩ feedback resistor (Pin 14) and the compensation capacitor (Pin 12). Note the use of the 2.5 kΩ bias current compensation resistors in these examples. These resistors perform the identical function in the ±1 gain case. Figure 30 demonstrates the performance of the AD630 when used to modulate a 100 kHz square wave carrier with a 10 kHz sinusoid. The result is the double sideband suppressed carrier waveform. 5V 10 00784-023 8 –VS Figure 29. AD630 Configured as a Gain-of-Two Balanced Modulator Rev. F | Page 16 of 20 Data Sheet AD630 LVDT SIGNAL CONDITIONER AC BRIDGE Many transducers function by modulating an ac carrier. A linear variable differential transformer (LVDT) is a transducer of this type. The amplitude of the output signal corresponds to core displacement. Figure 31 shows an accurate synchronous demodulation system, which can be used to produce a dc voltage that corresponds to the LVDT core position. The inherent precision and temperature stability of the AD630 reduce demodulator drift to a second-order effect. Bridge circuits that use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pick-up. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a lowpass filter. Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter. E1000 AD544 SCHAEVITZ FOLLOWER A LVDT 16 B 5kΩ 1 2.5kΩ 2.5kHz 2V p-p SINUSOIDAL EXCITATION AD630 ±2 DEMODULATOR 20 14 10kΩ 10kΩ 15 A C 19 B 17 13 100kΩ 12 D 1µF Figure 33 is an example of an ac bridge system with the AD630 used as a synchronous demodulator. The bridge is excited by a 1 V 400 Hz excitation. Trace A in Figure 32 is the amplified bridge signal. Trace B is the output of the synchronous demodulator and Trace C is the filtered dc system output. 2.5kΩ 9 00784-025 PHASE SHIFTER 10 Figure 31. LVDT Signal Conditioner [ T ] 500µs/DIV B. 200mV/DIV T 3 C. 200mV/DIV 00784-027 A. 200mV/DIV Figure 32. AC Bridge Waveforms (1 V Excitation) +15V 1V 400Hz 350Ω 350Ω 350Ω +IN A 49.9Ω AD8221 REF 9 11 SEL B +VS 16 RA 17 RINB 19 CH B– –IN AD630AR B VOUT 13 4.99kΩ 4.99kΩ 4.99kΩ 2µF 2µF 2µF C COMP 12 20 CH A– 15 RF RINA SEL A –VS RB 1 10 8 –15V Figure 33. AC Bridge System Rev. F | Page 17 of 20 14 00784-026 350Ω AD630 Data Sheet The test signal is produced by modulating a 400 Hz carrier with a 0.1 Hz sine wave. The signals produced, for example, by chopped radiation (that is, IR, optical) detectors may have similar low frequency components. A sinusoidal modulation is used for clarity of illustration. This signal is produced by a circuit similar to Figure 28 and is shown in the upper trace of Figure 34. It is attenuated 100,000 times normalized to the output, B, of the summing amplifier. A noise signal that might represent, for example, background and detector noise in the chopped radiation case, is added to the modulated signal by the summing amplifier. This signal is simply band limited, clipped white noise. Figure 34 shows the sum of attenuated signal plus noise in the center trace. This combined signal is demodulated synchronously using phase information derived from the modulator, and the result is low-pass filtered using a 2-pole simple filter which also provides a gain of 100 to the output. This recovered signal is the lower trace of Figure 34. LOCK-IN AMPLIFIER APPLICATIONS Lock-in amplification is a technique used to separate a small, narrow-band signal from interfering noise. The lock-in amplifier acts as a detector and narrow-band filter combined. Very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known. The lock-in amplifier is basically a synchronous demodulator followed by a low-pass filter. An important measure of performance in a lock-in amplifier is the dynamic range of its demodulator. The schematic diagram of a demonstration circuit which exhibits the dynamic range of an AD630 as it might be used in a lock-in amplifier is shown in Figure 35. Figure 34 is an oscilloscope photo demonstrating the large dynamic range of the AD630. The photo shows the recovery of a signal modulated at 400 Hz from a noise signal approximately 100,000 times larger. 5V 5V The combined modulated signal and interfering noise used for this illustration is similar to the signals often requiring a lock-in amplifier for detection. The precision input performance of the AD630 provides more than 100 dB of signal range and its dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example. A more sophisticated low-pass output filter aids in rejecting wider bandwidth interference. 5s MODULATED SIGNAL (A) (UNATTENUATED) 100 90 ATTENUATED SIGNAL PLUS NOISE (B) 10 00784-029 OUTPUT 0% 5mV Figure 34. Lock-In Amplifier Waveforms CLIPPED BAND LIMITED WHITE NOISE C B 16 AD542 5kΩ 15 20 19 100R 10kΩ 1 2.5kΩ 17 2.5kΩ 100dB ATTENUATION AD630 A 13 R AD542 B 100R 14 10kΩ C OUTPUT A 10 0.1Hz 9 MODULATED CARRIER 400Hz PHASE CARRIER REFERENCE 00784-028 LOW-PASS FILTER Figure 35. Lock-In Amplifier Rev. F | Page 18 of 20 Data Sheet AD630 OUTLINE DIMENSIONS 0.080 (2.03) MAX 0.005 (0.13) MIN 11 20 PIN 1 1 10 0.300 (7.62) 0.280 (7.11) 1.060 (28.92) 0.990 (25.15) 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.300 (7.62) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 36. 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-20) Dimensions shown in inches and (millimeters) 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 20 11 1 10 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 37. 20-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-20) Dimensions shown in inches and (millimeters) Rev. F | Page 19 of 20 070706-A 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) AD630 Data Sheet 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 19 18 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 0.050 (1.27) BSC 8 14 13 9 45° TYP 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 022106-A 0.100 (2.54) 0.064 (1.63) Figure 38. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) Dimensions shown in inches and (millimeters) 13.00 (0.5118) 12.60 (0.4961) 11 20 7.60 (0.2992) 7.40 (0.2913) 10 10.65 (0.4193) 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1.27 (0.0500) 0.40 (0.0157) 06-07-2006-A 1 Figure 39. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 AD630JNZ AD630KNZ AD630ARZ AD630ARZ-RL AD630ADZ AD630BDZ AD630SD AD630SD/883B 5962-8980701RA AD630SE/883B 5962-89807012A AD630SCHIPS 1 Temperature Range 0°C to 70°C 0°C to 70°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −25C to +85°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description 20-Lead Plastic Dual In-Line Package [PDIP] 20-Lead Plastic Dual In-Line Package [PDIP] 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W], 13" Tape and Reel 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 20-Terminal Ceramic Leadless Chip Carrier [LCC] 20-Terminal Ceramic Leadless Chip Carrier [LCC] Chip Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00784-0-7/15(F) Rev. F | Page 20 of 20 Package Option N-20 N-20 RW-20 RW-20 D-20 D-20 D-20 D-20 D-20 E-20-1 E-20-1