FEATURES FUNCTIONAL BLOCK DIAGRAM 1 pF off capacitance 2.6 pF on capacitance <1 pC charge injection 33 V supply range 120 Ω on resistance Fully specified at ±15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP Typical power consumption: <0.03 μW S1 IN1 D1 S2 IN2 ADG1212-EP APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems S3 IN3 D3 S4 IN4 D4 NOTES 1. SWITCHES SHOWN ARE FOR LOGIC 1 INPUT. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request D2 10012-001 Enhanced Product Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS Quad SPST Switches ADG1212-EP Figure 1. The ultralow capacitance and charge injection of this switch makes it an ideal solution for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth makes the part suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. The ADG1212-EP contains four independent single-pole/ single-throw (SPST) switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Additional application and technical information can be found in the ADG1212 data sheet. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG1212-EP is a monolithic complementary metal-oxide semiconductor (CMOS) device containing four independently selectable switches designed on an iCMOS® (industrial CMOS) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. 1. 2. 3. 4. 5. 6. Ultralow capacitance. <1 pC charge injection. 3 V logic compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <0.03 μW. 16-lead TSSOP package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. ADG1212-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Single Supply ..................................................................................4 Enhanced Product Features ............................................................ 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Product Highlights ........................................................................... 1 Test Circuits........................................................................................9 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 11 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 11 Dual Supply ................................................................................... 3 REVISION HISTORY 7/12—Rev. 0 to Rev. A Changed Operating Temperature Range from −40°C to +125°C to −55°C to +125°C; Table 3 ............................................................ 5 11/11—Revision 0: Initial Version Rev. A | Page 2 of 12 Enhanced Product ADG1212-EP SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 1 25°C 120 190 2.5 6 20 57 ±0.02 ±0.1 ±0.02 ±0.1 ±0.02 ±0.1 −40°C to +85°C −55°C to +125°C VDD to VSS 230 260 10 11 72 79 ±0.6 ±1 ±0.6 ±1 ±0.6 ±1 2.0 0.8 0.005 ±0.1 2.5 65 80 80 100 −0.3 80 90 0.15 95 110 115 135 1000 0.9 1.1 1 1.2 2.6 3 1.0 220 ISS 0.001 ISS 0.001 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ pF typ pF max pF typ pF max pF typ pF max 0.001 IDD Unit 420 1.0 1.0 Guaranteed by design, not subject to production test. Rev. A | Page 3 of 12 µA typ µA max µA typ µA max µA typ µA max µA typ µA max Test Conditions/Comments VS = ±10 V, IS = −1 mA; see Figure 15 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −1 mA VS = −5 V/0 V/+5 V; IS = −1 mA VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = 10 V; see Figure 11 VS = ±10 V, VD = 10 V; see Figure 11 VS = VD = ±10 V; see Figure 12 VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 18 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 18 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 13 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 14 RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz; see Figure 17 RL = 50 Ω, CL = 5 pF; see Figure 16 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V or VDD Digital inputs = 5 V ADG1212-EP Enhanced Product SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −55°C to +125°C 0 V to VDD 300 475 4.5 12 60 ±0.02 ±0.1 ±0.02 ±0.1 ±0.02 ±0.1 567 625 26 27 ±0.6 ±1 ±0.6 ±1 ±0.6 ±1 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Charge Injection Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 3 80 105 90 115 0 80 90 900 1.2 1.4 1.3 1.5 3.2 3.9 125 140 140 165 0.001 1.0 IDD 220 420 1 Guaranteed by design, not subject to production test. Rev. A | Page 4 of 12 Unit V Ω typ Ω max Ω typ Ω max Ω typ nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max µA typ µA max µA typ µA max Test Conditions/Comments VS = 0 V to 10 V, IS = −1 mA; see Figure 15 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −1 mA VS = 3 V/6 V/9 V, IS = −1 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 11 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 11 VS = VD = 1 V or 10 V; see Figure 12 VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 18 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 18 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 13 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 14 RL = 50 Ω, CL = 5 pF; see Figure 16 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V Enhanced Product ADG1212-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance (4-Layer Board) Lead Temperature, Soldering 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND – 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 25 mA −55°C to +125°C −65°C to +150°C 150°C 112°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Table 4. ADG1212-EP Truth Table ADG1212-EP INx 1 0 ESD CAUTION As per JEDEC J-STD-020 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. A | Page 5 of 12 Switch Condition On Off ADG1212-EP Enhanced Product IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 VSS 4 13 VDD GND 5 12 NC S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 ADG1212-EP TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 10012-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 Description Logic Control Input. Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Logic Control Input. Logic Control Input. Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Logic Control Input. Rev. A | Page 6 of 12 Enhanced Product ADG1212-EP TYPICAL PERFORMANCE CHARACTERISTICS 250 200 TA = +25°C 180 VDD = +15V VSS = –15V VDD = +13.5V VSS = –13.5V 160 200 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 140 120 100 VDD = +15V VSS = –15V 80 VDD = +16.5V VSS = –16.5V 60 TA = +125°C TA = +85°C 150 TA = +25°C 100 TA = –40°C TA = –55°C 50 40 –9 –6 –3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 18 Figure 3. On Resistance as a Function of VD (VS) for Dual Supply 0 –15 –10 –5 0 5 SOURCE OR DRAIN VOLTAGE (V) 10 15 10012-006 0 –18 –15 –12 10012-003 20 Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply 450 600 TA = +25°C VDD = 15V VSS = 0V 400 TA = +125°C 500 TA = +85°C VDD = +5.5V VSS = –5.5V 300 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 350 250 200 150 400 TA = –40°C TA = +25°C 300 200 TA = –55°C 100 100 –4 –3 –2 –1 0 1 2 3 SOURCE OR DRAIN VOLTAGE (V) 4 5 Figure 4. On Resistance as a Function of VD (VS) for Dual Supply 0 0 2 10 12 Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply 450 0.20 TA = 25°C 400 ID, IS (ON) 0.10 LEAKAGE (nA) 300 250 VDD = 13.2V VSS = 0V 200 VDD = +15V VSS = –15V VBIAS = +10V/–10V 0.15 VDD = 12V VSS = 0V VDD = 10.8V VSS = 0V 350 0.05 ID (OFF) 0 –0.05 IS (OFF) 150 –0.10 100 –0.15 50 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 –0.20 10012-005 0 Figure 5. On Resistance as a Function of VD (VS) for Single Supply 0 20 40 60 80 TEMPERATURE (°C) 100 120 10012-008 ON RESISTANCE (Ω) 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 10012-007 0 –5 10012-004 50 Figure 8. Leakage Currents as a Function of Temperature, Dual Supply Rev. A | Page 7 of 12 ADG1212-EP Enhanced Product 140 0.30 VDD = 12V VSS = 0V VBIAS = 1V/10V 0.25 120 tOFF (12V SINGLE SUPPLY) 0.20 100 tON (12V SINGLE 0.15 TIME (ns) 0.10 IS (OFF) SUPPLY) 80 tON (15V DUAL SUPPLY) 60 0.05 tOFF (15V DUAL SUPPLY) 40 0 ID (OFF) 20 –0.10 0 20 40 60 80 TEMPERATURE (°C) 100 120 10012-009 –0.05 0 –55 Figure 9. Leakage Currents as a Function of Temperature, Single Supply Rev. A | Page 8 of 12 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 Figure 10. tON/tOFF Times vs. Temperature 105 125 10012-010 LEAKAGE (nA) ID, IS (ON) Enhanced Product ADG1212-EP TEST CIRCUITS S D ID (ON) ID (OFF) A VD 10012-011 VS S NC D NC = NO CONNECT A VD Figure 15. On Resistance Figure 11. Off Leakage VDD VSS 0.1µF 0.1µF VDD IDS NETWORK ANALYZER VSS S 50Ω IN VS D V1 VIN S D GND 10012-012 RON = V1/IDS VS RL 50Ω INSERTION LOSS = 20 LOG Figure 12. On Leakage VDD VDD 0.1µF VDD VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 16. Bandwidth VSS 0.1µF VOUT 10012-016 A 10012-015 IS (OFF) VSS 0.1µF 0.1µF NETWORK ANALYZER VSS VDD AUDIO PRECISION VSS RS 50Ω IN S 50Ω IN VS D RL 50Ω GND VOUT VIN GND OFF ISOLATION = 20 LOG VOUT VS Figure 13. Off Isolation Figure 17. THD + Noise VDD VSS 0.1µF 0.1µF VOUT RL 50Ω VDD VSS S1 D S2 R 50Ω VS VOUT VS 10012-014 GND CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG RL 10kΩ 10012-013 VIN NETWORK ANALYZER VS V p-p D Figure 14. Channel-to-Channel Crosstalk Rev. A | Page 9 of 12 VOUT 10012-017 S ADG1212-EP Enhanced Product VDD VSS 0.1µF 0.1µF ADG1212-EP VSS S VS VIN 50% 50% VOUT D RL 300Ω IN CL 35pF 90% VOUT tOFF tON GND 90% 10012-018 VDD Figure 18. Switching Times VDD VSS VDD VSS ADG1212-EP VS S D VIN CL 1nF IN ON VOUT VOUT QINJ = CL × ∆VOUT GND Figure 19. Charge Injection Rev. A | Page 10 of 12 OFF ∆VOUT 10012--019 RS Enhanced Product ADG1212-EP OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model ADG1212SRU-EP-RL7 Temperature Range −55°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] Rev. A | Page 11 of 12 Package Option RU-16 ADG1212-EP Enhanced Product NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10012-0-7/12(A) Rev. A | Page 12 of 12