TOIM5232 Datasheet

Not for New Designs
TOIM5232
www.vishay.com
Vishay Semiconductors
SIR Endec for IrDA® Applications Integrated Interface Circuit
FEATURES
• Pulse shaping function according IrDA SIR
physical layer
• Directly interfaces the SIR transceiver to a
RS232 port
20810
• QFN-20 - package, 4 mm x 4 mm x 0.75 mm
DESCRIPTION
• Low operating current
The TOIM5232 endec IC provides proper pulse shaping for
the SIR IrDA front end infrared transceivers as of the
4000-series.
• Programmable baud clock generator (1200 Hz to
115.2 kHz), 13 baud rates
For transmitting the TOIM5232 shortens the RS232 output
signal to IrDA compatible electrical pulses to drive the
infrared transmitter. In the receive mode, the TOIM5232
stretches the received infrared pulses to the proper bit width
depending on the operating bit rate. The IrDA bit rate varies
from 2.4 kbit/s to 115.2 kbit/s.
• For 2.7 V to 3.6 V operation voltage, 5 V tolerant inputs
The TOIM5232 is using a crystal clock 3.6864 MHz
(< 7.5 MHz) for its pulse stretching and shortening. The
clock is generated by the internal oscillator. An external
clock can be used, too. The TOIM5232 is programmable to
operate from 1200 bit/s to 115.2 kbit/s by the
communication software through the RS232 port. The
output pulses are software programmable as either 1.627 μs
or 3/16 of bit time. The typical power consumption is very
low with about 10 mW in operational state and in the order
of a few microwatts in standby mode. TOIM5232 in the tiny
QFN-20 package is the space-minimized version of
TOIM4232.
ULC Technology: High performance gate array package
using multiple metal layer CMOS technology featuring
sub-micron channel lengths (0.35 μm).
• 3/16 bit pulse duration or 1.627 μs pulse selectable
• Qualified for lead (Pb)-free and Sn/Pb solder processing
(MSL3)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
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PARTS TABLE
PART
TOIM5232-TR3
DESCRIPTION
QTY/REEL
SIR Endec for IrDA application
6000 pcs
PRODUCT SUMMARY
PART NUMBER
TOIM5232
DATA RATE
(kbit/s)
DIMENSIONS
HxLxW
(mm x mm x mm)
LINK DISTANCE
(m)
OPERATING
VOLTAGE
(V)
IDLE SUPPLY
CURRENT
(mA)
1.2 to 115
4 x 4 x 0.75
-
2.7 to 3.6
2
Rev. 1.4, 15-Jan-15
Document Number: 81749
1
For technical questions within your region: [email protected], [email protected], [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Not for New Designs
TOIM5232
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Vishay Semiconductors
BLOCK DIAGRAM
VCC
TD_IR
TD_232
Endec
RD_232
RD_IR
TD_LED
Baud
generator
BR/D
RD_LED
S1
S2
Logic
RESET
VCC_SD
Oscillator
GND
X1
X2
18079
PIN ASSIGNMENT AND DESCRIPTION
PIN NUMBER SYMBOL
DISCRIPTION
Received signal data output of stretched signal to the RS232 RXD line (using level
converter).
Input of the signal to be transmitted from the RS232 port TXD line
(passing the level converter).
This pin can be used to shut down a transceiver (e.g., TFDx4xxx).
Output polarity: Inverted RESET input.
I/O
ACTIVE
O
High
I
High
O
Low
1
RD_232
2
TD_232
3
VCC_SD
4
X1
Crystal input clock, 3.6864 MHz nominal for 9.6 kbit/s default setting. Input for external
clock (1). Option: 7.3728 MHz for 19.2 kbit/s default operation.
I
5
X2
Crystal (1)
I
7
GND
Ground in common with the RS232 port and IrDA transceiver ground
9
TD_LED
Transmit LED indicator driver. Use 180  current limiting resistor in series to LED to
connect to VCC (VCC = 3.3 V).
O
Low
10
RD_LED
Receive LED indicator driver. Use 180  current limiting resistor in series to LED to connect
to VCC (VCC = 3.3 V).
O
Low
12
S1
O
Low
13
S2
O
Low
14
TD_IR
User programmable bit. Can be used to turn on/off a front-end infrared transceiver (e.g., an
infrared module at the adapter front).
User programmable bit. Can be used to turn on/off a front-end infrared transceiver (e.g., an
infrared module at the adapter back).
Data output of shortened signal to the infrared transceiver.
O
High
16
RD_IR
Data input from the infrared transceiver, min. pulse duration 1.63 μs (2)
I
Low
17
VCC
Supply voltage
I
RESET
Resets all internal registers. Initially must be high (“1”) to reset internal registers. When high,
the TOIM5232 sets the IrDA default bit rate of 9600 bit/s, sets pulse width to 1.627 μs.
The VCC_SD output is simply an inverted reset signal which allows shutdown of a TFDx4x00
transceiver when applying the reset signal to the TOIM5232. When using devices with
external SD like TFDU4101, the reset line can be used directly as shutdown signal.
RESET pin can be controlled by either the RTS or DTR line through RS232 level converter.
Minimum hold time for resetting is 1 μs.
Disables the oscillator when active.
18
19
BR/D
6, 8, 11, 15, 20
High
Baud rate control/data
BR/D = 0, data communication mode:
RS232 TXD data line is connected (via a level shifter) to TD_232 input pin. The TXD - signal
is appropriately shortened and applied to the output TD_IR, driving the TXD input of the IR
transceiver. The RXD line of the transceiver is connected to the RD_IR input. This signal is
stretched to the correct bit length according to the programmed bit rate and is routed to the
RS232 RXD line at the RD_232 pin.
BR/D = 1, programming mode:
Data received from the RS232 port is interpreted as control word. The control word
programs the baud rate width will be effective as soon as BR/D return to low.
NC
Notes
(1) Crystal should be connected as shown in the block diagram or in the recommended application circuit. Connect a 100 k resistor from pin
4 to pin 5 and from pin 4 and pin 5 a 22 pF capacitor to ground, respectively. When an external clock is available connect it to pin 4 leaving
pin 5 open. The external resistor of 100 k is used to accelerate the start of the oscillation after reset or power-on. The value depends on
the “Q” of the resonator. With low Q resonators no resistor is needed. The start-up time of the oscillator is between 30 μs (with piezo
resonators) and above 2 ms with high Q quartzes.
(2) This condition is fulfilled with all Vishay IR transceivers.
Rev. 1.4, 15-Jan-15
Document Number: 81749
2
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Not for New Designs
TOIM5232
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ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN.
Supply voltage
VCC
Input voltage
Output voltage
IOUT
Output sinking current
TYP.
MAX.
UNIT
-0.5
3.6
V
-0.5
5.5
V
-0.5
VCC + 0.5
8
TJ
Junction temperature
Tamb
-25
Storage temperature
Tstg
-25
Soldering temperature
Tsldr
Ambient temperature (operating)
NOTES
All pins
V
All pins
mA
All pins
125
°C
85
°C
85
°C
260
°C
DC CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Operating voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
2.7
3.3
3.6
V
VIH
2
VCC = 3.3 V ± 5 %, operating temperature = - 25 °C to + 85 °C
Input high voltage
Inputs tolerate levels as high as
5.5 V maximum. All inputs are
Schmitt trigger inputs
Input low voltage
V
0.8
VIL
Input Schmitt trigger hysteresis
0.6
Vhyst
Input leakage no pull-up/down
V
V
VIN = VCC or GND
IL
-10
IOH = - 2 mA
VOH
2
IOH = - 0.5 mA
VOH
2.4
IOL = + 2 mA
VOL
0.4
V
Consumption current standby
Inputs grounded, no output load
VCC = 3.3 V, T = 25 °C
ISB
1
μA
Consumption current dynamic
Inputs grounded, no output load
VCC = 3.3 V, T = 25 °C
ICC
Output high voltage
Output low voltage
OPERATION DESCRIPTION
The block diagram shows a typical example of an RS232
port interface. The TOIM5232 connects to an RS232 level
converter on one side, and an infrared transceiver on the
other. The internal TOIM5232 baud rate generator can be
software controlled.
When BR/D = 0, the TOIM5232 interprets the channels
TD_232 to TD_IR and RD_IR to RD_232 as data channels.
On the other hand, whenever BR/D = 1, the TOIM5232
interprets TD_232 as control word for setting the baud rate.
The baud rate can be programmed to operate from 1200
bit/s to 115.2 kbit/s. As RS232 level converter, EIA232 or
MAX232 or equivalent are recommended.
When using the TOIM5232 directly connected to an UART it
is compatible to 5 V TTL and 3.3 V CMOS logic.
Typical external resistors and capacitors are needed as
shown in the TFDU4...,TFBS4...-series references.
The output pulse duration can also be programmed, see
chapter “operation description”. It is strongly recommended
using 1.627 μs output pulses to save battery power. As
frequency determining component a Vishay XT49M crystal
is recommended, when no external clock is available.

±1
10
μA
V
V
2
mA

We strongly recommend not to use this 3/16 mode
because 3/16 pulse length at lower bit rates consumes
more power than the shorter pulse. At a data rate of
9600 bit/s, the ratio of power consumption of both
modes is a factor of 12 (!)
PROGRAMMING THE TOIM5232
For correct data rate dependent timing the TOIM5232 is
using a built-in baud rate generator. This is used when no
external clock is not available as in RS232 IR-dongle
applications. For programming the BR/D pin has to be set
active, BR/D = 1.
In this case the TOIM5232 interprets the 7 LSBs at the
TD_232 input as a control word. The operating baud rate will
change to its supposedly new baud rate when the BR/D
returns back to low (“0”) set the UART to 8 bit, no parity,
1 stop bit.
Rev. 1.4, 15-Jan-15
Document Number: 81749
3
For technical questions within your region: [email protected], [email protected], [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Not for New Designs
TOIM5232
www.vishay.com
Vishay Semiconductors
CONTROL BYTE (8 BIT)
BAUD RATE SELECT WORDS
FIRST CHARACTER
X
S2
S1
SECOND CHARACTER
S0
B3
B2
B1
B3
B2
B1
B0
2nd
CHAR
BAUD RATE
0
0
0
0
0
115.2 kHz
0
0
0
1
1
57.6 kHz
0
0
1
0
2
38.4 kHz
0
0
1
1
3
19.2 kHz
0
1
0
0
4
14.4 kHz
0
1
0
1
5
12.8 kHz
0
1
1
0
6
9.6 kHz
0
1
1
1
7
7.2 kHz
1
0
0
0
8
4.8 kHz
1
0
0
1
9
3.6 kHz
1
0
1
0
A
2.4 kHz
1
0
1
1
B
1.8 kHz
1
1
0
0
C
1.2 kHz
B0
LSB
X: do not care
S1, S2: user programmable bit to program the outputs S1
and S2
S0: IrDA pulse select
S0 = (1): 1.627 μs output pulses
S0 = (0): 3/16 bit time pulses, not recommended
B0 to B3: baud rate select words according following table.
Example: 
To set TOIM5232 at COM2 port (2F8) to 9600 bit/s with
3/16 bit time pulse duration send to the TOIM5232 in
programming mode in e.g. “basic”
OUT &H2F8, (&H6)
For same port, 9600 bit/s and 1.627 μs pulse duration send 
OUT &H2F8, (&H16)
For additionally activating S1 send 
OUT &H2F8, (&H36)
Note
IrDA standard only supports 2.4 kbit/s, 9.6 kbit/s, 19.2 kbit/s,
57.6 kbit/s, and 115.2 kbit/s (3.6864 MHz clock). Doubling the baud
rates is allowed by doubling the clock frequency.
SOFTWARE FOR THE TOIM4232 AND TOIM5232 UART PROGRAMMING
For proper operation, the RS232 must be programmed (using 8 bit, 1 stop, no parity) to send a two character control word, YZ.
The control word YZ is composed of two characters, written in hexadecimal, in format: YZ. The transfer rate for programming
must be identical with the formerly programmed data rate, or after resetting the TOIM5232, the default rate of 9600 bit/s is used.
STEP.
RESET
BR/D
TD_UART
RD_UART
RD_IR
TD_IR
DESCRIPTION AND COMMENTS
1
High
X
X
X
X
X
Resets all internal registers. Resets to
IrDA default data rate of 9600 bit/s
2
Low
X
X
X
X
X
Wait at least 2 ms, to allow start-up of
internal clock. When external clock is
used: wait at least 7 μs.
3
Low
High
X
X
X
X
Wait at least 7 μs. TOIM5232 now is set to
the control word programming mode
High
YZ
with Y = 1:
1.627 μs
Y=0
3/16 bit length
X
Sending the control word YZ.
Examples: Send “1Z” if 1.627 μs pulses
are intended to be used. Otherwise send
“0Z” for 3/16 bit period pulses. “Y6”
keeps the 9.6 kbit/s data rate. Z = 0 sets
to 115.2 kbit/s, see programming table.
Wait at least 1 μs for hold-time.
Data
With BR/D = 0, TOIM5232 is in the data
communication mode. Both RESET and
BR/D must be kept low (“0”) during data
transmission. Reprogramming to a new
data rate can be resumed by restarting
from step 3. The UART itself also must set
to the correct data rate (1).
4
5
Low
Low
Low
Data
X
Data
X
Data
Note
• It is recommended reading the I/O buffer after transmission waiting the specified latency allowance. That avoids receiving unexpected data
from pulses stochastically generated by many transceivers during the latency time.
(1) For programming the UART, refer to e.g., National Semiconductors datasheet of PC 16550 UART.
Rev. 1.4, 15-Jan-15
Document Number: 81749
4
For technical questions within your region: [email protected], [email protected], [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Not for New Designs
TOIM5232
www.vishay.com
Vishay Semiconductors
RECOMMENDED APPLICATION CIRCUIT FOR TOIM5232
R3
MAX3232CSE
1
C+
VCC
18
4
C1-
V+
U1
C2+
V-
2
19
6
1
+ C6 + C5 + C7
+
C4
5
C2-
GND
2
15
3
4
11
10
12
9
T1IN
T2IN
R1OUT
R2OUT
T1OUT
T2OUT
R1IN
R2IN
14
7
13
8
5
7
VCC
RESET
BR/D
U2
RD_IR
RD_232
TD_IR
TD_232
S2
VCC_SD
S1
X1
NC
X2
RD_LED
GND
TD_LED
17
C10
2
+
3
TFDU4301
TOIM5232
16
+
C3
R4
optional
C11
16
4
14
6
13
8
IRED
Cathode
RXD
IRED
Anode
TXD
U3
Vcc1
SD
GND
Vlog
1
3
5
7
12
*)
10
9
J1
*) NC: 6, 8, 11, 15, 20
1
6
2
7
3
8
4
9
5
RXD
RTS (BR/D)
TXD
R1
DTR (RESET)
Y1
Vcc
Z2
J2
CON9
External
input
3.6 V max.
1
2
Z1
C1
R2
+ C2
C8
CON2
C9
20799
Application circuit using TFDU4301 with integrated level shifter MAX3232CSE. When used directly with 3 V - or 5 V - logic, the
level shifter can be omitted.
RECOMMENDED APPLICATION CIRCUIT COMPONENTS
COMPONENT
RECOMMENDED VALUE
VISHAY PART NUMBER
1.
C1
100 nF
VJ 1206 Y 104 J XXMT
2.
C2
10 μF, 16 V
293D 106X9 016B 2T
3.
C3
100 nF
VJ 1206 Y 104 J XXMT
4.
C4
100 nF
VJ 1206 Y 104 J XXMT
5.
C5
100 nF
VJ 1206 Y 104 J XXMT
6.
C6
100 nF
VJ 1206 Y 104 J XXMT
7.
C7
1 μF, 16 V
293D 105X9 016A 2T
8.
C8
22 pF
VJ 1206 A 220 J XAMT
VJ 1206 A 220 J XAMT
9.
C9
22 pF
10.
C10
6.8 μF, 16 V (optional)
293D 685X9 016B 2T
11.
C11
100 nF
VJ 1206 Y 104 J XXMT
12.
Z1
3.6 V
BZT55C3V6
13.
Z2
3.6 V
BZT55C3V6
14.
R1
5.6 k
CRCW-1206-5601-F-RT1
15.
R2
100 k
CRCW-1206-1003-F-RT1
16.
R3
47 
CRCW-1206-47R0-F-RT1
17.
R4
27  (for reduced current only)
CRCW-1206-27R0-F-RT1
18.
Y1
3.686400 MHz
XT49S - 20 - 3.686400M
19.
U1
MAX 3232CSE
MAXIM MAX 3232CSE
20.
U2
TOIM5232
21.
U3
TFDU4301
22.
J1
9 pin - connector
Cannon
23.
J2
Power connector
Philmore PHI 211B
Rev. 1.4, 15-Jan-15
Document Number: 81749
5
For technical questions within your region: [email protected], [email protected], [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Not for New Designs
TOIM5232
www.vishay.com
Vishay Semiconductors
PACKAGE DIMENSIONS in millimeters
Recommanded footprint
2
0.5
0.3
4.3
0.55
Pin 1 ID
0.3
0.55
4.3
20797
REEL DIMENSIONS in millimeters
Drawing-No.: 9.800-5090.01-4
Issue: 1; 29.11.05
14017
TAPE WIDTH
(mm)
A MAX.
(mm)
N
(mm)
W1 MIN.
(mm)
W2 MAX.
(mm)
W3 MIN.
(mm)
W3 MAX.
(mm)
12
330
50
12.4
22.4
11.9
15.4
Rev. 1.4, 15-Jan-15
Document Number: 81749
6
For technical questions within your region: [email protected], [email protected], [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Not for New Designs
TOIM5232
www.vishay.com
Vishay Semiconductors
TAPE DIMENSIONS in millimeters
20798
Rev. 1.4, 15-Jan-15
Document Number: 81749
7
For technical questions within your region: [email protected], [email protected], [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Not for New Designs
TOIM5232
www.vishay.com
Vishay Semiconductors
TOIM4232 (TOIM5232) ENCODER - DECODER INTERFACE 
PROGRAMMING AND DATA TRANSMISSION
Operation and programming of the TOIM4232 and
TOIM5232 interface devices are described below. Figure 1
shows the basic circuit design with 3 blocks: the RS232 to
3 V logic level shifter, the encoder/decoder (endec) circuit
and the transceiver to build a dongle for RS232 IrDA
extension. U1 is the level shifter to convert the RS232 logic
levels to unipolar 3 V logic; U2 is the encoder/decoder
Interface (endec) converting the NRZ - RS232 logic to IrDA
RZI - logic. The transceiver U3 transmits and receives
IrDA-compliant optical signals.
R3
MAX3232
1
C+
16
1(18)
+
C3
VCC
3
4
RESET
U1
C1-
V+
C2+
V-
2
2(19)
6
3(1)
+
C4
TOIM4232
(TOIM5232)
+
5
C2-
GND
C6 + C5
+ C7
4(2)
15
5(3)
U2
BR/D
RD_232
Vcc
RD_IR
TD_IR
TD_232
S2
Vcc_SD
S1
T1IN
T2IN
R1OUT
R2OUT
T1OUT
T2OUT
R1IN
R2IN
X1
14
7
13
8
7(5)
8(7)
15(16)
C10
2
+
4
14(14)
6
13(13)
8
IRED
Cathode
RXD
Vcc1
GND
12(12)
6(4)
11
10
12
9
16(17)
X2
GND
NC
RD_LED
TD_LED
11 *)
R4
optional
TFDU4101
TFDU4301
C11
IRED
Anode
U3
TXD
SD
TFDU4101:NC
.
TFDU4300:Vlog
1
3
5
7
This line not used fot TFDU4101
10(10)
9(9)
J1
*) (6), (8), (11), (15), (20)
1
6
2
7
3
8
4
9
5
RXD
RTS (BR/D)
TXD
R1
DTR (RESET)
Y1
Vcc
Z2
CON9
External input
3.6V max.
J2
1
2
C1
CON2
R2
+ C2
C8
C9
21046
Fig. 1 - Circuit Diagram of the Demo Board
CIRCUIT DESCRIPTION
PROGRAMMING THE ENDEC
This circuit demonstrates the operation of an SIR IrDA
transceiver module. The transceiver U3 (e.g., as shown the
TFDU4101 or TFDU4301 or any other) converts the digital
electrical input signal to an optical output signal to be
transmitted, receives the optical signal, and converts these
to electrical digital signals. While the IrDA physical layer
protocol transmits only the “0” represented by a pulse with
a “Return to Zero Inverted (RZI)” logic, the RS232 protocol
needs a “No Return to Zero (NRZ)” representation. This
decoding/encoding process is done by U2, an interface
circuit stretching the received pulses and shortening the
pulses to be transmitted according to the IrDA physical layer
conditions. U1 interfaces the RS232 logic bipolar levels to
the 3 V logic of the Endec U2. The board is connected by
CON9 to the RS232 port (of a computer or other equipment.
The basic IrDA transmission speed is 9600 bit/s. This is the
default state of the Endec in power-on condition. Also,
activating the reset line at pin 1 (18) will set the device to this
basic state.
Note: The first pin number refers to TOIM4232; the second
number in brackets refers to TOIM5232. The crystal Y1
controls the timing of the Endec as a clock reference. The
outputs S1 and S2 are programmable outputs for control
operations and the outputs RD_LED and TD_LED can drive
LEDs for indicating data flow.
For decoding data rates other than the default, the endec is
to be programmed to set the internal counters and timers.
To switch the endec from the data transfer mode to the bit
rate programming mode, the input BR/D, pin 2 (19) is set
active high (BR/D = “1”). In this case the TOIM5232
interprets the 7 LSBs at the TD_232 input as a control word.
The operating bit rate will change to its supposedly new rate
when the BR/D returns back to low (“0”). Set the UART to 8
bit, no parity,
1 stop bit.
The control byte consists of 8 bit after the start bit (STA,
which is “0”). Keep in mind that the order is LSB first, MSB
last.
The diagram in figure 2 shows the programming byte
“0-1010-1100” in the order STA, B0, B1, B2, B3, S0, S1, S2,
X. This order is from right to left in table 1. B0 is sent first
as LSB (see figure 2).
The four least significant bits are responsible for the data
rate according to table 2 while the four higher bits are for
setting the IrDA pulse duration (S0), and the two outputs of
the endec S1 and S2. Bit 8 is not used.
Rev. 1.4, 15-Jan-15
Document Number: 81749
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TABLE 1 - CONTROL BYTE (8 BIT)
FIRST CHARACTER
X
MSB
S2
S1
S0
SECOND CHARACTER
B3
B2
B1
STA
B0
LSB
0
Example
0
0
1
1
0
1
0
1
0
In the oscilloscope that will be shown in the reserved order with
LSB first, see figure 2.
STA
0
FIRST CHARACTER
B0
LSB
B1
B2
B3
SECOND CHARACTER
S0
S1
S2
1->
2->
X
MSB
Example
0
1
0
1
0
1
1
0
0
Note
X: do not care
S1, S2: user-programmable bit to program the outputs S1 and S2. In
the example, S1 is set active, and S2 is inactive.
S0: IrDA pulse select
S0 = (1): 1.627 µs output
S0 = (0): 3/16 bit time pulses, not recommended
B0 to B3: baud rate select words according to the following table
below.
TABLE 2 - TRANSMISSION RATE SELECT
WORDS
B3
B2
B1
B1
HEX
BIT RATE
0
0
0
0
0
115.2 kHz
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
57.6 kHz
38.4 kHz
19.2 kHz
14.4 kHz
12.8 kHz
9.6 kHz
7.2 kHz
4.8 kHz
3.6 kHz
2.4 kHz
1.8 kHz
1.2 kHz
Notes
Bold: See example
IrDA standard only supports 2.4 kbit/s, 9.6 kbit/s, 19.2 kbit/s,
57.6 kbit/s, and 115.2 kbit/s (3.6864 MHz clock). Doubling the baud
rates is permissible by doubling the clock frequency.
In figure 2 the programming sequence is shown for a bit rate
of 12.8 kbit/s.
1) Ch1: BR/D; pin 2, vertical scale: 2 V/div., horizontal scale: 200 µs/div.
2) Ch2: TD_232; pin 4; programming sequence
21038
Fig. 2 - Programming sequence for setting the endec to a bit rate
of 12.8 kbit/s. After setting BR/D high (Ch1), the programming
sequence with the control byte (Ch2) is applied to TD_232, pin 4.
1->
STA 1
0
1
0
0
1
0
0
2->
1) Ch1: BR/D, pin 2, vertical scale: 2 V/div.,
horizontal scale: 200 µs/div.
2) Ch2: TD_232, pin 4; programming sequence
21030
Fig. 3 - Programming sequence for setting the endec to a bit rate of
12.8 kbit/s as in figure 2 but with a 3/16 bit pulse duration (S0 = “0”).
Example
0
MSB
0
1
0
0
1
0
1
0
LSB
STA

When correctly programmed, the endec shortens the pulse
to be transmitted from the full bit duration to either 3/16 of
the bit length or to 1.627 μs (which is 3/16 of the 115.2 kbit/s
bit duration). For power saving, the short pulse is
recommended.
The received optical pulse shows in case of most of the
Vishay SIR transceivers, constant pulse duration. The endec
stretches that to the correct bit time according the bit rate
setting. This is shown in the following chapters.
Rev. 1.4, 15-Jan-15
Document Number: 81749
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TRANSMIT (TXD) CHANNEL
Figure 4 shows the transmission in the default mode. For
data transfer, the endec is set to that mode by BR/D = “0”.
In the examples “6” is always transmitted (binary
“00000110”). The “0” is represented in the IrDA protocol by
an optical pulse. Also here the LSB is transmitted first after
the start bit. “1” is not transmitted.
1->
2->
3->
STA 0
1->
1
1
0
0
0
0
1) Ch1: TD_232, pin 4, vertical scale: 2 V/div., horizontal scale: 20 µs/div.
2) Ch2: TD_IR, pin 14; 1.6 µs pulse duration
3) Ch3: TD_LED, pin 9
0
21033
2->
T
3->
1) Ch1: TD_232 inp. pin 4, vertical scale: 2 V/div., horizontal scale: 200 µs/div.
2) Ch2: TD_IR, pin 14; 1.6 µs pulse duration
3) Ch3: TD_LED, pin 9
Fig. 6 - Data transmission with the setting 115.2 kbit/s, 1.627 μs
pulse duration. By definition, the pulse duration of 1.627 μs is
identical to the 3/16-bit pulse width.
RECEIVE (RXD) CHANNEL
In the default 9600 bit/s mode the signals will look like those
shown in figure 7 and figure 8.
21031
Fig. 4 - Data transmission with 9.6 kbit/s,1.627 μs pulse duration
Channel 1 shows the signal from the RS232 port already
converted to 3 V logic by U1. The Endec encodes that signal
to the RZI IrDA format where a “0” is represented by a pulse.
That is the trace of channel 2. This output is connected the
TXD input of the transceiver and this signal is transmitted as
optical output signal. Channel 3 is the signal for an indicator
lamp connected to the TD_LED driver output. Use 180 
serial resistor to supply voltage for limiting the current
through the LED (not shown in the circuit diagram).
When using the (not recommended) 3/16-bit pulse width the
oscillogram looks like figure 5.
1->
2->
3->
1) Ch1: TOIM4232; RD_IR, pin 15, vertical scale: 2 V/div.,
horizontal scale: 200 µs/div.
2) Ch2: TOIM4232; RD_232, pin 3
3) Ch3: TOIM4232; RD_LED, pin 10
21034
Fig. 7 - Data reception with the setting 9.6 kbit/s.
Short RXD pulse
1->
1->
2->
2->
3->
1) Ch1: TD_232, pin 4, vertical scale: 2 V/div., horizontal scale: 200 µs/div.
2) Ch2: TD_IR, pin 14; 3/16 bit pulse duration
3) Ch3: TD_LED, pin 9
21032
Fig. 5 - Data transmission with the setting 9.6 kbit/s,
3/16 bit pulse duration (19.5 μs)
The transmission with the highest SIR bit rate of 115.2 bit/s
looks like what is shown in figure 6. However, the horizontal
time scale is different.
3->
1) Ch1: TOIM4232; RD_IR, pin 15, vertical scale: 2 V/div.,
horizontal scale: 200 µs/div.
2) Ch2: TOIM4232; RD_232, pin 3
3) Ch3: TOIM4232; RD_LED, pin 10
21035
Fig. 8 - Data reception with the setting 9.6 kbit/s.
Same as in figure 7, extended pulse duration
The endec stretches the received pulses of about 2 µs
duration from the transceiver output (figure 7, channel 1)
independent of the pulse duration to the full bit width
generating NRZ code (channel 2). Channel 3 is the signal for
the indicator lamp.
As shown in figure 8, channels 2 and 3, the final NRZ signal
is identical to figure 7, even when longer pulses are received.
In the 115.2 kbit/s mode the signals will look like those shown
Rev. 1.4, 15-Jan-15
Document Number: 81749
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in figure 7 and figure 8. The difference is just the time scale.
It also indicates the delay of the decoded channel 2 vs.
channel 1.
Channel 1 shows the signal from the transceiver. In this case
it is TFDU4101 with unsymmetrical switching times.
TFDU4101 is using tri-state outputs with push-pull drivers
with symmetrical pulse switching times. All Vishay IrDA
transceivers exhibit constant output pulse duration in SIR
mode of about 2 µs independent of the duration of the optical
input pulse.
1->





2->
3->
1) Ch1: TOIM4232; RD_IR, pin 15, vertical scale: 2 V/div.,
horizontal scale: 10 µs/div.
2) Ch2: TOIM4232; RD_232, pin 3
3) Ch3: TOIM4232; RD_LED, pin 10
21036
Fig. 9 - Data reception with the setting 115.2 kbit/s
“ECHO-ON” OR “ECHO-OFF” AND “LATENCY ALLOWANCE”
handle that. The easiest way is to clean up the receiver
channel after sending the last pulse and waiting for the
latency period.
Later, many transceivers that block the RXD channel during
transmission and during the latency period were released to
the market. This behavior is called “Echo-off”.
Unfortunately, some OEMs like to use the signal from the
RXD channel during transmission, as a self-test feature for
testing the device on board without using the optical
domain. Therefore, many new devices have been developed
to echo the TXD input signal at the RXD output. Such
behavior is called “echo-on”.
Some software developed for “echo-off” applications is not
able to receive and understand the signals from echo-on
devices correctly.
Therefore, an add-on to the circuit shown in figure 1 was
generated to suppress the echo from the receiver during
transmission. This modification is shown in figure 10.
During transmission, the signal from the RXD output of the
transceiver is just gated by the transmit signal, (see the
oscilloscope picture in figure 11).
During transmission, the receiver inside a transceiver
package is exposed to very strong irradiance of the
transmitter, which causes overload conditions in the
receiver circuit. After transmission it takes some time to
recover from this condition and return to the specified
sensitivity.
During this time the receiver is in an unstable condition, and
at the output unexpected signals may arise. Also, during
transmission under overload conditions the receiver may
show signals on the RXD channel that are similar to or
identical with the transmitted signal. To get clean or at least
specified conditions for the receive channel during
transmission, different terms were defined. The time to allow
the receiver to recover from overload conditions is the
latency allowance or shorter, just the specified latency. This
is covered by the IrDA physical layer specification and is a
maximum of 10 ms. IrDA specifies shorter negotiable
latency. In SIR the minimum is 0.5 ms. This includes
software latency. Transceivers are in general below 0.3 ms.
In the first generations, some suppliers did not care for the
behavior of the RXD output of the transceivers during
transmission and latency time. The software is able to
R4
optional
R3
C11
MAX3232
1
C+
VCC
+
C3
3
1
U1
C1-
V+
C2+
V-
2
2
6
3
+ C6 + C5 + C7
5
4
15
C2-
5
6
11
10
12
9
T1IN
T2IN
R1OUT
R2OUT
T1OUT
T2OUT
R1IN
R2IN
R5
8
14
7
13
8
7
8
RESET
U2
Vcc
BR/D
RD_IR
RD_232
TD_IR
TD_232
S2
Vcc_SD
S1
X1
NC
X2
RD_LED
GND
TD_LED
16
15
1
14
5
+
U4
COM_1
NO_2
COM_2
Cathode
2
4
6
6
11
10
8
7
INS1
INS2
DG2039
9
J1
1
6
2
7
3
8
4
9
5
2
D
NC_1
13
12
TFDU4301
TFDU4101
C10
4
V+
+
C4
TOIM4232*)
16
RXD
Vcc1
GND
Anode
U3
TXD
SD
.
1
3
5
7
3
This line not used forTFDU4101
Pin7: TFDU4101:NC
TFDU4300:Vlog
*) For TOIM5232 pinning, see figure 1.
RXD
RTS (BR/D)
TXD
R1
DTR (RESET)
Y1
Vcc
J2
CON9
External input
3.6V max.
1
2
CON2
Z1
C1
+ C2
R2
Z2
C8
C9
21047
Fig. 10 - Demo Board Circuit with Echo-Suppression to be Used for Echo-On and Echo-Off Transceivers.
Rev. 1.4, 15-Jan-15
Document Number: 81749
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Additionally, with the programmable output S1 of the endec
the echo suppression feature can be switched on and off for
testing. The default mode is echo-off. To enable the echo,
S1 is to be set inactive/low. (See the chapter for
programming the TOIM4232, TOIM5232).
The oscilloscope diagrams are shown in figure 11.
Channel 2 shows the echo signal on the RXD output of the
TFDU4101 transceiver during transmission.
Channel 1 is the signal used for gating the path from the
transceiver RXD output to the endec. On channel 3 the
signal at the input of the endec is shown with a residual
signal. Finally, the output to the RS232 port, RD_232, is
clean without any noise signal.
Vishay Semiconductors
1->
2->
3->
4->
1) Ch1: TOIM4232; TD_232, pin 4, vertical scale: 2 V/div.,
horizontal scale: 20 µs/div.
2) Ch2: TFDU4101; RXD, pin 4 (IR)
3) Ch3: TOIM4232; RD_IR, pin 15
4) Ch4: TOIM4232; RD_232, pin 3
21037
Fig. 11 - Echo-Suppression
Rev. 1.4, 15-Jan-15
Document Number: 81749
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Revision: 02-Oct-12
1
Document Number: 91000