UG0447: SmartFusion2 and IGLOO2 FPGA High Speed Serial Interfaces User Guide

SmartFusion2 and IGLOO2 FPGA
High-Speed Serial Interfaces
UG0447 User Guide
SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Revision History
Date
Revision
Change
December 8, 2015
5
Fifth release
August 20, 2015
4
Fourth release
January 2015
3
Third release
July 2014
2
Second release
March 2014
1
First release
Confidentiality Status
This document is a non-confidential.
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table of Contents
About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 SERDESIF Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SERDESIF Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SERDESIF Serial Protocols Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Signal Interface of SERDESIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Getting Started with Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Using SERDESIF Macro in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overview of PCIe in SmartFusion2 and IGLOO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PCIe EP Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Using SERDESIF Block in PCIe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring High Speed Serial Interface Configurator for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating SERDESIF in PCIe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding SmartFusion2 or IGLOO2 PCIe Block to User Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
32
35
36
PCIe System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Coding Sublayer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCIe System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fabric Interface for PCIe System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCIe Clocking Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCIe Reset Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Designing with PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Base Address Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Translation on AXI3 Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AXI3 Slave Interface Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe System Credit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting up Lane Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe EP implementation supports L0, L1, and a special version of L2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Interrupts for Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECRC Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
55
56
58
58
59
60
61
61
61
Bridge Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 5
62
62
62
62
3
Table of Contents
Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Mapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EP Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Bridge Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
63
65
66
67
67
68
90
Hot Reset Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Global Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Stand Alone SERDESIF Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Appendix A: PCIe Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Common Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Extended Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type 0 Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IP Core Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSI Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe AER Extended Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
93
94
94
94
95
95
96
Appendix B: TLP Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.2 Content of a TLP with a Data Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Appendix C: SERDESIF PCIe Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3 XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Overview of XAUI Implementation in SmartFusion2/IGLOO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
XAUI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SmartFusion2 and IGLOO2 XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Using High-Speed Serial Configurator for XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Simulating SERDESIF with XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Application Example Using XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
XAUI IP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Overview of XAUI IP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
XAUI IP Fabric Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Reset and Clocks for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
XAUI Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
XAUI Mode Reset Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Using the MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI IP Block Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI Mode Loopback Test Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using MMD Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
122
124
125
MDIO Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SERDES Block System Register Configurations for XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4 EPCS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SmartFusion2/IGLOO2 EPCS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Using High Speed Serial Interfaces Configurator in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Simulating SERDESIF in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Create an Application in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SERDESIF Architecture in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SERDESIF Block in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SERDESIF Fabric Interface in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Reset and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
EPCS Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
EPCS Mode Reset Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
EPCS Interface: Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
EPCS SERDES Calibration and External Resistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Implementing SGMII Using EPCS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Customized EPCS Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5 Serializer/De-serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SERDES Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PMA Macro Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
TX Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX PLL and CDR PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERDES in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
161
163
167
170
SERDES Testing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Diagnostic Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pseudo-Random Bit Sequences Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pseudo-Random Bit Sequences Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Pattern Generator and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
172
173
173
Reset Requirement for Testing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using SmartDebug Utility for SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERDESIF- I/O Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
174
174
175
176
176
Acronym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6 SERDESIF Register Access Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Configuration of SERDESIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SERDESIF System Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SERDES Macro Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
SERDES Block Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
228
228
228
228
228
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Revision 5
5
Table of Contents
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6
R e vi s i o n 5
About This Guide
Purpose
This user guide provides details of the high speed serial interfaces (SERDES) and integrated
functionality support for multiple protocols within the SmartFusion®2 system-on-chip (SoC) field
programmable gate array (FPGA) or IGLOO®2 FPGA. The protocols supported in SmartFusion2 and
IGLOO2 FPGA devices are peripheral component interconnect express (PCI Express®) and ten gigabits
attachment unit interface (XAUI). In addition, user defined high serial protocol implemented in the
SmartFusion2 and IGLOO2 FPGA fabric can access SERDES lanes through the external physical
coding sublayer (EPCS) interface. The flexibility of EPCS can be used to build protocol specific
interfaces such as JESD204B, 1000Base-X, and serial gigabits independent interfaces (SGMII). The
integrated blocks can be configured to support single or multiple serial protocol modes of operation and
connected to the FPGA fabric.
Contents
This user guide contains the following chapters:
•
Chapter 1 - SERDESIF Block
•
Chapter 2 - PCI Express
•
Chapter 3 - XAUI
•
Chapter 4 - EPCS Interface
•
Chapter 5 - Serializer/De-serializer
•
Chapter 6 - SERDESIF Register Access Map
Additional Documentation
Table 1 lists additional documentation available on SmartFusion2 and IGLOO2 FPGAs. For a complete
and up-to-date listing, refer to the following web pages:
www.microsemi.com/products/fpga-soc/fpga/igloo2docs and http://www.microsemi.com/products/fpgasoc/soc-fpga/smartfusion2#documentation
Table 1 • Additional Documents for IGLOO2 FPGA and SmartFusion2 SoC FPGA
Document
Description
PB0121: IGLOO2 FPGA Product Brief
This product brief provides an overview of IGLOO2 family,
features, and development tools.
DS0451: IGLOO2 and SmartFusion2 Datasheet
This datasheet contains IGLOO2 DC and switching 
characteristics.
DS0124: IGLOO2 Pin Descriptions Datasheet
This document contains IGLOO2 pin descriptions, package
outline drawings, and links to pin tables in Excel format.
DS0115: SmartFusion2 Pin Descriptions Datasheet
This document contains SmartFusion2 pin descriptions,
package outline drawings, and links to pin tables in Excel
format.
Revision 5
7
About This Guide
Table 1 • Additional Documents for IGLOO2 (continued)FPGA and SmartFusion2 SoC FPGA
Document
Description
UG0445: IGLOO2 FPGA and SmartFusion2 SoC IGLOO2 FPGAs integrate fourth generation flash-based
FPGA Fabric User Guide
FPGA fabric. The FPGA fabric composed of 4-input look-up
table (LUT) logic elements, includes embedded memories
and mathblocks for DSP processing capabilities. This 
document describes the IGLOO2 FPGA fabric architecture,
embedded memories, mathblocks, fabric routing, and I/Os.
UG0448: IGLOO2 FPGA High Performance Memory IGLOO2 devices integrate a hard high performance memory
Subsystem User Guide
subsystem (HPMS) that consists of embedded memories,
DMA engines, and FPGA fabric interfaces. This document
describes the IGLOO2 HPMS and its internal peripherals.
UG0331: SmartFusion2 Microcontroller Subsystem SmartFusion2 devices integrate a hard microcontroller 
User Guide
subsystem (MSS). The MSS consists of a 
ARM® Cortex®-M3 processor with embedded trace macrocell (ETM), instruction cache, embedded memories, DMA
engines, communication peripherals, timers, real-time
counter (RTC), general purpose I/Os, and FPGA fabric 
interfaces. This document describes the SmartFusion2 MSS
and its internal peripherals.
UG0449: SmartFusion2
Resources User Guide
and
IGLOO2
Clocking IGLOO2 clocking resources include oscillators, FPGA fabric
global network, and clock conditioning circuitry (CCC) with
dedicated phase-locked loops (PLLs). These clocking
resources provide flexible clocking schemes to the on-chip
hard IP blocks—HPMS, fabric DDR (FDDR) subsystem, and
high-speed serial interfaces (PCIe, XAUI/XGXS, 
SERDES)—and logic implemented in the FPGA fabric.
UG0444: SmartFusion2 and IGLOO2 Low Power In addition to low static power consumption during normal
Design User Guide
operation, IGLOO2 devices support an ultra-low-power
Static mode (Flash*Freeze mode) with power consumption
less than 1 m. Flash*Freeze mode retains all the SRAM
and register data which enables fast recovery to Active
mode. This document describes the IGLOO2 Flash*Freeze
mode entry and exit mechanisms.
UG0443: SmartFusion2 and IGLOO2 FPGA Security The IGLOO2 device family incorporates essentially all the
and Reliability User Guide
security features that made third generation Microsemi SoC
devices the gold standard for security in the PLD industry.
Also included are unique design and data security features
and use models new to the PLD industry. IGLOO2 
flash-based FPGA fabric has zero FIT configuration rate due
to its single event upset (SEU) immunity, which is critical in
reliability applications. This document describes the
IGLOO2 security features and error detection and correction
(EDAC) capabilities.
UG0451: IGLOO2 and SmartFusion2 Programming Describes different programming modes supported in
User Guide
IGLOO2 devices. High-level schematics of these 
programming methods are also provided as a reference.
Important board-level considerations are discussed.
UG0450: SmartFusion2 SoC and IGLOO2 FPGA Sys- The system controller manages programming of the
tem Controller User Guide
IGLOO2 device and handles system service requests. The
subsystems, interfaces, and system services in the system
controller are discussed in this user guide.
8
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 1 • Additional Documents for IGLOO2 (continued)FPGA and SmartFusion2 SoC FPGA
Document
Description
AC393: SmartFusion2 and IGLOO2 Board Design This document provides guidelines for the hardware board
Guidelines Application Note
design schematics that incorporate IGLOO2 FPGA devices.
Good board design practices are required to achieve the
expected performance from the printed circuit board (PCB)
and IGLOO2 device.
AC394: Layout Guidelines for SmartFusion2/IGLOO2- This document provides guidelines for the hardware board
Based Board Design Application Note
layout that incorporates IGLOO2. Good board layout 
practices are required to achieve the expected performance
from the PCB and IGLOO2 device. These guidelines should
be treated as a supplement to standard board-level layout
practices. This document assumes that the readers have a
good understanding of the IGLOO2 chip and are 
experienced in digital and analog board layout, and 
knowledgeable transmission line theory and Signal Integrity.
TU0530: SmartFusion2 and IGLOO2 SmartDebug
Hardware Design Debug Tools Tutorial
The SERDES Debug tutorial demonstrates real-time system
and lane status information. SERDES configurations are
supported with Tcl scripting, allowing access to the entire
SERDES register map for real-time customized tuning.
3rd Party Documentation
PCISIG Specifications
PCI-SIG (originally formed as the Peripheral Component
Interconnect Special Interest Group) is the industry organization chartered with the development and management of
the PCI bus specification, the industry standard for a 
high-performance I/O interconnect to transfer data between
a CPU and its peripherals.
Revision 5
9
1 – SERDESIF Block
Introduction
The high speed serial interface block of the SmartFusion2 and IGLOO2 FPGA devices, also known as
serializer/de-serializer interface (SERDESIF), provides support for several serial communication
standards. This module integrates several functional blocks to support multiple high speed serial
protocols within the FPGA. The only difference between the SmartFusion2 and IGLOO2 SERDES
implementations is the means to initialize and configure the SERDESIF block. In the SmartFusion2
device, the embedded ARM Cortex-M3 processor within the MSS is used to perform these operations.
Whereas, the IGLOO2 family performs the same functions within the HPMS.
Features
The SERDESIF block has the following features:
•
PCIe protocol support.
•
XAUI protocol support.
•
External physical codings sub-layer (EPCS) interface supports user defined high serial protocols,
such as Serial gigabit media independent interface (SGMII) 1000-BaseX and JESD204B protocol
support.
•
Single or multiple serial protocol modes of operation. In multiple serial protocol modes, two
protocols can be implemented on the four physical lanes of the SERDESIF block.
Revision 5
10
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
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Figure 1-1 • SmartFusion2 and IGLOO2 SERDESIF Block Diagram
Device Support
Table 1-1 shows the total number of SERDESIF blocks available in each IGLOO2 device.
Table 1-1 • Available SERDESIF Blocks in SmartFusion2 and IGLOO2 Devices
M2S/M2GL
005
M2S/M2GL
010
M2S/M2GL
025
M2S/M2GL
050
M2S/M2GL
090
M2S/M2GL
060
M2S/M2GL
150
SERDESIF
available
0
1
1
Up to 2
1
1
Up to 4
SERDES
Lanes
0
4
4
8
4
4
16
Notes:
1. The specified number of SERDESIF blocks varies depending on the device package.
2. M2S/M2GL060/090 application interfaces have dual PCIe controller capability supporting up to two x1 or x2
endpoints within a SERDESIF. It can also support one x4 endpoint.
Revision 5
11
SERDESIF Block
SERDESIF Overview
The SmartFusion2 and IGLOO2 device families have up to four integrated high-speed serial interface
blocks (SERDESIF[3:0]). Each SERDESIF block interfaces with fabric, program control, and four duplex
SERDES differential I/O pads. Figure 1-1 on page 11 shows the inclusive high level view of the
SmartFusion2 or IGLOO2 SERDESIF block. Dependent on the implemented protocol, the SERDESIF
provides an AXI3 or AHB (PCIe), XGMII (XAUI) or native SERDES clock, and data (EPCS) along with
the control plane interface APB.
The SERDESIF is initially programmed at power-up with predefined parameters determined during the
FPGA design flow using the Libero® System-on-Chip (SoC) software.
Each of these SERDESIF blocks includes:
•
SERDES: This block implements up to four channels of high speed I/O, the physical media
attachment layer (PMA), and a physical coding sub-layer (PCS) of PCIe protocols. This PCS layer
is compliant to the Intel PIPE 2.0 specification. It also implements the PMA calibration and control
logic. The PCIe PCS functionality can be bypassed completely in order to use the SERDES lanes
for protocols other than PCIe. This allows use of the PMA in various PHY modes and implements
various protocols in the SmartFusion2 and IGLOO2 devices. Refer to the "Serializer/Deserializer" chapter on page 154 for more information on the SERDES block.
•
PCIe system: This block implements the x1, x2, and x4 lane PCIe endpoint (regular and reverse
lanes mode) with an AXI3/AHB interface to the fabric. The SmartFusion2 and IGLOO2 PCIe is
compliant with the PCIe Base Specification 1.1 for Gen1 and PCIe Base Specification 2.0 for
Gen1 or Gen2. Refer to the "PCI Express" chapter on page 28 for more information on the PCIe
system block.
•
XAUI Extender: This block is an XGMII extender to support the XAUI protocol through a FPGA IP
MAC core in the FPGA fabric. Refer to the "XAUI" chapter on page 104 for more information.
•
EPCS: This block is a basic mode used to extend the SERDES for custom support access to the
FPGA fabric. Refer to the "EPCS Interface" chapter on page 133 for more information.
•
SERDESIF system register: The SERDESIF system registers control the SERDES block
module for single protocol or multi-protocol support implementation. These registers can be
accessed through the 32-bit APB interface, and the default values of these registers are
configured using Libero System On-Chip (SoC) software. See Chapter 6 - "SERDESIF Register
Access Map" on page 177 for detailed register access descriptions. The SERDESIF is initially
configured at power-up with parameters determined during the FPGA design flow using the
Libero SoC software. The SERDES block Configuration can subsequently be changed by writing
the related control registers through the Advanced Peripheral Bus (APB) interface.
Table 1-2 • SERDESIF Module Single Protocol Usage Overview
Protocol
SERDESIF Description
Data Rate
(bps)
Reference
Clock (typ)
Input
Frequency
PCIe
SERDESIF is configured to use PCIe x4, x2, and x1 link mode. The
PCIe link can be configured in Regular or Reversed modes. In PCIe
only mode, unused lanes are forced to RESET state and the Extender
XAUI block is put in RESET state.
2.5G/5G
100 MHz
XAUI
SERDESIF is configured to use all four lanes. In XAUI mode, all lanes
are used and the PCIe system is put in RESET state.
4 x 3.125G
156.25 MHz
EPCS
In EPCS mode, any serial protocol can be run though the EPCS
interface to fabric using the EPCS interface. The PCIe system and
XAUI blocks are put in an inactive RESET state. EPCS mode is used
for implementing many other standard protocol interfaces such as
JESD204B, 1000Base-X, and SGMII.
User defined
100 - 160 MHz
12
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
SERDESIF Serial Protocols Support
The SERDESIF block supports the implementation of multiple high speed serial protocols. Although each
of the serial protocols is unique, all of them are layered protocol stacks, and the implementation can vary
greatly from one layer to the next layer. Typically, the physical layer consists of fixed functionality that is
common to multiple packet-based protocols, while the upper layers tend to be more customizable.
The advantage of being able to connect the FPGA logic and the SERDESIF blocks is that it allows
multiple serial protocols in SmartFusion2 and IGLOO2 devices. Figure 1-2 on page 14 shows the
implementation of PCIe, XAUI, and customized protocols using the SERDESIF block and FPGA fabric.
The Figure shows the fixed modules contained within the SERDESIF block per application. As shown in
the example, PCIe applications include several functional blocks within the SERDESIF, whereas EPCS
will require more FPGA IP blocks for complete system implementation.
Revision 5
13
SERDESIF Block
MAC Layer
CRC Generation
and Checking
Clock Tolerance
Compensation
GbE State Machine/
Auto Negotiation
Physical Layer
Scrambling/
Descrambling
Channel Alignment
(x4)
Channel Alignment
8b/10b
MAC Layer
Reconciliation
XAUI State Machine
A/K/R Translation
Link Training
and Status
Clock Tolerance
Compensation
MAC and Control
Clock Tolerance
Compensation
Physical Coding Sublayer
(PCS)
Link Width and Lane
Negotiation
Note - Typical SGMII Protocol (Shown)
Framing
Reconciliation
Physical Coding Sublayer
(PCS)
Data Link Layer
(CRC, Control, DLLP)
MAC and Control
Data Link Layer
Transaction Layer
Transaction
Layer
Application Layer
8b/10b
8b/10b
Word Alignment/
Link Sync
Word Alignment/
Link Sync
PMA (SERDES)
MDI
PCIe
Express
XAUI
- SERDESIF contained functionality
Figure 1-2 • Serial Protocol Using SERDESIF and FPGA Logic
14
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PMA (SERDES)
MDI
EPCS
Physical Medium
Attachment (PMA)
PMA (SERDES)
Physical Medium
Dependant (PMD)
Word Alignment/
Link Sync
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
The following sections describe each of the serial protocols and their implementation in the
SmartFusion2 and IGLOO2 devices using the SERDESIF block.
I/O Signal Interface of SERDESIF
The SERDESIF block interfaces with the FPGA fabric and SERDES differential I/O pad. The SERDESIF
I/Os can be grouped into a number of interfaces from functional protocol. The SERDESIF I/O signals
interface are listed below:
•
Reset Interface
•
Clock Interface
•
AXI3/AHB-Lite Master Interface
•
AXI3 /AHB-Lite - Slave Interface
•
APB Slave Interface
•
EPCS Interface
•
I/O - PAD Interface (refer to Table 5-4 on page 175 for more information)
•
PLL Control and Status Interface
•
SERDESIF Block-PCI Express Interrupt and Power Management Interface
Refer to protocol specific chapters for I/O details.
PCIe Protocol
The SmartFusion2 or IGLOO2 device family supports Gen1 and Gen2 PCIe endpoints. The PCIe
endpoint supports PCIe base specification 1.1 (2.5 Gbps) and PCIe base specification 2.0 (5.0 Gbps)
protocols with x1, x2, and x4 lane configurations. The application interface to the PCIe link is available
through the FPGA fabric, and can be programmed to AXI3 or AHB master and slave interfaces. The
SmartFusion2 and IGLOO2 devices have PCIe hard IP that is designed for performance and ease-ofuse. The hard IP consists of the PMA, data link, and transaction layers.
Features:
•
x1, x2, and x4 lane PCIe support
•
Suitable for Native Endpoint
•
PCIe base specification 2.0 and 1.1 compliant
•
Single-function/Single virtual channel (VC)
•
Three 64-bit base address registers or six 32-bit base address registers
•
2 KB Receive, 1 KB Transmit, 1 KB Retry Buffers
•
64-bit AXI3/32-bit AHB master and slave interface to the FPGA fabric
Revision 5
15
SERDESIF Block
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Figure 1-3 • SERDESIF Configuration for PCIe Protocol
16
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 1-3 shows the possible options for implementing the PCIe link on four physical SERDES lanes.
Refer to the "PCI Express" chapter on page 28 for details on PCIe protocol implementation in
SmartFusion2 and IGLOO2 devices. Lane[0:1] and Lane[2:3] share on-chip hardware resources which
create inter-dependency between the physical lanes. PCIe lanes are supported in Regular or Reversed
modes. These modes provide the physical to logical lane implementation.
Table 1-3 • Physical Interface Options for PCIe Endpoint in the SERDESIF Block
PHYSICAL SERDES LANES/LOGICAL LANES
SERDES_x_L01_REXT4
SERDES_x_L23_REXT4
PHY-MODE
LANE-0
LANE-1
LANE-2
LANE-3
PCIe Protocol
Protocol
Protocol
Protocol
Protocol
Single Protocol
PCIe
*
*
*
PHY -Mode
PCIe
PCIe
*
*
PCIe
PCIe
PCIe
PCIe
Single Protocol
*
*
*
PHY- Mode
*
*
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
Multi Protocol
PCIe
*
EPCS
EPCS
PHY – Mode
PCIe
PCIe
EPCS
EPCS
M2S/M2GL010/025/050/150
(PCIe link Non-Reversed-Mode)
(PCIe link Reversed Mode)
(PCIe link Non-Reversed-Mode)
Multi Protocol
*
PHY – Mode
PCIe
PCIe
EPCS
EPCS
Dual PCIe Protocol
PCIe_0
*
PCIe_1
*
PHY – Mode
PCIe_0
PCIe_0
PCIe_1
PCIe_1
*
PCIe_0
*
PCIe_1
PCIe_0
PCIe_0
PCIe_1
PCIe_1
*
PCIe_0
PCIe_1
*
PCIe_0
PCIe_0
PCIe_1
PCIe_1
Dual PCIe Protocol
PCIe_0
*
*
PCIe_1
PHY – Mode
PCIe_0
PCIe_0
PCIe_1
PCIe_1
Multi and Dual PCIe Protocol
PCIe_0
PCIe_1
EPCS
EPCS
PHY – Mode
PCIe_0
*
EPCS
EPCS
(PCIe link Reversed-Mode)
M2S/M2GL060/090
(Both PCIe link Non-Reversed-Mode)
Dual PCIe Protocol
PHY – Mode
(Both PCIe link Reversed-Mode)
Dual PCIe Protocol
PHY – Mode
(PCIe_0 in Reversed-Mode)
(PCIe_0 in Non-Reversed-Mode)
(PCIe_0 in Non-Reversed-Mode)
(PCIe_1 in Reversed-Mode)
(Non-Reversed-Mode)
Revision 5
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SERDESIF Block
Table 1-3 • Physical Interface Options for PCIe Endpoint in the SERDESIF Block (continued)
PHYSICAL SERDES LANES/LOGICAL LANES
SERDES_x_L01_REXT4
SERDES_x_L23_REXT4
PHY-MODE
LANE-0
LANE-1
LANE-2
LANE-3
PCIe Protocol
Protocol
Protocol
Protocol
Protocol
Notes:
1. PCIe 2.0 protocol is supported on SERDESIF with a maximum lane width of x4 (Single controller mode). PCIe link
can be operated at GEN1 (2.5GHz) or at GEN2 (5.0GHz) speed. STD speed grade for Gen1, -1 for Gen2.
2. M2S/M2GL060/090 application interfaces have dual controller capability supporting up to two x1 or x2 endpoints
within a SERDESIF.
3. Lane 2 and lane 3 EPCS interface is available in multi protocol PHY-MODE of operation.
4. SERDES_x_REXT: External calibration resistors are available on lane 0 and lane 2 physical lanes. Lane 1 and
lane 3 need to get calibration values from adjacent lane 0 and lane 2 respectively.
5. Lane 2 and Lane 3 EPCS interfaces are available where noted in multi-protocol PHY modes.
6. *: Designates Physical lane not used for any protocol. It is held in reset by device programming.
7. EPCS notations can be SGMII,JESD204, or any user defined serial protocol.
8. Non-M2S060/090 devices cannot support x1 PCIe Reverse modes.
XAUI Protocol
The XAUI implementation is an interface extending the XGMII, 10 gigabit media independent interface.
The XGMII is used to attach the Ethernet MAC to the PHY. The XAUI may be used in place of, or to
extend, the XGMII in chip-to-chip applications typical of most FPGA IP Ethernet MAC-to-PHY
interconnects.
Features:
18
•
Full compliance with IEEE 802.3
•
IEEE 802.3ae- clause 45 MDIO interface
•
IEEE 802.3ae- clause 48 state machines
•
Pseudo random idle insertion (PRBS Polynomial X7 + X3 + 1)
•
Reference clock frequency of 156.25 MHz
•
Double-width single data rate (SDR - 64 bit XGMII interface)
•
Comma alignment function
•
PHY-XS and DTE-XS loopback
•
IEEE 802.3ae- annex 48A jitter test pattern support
•
IEEE 802.3 clause 36 8B/10B encoding compliance
•
Tolerance of lane skew up to 16 ns (50 UI)
•
IEEE 802.3 PICs compliance matrix
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
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Figure 1-4 • SERDESIF Configuration for XAUI Protocol
Note: Contact Microsemi sales for 10G MAC FPGA IP information.
Table 1-4 shows the configuration bandwidth for using XAUI in four physical SERDES lanes. Refer to the
"XAUI" chapter on page 104 for more information on XAUI protocol implementation in the SmartFusion2
and IGLOO2 devices.
Table 1-4 • Bandwidth for Implementing XAUI in SERDESIF Block
Lane0
Lane1
Lane2
Lane3
XAUI Protocol
Protocol
Speed
(bps)
Protocol
Speed
(bps)
Protocol
Speed
(bps)
Protocol
Speed
(bps)
Single Protocol
PHY mode
XAUI
3.125 G
XAUI
3.125 G
XAUI
3.125 G
XAUI
3.125 G
EPCS Protocol
By using the EPCS interface, any other serial protocol can be implemented in the SmartFusion2 or
IGLOO2 device family. The SERDESIF block can be configured to bypass the embedded PCS logic in
the SERDES block and expose the EPCS interface to the fabric. The user-defined IP block in the FPGA
fabric can be connected to this EPCS interface.
Revision 5
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SERDESIF Block
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Figure 1-5 • SERDESIF Configuration for EPCS Protocol
Refer to the "EPCS Interface" chapter on page 133 for more information on EPCS implementation in
SmartFusion2 and IGLOO2 device families.
20
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
The four SERDES physical lanes can be configured to run different serial protocols, resulting in different
modes of operation. Table 1-5 summarizes the various modes of operation of the SERDESIF block.
Table 1-5 • Serial Protocol Implementation SmartFusion2 and IGLOO2 Devices
PHY Physical Lanes
Lane0
Serial Protocol
PCIe Protocol only
mode
Modes
PCIe (x4)
PCIe (x2)
PCIe (x1)
Lane1
Lane2
Lane3
PHY Logical Lanes Vs Logical Lanes
PCIe
PCIe
PCIe
PCIe
Lane0
Lane1
Lane2
Lane3
PCIe
PCIe
–
–
Lane0
Lane1
PCIe
–
–
–
Lane0
PCIe Reversed mode
(x4)
PCIe
PCIe
PCIe
PCIe
Lane3
Lane2
Lane1
Lane0
PCIe Reversed mode
(x2)
–
–
PCIe Reversed mode
(x1)
–
PCIe Reversed mode
(x2)
PCIe
PCIe
Lane1
Lane0
–
–
PCIe
Lane0
PCIe
PCIe
–
–
Lane1
Lane0
PCIe Reversed mode
(x1)
–
PCIe
–
–
XAUI only
XAUI (x4 lane)
XAUI-0
XAUI-1
XAUI-2
XAUI-3
EPCS only
All lanes are used for
user-defined protocol
EPCS
EPCS
EPCS
EPCS
PCIe (x2)
PCIe
PCIe
EPCS
EPCS
Lane0
Lane1
PCIe
–
EPCS
EPCS
EPCS
EPCS
EPCS
EPCS
Multi-protocol (PCIe and
EPCS)
PCIe (x1)
Lane0
Lane0
PCIe Reversed mode
(x2)
PCIe Reversed mode
(x1)
PCIe
PCIe
Lane1
Lane0
–
PCIe
Lane0
Notes:
1. Lane Tx-clk is used for lane0 for PCIe protocol purposes.
2. In Multi-protocol mode, EPCS is available only on lane2 and lane3.
3. Refer to Table 1-4 on page 19 for complete device listing with PCIe implementations.
4. EPCS can be used to build protocol specific interfaces such as JESD204B, 1000Base-X, and SGMII.
Revision 5
21
SERDESIF Block
Getting Started with Libero SoC
Using SERDESIF Macro in Libero SoC
Figure 1-6 • SERDESIF Module
The main SERDESIF GUI wizard interrogates customizable design parameters and initiates the available
options. This enables the user to step through the building blocks to assemble the correct SERDESIF
module.
22
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Figure 1-7 • Libero SoC SERDESIF GUI
Note: The GUIs are examples of Libero SoC/SysBuilder GUIs and maybe enhanced over time to ease
user experience.
The High Speed Serial Interface Configurator available in Libero SoC allows generation of the
SERDESIF block with various protocol modes. It allows module creation of Single and Multi protocol
modes. This information is detailed in the protocol sections of this chapter.
Clocking and Resets
This section describes the clocking and reset scheme for the SERDESIF block. Generally the
SERDESIF block has varying reset and clocking options that are exposed for the different protocol
choices. More details of these options are found in the specific protocol chapters.
Clocking System for SERDESIF
The clocking system in the SERDESIF block includes the following:
•
•
SERDES reference clocks
–
REFCLK0 and REFCLK1 - Dedicated input pins
–
Fabric Clock available only for EPCS protocols
Fabric/serial PLL (SPLL) clocking
–
PCIe system block clocking
–
XAUI block clocking
SERDES Reference Clocks
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through PLLs. Refer to the "Serializer/De-serializer" chapter on page 154 for more
information on Tx and Rx clock generation through PLLs. There are two dedicated reference clock
(REFCLK0 and REFCLK1) inputs on the SERDESIF. The two reference clocks, REFCLK0 and
REFCLK1, are connected to I/O pads REFCLK0_P/N and REFCLK1_P/N. The reference clock can also
Revision 5
23
SERDESIF Block
come from the fabric, but that clock source might not be optimal for certain implementations. This is
discussed later in specific chapters.
Figure 1-8 shows the reference clock selection in the High Speed Serial Interface Configurator available
in the Libero SoC. It sets the MUX selection, depending on the selected reference clocks.
Figure 1-8 • SERDES Reference Clock Using the High Speed Serial Interface Generator
Serial PLL (SPLL)
A dedicated PLL located within the SERDESIF is provided within the SERDESIF block and used
transparently by the design for handling clock domain transfers between the blocks of the SERDESIF
and fabric. The SPLL manages the skew between the FABRIC and SERDESIF module and is used for
PCIe and XAUI protocol implementations.
The SPLL is powered by the SERDES_[01]_PLL_VDDA supplies. This supply is selected by the user to
be typically 2.5 V or 3.3 V. This selection does not impact the SPLL frequency range. Refer to the
DS0451: IGLOO2 and SmartFusion2 Datasheet for more information on the PLL power supply
requirement. The user must select this supply in the Libero software to correctly provision this supply in
conjunction with the MDDR_PLL_VDDA, FDDR_PLL_VDDA, PLL0_PLL1_MDDR_VDDA, and
CCC_XX[01]_PLL_VDDA.
Refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for details on
fabric based PLLS.
This PLL power setting is not related to analog power for the SERDES PMA which is powered by the
SERDES_[01]_L[0123]_VDDAPLL supplies.
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Figure 1-9 shows the SPLL power supply UI.
Figure 1-9 • SPLL Power Supply Selection in the Libero SoC New Project Wizard
SERDESIF Reset
Refer to the "PCI Express" chapter on page 28, the "XAUI" chapter on page 104, and the "EPCS
Interface" chapter on page 133 for more information on using these reset signals.
A FPGA IP module, CORERESETP, controls the SERDESIF reset operation at initialization. The
CORERESETP module ensures that the SERDES (PHY and CORE) reset signals remain asserted (low)
until APB-based configuration has been completed. Until complete, no accesses should be initiated from
the fabric to the SERDESIF through the AXI3/AHB interface. This provides a predictable behavior for the
SERDESIF at startup.
The Libero software flow provides firmware for the correct SERDESIF initialization sequence as below.
•
Write PMA and System Registers
•
De-assert PHY_RESET_N
•
Wait 130us
•
De-assert CORE_RESET_N
The following is only done for PCIe (done for each PCIe core for the 090 SERDES block)
•
Select 0th lane (must take care of PCIe reverse; for x2 for instance, lane 1 is lane 0)
•
Wait for PMA ready on that lane
•
Write PCIe registers
•
Issue INIT_DONE
Refer to specific protocol chapters for detailed pin descriptions and information on reset behaviors for
each protocol.
Revision 5
25
SERDESIF Block
Serial Protocols Setting Using the SERDESIF System Registers
The SERDESIF is configured to support various modes of operation. This configuration of the protocols
is through high level SERDESIF system registers. These registers are configured using the APB
interface. To facilitate the initial configuration, a GUI in Libero SoC is provided. Figure 6-1 on page 177
describes the settings for the three SERDESIF system registers to force the SERDESIF block into a
specific mode of operation. Refer to Chapter 6 – SERDESIF Register Access Map for more details.
Table 1-6 • Reset Interface
Port
Type
Connected To
CORE_RESET_N
Input
Fabric
PCIe or XAUI mode: Active reset for PCIe and XAUI
fundamental core
PHY_RESET_N
Input
Fabric
SERDES-PHY-Active low reset. If not, lanes are used for any
serial protocol. Tie it to High.
APB_S_PRESET_N
Input
Fabric
Asynchronous set signal for APB slave interface.
EPCS_0_RESET_N
Input
Fabric
External EPCS interface mode: External PCS reset control
lane0, lane1, lane2, and lane3.
Output
Fabric
External EPCS interface mode (lane0, lane1, lane2, and lane3):
Clean reset deasserted on rxclk.
Output
Fabric
External EPCS interface mode (lane0, lane1, lane2, and lane3):
Clean reset deasserted on txclk.
PLL_SERDESIF_RESET
Output
SPLL
SPLL reset output
PLL_SERDESIF_PD
Output
SPLL
SPLL power-down enable
EPCS_1_RESET_N
EPCS_2_RESET_N
Description
EPCS_3_RESET_N
EPCS_0_RX_RESET_N
EPCS_1_RX_RESET_N
EPCS_2_RX_RESET_N
EPCS_3_RX_RESET_N
EPCS_0_TX_RESET_N
EPCS_1_TX_RESET_N
EPCS_2_TX_RESET_N
EPCS_3_TX_RESET_N
26
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
List of Changes
The following table shows important changes made in this document for each revision.
Date
Revision 4
(August 2015)
Changes
Page
Updated Table 1-1 and Table 1-3 (SAR 69996).
11 and
17
Updated Figure 1-6, Figure 1-7, Figure 1-8, and Figure 1-9 (SAR 69885).
22, 23,
24, 25
Updated Figure 1-1 and Figure 1-5.
11 and
20
Updated "Features" section.
10
Updated "SERDESIF Overview" section.
12
Updates are made to maintain the style and consistency of the document.
NA
Revision 3
(January 2015)
Consolidated SmartFusion2 and IGLOO2 User Guides.
NA
Revision 2
(July 2014)
Updated "PCIe Protocol" section (SAR56868).
15
Updated Table 1-3 (SAR 57190).
17
Initial release.
NA
Revision 1
(March 2014)
Revision 5
27
2 – PCI Express
Introduction
This chapter describes using PCIe in the SmartFusion2 and IGLOO2 FPGA devices. PCIe is a highspeed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus
standards. The SmartFusion2 or IGLOO2 SERDESIF allows fully integrated PCIe endpoint (EP)
implementation. This chapter provides detailed information on implementing, verifying, and debugging
the PCIe EP design in the SmartFusion2 and IGLOO2 devices.
JTAG I/O SPI I/O
Multi-Standard User I/O (MSIO)
SPI x 2
MMUART x 2
I2C x 2
Timer x 2
System Controller
AES256
SHA256
ECC
NRBG
SRAM-PUF
Microcontroller Subsystem (MSS) for SmartFusion2
OR
High Performance Memory Subsystem (HPMS) for IGLOO2
CAN
APB
HS USB
OTG ULPI
PDMA
WDT
In-Application
Programming
Flash*Freeze
sh*Freeze
DDR User I/O
SYSREG
MSS/HPMS
DDR Controller
+ PHY
AHB Bus Matrix (ABM)
Multi-Standard User I/O (MSIO)
TSEMAC
eSRAM
HPDMA
OR
Interrupts
FPGA
GA Fabric
AHB
Mi SRAM
Micro
(64x18)
Micro SRAM
(64x18)
AHB
SMC_FIC Config
AHB
Large SRAM
(1024x18)
Large SRAM
(1024x18)
AXI/AHB
Math Block
MACC (18x18)
Multi-Standard User I/O (MSIO)
FIC_1
SERDES
I/O
PMA
LANE1
PCIe PCS
LANE0
PMA
Control
Logic
LANE[0:1] Calibration
FIIC
FIC_0
PMA
LANE0
DDR
Bridge
eNVM
RTC
COMM_BLK
SERDES
I/O
PCIe PCS
LANE1
PMA
Control
Logic
PIPE
Controller
APB Bus
SERDES
I/O
PMA
LANE2
SERDES
I/O
PMA
LANE3
EPCS
LANE
0:1
Lane
0:1
XAUI
Extender
PCIe PCS
LANE2
PMA
Control
Logic
LANE[2:3] Calibration
PMA
Control
Logic
PCIe PCS
LANE3
Lane
2:3
EPCS
LANE
2:3
Math Block
MACC (18x18)
FPGA Fabric Interface
Config
Config
AXI/AHB/XGXS
Serial Controller 0
(PCIe, XAUI/XGXS)
+ Native SERDES
OSCs
AXI/AHB/XGXS
Serial Controller 1
(PCIe, XAUI/XGXS)
+ Native SERDES
Config
PLLs
Serial 1 I/O
Serial 0 I/O
AXI/AHB
Fabric DDR
Controller + PHY
Standard Cell /
SEU Immune
APB Slave
Auxilliary
Register Space Power
Interface
Wake-Up
Logic
Flash Based /
SEU Immune
AXI/AHB
Master/
Slave
User PCIe
System
DDR User I/O
Figure 2-1 • SmartFusion2 and IGLOO2 SERDESIF Block Diagram
Features
The SmartFusion2 or IGLOO2 family supports up to four hard SERDESIF blocks in one device, and each
block supports up to 4 serialization/deserialization (SERDES) lanes, thus allowing to have up to 16
SERDES lanes. Figure 2-1 shows the SmartFusion2 M2S050 or IGLOO2 M2GL050 device block
diagram with PCIe implementation. Each SERDESIF block contains a integrated PCIe system block,
also known as a PCIe system, which implements the PCIe transaction layer and data link layer. The
SERDESIF block also has a SERDES block that implements the physical layer. The PCIe system block
along with the SERDES block provide the integrated PCIe EP solution in SmartFusion2 and IGLOO2.
Following are the main features of PCIe implemented in SmartFusion2 and IGLOO2:
•
x1, x2, x4 lane support
•
Implements native endpoint
•
Compliant with PCIe Base Specification Revision 2.1 and 1.1
•
Single-function/Single virtual channel (VC)
•
Receives, transmits, and retries buffer
Revision 5
28
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
•
AXI3/AHB master and slave interface to the SmartFusion2 or IGLOO2 FPGA fabric
•
Supports design time selection of the PCIe lane reversal for flexibility of lane assignments for
board layout.
Note: A PCIe Endpoint refers to the location of the connection in the PCIe topology. A PCIe Endpoint can
connect to Switches Downstream Port or a Root Complex Downstream Port. As an Endpoint the
PCIe can initiate and respond to transactions in the system.
Device Support
The SmartFusion2 and IGLOO2 families have a number of devices available. Table 2-1 shows the total
number of SERDESIF Blocks available in each SmartFusion2 and IGLOO2 device that can be
configured to support PCIe.
Table 2-1 • SERDESIF PCIE Endpoint Blocks Available in SmartFusion2 and IGLOO2
PCIE EP
available
M2S/M2GL
005
M2S/M2GL
010
M2S/M2GL
025
M2S/M2GL
050
M2S/M2GL
060
M2S/M2GL
090
M2S/M2GL
150
0
1
1
Up to 2
Up to 2
Up to 2
Up to 4
Notes:
1. The specified number of SERDESIF blocks varies depending on the device package.
2. M2S/M2GL060/090 application interfaces have dual PCIe controller capability supporting up to two x1 or x2
endpoints within a SERDESIF. It can also support one x4 endpoint.
Overview of PCIe in SmartFusion2 and IGLOO2
The PCIe protocol is software backward-compatible with the earlier PCI and PCI-X protocols, but is
significantly different from its predecessors. The performance is scalable based on the number of lanes
and the generation that is implemented. The PCIe protocol specifies 2.5 giga-transfers per second for
Gen1, and 5 giga-transfers per second for Gen2, because the PCIe protocol uses 8B/10B encoding,
there is a 20% overhead. Table 2-2 shows the aggregate bandwidth of a PCIe link.
Table 2-2 • Theoretical PCIe Throughput
Link Width
x1
x2
x4
Unit
PCI Express Gen1 Gbps (1.x compliant)
2
4
8
Gbps
PCI Express Gen2 Gbps (2.x compliant)
4
8
16
Gbps
Description
SmartFusion2/IGLOO2 support implementing PCIe Endpoints (Eps). The EP in PCIe refers to a type of
function that can be the requester or the completer of a PCIe transaction. The PCIe system and
SERDES high-speed serial interface (SERDESIF Block) blocks implement the PCIe EP specification for
the transaction, data link, and physical layers.
Figure 2-2 on page 30 shows a simplified view of a PCIe EP implementation in a SmartFusion2/IGLOO2
device. The PCIe system interfaces to the FPGA fabric on one side and the SERDES block on the other
side. The SERDES block interfaces to the dedicated I/O in device is called a SERDES I/O. Refer to the
“SERDESIF- I/O Signal Interface” listed in Table 5-4 on page 175 for more information. The PCIe system
interface to the FPGA fabric consists of an application interface and a configuration interface. In addition,
it has several signals for clocking, reset, and power management.
Revision 5
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PCI Express
•
•
Application interface: The application interface is used to transfer transaction layer packets
(TLP). It can be AXI3/AHB master only, or AXI3/AHB slave only, or AXI3/AHB master plus slave
interface.
–
AXI3/AHB master interface: The master interface can be a 64-bit AXI3 master or a 32-bit AHB
master. A typical application interface uses a master interface which is used to respond to
data read requests and a slave interface which is used to initiate requests. It is also possible
to use a master and/or the slave interface by itself for specific applications.
–
AXI3/AHB slave interface: The slave interface can be a 64-bit AXI3 slave or a 32-bit AHB
slave interface. The SmartFusion2 or IGLOO2 fabric initiates PCIe transactions using the
slave interface (that is, Memory Write TLP and Memory Read TLP). The data on a read
request comes back to this same interface.
Configuration interface: The configuration interface uses the APB slave interface.
–
•
6(5'(6
,2
APB interface: The APB interface has access to various registers, including PCIe
configuration registers, AXI3/AHB bridge register and SERDESIF register. The APB provides
access to the memory map of the SERDESIF which includes a section for the PCIe controller.
Other signals: The PCIe system also has several clocking signals, reset signals, phase-locked
loop (PLL) signals, interrupts, and power management signals to the FPGA fabric.
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Figure 2-2 • SERDESIF Configuration for PCIe Single Protocol Mode
30
R e visio n 5
(3&6
/$1(
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIe EP Application Example
Figure 2-3 shows a relatively simple application with a switch port connected to a PCIe EP implemented
in a SmartFusion2 or IGLOO2 device. MSS/HPMS
PCIe/SERDES Configuration Data
FIC_2
Fabric
User Logic
AXI/AHB Master
and Slave Interface
SERDESIF in PCIe Mode
APB Slave Interface
SmartFusion2/IGLOO2
PCI Express Connector
PCIe Link
SWITCH
Figure 2-3 • SmartFusion2 and IGLOO2 PCIe EP Implementation
Getting Started
Using SERDESIF Block in PCIe Mode
This section provides an overview of configuring the SERDESIF block in PCIe mode, simulating the
SERDESIF block in PCIe mode, and implementing a PCIe EP in a SmartFusion2 or IGLOO2 device.
The High Speed Serial Interface Configurator in Libero SoC provides the configuration options for the
PCIe EP implementation. It includes options for selecting the protocol for various SERDES lanes, serial
rate settings, fabric interface, PCIe Identification registers, PCIe base address register (BAR). These
setting are implemented during programming using dedicated flash bits for fast configuration or via the
APB interface. These registers can be reviewed by using the advanced peripheral bus (APB) interface,
which can access all the registers in the SERDESIF block.
The following sub-sections show how to instantiate PCIe in a design:
•
Configuring High Speed Serial Interface Configurator for PCIe
•
Simulating SERDESIF in PCIe Mode
•
Adding SmartFusion2 or IGLOO2 PCIe Block to User Design
Revision 5
31
PCI Express
Configuring High Speed Serial Interface Configurator for PCIe
This sub-section describes configuring and generating the SERDESIF block for PCIe EP mode using the
Libero SoC software.
The High Speed Serial Interface Configurator (SERDESIF Configurator) in Libero allows configuration of
the SERDESIF block in PCIe mode. Refer to Figure 2-4 for setting the SERDESIF Configurator in PCIe
only protocol mode. Refer to Figure 2-5 on page 33 for setting the SERDESIF Configurator in PCIe and
other protocol mode.
Figure 2-4 • PCIe Single Protocol Mode Setting in SERDESIF Configurator
32
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Figure 2-5 • PCIe Multi-Protocol Mode Setting in SERDESIF Configurator
Following is a brief description of the various protocol configuration options. Refer to the "SERDESIF
Block" chapter on page 10 for details.
Protocol Selection
These settings are used for protocol selection.
•
Protocol Type 1 – Protocol settings. Select PCIe from the drop-down menu.
•
Number of Lanes – Select number of lanes used.
•
Speed – Select Gen1 or Gen2 speed for the PCIe lanes.
•
Protocol 1 PHY Reference Clock – Select the inputs for the PHY reference clock selection.
Refer to the "SERDES Reference Clocks Selection" section on page 51 for details on PHY
reference clock selection.
Revision 5
33
PCI Express
In addition to the protocol settings, various other options for PCIe implementation can be set, as shown in
Figure 2-6.
Figure 2-6 • High-Speed Serial Configurator with PCIe Implementation Options
Following is a brief description of the various configuration options:
PCIe SPLL Configuration
These settings are used for SPLL that synchronizes data between the AXI3/AHB interface to the
SERDESIF block.
•
CLK_BASE: This is an AXI3/AHB clock setting.
•
The SPLL is a PLL embedded in the SERDESIF to manage the clock phase used for transfers
across the SERDESIF to FPGA fabric interface.
PCIe Fabric Interface (AXI3/AHB-Lite)
CLK_BASE frequency must be set to the same frequency of the APB interface as the operating
frequency.These settings select the PCIe system interfaces to the fabric. It can be AXI3 or AHB-Lite bus
as master only, slave only, or both master and slave.
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIe Base Address Registers
These settings are used to set six 32-bit or three 64-bit base address registers.
•
Width: Width can be 32-bit or 64-bit. If an even register is selected to be 64-bits wide, the
subsequent (odd) register serves as the upper half of 64 bits. Otherwise, the width of odd
registers is restricted to 32 bits.
•
Size: Ranges from 4 Kbytes to 2 Gbytes
•
Prefetchable: Prefetchable option for memory BAR.
PCIe Identification Registers
These settings are used to set the six identification registers for PCIe.
•
Vendor ID: 0x11AA is the Vendor ID assigned to Microsemi by PCI-SIG. Contact Microsemi to
allocate subsystems under the Microsemi vendor ID.
•
Subsystem vendor ID: Card manufacturer’s ID
•
Device ID: Manufacturer’s assigned part number by the vendor
•
Revision ID: Revision number, if available
•
Subsystem Device ID: Assigned by the subsystem vendor
•
Class Code: PCIe device's generic function
PCIe Other Options
These settings are used to set other PCIe options:
•
L2_P2 Entry/Exit: Selecting this option adds PCIE_WAKE_N, PCIE_WAKE_REQ, and
PCIE_PERST_N ports to control the L2/P2 state.
•
PHY Reference Clock Slot: Select this option if the PHY reference clock is coming from a PCIe
slot or it is generated separately.
Note: Slot refers to a clock source that is shared in the PCIe system between both ends of the link. The
other setting, Independent, is used in a system which uses independent clock sources on either
side of the link. This setting changes the PCIe configuration space register to advertise to the
system root which clocking topology is used. It makes no other functional changes to the endpoint.
•
De-emphasis: Set the de-emphasis (3.5 dB and 6.0 dB) for PCIe GEN 2 speed.
•
Transmit Swing: Set transmit swing for PCIe GEN 2 speed.
•
PCIe Specification Version: Specifies the version
PCIE_WAKE_N, PCIE_WAKE_REQ, and PCIE_PERST_N ports are added optionally with L2/P2
selection. PCIE_WAKE_N is an output and PCIE_WAKE_REQ, and PCIE_PERST_N ports are inputs to
the PCIE core.
Entry of L2P2 can only be requested by the host and when it is requested, the SmartFusion2 or IGLOO2
PCIE core responds to the protocol request and its state machine will go to L2 state. Its response will be
in conjunction with the CFGR_L2_P2_ENABLE bit of the CONFIG_PCIE_PM register. If the bit is
configured as CFGR_L2_P2_ENABLE = 0 or 1, the device goes into L2, and it needs a fundamental
reset (PCIE_PERST_N) to get out of L2.
If CFGR_L2_P2_ENABLE=1, the device shows much lower power when it enters L2. In either case the
host needs to perform enumeration.
PCIE_WAKE_REQ is an input into the SmartFusion2 or IGLOO2 PCIE reset controller. When
PCIE_WAKE_REQ is asserted, the PCIe reset controller drives out the PCIE_WAKE to RC as WAKE#
side band signal.
Simulating SERDESIF in PCIe Mode
Refer to the SERDESIF BFM Simulation Guide for more information on simulation detail.
Revision 5
35
PCI Express
Adding SmartFusion2 or IGLOO2 PCIe Block to User Design
To use the SmartFusion2 or IGLOO2 PCIe block in user design, the appropriate setting must be set in
the SERDESIF Configurator and then generate the SERDESIF block. Figure 2-7 shows the SERDESIF
block in Libero. Libero promotes the SERDES I/Os to the top level and exposes the AXI3/AHB (based on
user settings) and APB interface to the FPGA fabric. In addition, the SERDESIF block exposes the
clocks, resets, PLL locks, and power management signals for PCIe implementation.
Figure 2-7 • High Speed Serial Interface Block in Libero SoC
The user logic block implements an AXI3 slave interface to transfer data to the PCIe link and an AXI3
master interface to receive the data from the PCIe link. The user connects the HPMS SDIF bus to the
APB3 interface of the SERDESIF. The HPMS will configure the SERDESIF and control specific resets of
the SERDESIF. A FAB clock conditioning circuit (CCC) generates the clock for the AXI3 interface on the
port CLK_BASE.
36
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIe System Architecture
PCIe is a high speed, packet based, point-to-point, low pin count, serial interconnect bus. SmartFusion2
and IGLOO2 have a fully integrated PCIe End Point (EP) implementation. This section describes the
architecture of the PCIe system that implements the main PCIe IP function.
Physical Coding Sublayer Block
The PCS block implements 8b/10b encoder/decoder, RX detection, and an elastic buffer for the PCIe
protocol. It has transmitter and receiver blocks.
Transmitter Block
The Transmitter block consists of an 8b/10b encoder and a phase matching first-in-first-out (FIFO), as
shown in Figure 2-8. The transmitter block passes the input data in the PCLK domain (PIPE clock
domain) to the PMA hard macro in the TX clock domain.
PIPE
Interface
CLK MUX
TXCLK
TXClk
RefClk
CLK
Divider
PIPE_PCLKOUT
To
PCIe
System
Single
Lane PMA
Hard
Macro
TXDP/N Pins
TX Data
MUX
TX Clock Domain
Phase
Matching
FIFO
PIPE_PCLKIN
8b/10b
Txdata0
PCLK Clock Domain
Figure 2-8 • Transmit Clock and Transmit Datapath
The reference clock (RefClk) is the per-lane PCIe reference clock, which is generally the PCIe 100 MHz
reference clock. During multiple lane implementations, the clock is sent to each PMA single lane macro
and skew between lanes is finely controlled. Effectively, each PMA macro generates a transmit clock TX
clock, from which is generated the pipe clock (generated by one lane) used by the PCIe controller and
also used by the PCS logic in all lanes.
•
CLK MUX Block: is a glitchless clock multiplier for sourcing the RefClk or TXClk to the TX Clock
Domain of the PCS sublayer. This MUX is used for operation at power-up and during speed
changes.
•
CLK Divider Module: is used to generate the PIPE clock (PCLK) for the PCIe controller. The
PIPE_PCLKOUT signal is the output signal of the PCS and is generated on a per-lane basis.
•
Phase Matching FIFO: is used to recapture the transmitted data generated on the PCLK clock
domain back to the aTXClk domain, considering the two clocks are fully independent
(asynchronous). The TX data MUX performs multiplexing between data coming from the PCIe
PCS and the external PCS.
•
8b/10b Encoder: is used to implement an 8-bit to 10-bit encoder that encodes 8-bit data or
control characters in to 10-bit symbols.
Revision 5
37
PCI Express
Receiver Block
The Receiver block consists of receive capture logic, word alignment logic, elastic buffer, and an 8b/10b
decoder, as shown in Figure 2-9.
aRxClkp
CLK
Down
CLK
Divider
Single
Lane PMA
Hard
Macro
RXDP
Elastic
Buffer
aRXDo[19:0]
RXDN
To
PCIe
System
RXCLK
Capture
Register
Word
Aligner
CDR Clock Domain
8b/10b
PCLK Clock Domain
Figure 2-9 • Receive Clock and Receive Datapath
38
•
CLK down block shuts down the receive clock when it is not stable and glitch-free.
•
CLK divider function on the RX path is very similar to the one on the transmit side.
•
Capture Register is clocked directly by RXCLK (output of clock divider) rising edge which is a
“divide by” and delayed version of the RX clock from the PMA block.
•
Elastic buffers (also known as elasticity buffers, synchronization buffers, and elastic stores) are
used to ensure data integrity when bridging two different clock domains using the PCIe SKP
symbol for rate monitoring. Each receiver lane incorporates a decoder, which is fed from the
elastic buffer.
•
8b/10b Decoder uses two lookup tables (LUT) (the D and K tables) to decode the 10-bit symbol
stream into 8-bit Data (D) or Control (K) characters plus the D/K# signal.
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIe System
The PCIe system sub-block inside the SERDESIF block implements the PCIe physical layer, data link
layer, and transaction layer of the PCIe specification. It interfaces with the SERDES block on one side
and the FPGA fabric on the other side. Figure 2-10 shows the SmartFusion2 or IGLOO2 SERDESIF
block in PCIE mode, and also shows various sub-blocks for the PCIe system block. The main sub-blocks
for PCIe system include:
•
PCIe IP Block with AXI3 Interface
•
AXI to AXI3/AHBL Bridge
•
AHBL Master Interface
•
Glue Logic Blocks
SERDESIF
Fabric
PCIe System
CORE_RESET_N
PHY
Ref CLK
MUX
RESET
CONTROLLER
PHY_RESET_N
AXI3 - Master
Interface
PCIe IP with
AXI Interface
AXI3 - Slave
Interface
SERDES
(PMA + PCS)
x4 PIPE Interface
16-bit
Pad Signals
phy_clk
PCIe Bridge
Registers
AXI3/AHBL Bridge
AHBL/AXI3 Bridge
AXI3 - Slave
AHBL - Slave
Interface
AXI3 - Master
AHBL - Master
Interface
L2/P2 Control Logic
Lane-to-Lane
Calibration Logic
SERDESIF
System Registers
APB Interface
APB
Decoder
APB Interface
Figure 2-10 • Detailed PCIe System Block Diagram
PCIe IP Block with AXI3 Interface
The PCIe IP block is a integrated block in the SmartFusion2 or IGLOO2 FPGA which implements a x1,
x2, or x4 PCIe interface. On the application side, it has one master interface and one slave interface. The
master interface can be a 64-bit AXI3 master or a 32-bit AHBL master. The slave interface can be a 64bit AXI3 slave or a 32-bit AHBL slave interface. The PCIe link initiates transactions to the SmartFusion2
or IGLOO2 fabric through the AXI3 master or AHBL master. IGLOO2 fabric initiates transactions towards
the PCIe link through the AXI3 slave or the AHBL slave interface. There is an APB interface that has
access to the SERDESIF system registers.
Revision 5
39
PCI Express
Figure 2-11 shows the architecture of the PCIe IP block.
PCIe to AXI Window0
PCIe to AXI Window1
AXI Master
AXI
PCIe to AXI Window3
PCIe to AXI Window3
Controls
PCIe Base
IP core
SERDES
x4 Link
IRQ
AXI to PCIe Window0
AXI to PCIe Window1
AXI to PCIe Window2
AXI Slave
AXI
AXI to PCIe Window3
PCIe Bridge Registers
APB Slave
APB
Figure 2-11 • PCIe Hard Block Diagram
The main components for the PCIe IP sub-block include the following:
•
PCIe Base IP Core
•
PCIe to AXI Window
•
AXI3 Master Block
•
AXI3 to PCIe Window
•
AXI3 Slave Block
•
PCIe Core Bridge Register
•
APB Slave Interface
PCIe Base IP Core
The PCIe base IP core implements an x4 PCIe EP link, compliant to PCIe Rev. 2.0. The following
sections describe the features of the SmartFusion2 or IGLOO2 PCIe IP.
General
•
x1, x2, x4 PCIe core
•
Supports link rate of 2.5 and 5.0 Gbps per lane
•
Endpoint Topology
•
PCIe Base Specification Revision 2.0 and Revision 1.1 compliant
•
Single-function/Single virtual channel (VC)
•
AXI3 64-bit or AHB-Lite 32-bit Master and Slave Interfaces
•
Advanced error reporting (AER) support
•
End-to-end cyclic redundancy check (ECRC) generation, check, and forward support
Data Transfer
40
•
Supports all base memory, configuration, and message transactions
•
Implements type 0 configuration space for EP (refer to "Appendix A: PCIe Configuration Space"
on page 92)
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Configuration
•
Supports three 64-bit BARs or six 32-bit BARs
Power Management and Interrupts
•
Native active state power management L0s, L1, and L2 state support
•
Power management event (PME message)
The PCIe base IP core implements the transaction layer and data link layer described by the PCIe base
specifications.
•
Transaction layer: The transaction layer (TL) contains the configuration space, which manages
communication with the user application layer: the receive and transmit channels, the receive
buffer, and flow control (FC) credits.
•
Data link layer: The data link layer (DLL) is responsible for link management, including transaction
layer packet (TLP) acknowledgment, a retry mechanism in case of a non-acknowledged packet,
flow control across the link (transmission and reception), power management, CRC generation
and CRC checking, error reporting, and logging.
Toward SERDES
RX
Clock Domain Crossing
TX
Toward Application Layer
The Data Link Layer
ensures packet
integrity, and adds
a sequence number
and Link Cyclic
Redundancy Check
(LCRC) to the
packet.
The Transaction Layer
generates a TLP
from information
sent by the
Application Layer.
This TLP includes
a header and can
also include a
data payload.
The Data Link Layer
verifies the packet’s
sequence number
and checks for errors.
The Transaction Layer
disassembles the
transaction and
transfers data to
the Application Layer
in a form that it
recognizes.
Data Link Layer
Transaction Layer
Figure 2-12 • PCIe Transaction Layer and Data Link Layer
The PCIe IP core also utilizes a clock domain crossing (CDC) synchronizer between the DLL and the
physical layer that enables the data link and transaction layers to operate at a frequency independent
from that of the physical layer.
PCIe to AXI Window
The PCIe base IP receives both 32-bit address and 64-bit address PCIe requests, but only 32-bit
address bits are provided to the AXI3 master. The PCIe to AXI3 address windows manage read and write
requests from the PCIe link and are used to translate a PCIe 32-bit or 64-bit base address to a 32-bit
AXI3 base address transaction.
AXI3 Master Block
The AXI3 master only supports memory read and write transactions.
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AXI Master Write Transaction Handling
•
The write transaction is handled in big-endian order, as required by the "PCI Express" section on
page 28.
•
PCIe transactions can be any size up to the configurable maximum payload size (256 bytes).
•
AXI3 transactions are limited to 128 bytes, a received TLP is divided into several AXI3
transactions.
•
AXI3 master receives a write transaction, it processes the transaction as 128-byte segments
(aligned on a 128-byte address boundary) until the segments in the transaction have been
processed.
•
TLP is de-constructed and sent to the AXI3/AHB interface and the data is presented as little
endian.
AXI Master Read Transaction Handling
•
Read transactions are handled the same way as write transactions, except that before
transferring the transaction to the AXI3 master read channel, the PCIe IP checks the transmit
buffer for available space.
•
PCIe IP does not transfer the read transaction. If there is not sufficient space in the transmit
replay buffer to store PCIe completions.
•
The number of outstanding AXI3 master read transactions is therefore limited by the size of the
Tx buffer.
•
The AXI3 master read channel can receive transactions in any order, and data can be completely
interleaved. However, the PCIe IP generates completions in the order they are initiated on the
link.
AXI3 to PCIe Window
The AXI3 to PCIe address windows are used to translate a 32-bit AXI3 base address for a transaction to
a PCIe 32-bit or 64-bit base address to generate a PCIe TLP.
AXI3 Slave Block
The AXI3 slave interface forwards AXI3 read and write requests from the FPGA fabric to the PCIe link.
AXI Slave Write Transaction Handling
•
Minimum 128 bytes must be available for write transaction.
•
Data interleaving is not supported.
•
Wait states are used if buffer is full or has less than 128 Bytes of available space.
•
Write responses are generated as soon as the last data phase is over.
•
Maximum of 128 Byte data packet can be created.
•
Only four outstanding write transactions are supported.
•
Incrementing-address burst is supported.
AXI Slave Read Transaction Handling
42
•
Minimum 128 bytes must be available for read transaction.
•
PCIe IP generates a PCIe tag, arbitrates between write requests and completions, then checks
for available FC credits.
•
Response is generated if a timeout occurs or if a completion with error status is received.
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Outstanding Requests
The AXI3 interface supports the following number of outstanding requests as listed in Table 2-3.
Table 2-3 • AXI3 and Outstanding Transactions
AXI3 Transaction
Outstanding Transactions
Master Write
Limited by Tx Credits
Master Read
4
Slave Write
Limited by Rx Credits
Slave Read
4
AXI3 Transaction and TLP Ordering Rules
This section describes the TLP ordering rules for sending and receiving TLPs.
AXI3 Slave Interface
The slave path does not reorder transactions, but does arbitrate between transactions when they occur
simultaneously. The order of priority for arbitrations is master read completions, slave write requests,
then slave read requests.
AXI3 Master Interface
The master path does not reorder transactions, but does arbitrate between transactions at the AXI3
master interface. If a transaction is currently waiting for a response phase, the transaction is allowed to
complete before the read transaction is forwarded to the AXI3 master interface.
PCIe Core Bridge Register
The PCIe core bridge registers occupy 4 KB of the configuration memory map. These registers set the
PCIe configuration and status. These registers are initialized from flash and through the HPMS while
configuring the high speed serial interface generator in the Libero SoC. These registers can also be
accessed through the 32-bit APB interface. The physical offset location of the PCIe core registers is
0x0000-0x0FFF from the SERDESIF system memory map. Refer to the "PCI Express" chapter on
page 28 for more information on the PCIe core register.
APB Slave Interface
The APB slave interface provide APB interface to SERDESIF System registers. Refer to the "Bridge
Register Space" section on page 61 for details.
AXI to AXI3/AHBL Bridge
The PCIe user interface can support either an AXI3 master/a slave interface, or an AHBL master/a slave
interface. Table 2-4 on page 45 and Table 2-5 on page 46 list the fabric interface pins. The AXI3 interface
uses a 64-bit data bus while the AHBL interface uses a 32-bit data bus. In the PCIe core, the native
interface to the controller is AXI3. If the user selects the AHBL interface, a bridge is available between
the PCIe controller and user interface. This bridge is completely transparent to the user and the following
sections describe the special conditions.
AHBL Master Interface
The AHBL master interface is used for processing TLPs coming into the PCIe controller towards the
FPGA fabric. Memory Read TLPs received by the PCIe controller are constructed as AHBL read
transactions. Memory Write TLPs received are constructed as AHBL write transactions. The AHBL
master supports both Single and Burst type transactions. For Burst transactions, the AHBL uses either
the INCR or WRAP burst type.
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Following are three special conditions for Single transactions:
•
If an 8-bit, 16-bit, 32-bit, or 64-bit read transaction is received on the PCIe link, the AHBL master
initiates two 32-bit read transactions using an increasing 32-bit address. It is done as the internal
AXI3 bus is 64-bits and a read on this interfaces always 64-bit wide requiring the AHBL to issue
two AHBL transactions to satisfy the AXI3 transaction.
•
If a 64-bit or 32-bit read or write transaction is received on the PCIe link, the transaction is broken
up to two AHBL master transactions.
•
If a 64-bit or 32-bit write transfer is received on the PCIe link with some of the byte lanes are not
enabled, the AHBL master breaks the transaction up in to byte and/or halfword transactions with
the proper address offsets to only write data for those bytes that are needed.
AHBL Slave Interface
The AHBL slave interface is used for sending the transactions via TLPs over the PCIe link. The AHBL
write transactions create Memory Write TLPs. The AHBL read transactions create Memory Read TLPs.
A Completion TLP from the PCIe link contains the read data for an AHBL read transaction. The AHBL
interface is limited to one outstanding transaction. It requires the AHBL transaction to stall until the
Completion TLP is received to terminate the transaction with read data. The AHBL slave interface
supports all BURST types. The notable special case for burst type of INCR (001) is that the burst is
broken up into single DW PCIe TLPs on the PCIe link. The PCIe core supports a 64-bit AXI3 transaction.
Figure 2-13 shows the block diagram of AXI3-AHB top bridge.
AXI-AHB
AXI-AXI
AXI64 - Master
AHB32 - Master
Interface
PCIe
AXI64
Master
Interface
AXI64 - Slave
Interface
AXI-AHB-TOP
AXI64 - Slave
AHB32 - Slave
Interface Fabric
Figure 2-13 • AXI3-to-AXI3/AHBL Bridge Block Diagram
Glue Logic Blocks
The PCIe system block has several small logic blocks for PCIe subsystem functionality.
•
PCIe/PHY reset controller: This block controls the assertion and deassertion of reset to the PCIe
core, SERDES macro, and other glue-logic.
•
L2/P2 control logic: This block controls logic to implement the L2/P2 state.
Fabric Interface for PCIe System
The SmartFusion2 and IGLOO2 PCIe system block interfaces with the FPGA fabric on one side and the
SERDES block on the other side. Following are the PCIe system block interface signals to the FPGA
fabric:
44
•
PCIe System AXI3/AHBL Master Interface
•
PCIe System AXI3/AHBL Slave Interface
•
PCIe System APB Slave Interface
•
PCIe System Clock Signals
•
PCIe System Reset Signals
•
PCIe Interrupt and Power Management Interface
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Table 2-4 • PCIe System AXI3/AHBL Master Interface
Port
Type
Description
AXI_M_AWID[3:0]
Output
AXI3 master mode: AWID (not supported)
AXI_M_AWADDR[31:0]
Output
AXI3 master mode: AWADDR AHBL master mode: HADDR
AXI_M_AWLEN[3:0]
Output
AXI3 master mode: AWLEN AHBL master mode: HBURST
AXI_M_AWSIZE[1:0]
Output
AXI3 master mode: AWSIZE AHBL master mode: HSIZE
AXI_M_AWBURST[1:0]
Output
AXI3 master mode: AWBURST AHBL master mode: HTRANS
AXI_M_AWVALID
Output
AXI3 master mode: AWVALID AHBL master mode: HWRITE
AXI_M_AWREADY
Input
AXI3 master mode: AWREADY
AXI_M_WID[3:0]
Output
AXI3 master mode: WID (not supported)
AXI_M_WSTRB[7:0]
Output
AXI3 master mode: WSTRB
AXI_M_WLAST
Output
AXI3 master mode: WLAST
AXI_M_WVALID
Output
AXI3 master mode: WVALID
AXI_M_WDATA[63:0]
Output
AXI3 master mode: WDATA AHBL master mode: HWDATA
AXI_M_WREADY
Input
AXI3 master mode: WREADY AHBL master mode: HREADY
AXI_M_BID[3:0]
Input
AXI3 master mode: BID
AXI_M_BRESP[1:0]
Input
AXI3 master mode: BRESP AHBL master mode: HRESP. In response to a
write the value is ignored.
AXI_M_BVALID
Input
AXI3 master mode: BVALID
AXI_M_BREADY
Output
AXI3 master mode: BREADY
AXI_M_ARID[3:0]
Output
AXI3 master mode: ARID. Used to indicate the ID of the current outstanding
read completion. Read completions can be interleaved.
AXI_M_ARADDR[31:0]
Output
AXI3 master mode: ARADDR
AXI_M_ARLEN[3:0]
Output
AXI3 master mode: ARLEN
AXI_M_ARSIZE[1:0]
Output
AXI3 master mode: ARSIZE (Tied to 11)
AXI_M_ARBURST[1:0]
Output
AXI3 master mode: ARBURST
AXI_M_ARVALID
Output
AXI3 master mode: ARVALID
AXI_M_ARREADY
Input
AXI3 master mode: ARREADY
AXI_M_RID[3:0]
Input
AXI3 master mode: RID. Used to indicate the ID of the current outstanding
read completion. Read completions can be interleaved.
AXI_M_RDATA[63:0]
Input
AXI3 master mode: RDATA AHBL master mode: HRDATA
AXI_M_RRESP[1:0]
Input
AXI3 master mode: RRESP. In response to a read request, a SLVERR
(0b10) or DECERR (0b11) response causes the PCIe core to issue an
Unsupported Request back to the initiator.
AXI_M_RLAST
Input
AXI3 master mode: RLAST
AXI_M_RVALID
Input
AXI3 master mode: RVALID
AXI_M_RREADY
Output
AXI3 master mode: RREADY
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Table 2-4 • PCIe System AXI3/AHBL Master Interface (continued)
Port
Type
Description
Note:
1. AXI_M_awsize[2:0] is hardwired to ‘011’, that is, fixed at 8 bytes = 64 bit only. Same applies to AXI_M_arsize[2:0].
2. Refer to AMBA AXI3 specifications for further details.
Table 2-5 • PCIe System AXI3/AHBL Slave Interface
Port
Type
Description
AXI_S_AWID[3:0]
INPUT
AXI3 slave mode: AWID (not supported)
AXI_S_AWADDR[31:0]
INPUT
AXI3 slave mode: AWADDR
AXI_S_AWLEN[3:0]
INPUT
AXI3 slave mode: AWLEN
AXI_S_AWSIZE[1:0]
INPUT
AXI3 slave mode: AWSIZE
AXI_S_AWBURST[1:0]
INPUT
AXI3 slave mode: AWBURST
AXI_S_AWVALID
INPUT
AXI3 slave mode: AWVALID
AXI_S_AWREADY
OUTPUT AXI3 slave mode: AWREADY
AXI_S_AWLOCK[1:0]
INPUT
AXI3 slave mode: AWLOCK
AXI_S_WID[3:0]
INPUT
AXI3 slave mode: WID (not supported)
AXI_S_WSTRB[7:0]
INPUT
AXI3 slave mode: WSTRB
AXI_S_WLAST
INPUT
AXI3 slave mode: WLAST
AXI_S_WVALID
INPUT
AXI3 slave mode: WVALID
AXI_S_WDATA [63:0]
INPUT
AXI3 slave mode: WDATA
AXI_S_WREADY
OUTPUT AXI3 slave mode: WREADY
AXI_S_BID[3:0]
OUTPUT AXI3 slave mode: BID
AXI_S_BRESP[1:0]
OUTPUT AXI3 slave mode: BRESP
AXI_S_BVALID
OUTPUT AXI3 slave mode: BVALID
AXI_S_BREADY
INPUT
AXI3 slave mode: BREADY
AXI_S_ARID[3:0]
INPUT
AXI3 slave mode: ARID
AXI_S_ARADDR[31:0]
INPUT
AXI3 slave mode: ARADDR
AXI_S_ARLEN[3:0]
INPUT
AXI3 slave mode: ARLEN. PCIe AXI-Slave interface supports only single
length transactions (S_ARLEN = 3’b000) when the size of the transfer is less
than 64 bits.
AXI_S_ARSIZE[1:0]
INPUT
AXI3 slave mode: ARSIZE. A size value of 0b11 allows all values of burst
length. A size value of 0b00, 0b01, and 0b10 allows only a burst length of 1.
AXI_S_ARBURST[1:0]
INPUT
AXI3 slave mode: ARBURST
AXI_S_ARVALID
INPUT
AXI3 slave mode: ARVALID
AXI_S_ARLOCK[1:0]
INPUT
AXI3 slave mode: ARLOCK
AXI_S_ARREADY
OUTPUT AXI3 slave mode: ARREADY
AXI_S_RID[3:0]
OUTPUT AXI3 slave mode: RID
AXI_S_RDATA[63:0]
OUTPUT AXI3 slave mode: RDATA
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Table 2-5 • PCIe System AXI3/AHBL Slave Interface (continued)
Port
AXI_S_RRESP[1:0]
Type
Description
OUTPUT AXI3 slave mode: RRESP. The interface responds with a SLVERR under the
following conditions:
•
If a completion TLP has the EP (poisoned) bit set.
•
If a completion with error TLP is received.
•
If a completion timeout event happens.
•
If an invalid AXI3 slave transaction is encountered such as invalid
burst type.
AXI_S_RLAST
OUTPUT AXI3 slave mode: RLAST
AXI_S_RVALID
OUTPUT AXI3 slave mode: RVALID
AXI_S_RREADY
INPUT
AXI3 slave mode: RREADY
Note: Refer to AMBA AXI3 specifications for further details
Table 2-6 • PCIe System APB Slave Interface
Port
Type
Description
APB_S_PSEL
Input
APB slave select; select signal for register for reads or writes.
APB_S_PENABLE
Input
APB strobe. This signal indicates the second cycle of an APB transfer.
APB_S_PWRITE
Input
APB write or read. If High, a write occurs when an APB transfer takes place. If low,
a read takes place.
APB_S_PADDR[13:0]
Input
APB address bus.
APB_S_PWDATA[31:0]
Input
APB write data.
APB_S_PREADY
Output APB ready. Used to insert wait states.
APB_S_PRDATA[31:0]
Output APB read data.
APB_S_PSLVERR
Output APB Error.
Table 2-7 • PCIe System Clock Signals
Port
Type
Description
CLK_BASE
Input
Fabric source clock. This clock input is used for the Master and Slave interfaces.
It is also used as the reference clock to the SPLL which is used to achieve
interface timing across the fabric to SERDES block.
Note: The frequency of this clock must match the GUI option for the CLK. BASE
rate to guarantee timing is met across the fabric interface.
APB_S_CLK
Input
PCLK for APB slave interface in SERDES Block
SPLL_LOCK
Output PLL Lock signal. High indicates that the frequency and phase lock are achieved.
PLL_LOCK_INT
Output The SPLL Lock status register (Active High indicates locked).
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Table 2-7 • PCIe System Clock Signals
PLL_LOCKLOST_INT
Output The SPLL Lock lost status register (Active high indicates that the lock is lost).
Table 2-8 • PCIe System Reset Signals
Ports
Type
Description
CORE_RESET_N
Input
PCIe core active low reset. Top-level fundamental asynchronous RESET to the
PCIe system. It affects only those SERDES lanes which are in PCIe mode.
Lanes associated with the PCIe link must have one reset for all lanes.
PHY_RESET_N
Input
Active low – SERDES – reset. Top-level fundamental asynchronous RESET to
the SERDES block.
APB_S_PRESET_N
Input
APB slave interface – PRESETN: Async set. APB asynchronous reset to all APB
registers.
Note: More information about these resets is provided in Table 2-14 on page 63.
PCIE_WAKE_N, PCIE_WAKE_REQ, and PCIE_PERST_N ports are added optionally with L2/P2
selection. PCIE_WAKE_N is an output and PCIE_WAKE_REQ, and PCIE_PERST_N ports are inputs to
the PCIE core.
Table 2-9 • PCIe Interrupt and Power Management Interface
Port
Type
Description
PCIE_INTERRUPT[3:0]
Input
PCIe system interrupt inputs. When using INTx legacy interrupts
PCIE_INTERRUPT[0] is used to assert/deassert INTA. When using MSI
interrupts up to 4 MSI interrupts can be sent. Each bit sends an MSI vector with
bit 0 starting at the MSI base and each bit increments the vector. Asynchronous.
Synchronized internally to each lane’s PIPE clock.
PCIE_SYSTEM_INT
PCIE_WAKE_REQ
Output PCIe system interrupt output (not supported)
Input
L2/P2 implementation: (L2 requests from fabric)*
Asynchronous. Input to power-management state machine.
PCIE_WAKE_N
PCIE_PERST_N
Output L2/P2 implementation: (L2 exit request to RP)*
Input
L2/P2 implementation: (L2 exit request from RP)*
Asynchronous. Synchronized to the internal 50 MHz RC Oscillator.
PCIE_LTSSM[5:0]
Output Ports indicate the status of ltssm state management. Equivalent to LTSSM
Register (044h) [28:24]. These bits set to LTSSM state encoding (RO)- output
bits [4:0] ltssm state. Bit[5] Pulses high to indicate that a hot-reset, data link up or
L2 exit condition has occurred. Synchronized to the PIPE clock.
PCIE_L2P2_ACTIVE
Output Active high output indicating the LTSSM is in low-power state.
PCIE_RESET_PHASE
Output Active high output indicating the LTSSM is in reset state.
Note: *: This in only available when L2/P2 option is selected in SERDESIF Configurator GUI.
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Functional Description
This section covers the functional aspects of the reset and clock circuitry inside the SERDESIF block for
PCIe. It includes the following sub-sections:
•
PCIe Clocking Architecture
•
PCIe Reset Network
PCIe Clocking Architecture
The SmartFusion2 and IGLOO2 SERDESIF, when configured in PCIe mode, uses multiple clocks inside
the SERDESIF block. This sub-section describes the PCIe clocking architecture inside SERDESIF in
PCIe mode. Figure 2-14 on page 50 shows the PCIe clocking architecture in the SmartFusion2 or
IGLOO2 device. The two main clock inputs are a differential SERDES reference clock (100 MHz) for
SERDES physical media attachment (PMA), and a CLK_BASE input for SERDESIF from the FPGA
fabric. In addition, there is a APB clock input for SERDESIF from the FPGA fabric.
SERDES reference clock: The differential 100MHz reference clock is used by SERDES (TX PLL and
CDR PLL) to generate 250 MHz or 125 MHz clock (depending on lane speed settings) and passed to
PCIe System IP block. The setting for TX PLL and CDR PLL are calculated automatically by the Libero
software. This 250 MHz or 125 MHz clock output from SERDES is used by PCIe system. There are
several options for providing this SERDES reference clock. Refer to the "SERDES Reference Clocks"
section in the "Serializer/De-serializer" chapter on page 154 for details.
The PCIe standard specifies a 100 MHz clock (Refclk) with greater than ±300 ppm frequency stability at
both the transmitting and receiving devices. SmartFusion2 and IGLOO2 support two distinct clocking
topologies: Common Refclk and Separate Refclk.
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Common Refclk is the most widely supported clocking method in open systems where the root provides
a clock to the end point. An advantage of this clocking architecture is that it supports spread spectrum
clocking (SSC) which can be very useful in reducing electromagnetic interference (EMI). SmartFusion2
and IGLOO2 support SSC clocking in common clock systems.
Separate Refclk uses two independent clock sources. One clock for the root and another clock source for
the endpoint. The clock sources still must be ±300 ppm frequency accuracy and cannot use any SSC.
TXDP
TXDN
Gen1 2.5 GHz / 5 GHz
RXDP
RXDN
Gen1 2.5 GHz / 5 GHz
Fabric
SERDESIF
TX
PLL
CDR
PLL
SERDES Reference
Clock (100 MHz)
500 MHz
RxCLK-x4clks
500 MHz
TxClk-x4clks
PCIe PCS
Div 2/4
APB_S_PCLK
250/125 MHz
TxClk-x4clks
CLK_BASE
PCIe
System
4 to 1
MUX
250/125 MHz TxClk
Deskew
PLL_SERDESIF_REF
SPLL
PCIE_AXI_AHB_CLK
Deskew
PLL_SERDESIF_FB
PLL_ACLK
Figure 2-14 • Various Clocks in PCIe Mode
The clocking architecture also uses SPLL to synchronize data between CLK_BASE and the clock
generated from SERDES (250 MHz or 125 MHz clocks). The SPLL allows the reduction of the skew
between the fabric and the SmartFusion2 or IGLOO2 SERDESIF module. Table 2-10 on page 51
summarizes the SERDESIF clock signal in PCIe mode.
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SERDES Reference Clocks Selection
The PLLs in the SERDES block generate the 250/125 MHz clock for the PCIe system. REFCLK0, or
REFCLK1, as the reference clock depending on Protocol mode (single or multiple protocol). Lane0 and
lane1 share the same reference clock and lane2 and lane3 share the same reference clock. The
reference clock pads are differential input. In Single-protocol mode, the same reference clock can be
selected for all four lanes. SERDES_x_REFCLK0P
SERDES_x_REFCLK0N
REF_CLK0
SERDES_x_REFCLK1P
SERDES_x_REFCLK1N
REF_CLK1
0
1
aREFCLK[1:0]
2
FAB_REF_CLK*
SERDES
0
LANE01_REFCLK_SEL[1:0]
1
aREFCLK[3:2]
2
LANE23_REFCLK_SEL[1:0]
Note: ‘*’ - FAB_REF_CLK not available with PCIe Mode
Figure 2-15 • SERDES Reference Clock for PCIe Mode
The reference clock needs to be compliant with the PCIe protocol. Refer to the DS0451: IGLOO2 and
SmartFusion2 Datasheet for the specification. Microsemi recommends using REFCLK0 or REFCLK1 for
PCIe mode.
Table 2-10 • Reference Clock Signals for SERDES
Clock Signal
Description
REFCLK0
Reference clock output of SERDES_x_REFCLK0P and SERDES_x_REFCLK0N
REFCLK1
Reference clock output of SERDES_x_REFCLK1P and SERDES_x_REFCLK1N
Figure 2-16 shows the reference clock selection in the high speed serial interface generator that is
available in Libero. Libero sets the multiplexer (MUX) selection depending on the reference clocks
selected.
Figure 2-16 • SERDES Reference Clock Using the High Speed Serial Interface Generator
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PCIe Reset Network
SERDESIF, when configured in PCIe mode, has different reset inputs. Figure 2-17 shows a simplified
view of the reset signal in SERDESIF block in PCIe mode. Table 2-14 on page 63 shows the reset
signals and recommended connection.
Fabric
CORE_RESET_N
SERDESIF
PHY CLK
PCIe/PHY
Reset
Controller
Sync
SERDES
PHY_RESET_N
Sync
PCIe IP Block
APB_S_PCLK
APB_S_PRESET_N
Sync
Figure 2-17 • Reset Signals in PCIe Mode
Microsemi recommends using System Builder module and the embedded CoreResetP to control
CORE_RESET_N and PHY_RESET_N. The System Builder module uses the recommended sequences
for the various reset signals. APB_S_PRESET_N signal can be controlled from the FIC_2 interface of the
HPMS or user logic, as shown in Figure 2-18.
System Builder Module
SERDESIF
PHY_RESET_N
CoreResetP
CORE_RESET_N
APB_S_PRESET_N
(from FIC_2 or user logic)
Figure 2-18 • Reset Signals in PCIe Mode
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Designing with PCIe
This section provides instruction for using the SmartFusion2 or IGLOO2 PCIe EP implementation user
design. It includes the following sub-sections:
•
Base Address Register Settings
•
Address Translation on AXI3 Master Interface
•
AXI3 Slave Interface Address Translation
•
PCIe System Credit Settings
•
Setting up Lane Reversal
•
PCIe Power Management
Base Address Register Settings
The PCIe implementation supports up to six 32-bit BARs or three 64-bit BARs. The BARs can be one of
two sizes:
•
32-bit BAR: The address space can be as small as 16 bytes or as large as 2 gigabytes.
•
64-bit BAR: The address space can be as small as 128 bytes or as large as 8 gigabytes. Used
for memory only.
Each BAR register is 32 bits, but BARs can be combined to make a 64-bit BAR. For example, BAR0
(address offset 010h) and BAR1 (address offset 014h) define the type and size of BAR01 of the PCIe
native endpoint. BAR01 can be memory-mapped prefetchable (64-bit BAR) or non-prefetchable (32-bit
BAR).
The SERDESIF Configurator in Libero provides a GUI to configure the BAR settings for the EP
application. Refer to Figure 2-19 on page 54 for details. The BAR registers share the options below:
•
Width: Width can be 32-bit or 64-bit. If an even register is selected to be 64-bit wide, then the
subsequent (odd) register serves as the upper half of 64 bits. Otherwise, the width of odd
registers is restricted to 32-bit.
•
Size: Ranges from 4 Kbytes to 1 Gbyte.
•
Prefetchable: Prefetchable option for memory BAR.
–
A PCI Express Endpoint requesting memory resources through a BAR must set the BAR’s
prefetchable bit unless the range contains locations with read side-effects or locations in
which the device does not tolerate write merging. It is strongly encouraged that memorymapped resources be designed as prefetchable whenever possible. For a PCI Express
Endpoint, 64-bit addressing must be supported for all BARs that have the prefetchable bit set.
32-bit addressing is permitted for all BARs that do not have the prefetchable bit set.
Revision 5
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Figure 2-19 • Configuring Base Address Register
The BAR setting is read by the PCIe bridge register inside the SERDESIF block using the APB interface.
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Address Translation on AXI3 Master Interface
The address space for PCIe is different from the AXI3 address space. To access one address space from
another address space requires an address translation process.
The PCIe IP can receive both 32-bit address and 64-bit address PCIe requests, but only 32-bit address
bits are provided to the AXI3 master. In order to manage address translation, the PCIe IP can implement
up to 4 AXI3 master address windows, which can be mapped to 3 BARs in the main PCIe IP core.
The address mapping registers (AXI_MASTER_WINDOWx[x], where x can be 0, 1, 2, or 3) are shown in
Table 2-11 and are used to set the address mapping.
Table 2-11 • AXI_MASTER_WINDOW Registers
Bit
Number
[31:12]
Name
AXI_MASTER_WINDOWx[0]
[11:0]
[31:12]
Description
Base address AXI3 master window x
Reserved
AXI_MASTER_WINDOWx[1]
Size of AXI3 master window x
[11:1]
Reserved
0
Enable bit of AXI3 master window x
[31:12]
AXI_MASTER_WINDOWx[2]
LSB of base address PCIe window x
[11:6]
Reserved
[5:0]
These bits set the BAR. To select a BAR, set the following
values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
[31:0]
AXI_MASTER_WINDOWx[3]
MSB of base address PCIe window x
Note: x = 0, 1, 2, 3
Each AXI3 master address window implemented can be mapped to a BAR, and several address
windows can be mapped to the same BAR. When transferring PCIe receive requests to the AXI3 Master,
the PCIe IP core automatically removes the decoded BAR base address, then performs a windows
match using the PCIe offset address. If a match is found, the bridge then maps the corresponding AXI3
base address.
For example, in Figure 2-20 on page 56, four BARS are enabled in the bridge; two 64-bit BARS (BAR01
and BAR23), and two 32-bit BARS (BAR4 and BAR5). All AXI3 master windows are utilized: 64-bit
BAR01 is mapped to AXI3 master window 0; 64-bit BAR23 is mapped to AXI3 master window 1; and
AXI3 master window 2 is mapped to the upper 64 bytes of BAR23. AXI3 master window 3 is connected to
BAR4. BAR5 is not mapped to an AXI3 window; its offset is passed directly to the AXI3 master and
translation is not performed.
To configure AXI_MASTER_WINDOW[0], four APB write operations are performed to
AXI_MASTER_WINDOW0[0], AXI_MASTER_WINDOW0[1], AXI_MASTER_WINDOW0[2] and
AXI_MASTER_WINDOW0[3] registers:
•
APB write to AXI_MASTER_WINDOW0[0]: APB PADDR = 100h, APB PWDATA = FFF0 0000
•
APB write to AXI_MASTER_WINDOW0[1]: APB PADDR = 104h, APB PWDATA = FFF0 0001
•
APB write to AXI_MASTER_WINDOW0[2}: APB PADDR = 108h, APB PWDATA = 0000 0001
•
APB write to AXI_MASTER_WINDOW0[3]: APB PADDR = 10Ch, APB PWDATA = 0000 0000
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PCI Express
The example is shown using relative SERDESIF addressing for PADDR.
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Figure 2-20 • 16 PCIe to AXI3 Master Address Translation
If window size is not enabled or if the PCIe offset address is located in a BAR but not in any of the
windows, address translation is not performed. In this case, the PCIe base address is removed to create
the AXI3 address and, for BARs larger than 4 Kbytes, MSBs are ignored.
The address translation needs to be pre-defined in the user design. This is completed using the
SERDESIF configurator GUI.
The PCIe AXI3 master windows are used to translate the PCIe address domain to the local device
address domain. Typically the PCIe AXI3 master windows are used to translate the address of base
address registers.
AXI3 Slave Interface Address Translation
The bridge can configure up to four AXI3 slave address windows to handle address translation on
read/write requests initiated from the FPGA fabric. The AXI3 slave address windows are used to
translate a 32-bit AXI3 base address for a transaction to a PCIe 32-bit or 64-bit base address to generate
a PCIe TLP. The slave address windows can also be used to generate the following PCIe parameters:
•
TC selection: Indicates the PCIe traffic class in the PCIe packet header.
•
RO bit selection: Generates the PCIe TLP using a selectable relaxed ordering bit.
•
No snoop bit selection: Generates the PCIe TLP using a selectable no snoop bit. See Section
2.2.6.5 of the PCIE 2.0 Base specification for option details.
The address mapping registers (AXI_SLAVE_WINDOWx[x], x can be 0, 1, 2, or 3) is used to set the 
address mapping, refer to Table 2-12 on page 57.
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Table 2-12 • AXI_SLAVE_WINDOW Registers
Bit
Number
[31:12]
Name
Description
AXI_SLAVE_WINDOWx[0]
Base address AXI3 slave window x
[11:0]
[31:12]
Reserved
Size of AXI3 slave window x
AXI_SLAVE_WINDOWx[1]
[11:1]
Reserved
0
Enable bit of AXI3 slave window x
[31:12]
LSB of base address PCIe window 0
AXI_SLAVE_WINDOWx[2]
[11:5]
Reserved
[4:2]
AXI3 slave window 0 traffic class (TC)
1
AXI3 Slave window 0 relaxed ordering (RO)
0
AXI3 Slave window 0 no snoop (NS)
[31:0]
AXI_SLAVE_WINDOWx[3]
Note: x = 0, 1, 2, 3
MSB of base address PCIe window x
Figure 2-21 shows address translation when AXI3 slave address window 0 and window 2 target two
different regions of the host memory and the AXI3 slave address window 1 targets a PCIe memorymapped device (enabling peer-to-peer transactions). Window 3 is not used in this example.
PCIe
full address
AXI
full address
Host processor
address space
0x00000000
Local device
address space
0x00000000
Host
memory
Window0
0x40000000
Window1
0x80000000
Window2
Window3
PCIe
memorymapped
PCIe-to-AXI Bridge
0xC0000000
0xFF640000
0xFFFFFFFF
0xFFFFFFFF
Figure 2-21 • AXI3 Slave to PCIe Address Translation
If AXI3 slave windows are not enabled, address translation is not performed and AXI3 slave requests are
transferred to the PCIe IP core with defaults of TC = 0, RO = 0, and NS = 0.
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PCIe System Credit Settings
PCIe system has 2 Kbytes of receive buffer (RAM) and 1 Kbyte of transmit and replay buffer (RAM). The
following sections describe the different features that impact credit processing. All of the credit settings
are set automatically by the Libero software based on the buffer sizes fixed in the SERDESIF.
Maximum Payload Size
The size of TLP is restricted by the capabilities of both link partners. After the link is trained, the root
complex sets the MAX_PAYLOAD_SIZE (maximum payload size register) value in the device control
register. The permitted settings for MAX_PAYLOAD_SIZE are 128 and 256 bytes.
Replay Buffer
The replay buffer, located in the data link layer, stores a copy of a transmitted TLP until the transmitted
packet is acknowledged by the receiving side of the link. Each stored TLP includes the header, an
optional data payload (of which the maximum size is determined by the maximum payload size
parameter), an optional ECRC, the sequence number, and the link cyclic redundancy check (LCRC) field.
Transmit Buffer
The transmit buffer (Tx buffer) stores the read data payload from the AXI3 master as well as the write
data payload from the AXI3 slave.
Receive Buffer
The receive buffer is located in the transaction layer and accepts incoming TLPs from the link and then
sends them to the application layer for processing. The receive buffer stores TLPs based on the type of
transaction, not the TC of a transaction. Types of transactions include posted transactions, non-posted
transactions, and completion transactions. A transaction always has a header but does not necessarily
have data. The receive buffer accounts for this distinction, maintaining separate resources for the header
and data of each type of transaction. To summarize, distinct buffer resources are maintained for each of
the following elements:
•
Posted transactions, header (PH)
•
Posted transactions, data (PD)
•
Non-posted transactions, header (NPH)
•
Non-posted transactions, data (NPD)
•
Completion transactions, header (CPLH)
•
Completion transactions, data (CPLD)
TLPs are stored in the received buffer in 64-bit addressing format, with each AXI3 slave read outstanding
request consuming 16 credits (128 bytes), plus headers and data credits consuming 1 credit each (16
bytes).
User Data Throughput
PCIe uses credits to handle throughput balancing between both ends of the link. At the initial link-up,
both sides of the link share their transmit and receive buffer sizes in terms of credits. As TLPs are sent
across the link, credits are used. As user data is pulled out of the TLPs stored in the receive buffers
credits are released. Information on the current state of the credits is continuously sent across the link
using data link layer packets. All of this happens transparent to the user inside the PCIe core.
The [SmartFusion2/IGLOO2] PCIe core uses an AHB or AXI3 fabric interface for user data. AHB and
AXI3 slave interface will only allow a transaction when 128 byte TLP worth of credits are available to be
sent. Using this method, the PCIe core can back-pressure the fabric interface when credits are not
available to send a TLP.
The flow control works by releasing credits to the sender as data is pulled across to the fabric. If the user
is not pulling the data out fast enough, then the sender will run out of credits. In the worst case situation
where the sender is 100% writing data to the PCIe core only 1325 Mbps will be able to go through. The
credit system holds the sender back from sending more data. Similar for where the sender is 100%
pulling data via a read, only 1325 Mbps comes back. In this case, PCIe core is never throttled back due
to a lack of credits.
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Reverse the situation with the PCIe core as the sender. For 100% write data, the fabric interface is held
up at 1325 Mbps. For 100% read requests the receiver wants to send them back faster than 1325 Mbps,
but the fabric interface will only pull them out at 1325 Mbps. The receiver is blocked by a lack of
completion credits until credits are released.
The transaction size in this situation is more efficient when small (128 byte TLPs). Smaller packet sizes
allow PCIe core to release credits faster compared to large packets. As a packet is pulled across the
fabric interface the credit is released for the sender to send another. If this happens quickly the next
packet can be sent. For large packets it takes longer to release the credit and therefore the next packet is
not sent as quickly.
Setting up Lane Reversal
PCIe system supports lane reversal capabilities and therefore provides flexibility in the design of the
board. It is possible to choose to lay out the board with reversed lane numbers and the PCIe EP
continues to link train successfully and operate normally. The SERDESIF Configurator in Libero allows
configuration of the SERDESIF block in reverse lane PCIe mode, as shown in Figure 2-22. Using lane
reversal allows the PCIE logical lane to be remapped to its respective physical lane. Figure 2-22 shows
that using this reversal assists with routing the PCB and permits a cleaner interface between the PCIE
host and Endpoint. Polarity swapping or inversion capability within a PCIE receive or transmit lane is not
available in SmartFusion2 and IGLOO2.
PCIE Host
PCIE Host
0 1
2 3
0 1
2 3
0 1
2 3
0 1
2 3
After Lane
Reversal
Before Lane
Reversal
0 1
3 2
1 0
3 2
SmartFusion2/IGLOO2
Endpoint
1 0
3 2
2 3
1 0
0 1
2 3
3 2
1 0
SmartFusion2/IGLOO2
Endpoint
PCB Connections
Figure 2-22 • PCIe Protocol Mode Setting in Reverse Lane Mode
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PCI Express
Polarity swapping or inversion capability within a PCIE receive or transmit lane is not available in
SmartFusion2 and IGLOO2.
PCIe Power Management
This section describes the power management scheme in the FPGA PCIe implementation. This has the
following sub-sections:
•
Power Domain Implementation
•
Legacy Power Management
•
PCIe Power Management
Power Domain Implementation
In SmartFusion2 and IGLOO2 devices, the FPGA and PCIe link (including PMA, PCS, and PCIe
controller) are combined in a single chip, so they have separate power supplies. Figure 2-23 shows the
SmartFusion2 and IGLOO2 power rails. Refer to the AC393: SmartFusion2 and IGLOO2 Board Design
Guidelines Application Note for detailed power supply connections.
SERDES_0_VDD
VDD
SERDES_0_L[01:23]_VDDAIO
SERDES_0_PLL_VDDA
SERDES I/O
Pads
SERDES_0_L[01:23]_VDDAPLL
PMA
Macro
Block
PMA
Control
Logic
PCIe PCS
(Lane0)
PMA
Macro
Block
PMA
Control
Logic
PCIe PCS
(Lane1)
TX/CDR
PLL
PCIe System
Fabric
SPLL
Common
Logic
PMA
Macro
Block
PMA
Control
Logic
PCIe PCS
(Lane2)
PMA
Macro
Block
PMA
Control
Logic
PCIe PCS
(Lane3)
Figure 2-23 • IGLOO2 Power Supply to the PCIe Link Implementation
Legacy Power Management
The PCIe bridge register space defines the capabilities of the PCIe bridge in term of legacy power
management (PME support, auxiliary current requirement and so on). The power management control
and status register also contain the current power management state. The PM data and PM scale value
array can define the power consumed in each power state. Refer to the "Bridge Register Space" section
on page 61 for more information.
PCIe Power Management
PCIe active state power management (ASPM) defines link power management states that a PCIe
physical link is permitted to enter in response to software-driven D-state transitions or active state link
power management activities.
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The PCIe protocol defines the following low power link states.
Table 2-13 • PCIe Low Power States
Low Power State
Description
L0s
Autonomous electrical idle: This state reduces power during short intervals of idle. Devices must
transition to L0s independently on each direction of the link.
L1
Directed electrical idle: The L1 state reduces power when the downstream port directs the
upstream ports. This state saves power in two ways:
•
Shutting down the transceiver circuitry and associated PLL
•
Significantly decreasing the number of internal core transitions
L2
In this state, a WAKE# signal is required to reinitialize the Link. However, the Auxiliary power is
still available.
L2/L3 ready
This state prepares the PCIe link for the removal of main power and the reference clock.
PCIe EP implementation supports L0, L1, and a special version of L2.
PCIe Interrupts for Endpoints
The IGLOO2 PCIe EP implementation supports 32 MSI interrupt and INTx interrupts. It cannot support
both at the same time. The user can select which interrupt model to use in the High Speed Serial
Interfaces Configurator. For MSI, the user has a selection of up to 32 MSI vectors. When using MSI, the
first 4 interrupts can be sent using the PCIE_INTERRUPTS[3:0] port of the SERDESIF[0] for MSI0, [1] for
MSI1, etc. To send more than 4 interrupts the user must use the AXI3 Slave interface and send a
memory write transaction to the specific address set by the root complex during interrupt negotiation.
ECRC Handling
The ECRC ensures end-to-end data integrity. The PCIe implementation transmits a TLP with ECRC from
the transmit port of the application layer. When using ECRC forwarding mode, the ECRC check and
generate are done in the application layer. The AER_ECRC_CAPABILITY register in bridge configuration
registers sets the ECRC settings.
Bridge Register Space
The PCIe core bridge register space is used to configure the PCIe core settings at power-up and is
handled by the CoreConfigP as part of the HPMS module. CoreConfig IP module facilitates configuration
of the SERDESIF block in an SmartFusion2 or IGLOO2 device. For more details refer to the UG0448:
IGLOO2 FPGA High Performance Memory Subsystem User Guide. These registers are 32 bits wide and
part of the SERDESIF system register. Refer to the "SERDESIF System Register" section in the
"SERDESIF Register Access Map" chapter on page 177.
The PCIe system block registers consist of:
•
Read-only registers that report control and status registers to the AXI3 side through the APB bus
•
Bridge settings that must be configured at power-up, such as local interrupt mapping to MSI and
test mode
•
Control/status registers that can be used by the AXI3 bus to control bridge behavior during an
operation
Most bridge registers are hardwired to a fixed value.
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PCI Express
These registers are described in the next section according to their function:
•
Information Registers: provide device, system, and bridge identification information.
•
Bridge Configuration Registers: enable configuration of bridge functionality.
•
Power Management Registers: enable configuration of the power management capabilities of the
bridge.
•
Address Mapping Registers: provide address mapping for AXI3 master and slave windows.
These windows are used for address translation.
•
EP Interrupt Registers: used in EP mode to manage interrupts.
•
PCIe Control and Status Registers: read-only registers enable the local processor to check useful
information related to the PCIe interface status. This enables the local processor to detect when
the bridge’s PCIe interface is initialized and to monitor PCI link events.
Register Initialization
The registers contained in the SERDESIF are initialized automatically when the device powers-up using
data stored in non-volatile storage in the device. There are two types of initialization that are used to set
the value in the registers.
Flash Bits
There are several flash bits that are associated with each SERDESIF block. These flash bits contain the
settings for registers that need to be initialized quickly when the device powers up such as PLL and clock
configurations, PCIe configuration space, and resets. The flash bits are set by the Libero configuration
GUI based on the user selections and are statically set at device power-up.
APB
The SERDESIF supports an APB slave interface connected to the fabric interface. When the Libero
System Builder assembles the SERDESIF supporting modules the APB needs to be connected to the
HPMS module's APB master port. After the device powers up the HPMS and supporting modules
initializes the necessary registers in the SERDESIF that use the APB interface.
It is possible that the APB initialization overwrites registers that have been initialized by the flash bits
since the APB is written after the flash bit value has been loaded.
Fixed
These registers are read-only registers and there value is fixed based on the implementation of the
device.
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Information Registers
The registers listed in Table 2-14 provide device, system, and bridge identification information.
Table 2-14 • Information Registers
Address Register
Type
Initialization
Offset
Register Name
Description
PCIE_VID_DEVID
000h
RO
Flash
Identifies the manufacturer of the
device or application. Refer to the PCIe
specification for details.
PCIE_CLASS_CODE_REG
008h
RO
Flash
Identifies the manufacturer of the
device or application. Refer to the PCIe
specification for details.
PCIE_CAPTURED_BUS_DEVICE_NB
03Ch
RO
NA
Reports the bus and device number of
the EP device for each configuration
write TLP received.
SUBSYSTEM_ID
02Ch
RO
Flash
Identifies the manufacturer of the
device or application. Refer to the PCIe
specification for details.
PCIE_INFO
16Ch
RO
NA
Reports the bridge version.
Bridge Configuration Registers
The registers listed in Table 2-15 enable to configure bridge functionality.
Table 2-15 • Bridge Configuration Registers
Byte
Offset
State
Initialization
PCIE_PCIE_CONFIG
204h
RO
Flash
Sets the PCIe configuration.
BAR0
010h
R/W
Flash
Defines the type and size of BAR0 of the PCIe
native endpoint. This register combines with
BAR1 for defining the type and size of BAR01 of
the PCIe native endpoint.
BAR1
014h
R/W
Flash
Defines the type and size of BAR1 of the PCIe
native endpoint. This register combines with
BAR0 for defining the type and size of BAR01 of
the PCIe native endpoint.
BAR2
01 8h
R/W
Flash
Defines the type and size of BAR2 of the PCIe
native endpoint. This register combines with
BAR3 for defining the type and size of BAR23 of
the PCIe native endpoint.
BAR3
01Ch
R/W
Flash
Defines the type and size of BAR3 of the PCIe
native endpoint. This register combines with
BAR2 for defining the type and size of BAR23 of
the PCIe native endpoint.
BAR4
020h
R/W
Flash
Defines the type and size of BAR4 of the PCIe
native endpoint. This register combines with
BAR5 for defining the type and size of BAR45 of
the PCIe native endpoint.
BAR5
024h
R/W
Flash
Defines the type and size of BAR5 of the PCIe
native endpoint. This register combines with
BAR4 for defining the type and size of BAR45 of
the PCIe native endpoint.
Register Name
Revision 5
Description
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PCI Express
Table 2-15 • Bridge Configuration Registers (continued)
Byte
Offset
State
Initialization
Description
PCIE_AER_ECRC_CAPABILITY
050h
R/W
APB
Defines whether the bridge supports AER and
ECRC
generation/check
and
whether
AER/ECRC is implemented. ECRC generation
and check bits can only be set if AER is
implemented.
MAX_PAYLOAD_SIZE
058h
RO
Fixed
Negotiated maximum payload size.
PCIE_CREDIT_ALLOCATION_0
0B0h
RO
Fixed
Provides the initial credit values for posted
transactions.
PCIE_CREDIT_ALLOCATION_1
0B4h
RO
Fixed
Provides the initial credit values for non-posted
transactions.
PCIE_ERROR_COUNTER_0
0A0h
R/W
NA
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
PCIE_ERROR_COUNTER_1
0A4h
R/W
NA
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
PCIE_ERROR_COUNTER_2
0A8h
R/W
NA
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
PCIE_ERROR_COUNTER_3
0ACh
R/W
NA
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
Register Name
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Power Management Registers
The registers listed in Table 2-16 enable to configure the power management capabilities of the bridge.
Table 2-16 • Bridge Power Management Registers
Byte
Offset
State
Description
PCIE_LTSSM
044h
R
Can be used to monitor the core state or to select a specific
test mode on bits [31:16] and to control L2 entry on bits [15:0].
PCIE_POWER_MGT_CAPABILITY
048h
R/W
Enables the local processor to configure power management
capability.
PCIE_PM_DATA_SCALE_0
070h
R/W
PCIE_PM_DATA_SCALE_1
074h
R/W
PCIE_PM_DATA_SCALE_2
078h
R/W
There are four PM data and scale registers that define the PM
data value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
PCIE_PM_DATA_SCALE_3
07Ch
R/W
PCIE_ASPM_L0S_CAPABILITY
060h
R/W
Defines the EP L0s acceptable latency and the number of fast
training sequences (FTS) required by the SERDES to
resynchronize its receiver on incoming data, depending on
clock mode configuration (separated clock or common clock).
The number of FTS required in separated clock mode must be
higher than that required in common clock mode. The bridge
automatically computes the ASPM L0s exit latency based on
these two register values, and on the maximum payload size
of the control register. The selected NFTS field is that
transmitted by the link training and status state machine
(LTSSM) to the opposite component in order to define the
number of FTS that the opposite component must send to be
sure that the device receiver has re-locked onto incoming data.
PCIE_ASPM_L0S_GEN2
260h
R/W
Defines the EP L0s acceptable latency and the number of FTS
required by the SERDES to resynchronize its receiver on
incoming data, depending on clock mode configuration
(separate clock or common clock) at 5.0 Gbps. The number of
FTS required in separated clock mode must be higher than
that required in common clock mode. The bridge automatically
computes the ASPM L0s exit latency based on these two
register values and the maximum payload size of the control
register. The selected NFTS field is that transmitted by the
LTSSM to the opposite component in order to define the
number of FTS that the opposite component must send to be
sure that the device receiver has re-locked onto incoming data.
PCIE_ASPM_L1_CAPABILITY
064h
R/W
Defines the EP L1 acceptable latency and the number of FTS
required. The EP L1 acceptable latency is used to enable or
disable ASPM L1 entry by comparing its value to the maximum
ASPM L1 exit latency of all components in the hierarchy (plus
1 microsecond per switch). If the ASPM L1 acceptable latency
is lower than the maximum ASPM L1 exit latency, ASPM L1
entry is not enabled.
PCIE_TIMEOUT_COMPLETION
068h
R/W
Defines four timeout ranges for the completion timeout
mechanism.
Register Name
Revision 5
65
PCI Express
Address Mapping Registers
The registers listed in Table 2-17 provide the address mapping for AXI3 master and slave windows.
These windows are used for address translation.
Table 2-17 • Address Mapping Registers
Address Offset
Register Type
Description
PCIE_AXI_SLAVE_WINDOW0_0
0C0h
R/W
PCIE_AXI_SLAVE_WINDOW0_1
0C4h
There are four register sets that define the
address mapping for AXI3 slave window 0.
PCIE_AXI_SLAVE_WINDOW0_2
0C8h
PCIE_AXI_SLAVE_WINDOW0_3
0CCh
PCIE_AXI_SLAVE_WINDOW1_0
0D0h
R/W
PCIE_AXI_SLAVE_WINDOW1_1
0D4h
There are four register sets that define the
address mapping for AXI3 slave window 1.
PCIE_AXI_SLAVE_WINDOW1_2
0D8h
PCIE_AXI_SLAVE_WINDOW1_3
0DCh
PCIE_AXI_SLAVE_WINDOW2_0
0E0h
R/W
PCIE_AXI_SLAVE_WINDOW2_1
0E4h
There are four register sets that define the
address mapping for AXI3 slave window 2.
PCIE_AXI_SLAVE_WINDOW2_2
0E8h
PCIE_AXI_SLAVE_WINDOW2_3
0ECh
PCIE_AXI_SLAVE_WINDOW3_0
0F0h
R/W
PCIE_AXI_SLAVE_WINDOW3_1
0F4h
There are four register sets that define the
address mapping for AXI3 slave window 3.
PCIE_AXI_SLAVE_WINDOW3_2
0F8h
PCIE_AXI_SLAVE_WINDOW3_3
0FCh
PCIE_AXI_MASTER_WINDOW0_0
100h
R/W
PCIE_AXI_MASTER_WINDOW0_1
104h
There are four register sets that define the
address mapping for AXI3 master window
0.
PCIE_AXI_MASTER_WINDOW0_2
108h
PCIE_AXI_MASTER_WINDOW0_3
10Ch
PCIE_AXI_MASTER_WINDOW1_0
110h
R/W
PCIE_AXI_MASTER_WINDOW1_1
114h
There are four register sets that define the
address mapping for AXI3 master window
1.
PCIE_AXI_MASTER_WINDOW1_2
118h
PCIE_AXI_MASTER_WINDOW1_3
11Ch
PCIE_AXI_MASTER_WINDOW2_0
120h
R/W
PCIE_AXI_MASTER_WINDOW2_1
124h
There are four register sets that define the
address mapping for AXI3 master window
2.
PCIE_AXI_MASTER_WINDOW2_2
128h
PCIE_AXI_MASTER_WINDOW2_3
12Ch
PCIE_AXI_MASTER_WINDOW3_0
130h
R/W
PCIE_AXI_MASTER_WINDOW3_1
134h
There are four register sets that define the
address mapping for AXI3 master window
3.
PCIE_AXI_MASTER_WINDOW3_2
138h
PCIE_AXI_MASTER_WINDOW3_3
13Ch
Register Name
66
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
EP Interrupt Registers
The PCIe IP core can generate interrupts through the input signal. This signal may be required by a
device in order to interrupt the host processor, call its device drivers, or report application layer-specific
events or errors. The parameter of the bridge defines the number of interrupt bits for this signal.
Table 2-18 • EP Interrupt Registers
Register Name
Address Register
Type
Offset
Description
PCIE_MSI_0
080h
R/W
Defines 8 MSI_MAP0 registers, with up to 32 possible MSI messages.
32 possible MSI messages.
MSI_CTRL_STATUS
040h
R/W
This register sets MSI control and status. All bits are RO except the
number of MSI requested and the multiple message enable fields, which
are R/W. Up to 32 MSI messages can be requested by the device,
although the PCI software can allocate less than the number of MSI
requested. This information can be read by the local processor through
the multiple message enable field of the register.
PCIe Control and Status Registers
The following registers, as shown in Table 2-19, are read-only registers that enable the local processor to
check useful information related to the PCIe interface status, such as when the PCIe interface is
initialized and monitoring of PCI link events. A complete description of these registers can be found in the
PCIe specifications.
Table 2-19 • PCIe Control and Status Registers
Register Name
Address
Offset
Register
Type
CFG_PRMSCR
004h
RO
The command and status register of PCI configuration space.
PCIE_DEVSCR
030h
RO
Reports the current value of the PCIe device control and status register.
It can be monitored by the local processor when relaxed ordering and
no snoop bits are enabled in the system.
PCIE_DEV2SCR
230h
RO
Reports the current value of the PCIe device control and status register.
It can be monitored by the local processor when relaxed ordering and
no snoop bits are enabled in the system. This register is used when link
speed is set to 5.0 Gbps.
PCIE_LINKSCR
034h
RO
Reports the current value of the PCIe link control and status register. It
can be monitored by the local processor when relaxed ordering and no
snoop bits are enabled in the system.
PCIE_LINK2SCR
234h
RO
Reports the current value of the PCIe link control and status register. It
can be monitored by the local processor when relaxed ordering and no
snoop bits are enabled in the system. This register is used when link
speed is set to 5.0 Gbps.
CFG_PRMSCR
04Ch
RO
Reports the current values of the XpressRich2 core’s power
management control status register.
PCIE_SLOTCAP
154h
Reserved
PCIE_SLOTCSR
158h
Reserved
PCIE_ROOTCSR
15Ch
Reserved
Description
Revision 5
67
PCI Express
PCIe Bridge Registers
The following sub-section describes all PCIe bridge registers in detail.
PCIE_VID_DEVID Register (000h)
Table 2-20 • PCIE_VID_DEVID
Bit
Number
Name
Reset Value
Description
[31:16]
Device ID
0x11AA
Identifies the manufacturer of the device or application. The values
are assigned by PCI-SIG. The default value, 11AA, is the Vendor ID
for Microsemi.
[15:0]
Vendor ID
0x1556
The field Identifies the manufacturer of the device or application. The
values are assigned by PCI-SIG. The default value, 1556, is the
Vendor ID for Microsemi.
PCIE_CFG_PRMSCR Register (004h)
Table 2-21 • CFG_PRMSCR
Bit
Number
[31:0]
Name
Class Code
Reset Value
Description
0x00100000 The command and status register of PCI configuration space.
PCIE_CLASS_CODE Register (008h)
Table 2-22 • PCIE_CLASS_CODE_REG
Bit
Number
Name
Reset Value
Description
[31:16]
PCIE_CLASS_CODE
0x0000
Identifies the manufacturer of the device or application. The values
are assigned by PCI-SIG.
[15:0]
RESERVED0
0x0000
Identifies the manufacturer of the device or application. The values
are assigned by PCI-SIG.
BAR0 Register (010h)
Table 2-23 • BAR0
Bit
Number
Name
Reset Value
0x000000
Description
[31:4]
BAR0_31_4
3
BAR0_3
0x1
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR0_2_1
0x10
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR0_0
0x0
Memory space indicator
68
Defines the type and size of BAR0 of the PCIe native endpoint.
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
BAR1 Register (014h)
Table 2-24 • BAR1
Bit
Number
Name
Reset Value
0x000000
Description
[31:4]
BAR1_31_4
Defines the type and size of BAR1 of the PCIe native endpoint.
3
BAR1_3
0x0
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR1_2_1
0x00
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR1_0
0x0
Memory space indicator.
BAR2 Register (018h)
Table 2-25 • BAR2
Bit
Number
Name
Reset Value
Description
0x000000
The register defines the type and size of BAR0 of the PCIe native EP
[31:4]
BAR2_31_4
3
BAR2_3
0x1
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR2_2_1
0x10
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR2_0
0x0
Memory space indicator.
BAR3 Register (01Ch)
Table 2-26 • BAR3
Bit
Number
[31:4]
Name
BAR3_31_4
3
BAR3_3
0x0
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR3_2_1
0x00
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR3_0
0x0
Memory space indicator.
Reset Value
Description
0x000000 The register defines the type and size of BAR1 of the PCIe native EP.
BAR4 Register (020h)
Table 2-27 • BAR4
Bit
Number
Name
Reset Value
Description
0x000000
The register defines the type and size of BAR0 of the PCIe native EP.
[31:4]
BAR4_31_4
3
BAR4_3
0x1
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR4_2_1
0x10
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR4_0
0x0
Memory space indicator.
Revision 5
69
PCI Express
BAR5 Register (024h)
Table 2-28 • BAR5
Bit
Number
Name
Reset Value
Description
0x000000
The register defines the type and size of BAR1 of the PCIe native EP.
[31:4]
BAR5_31_4
3
BAR5_3
0x0
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR5_2_1
0x00
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR5_0
0x0
Memory space indicator.
SUBSYSTEM_ID Register (02Ch)
Table 2-29 • SUBSYSTEM_ID
Bit
Number
Name
Reset Value
Description
[31:16]
SUBSYSTEM_ID
0x11AA
This field further qualifies the manufacturer of the device or
application. This value is typically the same as the Device
ID.
[15:0]
SUBSYSTEM_VENDOR_ID
0x1556
This field further qualifies the manufacturer of the device or
application.
PCIE_DEVSCR Register (030h)
Table 2-30 • PCIE_DEVSCR
Bit
Number
[31:0]
Name
PCIE_DEVSCR
Reset Value
Description
0x00000000 Device control and status: This register reports the current
value of the PCIe device control and status register. It can
be monitored by the local processor when relaxed ordering
and no snoop bits are enabled in the system.
Note: This register is READ_ONLY.
PCIE_LINKSCR Register (034h)
Table 2-31 • PCIE_LINKSCR
Bit
Number
[31:0]
70
Name
PCIE_LINKSCR
Reset Value
Description
0x00000050 This register reports the current value of the PCIe link
control and status register. It can be monitored by the local
processor when relaxed ordering and no snoop bits are
enabled in the system.
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
TC_VC_MAPPING Register (038h)
Table 2-32 • TC_VC_MAPPING
Bit
Number
Name
Reset Value
Description
[31:24]
TC_VC_MAPPING_31_24
0x0
Reserved
[23:21]
TC_VC_MAPPING_23_21
0x0
Mapping for TC7
[20:18]
TC_VC_MAPPING_20_18
0x0
Mapping for TC6
[17:15]
TC_VC_MAPPING_17_15
0x0
Mapping for TC5
[14:12]
TC_VC_MAPPING_14_12
0x0
Mapping for TC4
[11:9]
TC_VC_MAPPING_11_9
0x0
Mapping for TC3
[8:6]
TC_VC_MAPPING_8_6
0x0
Mapping for TC2
[5:3]
TC_VC_MAPPING_5_3
0x0
Mapping for TC1
[2:0]
TC_VC_MAPPING_2_0
0x0
Mapping for TC0 (always 0)
PCIE_CAPTURED_BUS_DEVICE_NB Register (03Ch)
Table 2-33 • PCIE_CAPTURED_BUS_DEVICE_NB
Bit
Number
[31:0]
Name
PCIE_CAPTURED_BUS_DEVICE_NB
Reset
Value
0x0
Description
This register reports the bus and device number of
the EP device for each configuration write TLP
received.
MSI_CTRL_STATUS Register (040h)
Table 2-34 • MSI_CTRL_STATUS
Bit
Number
Name
Reset
Value
Description
[31:24]
MSI_CTRL_STATUS_31_24
0x0
These RO bits are hardwired to 00000000.
23
MSI_CTRL_STATUS_23
0x0
This RO bit is hardwired to 1.
[22:20]
MSI_CTRL_STATUS_22_20
0x0
Multiple message enable. Fabric logic/MSS checks
this RO APB register to see how many MSI interrupt
resources are allocated from the host side.
[19:17]
MSI_CTRL_STATUS_19_17
0x0
Number of MSI requested. Fabric logic/MSS writes
this RW APB register to request the number of MSI
interrupt resources needed from the host.
16
MSI_CTRL_STATUS_16
0x0
MSI is enabled. Fabric logic/MSS checks this RO
APB register to see if host has enabled MSI on the
PCIe bus.
[15:0]
MSI_CTRL_STATUS_15:0
0x0
This bits are hardwired to 0x7805.
Revision 5
71
PCI Express
LTSSM Register (044h)
Table 2-35 • PCIE_LTSSM
Bit
Number
Name
[31:29]
LTSSM_31_29
[28:24]
LTSSM_28_24
Reset
Value
Description
Reserved
0x0
These bits set LTSSM state encoding (RO):
00000: Detect.quiet
00001: Detect.active
00010: Polling.active
00011: Polling.compliance
00100: Polling.configuration
00101: Reserved (ex polling.speed)
00110: Configuration.linkwidth.start
00111: Configuration.linkwidth.accept
01000: Configuration.lanenum.accept
01001: Configuration.lanenum.wait
01010: Configuration.complete
01011: Configuration.idle
01100: Recovery.RcvrLock
01101: Recovery.RcvrCfg
01110: Recovery.idle
01111: L0
10000: Disabled
10001: Loopback.entry
10010: Loopback.active
10011: Loopback.exit
10100: Hot reset
10101: L0s (transmit)
10110: L1.entry
10111: L1.Idle
11000: L2.idle
11001: L2.TransmitWake
11010: Recovery.speed
11011 - 11111: Reserved
[23:20]
LTSSM_23_20
0x0
Reserved
19
LTSSM_19
0x0
Forces compliance pattern (R/W).
18
LTSSM_18
0x0
Fully disables power management (R/W).
17
LTSSM_17
0x0
Sets master loopback (R/W).
16
LTSSM_16
0x0
Disables scrambling (R/W).
[15:2]
LTSSM_15_2
0x0
Reserved
1
LTSSM_1
0x0
Indicates if PME_TURN_OFF was received (RO).
0
LTSSM_0
0x0
Acknowledges PME_TURN_OFF (R/W).
72
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_POWER_MGT_CAPABILITY Register (048h)
Table 2-36 • PCIE_POWER_MGT_CAPABILITY
Bit
Number
Name
Reset
Value
[31:27]
POWER_MGT_CAPABILITY_31_27
0x0
These bits set PME support.
26
POWER_MGT_CAPABILITY_26
0x0
Sets D2 support. If this field is cleared,
PME_SUPPORT bit 29 must also be cleared.
25
POWER_MGT_CAPABILITY_25
0x0
Sets D1 support. If this field is cleared,
PME_SUPPORT bit 28 must also be cleared.
[24:22]
POWER_MGT_CAPABILITY_24_22
0x0
These bits set maximum current required.
21
POWER_MGT_CAPABILITY_21
0x0
Sets device specification initialization.
[20:19]
POWER_MGT_CAPABILITY_20_19
0x0
Reserved
18
POWER_MGT_CAPABILITY_18
0x0
Sets PCI power management interface specification
version; hardwired to 011b (PCIe Spec. v1.1)
[17:0]
POWER_MGT_CAPABILITY_17_0
0x0
Reserved
Description
PCIE_CFG_PMSCR Register (04Ch)
Table 2-37 • PCIE_CFG_PMSCR
Bit
Number
31:0
Name
Reset
Value
0x0
CFG_PMSCR
Description
Reports the current values of the PCIe IP core’s power
management control status register.
PCIE_AER_ECRC_CAPABILITY Register (050h)
Table 2-38 • PCIE_AER_ECRC_CAPABILITY
Bit
Number
Name
Reset
Value
Description
[31:3]
AER_ECRC_CAPABILITY_31_3
Reserved
2
AER_ECRC_CAPABILITY_2
0x0
Defines whether advanced error reporting (AER) is
implemented or not.
1
AER_ECRC_CAPABILITY_1
0x0
Defines ECRC generation.
0
AER_ECRC_CAPABILITY_0
0x0
Defines ECRC check.
PCIE_VC1_CAPABILITY Register (054h)
Table 2-39 • PCIE_VC1_CAPABILITY
Bit
Number
[31:0]
Name
Reset
Value
Description
Reserved
Revision 5
73
PCI Express
PCIE_MAX_PAYLOAD_SIZE Register (058h)
Table 2-40 • MAX_PAYLOAD_SIZE
Bit
Number
Name
Reset
Value
[31:3]
2:0
Description
Reserved
MAX_PAYLOAD_SIZE_2_0
0x0
Negotiated max payload size. The EP sets its own max
payload size to 2 KB:
000: 128 bytes
001: 256 bytes
010: 512 bytes
011: 1 Kbytes
100: 2 Kbytes
PCIE_ASPM_L0S_CAPABILITY Register (060h)
Table 2-41 • PCIE_ASPM_L0S_CAPABILITY
Bit
Number
Name
Reset
Value
[31:24]
ASPM_L0S_CAPABILITY _31_24
0x0
NFTS_COMCLK in common clock mode
[23:16]
ASPM_L0S_CAPABILITY _23_16
0x0
NFTS_SPCLK in separated clock mode
[15:10]
ASPM_L0S_CAPABILITY _15_10
0x0
Reserved
[9:7]
ASPM_L0S_CAPABILITY _9_7
0x0
L0s exit latency for separate clock
[6:4]
ASPM_L0S_CAPABILITY _6_4
0x0
L0s exit latency for common clock
[3:1]
ASPM_L0S_CAPABILITY _3_1
0x0
EP L0s acceptable latency
0
ASPM_L0S_CAPABILITY _0
0x0
Reserved
Description
PCIE_ASPM_L1_CAPABILITY Register (064h)
Table 2-42 • PCIE_ASPM_L1_CAPABILITY
Bit
Number
Name
Reset
Value
Description
[31:27]
ASPM_L1_CAPABILITY_31_27
0x0
Reserved
[26:24]
ASPM_L1_CAPABILITY_26_24
0x0
L1 exit latency common clock
[23:19]
ASPM_L1_CAPABILITY_23_19
0x0
Reserved
[18:16]
ASPM_L1_CAPABILITY_18_16
0x0
L1 exit latency separated clock mode: this value must be
higher than for common clock mode
[15:4]
ASPM_L1_CAPABILITY_15_4
0x0
Reserved
[3:1]
ASPM_L1_CAPABILITY_3_1
0x0
Endpoint L1 acceptable latency
[0]
ASPM_L1_CAPABILITY_0
0x0
ASPM L1 support: If this field is not set (no ASPM L1
support), all other fields must be set to 0. ASPM L1 is
mandatory for ExpressCard devices.
74
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_TIMEOUT_COMPLETION Register (068Ch)
Table 2-43 • PCIE_TIMEOUT_COMPLETION
Bit
Number
Name
[31:4]
TIMEOUT_COMPLETION_31_4
[3:0]
TIMEOUT_COMPLETION_3_0
Reset
Value
Description
Reserved
0x0
Completion Timeout Ranges Supported – This field
indicates device Function support for the optional
Completion Timeout programmability mechanism. This
mechanism allows system software to modify the
Completion Timeout value.
Four time value ranges are defined:
Range A: 50 μs to 10 ms
Range B: 10 ms to 250 ms
Range C: 250 ms to 4 s
Range D: 4 s to 64 s
Bits are set according to the table below to show timeout
value ranges supported.
0000b Completion Timeout programming not supported.
–0000b is default setting. An error is not be produced if a
completion does not come back.
0001b Range A
0010b Range B
0011b Ranges A and B
0110b Ranges B and C
0111b Ranges A, B, and C
1110b Ranges B, C and D
1111b Ranges A, B, C, and D
All other values are reserved.
Revision 5
75
PCI Express
PCIE_PM_DATA_SCALE_0 Register (070h)
Table 2-44 • PCIE_PM_DATA_SCALE_0
Bit
Number
Name
Reset
Value
Description
[31:24]
PM_DATA_SCALE_0_31_24
0x0
Set the register that defines Data3 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[23:16]
PM_DATA_SCALE_0_23_16
0x0
Set the register that defines Data2 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[15:8]
PM_DATA_SCALE_0_15_8
0x0
Set the register that defines Data1 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[7:0]
PM_DATA_SCALE_0_7_0
0x0
Set the register that defines Data0 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
PCIE_PM_DATA_SCALE_1 Register (074h)
Table 2-45 • PCIE_PM_DATA_SCALE_1
Bit
Number
Name
Reset
Value
Description
[31:24]
PM_DATA_SCALE_1_31_24
0x0
Set the register that defines Data7 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[23:16]
PM_DATA_SCALE_1_23_16
0x0
Set the register that defines Data6 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[5:8]
PM_DATA_SCALE_1_15_8
0x0
Set the register that defines Data5 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[7:0]
PM_DATA_SCALE_1_7_0
0x0
Set the register that defines Data4 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
76
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_PM_DATA_SCALE_2 Register (078h)
Table 2-46 • PCIE_PM_DATA_SCALE_2
Bit
Number
Name
[31:26]
PM_DATA_SCALE_2_31_26
[25:24]
PM_DATA_SCALE_2_25_24
[23:18]
PM_DATA_SCALE_2_23_18
[17:16]
PM_DATA_SCALE_2_17_16
[15:10]
PM_DATA_SCALE_2_15_10
[9:8]
PM_DATA_SCALE_2_9_8
[7:2]
PM_DATA_SCALE_2_7_2
[1:0]
PM_DATA_SCALE_2_1_0
Reset
Value
Description
Reserved
0x0
Set the register that defines data scale 3 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
0x0
Set the register that defines data scale 2 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
0x0
Set the register that defines data scale 1 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
0x0
Set the register that defines data scale 0 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Revision 5
77
PCI Express
PCIE_PM_DATA_SCALE_3 Register (07Ch)
Table 2-47 • PCIE_PM_DATA_SCALE_3
Bit
Number
Name
[31:26]
PM_DATA_SCALE_3_31_26
[25:24]
PM_DATA_SCALE_3_25_24
[23:18]
PM_DATA_SCALE_3_23_18
[17:16]
PM_DATA_SCALE_3_17_16
[15:10]
PM_DATA_SCALE_3_15_10
[9:8]
PM_DATA_SCALE_3_9_8
[7:2]
PM_DATA_SCALE_3_7_2
[1:0]
PM_DATA_SCALE_3_1_0
Reset
Value
Description
Reserved
0x0
Set the register that defines data scale 7 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
0x0
Set the register that defines data scale 6 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
0x0
Set the register that defines data scale 5 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
0x0
Set the register that defines data scale 4 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
PCIE_MSI_0 Register (080h)
Table 2-48 • PCIE_MSI_0
Bit
Number
Name
Reset
Value
Description
[31:27]
MSI0_31_27
0x0
These bits set MSI_Offset[4] of MSI_MAP0.
[26:24]
MSI0_26_24
0x0
These bits set MSI_TC[4] of MSI_MAP0.
[23:19]
MSI0_23_19
0x0
These bits set MSI_Offset[3] of MSI_MAP0.
[18:16]
MSI0_18_16
0x0
These bits set MSI_TC[3] of MSI_MAP0.
[15:11]
MSI0_15_11
0x0
These bits set MSI_Offset[2] of MSI_MAP0.
[10:8]
MSI0_10_8
0x0
These bits set MSI_TC[2] of MSI_MAP0.
[7:3]
MSI0_7_3
0x0
These bits set MSI_Offset[1] of MSI_MAP0.
[2:0]
MSI0_2_0
0x0
These bits set MSI_TC[1] of MSI_MAP0.
78
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_ERROR_COUNTER_0 Register (0A0h)
Table 2-49 • PCIE_ERROR_COUNTER_0
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER0_31_24
0x0
8-bit counter that reports the following error source: 
A3: DLLP error
[23:16]
ERROR_COUNTER0_23_16
0x0
8-bit counter that reports the following error source: 
A2: TLP error
[15:8]
ERROR_COUNTER0_15_8
0x0
8-bit counter that reports the following error source: 
A1: Training error (not supported)
[7:0]
ERROR_COUNTER0_7_0
0x0
8-bit counter that reports the following error source: 
A0: Receiver port error
PCIE_ERROR_COUNTER_1 Register (0A4h)
Table 2-50 • PCIE_ERROR_COUNTER_1
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER1_31_24
0x0
8-bit counter that reports the following error source: 
A7: Poisoned TLP received error
[23:16]
ERROR_COUNTER1_23_16
0x0
8-bit counter that reports the following error source: 
A6: Data link layer protocol error
[15:8]
ERROR_COUNTER1_15_8
0x0
8-bit counter that reports the following error source: 
A5: Replay number rollover error
[7:0]
ERROR_COUNTER1_7_0
0x0
8-bit counter that reports the following error source: 
A4: Replay time error
PCIE_ERROR_COUNTER_2 Register (0A8h)
Table 2-51 • PCIE_ERROR_COUNTER_2
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER2_31_24
0x0
8-bit counter that reports the following error source: 
AB: Completer abort error
[23:16]
ERROR_COUNTER2_23_16
0x0
8-bit counter that reports the following error source: 
AA: Completion timeout error
[15:8]
ERROR_COUNTER2_15_8
0x0
8-bit counter that reports the following error source: 
A9: Unsupported request error
[7:0]
ERROR_COUNTER2_7_0
0x0
8-bit counter that reports the following error source: 
A8: ECRC error
Revision 5
79
PCI Express
PCIE_ERROR_COUNTER_3 Register (0ACh)
Table 2-52 • PCIE_ERROR_COUNTER_3
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER3_31_24
0x0
8-bit counter that reports the following error source:
AF: Malformed TLP error
[23:16]
ERROR_COUNTER3_23_16
0x0
8-bit counter that reports the following error source: 
AE: Flow control protocol error
[15:8]
ERROR_COUNTER3_15_8
0x0
8-bit counter that reports the following error source:
AD: Receiver overflow error
[7:0]
ERROR_COUNTER3_7_0
0x0
8-bit counter that reports the following error source:
AC: Unexpected completion error
PCIE_CREDIT_ALLOCATION_0 Register(0B0h)
Table 2-53 • PCIE_CREDIT_ALLOCATION_0
Bit
Number
Reset
Value
Name
Description
[31:28]
CREDIT_ALLOCATION0_31_28
0x0
Reserved
[27:16]
CREDIT_ALLOCATION0_27_16
0x0
VC0 posted header/data credit pd_cred0
[15:8]
CREDIT_ALLOCATION0_15_8
0x2
Reserved
[7:0]
CREDIT_ALLOCATION0_7_0
0x2
VC0 posted header/data credit ph_cred0
Note: Refer to Table 2-55 for CREDIT ALLOCATION Details
CREDIT_ALLOCATION_1 Register (0B4h)
Table 2-54 • PCIE_CREDIT_ALLOCATION_1
Bit
Number
Name
Reset
Value
Description
[31:28]
CREDIT_ALLOCATION1_31_28
0x0
Reserved
[27:16]
CREDIT_ALLOCATION1_27_16
0x0
VC0 non-posted header/data credit npd_cred0
[15:8]
CREDIT_ALLOCATION1_15_8
0x2
Reserved
[7:0]
CREDIT_ALLOCATION1_7_0
0x2
VC0 non-posted header/data credit nph_cred0
Note: Refer to Table 2-55 for CREDIT ALLOCATION Details
80
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 2-55 • Credit Allocation Details
Credit Type
Credit Size
Buffer Space (KB)
Posted Header (PH)
16
256
Posted Data (PD)
16
256
Non-Posted Header (NPH)
16
256
Non-Posted Data (NPD)
16
256
Completion Header (CPLH)
N/A
N/A
Infinite
512
Completion Data (CPLD)
Note: The CPLD buffer space is allocated based on the number of supported outstanding transactions. The PCIe
slave interface supports up to 4 outstanding transactions therefore reserving 128 byte x 4 amount of buffer
space.
PCIE_AXI_SLAVE_WINDOW0_0 Register (0C0h)
Table 2-56 • PCIE_AXI_SLAVE_WINDOW0_0
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW00_31_12
0x0
Base address AXI3 slave window 0
[11:0]
Reserved
0x0
Reserved
PCIE_AXI_SLAVE_WINDOW0_1 Register (0C4h)
Table 2-57 • PCIE_AXI_SLAVE_WINDOW0_1
Bit
Number
Reset
Value
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW0_1_31_12
[11:1]
Reserved
0
PCIE_AXI_SLAVE_WINDOW0_1_0
0x0
Description
Size of AXI3 Slave window 0
Reserved
0x0
Enable bit of AXI3 slave window 0
PCIE_AXI_SLAVE_WINDOW0_2 Register (0C8h)
Table 2-58 • PCIE_AXI_SLAVE_WINDOW0_2
Bit
Number
Name
Reset
Value
0x0
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW0_2_31_12
LSB of base address PCIe window 0
[11:5]
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW0_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCiE_AXI_SLAVE_WINDOW0_2_1
0x0
AXI3 Slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW0_2_0
0x0
AXI3 Slave window 0 no snoop (NS)
Reserved
PCIE_AXI_SLAVE_WINDOW0_3 Register (0CCh)
Table 2-59 • PCIE_AXI_SLAVE_WINDOW0_3
Bit
Number
[31:0]
Name
PCIE_AXI_SLAVE_WINDOW0_3_31_0
Reset
Value
0x0
Revision 5
Description
MSB of base address PCIe window 0
81
PCI Express
PCIE_AXI_SLAVE_WINDOW1_0 Register (0D0h)
Table 2-60 • PCIE_AXI_SLAVE_WINDOW1_0
Bit
Number
Reset
Value
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW1_0_31_12
[11:0]
Reserved
0x0
Description
Base address AXI3 slave window 1
Reserved
PCIE_AXI_SLAVE_WINDOW1_1 Register (0D4h)
Table 2-61 • PCIE_AXI_SLAVE_WINDOW1_1
Bit
Number
Reset
Value
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW1_1_31_12
[11:1]
Reserved
0
PCIE_AXI_SLAVE_WINDOW1_1_0
0x0
Description
Size of AXI3 slave window 1
Reserved
0x0
Enable bit of AXI3 slave window 1
PCIE_AXI_SLAVE_WINDOW1_2 Register (0D8h)
Table 2-62 • PCIE_AXI_SLAVE_WINDOW1_2
Bit
Number
Reset
Value
Name
0x0
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW1_2_31_12
LSB of base address PCIe window 1
[11:5]
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW1_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCIE_AXI_SLAVE_WINDOW1_2_1
0x0
AXI3 slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW1_2_0
0x0
AXI3 slave window 0 no snoop (NS)
Reserved
PCIE_AXI_SLAVE_WINDOW1_3 Register (0DCh)
Table 2-63 • PCIE_AXI_SLAVE_WINDOW1_3
Bit
Number
[31:0]
Name
PCIE_AXI_SLAVE_WINDOW1_3_31_0
Reset
Value
0x0
Description
MSB of base address PCIe window 1
PCIE_AXI_SLAVE_WINDOW2_0 Register (0E0h)
Table 2-64 • PCIE_AXI_SLAVE_WINDOW2_0
Bit
Number
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW2_0_31_12
[11:0]
Reserved
82
Reset
Value
0x0
R e visio n 5
Description
Base address AXI3 slave window 2
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_AXI_SLAVE_WINDOW2_1 Register (0E4h)
Table 2-65 • PCIE_AXI_SLAVE_WINDOW2_1
Bit
Number
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW2_1_31_12
[11:1]
Reserved
0
PCIE_AXI_SLAVE_WINDOW2_1_0
Reset
Value
0x0
Description
Size of AXI3 slave window 2
Reserved
0x0
Enable bit of AXI3 slave window 2
PCIE_AXI_SLAVE_WINDOW2_2 Register (0E8h)
Table 2-66 • PCIE_AXI_SLAVE_WINDOW2_2
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW2_2_31_12
[11:5]
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW2_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCIE_AXI_SLAVE_WINDOW2_2_1
0x0
AXI3 slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW2_2_0
0x0
AXI3 slave window 0 no snoop (NS)
0x0
LSB of base address PCIe window 2
Reserved
PCIE_AXI_SLAVE_WINDOW2_3 Register (0ECh)
Table 2-67 • PCIE_AXI_SLAVE_WINDOW2_3
Bit
Number
[31:0]
Name
PCIE_AXI_SLAVE_WINDOW2_3_31_0
Reset
Value
0x0
Description
MSB of base address PCIe window 3
PCIE_AXI_SLAVE_WINDOW3_0 Register (0F0h)
Table 2-68 • PCIE_AXI_SLAVE_WINDOW3_0
Bit
Number
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW3_0_31_12
[11:0]
Reserved
Reset
Value
0x0
Description
Base address AXI3 slave window 3
PCIE_AXI_SLAVE_WINDOW3_1 Register (0F4h)
Table 2-69 • PCIE_AXI_SLAVE_WINDOW3_1
Bit
Number
Name
[31:12]
PCIE_AXI_SLAVE_WINDOW3_1_31_12
[11:1]
Reserved
0
PCIE_AXI_SLAVE_WINDOW3_1_0
Reset
Value
0x0
Description
Size of AXI3 slave window 3
Reserved
0x0
Revision 5
Enable bit of AXI3 slave window 3
83
PCI Express
PCIE_AXI_SLAVE_WINDOW3_2 Register (0F8h)
Table 2-70 • PCIE_AXI_SLAVE_WINDOW3_2
Bit
Number
Reset
Value
Name
0x0
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW3_2_31_12
LSB of base address PCIe window 3
[11:5]
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW3_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCIE_AXI_SLAVE_WINDOW3_2_1
0x0
AXI3 Slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW3_2_0
0x0
AXI3 Slave window 0 no snoop (NS)
Reserved
PCIE_AXI_SLAVE_WINDOW3_3 Register (0FCh)
Table 2-71 • PCIE_AXI_SLAVE_WINDOW3_3
Bit
Number
[31:0]
Reset
Value
Name
0x0
PCIE_AXI_SLAVE_WINDOW3_3_31_0
Description
MSB of base address PCIe window 0
PCIE_AXI_MASTER_WINDOW0_0 Register (100h)
Table 2-72 • PCIE_AXI_MASTER_WINDOW0_0
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW0_0_31_12
0x0
[11:0]
Reserved
Description
Base address AXI3 master window 0
Reserved
PCIE_AXI_MASTER_WINDOW0_1 Register (104h)
Table 2-73 • PCIE_AXI_MASTER_WINDOW0_1
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW0_1_31_12
0x0
[11:1]
Reserved
Reserved
0
PCIE_AXI_MASTER_WINDOW0_1_0
Enable bit of AXI3 master window 0
84
R e visio n 5
Description
Size of AXI3 master window 0
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_AXI_MASTER_WINDOW0_2 Register (108h)
Table 2-74 • PCIE_AXI_MASTER_WINDOW0_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW0_2_31_12
0x0
LSB of base address PCIe window 0
[11:6]
Reserved
0x0
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW0_2_5_0
0x0
These bits set the BAR. To select a BAR, set the
following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW0_3 Register (10Ch)
Table 2-75 • PCIE_AXI_MASTER_WINDOW0_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW0_3_31_0
0x0
Description
MSB of base address PCIe window 0
PCIE_AXI_MASTER_WINDOW1_0 Register (110h)
Table 2-76 • PCIE_AXI_MASTER_WINDOW1_0
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW1_0_31_12
0x0
[11:0]
Reserved
Description
Base address AXI3 master window 1
Reserved
PCIE_AXI_MASTER_WINDOW1_1 Register (114h)
Table 2-77 • PCIE_AXI_MASTER_WINDOW1_1
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW1_1_31_12
0x0
[11:1]
Reserved
0
PCIE_AXI_MASTER_WINDOW1_1_0
Description
Size of AXI3 master window 1
Reserved
0x0
Revision 5
Enable bit of AXI3 master window 1
85
PCI Express
PCIE_AXI_MASTER_WINDOW1_2 Register (118h)
Table 2-78 • PCIE_AXI_MASTER_WINDOW1_2
Bit
Number
Reset
Value
Name
[31:12]
PCIE_AXI_MASTER_WINDOW1_2_31_12
[11:6]
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW1_2_5_0
0x0
Description
LSB of base address PCIe window 1
Reserved
0x0
These bits set the BAR. To select a BAR, set
the following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit
BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit
BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit
BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW1_3 Register (11Ch)
Table 2-79 • PCIE_AXI_MASTER_WINDOW1_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW1_3_31_0
0x0
Description
MSB of base address PCIe window 1
PCIE_AXI_MASTER_WINDOW2_0 Register (120h)
Table 2-80 • PCIE_AXI_MASTER_WINDOW2_0
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW2_0_31_12
0x0
Base address AXI3 master window 2
[11:0]
Reserved
0x0
Reserved
86
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_AXI_MASTER_WINDOW2_1 Register (124h)
Table 2-81 • PCIE_AXI_MASTER_WINDOW2_1
Bit
Number
Reset
Value
Name
[31:12]
PCIE_AXI_MASTER_WINDOW2_1_31_12
[11:1]
Reserved
0
PCIE_AXI_MASTER_WINDOW2_1_0
0x0
Description
Size of AXI3 master window 2
Reserved
0x0
Enable bit of AXI3 master window 2
PCIE_AXI_MASTER_WINDOW2_2 Register (128h)
Table 2-82 • PCIE_AXI_MASTER_WINDOW2_2
Bit
Number
Reset
Value
Name
[31:12]
PCIE_AXI_MASTER_WINDOW2_2_31_12
[11:6]
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW2_2_5_0
0x0
Description
LSB of base address PCIe window 2
Reserved
0x0
These bits set the BAR. To select a BAR, set the
following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW2_3 Register (12Ch)
Table 2-83 • PCIE_AXI_MASTER_WINDOW2_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW2_3_31_0
0x0
Description
MSB of base address PCIe window 3
AXI_MASTER_WINDOW3_0 Register (130h)
Table 2-84 • PCIE_AXI_MASTER_WINDOW3_0
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW3_0_31_12
0x0
[11:0]
Reserved
Description
Base address AXI3 master window 3
Reserved
PCIE_AXI_MASTER_WINDOW3_1 Register (134h)
Table 2-85 • PCIE_AXI_MASTER_WINDOW3_1
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW3_1_31_12
0x0
[11:1]
Reserved
0
PCIE_AXI_MASTER_WINDOW3_1_0
Description
Size of AXI3 master window 3
Reserved
0x0
Revision 5
Enable bit of AXI3 master window 3
87
PCI Express
PCIE_AXI_MASTER_WINDOW3_2 Register (138h)
Table 2-86 • PCIE_AXI_MASTER_WINDOW3_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW3_2_31_12
0x0
LSB of base address PCIe window 3
[11:6]
Reserved
0x0
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW3_2_5_0
0x0
These bits set the BAR. To select a BAR, set the
following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW3_3 Register (13Ch)
Table 2-87 • PCIE_AXI_MASTER_WINDOW3_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW3_3_31_0
0x0
Description
MSB of base address PCIe window 0
PCIE_INFO Register (016Ch)
Table 2-88 • PCIE_INFO
Bit
Number
Name
[31:12]
INFO_31_12
[11:0]
INFO_11_0
88
Reset
Value
0x0
Description
Bridge version
Reserved
R e visio n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
PCIE_PCIE_CONFIG Register (204h)
Table 2-89 • PCIE_PCIE_CONFIG
Bit
Number
Name
Reset
Value
Description
[31:5]
Reserved
Reserved
4
PCIE_CONFIG_4
0x0
Selects the level of de-emphasis for an upstream component when the
link speed is 5.0 Gbps.
[3:0]
PCIE_CONFIG_3_0
0x0
Sets PCIe Specification version capability:
0000: Core is compliant with PCIe Specification 1.0a or 1.1
0001: Core is compliant with PCIe Specification 1.0a or 1.1
0010: Core is compliant with PCIe Specification 2.0
PCIE_DEV2SCR Register (230h)
Table 2-90 • PCIE_DEV2SCR
Bit
Number
[31:0]
Name
Reset
Value
PCIE_DEV2SCR_31_0
0x0
Description
Reports the current value of the PCIe device control and status register.
It can be monitored by the local processor when relaxed ordering and
no snoop bits are enabled in the system. This register is used when link
speed is set to 5.0 Gbps.
PCIE_LINK2SCR Register (234h)
Table 2-91 • PCIE_LINK2SCR
Bit
Number
[31:0]
Name
PCIE_INK2SCR_31_0
Reset
Value
0x0
Description
Reports the current value of the PCIe Link Control and Status register. It
can be monitored by the local processor when Relaxed Ordering and
No Snoop bits are enabled in the system. This register is used when
link speed is set to 5.0 Gbps.
PCIE_ASPM_L0S_GEN2 Register (260h)
Table 2-92 • PCIE_ASPM_L0S_GEN2
Bit
Number
Name
Reset
Value
[31:24]
PCIE_ASPM_L0S_GEN2_31_24
0x0
NFTS_COMCLK in common clock mode at 5.0 Gbps
[23:16]
PCIE_ASPM_L0S_GEN2_23_16
0x0
NFTS_SPCLK in independent clock mode at 5.0 Gbps
[15:4]
PCIE_ASPM_L0S_GEN2_15_4
0x0
Reserved
[3:0]
PCIE_ASPM_L0S_GEN2_3_0
0x0
Number of electrical idle exit (EIE) symbols sent before
transmitting the first FTS
Description
Revision 5
89
PCI Express
PCI Express Power-Up
The PCI Express (PCIe) specification provides timing requirements for power-up. As with SRAM-based
FPGA endpoint devices, power-up is a concern when working within these tight specifications. The PCIe
specification specifies the release of the fundamental reset (PERST#) in the connector specification. The
PERSTn release time (TPVPERL) of 100ms is used for the PCIe Card Electromechanical Specification
for add-in cards. From the point of power stable to at least 100 ms, the PERST# must remain asserted.
Different PCIe systems hold PERSTn longer than 100 ms, but the minimum time is 100 ms.
The advantage of flash-based SmartFusion2 or IGLOO2 device is that its wake up time is very fast in
contrast to SRAM FPGA endpoints. The semi-autonomous nature to the PCIe Core in the SmartFusion2
or IGLOO2 device will quickly move from power-up to link detectable allowing the device to be detected
by the root. When the device is detected by the root, it proceeds to the Polling state of the LTSSM.
Afterwards the device goes through Detect and then enters the Polling state. The link now cycles through
the remainder of the LTSSM.
In use cases where the root and endpoint power-up separately, the PERSTn signal must be used to
handshake the link startups. This is detailed in Figure 2-24.
Pwr
Stable
Power Up
EP
Device
PERSTn
Wake up
Link
Detect
See Note*
Link Training
Link State
L0 (Active)
Inactive
Figure 2-24 • PCI Express Power-Up States
1. EP device wake up: The internal flash loads the programming data to the device. If PERSTn is
required, a fabric GPIO must be connected to the PERSTn of the Root. This GPIO must be
connected in the FPGA design to the CORE_RESETn pin of the PCIe core. The embedded PCIe
core will be held in reset by PERSTn, and is released afterwards to start PCIe link detection and
training.
2. Link Detection: Out-of-band pulse looks for far-end connection.
3. The PCIe link completes the training phase and reaches the L0 state.
4. After the embedded PCIe endpoint core reaches the L0 state, the host operating system (OS)
accesses the PCIe core’s configuration space registers (CSR) to perform configuration write
access cycles that are part of the system enumeration process.
Note: PERSTn is controlled by the root. If not connected to the EP, the EP enters Link Detect as soon as
the device wake up is complete.
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Hot Reset Solutions
PCI Express supports an in-band method to reset the PCIe link. A Hot Reset can be initiated by the host
setting a specific bit in a training sequence ordered set. A Hot Reset resets the controller that resets the
LTSSM state to the Detect state.
When the SmartFusion2 and IGLOO2 PCIe controller is reset by a Hot Reset, the configuration of the
SERDESIF needs to be re-initialized. The following methods can be used to re-initialize the SERDESIF:
•
Global Re-Initialization
•
Stand Alone SERDESIF Re-Initialization
Global Re-Initialization
For SmartFusion2 and IGLOO2, there is a fully automated solution for initializing the SERDESIF by using
the System Builder in Libero SoC. When the System Builder is used, all of the peripheral configuration
data is written into the SERDESIF APB interface after the device is powered up. The same method can
be used to re-initialize the PCIe controller in the SERDESIF after a Hot Reset.
When using global re-initialization, the entire device and all peripherals will be re-initialized. This means
that all lanes of the SERDES across the device as well as memory controllers (MDDR/FDDR) will also be
re-initialized. If the application can handle a complete device re-initialization, then this is the easiest
method to be implemented.
To reset the System Builder generated module to re-initialize all of the peripherals, the active-low
FAB_RESET_N port must be used. To identify when the PCIe controller goes into the Hot Reset, the
LTSSM must be monitored for a value of 5'b10100. For more information about how to monitor the
LTSSM state, refer to "Appendix C: SERDESIF PCIe Debug Interface" on page 101.
Stand Alone SERDESIF Re-Initialization
The Stand Alone Initialization method can also be used for initialization. The Stand Alone SERDESIF
initialization localizes the programming of the SERDESIF registers through the APB for each SERDESIF
instance. A CoreABC programmable microcontroller is used to load the SERDESIF registers over the
APB. For more information about the Stand Alone Peripheral Initialization, refer to the SmartFusion2
Standalone Peripheral Initialization User Guide and IGLOO2 Standalone Peripheral Initialization User
Guide.
When using stand alone re-initialization, only the SERDESIF that is connected to the CoreABC will be reinitialized. However, all of the SERDES lanes in that SERDESIF will be disrupted by the re-initialization.
For more information about developing and using the stand along re-initialization, refer to the following
web-pages:
•
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#design-resources
•
http://www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga#design-resources
Note: Re-initializing the PCIe controller in response to a Hot Reset resets all of the status bits in the PCIe
controller. In the PCIe configuration space, there are a few bits that are specified as RWS
(Read/Write/Sticky). These sticky bits loses their value under a Hot Reset due to the re-initialization.
Revision 5
91
PCI Express
Appendix A: PCIe Configuration Space
The PCIe base IP core transaction layer (TL) contains the 4Kbyte configuration space. The configuration
space implements all configuration registers and associated functions. It manages BAR and window
decoding, interrupt/MSI message generation, power management negotiation, and error handling. For
upstream ports, the configuration space is accessed through the PCIe link using Type 0 requests. Type 1
requests are forwarded to the application layer. For downstream ports, the configuration space is
accessed through the application interface using Type 0 requests. Type 1 requests are forwarded to the
PCIe link. The first 256 bytes of the configuration space are the function’s configuration space, and the
remaining configuration space is PCIe extended configuration space (see Figure 2-25).
FFFh
Extended
Configuration
Space
for PCI Express
parameters and
capabilities (not
available on legacy
operating systems)
PCI Express
Extended
Configuration
Space
(not visible on
legacy operating
systems)
PCI Express
Capability Structure
Capabioity needed
by BIOS or by
driver software on
non PCI Express
aware operating
systems
0FFh
PCI Configuration
Space (available on
legacy operating
systems through
legacy PCI
mechanisms)
03Fh
PCI 3.0 Compatible
Configuration Space
Header
000h
Figure 2-25 • PCIe Configuration Space
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Common Configuration Space Header
Table 2-93 shows the common configuration space header. The PCIe common configuration space
includes the following registers:
•
Type 0 configuration settings
•
MSI capability structure
•
Power management capability structure
•
PCIe capability structure
For comprehensive information about these registers, refer to PCIe Base Specification Revision 1.0a, 1.1
or 2.0 specifications.
Table 2-93 • Configuration Inputs for AHBL/AXI3 to AXI3 Bridge
[31:24]
[23:16]
[15:8]
[7:0]
TYPE 0 configuration registers
Byte Offset
000h...03Ch
Reserved
040h
Core Version Register
044h
Reserved
048h...04Ch
MSI capability structure
050...05Ch
Reserved
060h...064h
Power management capability structure
078...07Ch
PCIe capability structure
080h...0BCh
Reserved
0C8h...0FCh
PCIe Extended Capability Structure
Table 2-94 shows the PCIe extended capability structure. SmartFusion2 or IGLOO2 PCIe common
configuration space includes the following registers:
•
PCIe advanced error reporting (AER) extended capability structure
Table 2-94 • PCIe Extended Capability Structure (Function 0)
[31:24]
[23:16]
[15:8]
[7:0]
AER
Byte Offset
800h..834h
Revision 5
93
PCI Express
Type 0 Configuration Settings
Table 2-95 shows the type 0 configuration settings.
Table 2-95 • Type 0 Configuration Register
[31:24]
[23:16]
[15:8]
[7:0]
Device ID
Vendor ID
000h
Status
Command
004h
Class Code
BIST
Byte Offset
Header Type
Latency Timer
Revision ID
008h
Cache Line Size
00Ch
Base address 0
010h
Base address 1
014h
Base address 2
018h
Base address 3
01Ch
Base address 4
020h
Base address 5
024h
Expansion ROM Base Address (READ_ONLY)
028h
Subsystem ID
Subsystem Vendor ID
02Ch
Reserved
030h
Capabilities PTR
Reserved
034h
038h
Int. pin
Int. line
03Ch
IP Core Status Register
Table 2-96 illustrates the content of the IP Core Status Register.
Table 2-96 • IP Core Status Register
[31:28]
Reserved
[27:16]
[15:4]
[3:0]
Core version
Signature
Reserved
MSI Capability Structure
Table 2-97 illustrates the content of the MSI capability structure.
Table 2-97 • MSI Capability Structure Register
[31:24]
[23:16]
Message control
Reserved
94
[15:8]
[7:0]
Byte Offset
Next pointer
Cap ID
050h
Message address
054h
Message upper address
058h
Reserved
Message data
R e visio n 5
05Ch
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Power Management Capability Structure
Table 2-98 illustrates the content of the power management capability structure.
Table 2-98 • Power Management Capability Structure
[31:24]
[23:16]
Capabilities register
Data
PM control/status
[15:8]
[7:0]
Byte Offset
Next cap PTR
Cap ID
078h
Power management status and control
07Ch
bridge extensions
PCIe Capability Structure
Table 2-99 illustrates the content of the PCIe capability structure.
Table 2-99 • PCIe Capability Structure Register
[31:24]
[23:16]
Capabilities register
[15:8]
[7:0]
Byte Offset
Next cap PTR
cap ID
080h
Device capabilities
Device status
084h
Device control
Link capabilities
Link status
088h
08Ch
Link control
Slot capabilities
090h
094h
Slot status
Slot control
098h
Reserved
Root control
09Ch
Root status
0A0h
Device capabilities 2
0A4h
Device status 2
Device control 2
Link capabilities 2
Link status 2
0ACh
Link control 2
Revision 5
0A8h
0B0h
95
PCI Express
PCIe AER Extended Capability Structure
Table 2-100 shows the advanced error reporting (AER) extended capability structure for Function 0. For
Functions 1 - 7, the byte offset is from 100h to 134h.
Table 2-100 • PCIe AER Extended Capability Structure
[31:24]
[23:16]
[7:0]
Byte Offset
PCIe enhanced capability header
800h
Uncorrectable error status register
804h
Uncorrectable error mask register
808h
Uncorrectable error severity register
80Ch
Correctable error status register
810h
Correctable error mask register
814h
Advanced error capabilities and control register
818h
Header log register
81Ch
Root error command
82Ch
Root error status
830h
Error source identification register
96
[15:8]
Correctable error source ID register
R e visio n 5
834h
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Appendix B: TLP Contents
The following tables describe the contents of all TLPs. The bit assignments are mapped with the MSB in
the top-left and the LSB in the bottom-right of the tables.
B.1 Content of a TLP without a Data Payload
Table 2-101 • Memory Read Request 32-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 0 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [31:2]
Byte 12
Reserved
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 2-102 • Memory Read Request-Locked 32-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 0 0 0 0 0 1 0 TC
Byte 4
Requester ID
Byte 8
Address [31:2]
Byte 12
Reserved
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 2-103 • Memory Read Request 64-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 1 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [63:32]
Byte 12
Address [31:2]
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 2-104 • Memory Read Request-Locked 64-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 1 0 0 0 0 1 0 TC
Byte 4
Requester ID
Byte 8
Address[63:32]
Byte 12
Address [31:2]
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
Tag
0 0 Length
Last BE
First BE
0 0
Revision 5
97
PCI Express
Table 2-105 • Type 0 Configuration Read Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
Table 2-106 • Type 0 Configuration Read Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0000
0
0 0 Ext. Reg.
First BE
Register Nb.
0 0
Table 2-107 • Message (without data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 1 1 0 r r r 0 TC
2 1 0
Byte 4
Requester ID
Byte 8
Vendor defined or all zeros
Byte 12
Vendor defined or all zeros
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP 0 0
0 0 0 0 0 0 0 0 0 0 0 0
Tag
Message Code
+2
+3
Table 2-108 • Completion (without data) Descriptor Format
+0
+1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
6
Byte 0
0 0 0 0 1 0 1 0 0 TC
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
Byte 12
R
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
B Byte Count
0 Lower Address
Table 2-109 • Completion Locked (without data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
Byte 0
0 0 0 0 1 0 1 1 0 TC
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
0 0 0 0 TD EP Attr
Byte 12
98
5 4 3 2 1 0 7 6 5 4 3 2 1 0
R e visio n 5
0 0 Length
B Byte Count
0 Lower Address
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
B.2 Content of a TLP with a Data Payload
Table 2-110 • Memory Write Request 32-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 1 0 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [31:2]
Byte 12
R
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 2-111 • Memory Write Request 64-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 1 1 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [63:32]
Byte 12
Address [31:2]
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 2-112 • Type 0 Configuration Write Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
Table 2-113 • Type 0 Configuration Write Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
Table 2-114 • Type 1 Configuration Write Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
Revision 5
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
99
PCI Express
Table 2-115 • Completion (with data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
Byte 0
0 1 0 0 1 0 1 0 0 TC
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
Byte 12
R
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
B Byte Count
0 Lower Address
Table 2-116 • Completion Locked (with data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 1 0 1 1 0 TC
0 0 0 0 TD EP Attr
0 0 Length
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
0 Lower Address
+2
+3
B Byte Count
Byte 12
Table 2-117 • Message (with data) Descriptor Format
+0
+1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 1 1 1 0 r r r
2 1 0
Byte 4
Requester ID
Byte 8
Vendor defined or all zeros for Slot Power Limit
Byte 12
Vendor defined or all zeros for Slots Power Limit
100
TC
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP 0 0
Tag
R e vi s i o n 5
0 0 Length
Message Code
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Appendix C: SERDESIF PCIe Debug Interface
SERDES block has a debug mode mostly for debugging PCIe link. A number of internal status/error
signals are available to the fabric to be used for end-to-end system debug functions. To keep the number
of signals interfacing between the fabric and SERDES block to a minimum, these debug signals are
multiplexed on PRDATA signals of the APB bus. Debug mode is enabled only when
SYSTEM_DEBUG_MODE_KEY (8'b1010_0101) is written (offset - address: A8). Once correctly written,
the APB READ-BUS is multiplexed with PCIe debug data. PCIe DEBUG data is available only when
APB-READ is not taking place. This feature can be activated only from the Edit Registers GUI of the
SERDES Configurator.
Table 2-118 shows the condition where debug information is available, and Table 2-119 shows the debug
signals that are mapped to APB PRDATA bus.
Table 2-118 • Debug Information Available Conditions
Debug Mode
APB-Bus Operation
APB_PRDATA Bus Behavior
Enabled
Write
Debug information
Enabled
Read
APB read data
Enabled
Idle
Debug information
Disabled
Don’t care
APB read data
Table 2-119 • Debug Signals Mapping to APB Bus
APB_PRDAT Signals
APB_S_PRDATA[31]
Debug Signal
PHY_LOCK_STATUS
Description
SERDES PHY related status signals. Combined status of 
PHY - Tx/CDR- PLL lock status. Only PHY-lanes which are used
are considered for this phy_lock_status signal generation. When
any used PLL's PHY lanes are locked, phy_lock_status is either
1'b1 or it is 1'b0.
Note: Individual PHY lane's PLL information is available in
SYSTEM_SERDES_TEST_OUT (0x2074) register in the
SERDESIF system block.
APB_S_PRDATA[30:26]
LTSSM_R [4:0]
LTSSM state: LTSSM state encoding. Refer to LTSSM_28_24
register for more information.
APB_S_PRDATA[25:24]
ERR_PHY [1:0]
PHY error: Physical layer error
bit0: Receiver port error
bit1: Training error
APB_S_PRDATA[23:19]
ERR_DLL [4:0]
DLL error: Data link layer error
bit0: TLP error
bit1: DLLP error
bit2: Replay timer error
bit3: Replay counter rollover
bit4: DLL protocol error
Revision 5
101
PCI Express
Table 2-119 • Debug Signals Mapping to APB Bus (continued)
APB_PRDAT Signals
Debug Signal
APB_S_PRDATA[18:10]
ERR_TRN [8:0]
Description
TRN error: Transaction layer error
bit0: Poisoned TLP received
bit1: ECRC check failed
bit2: Unsupported request
bit3: Completion timeout
bit4: Completer abort
bit5: Unexpected completion
bit6: Receiver overflow
bit7: Flow control protocol error
bit8: Malformed TLP
APB_S_PRDATA[9]
ERR_DL
Error ACK/NACK DLLP parameter: This signal reports that the
received ACK/NACK DLLP has a sequence number higher than
the sequence number of the last transmitted TLP.
APB_S_PRDATA[8]
TIMEOUT
LTSSM timeout: This signal serves as a flag, which indicates that
the LTSSM timeout condition is reached for the current LTSSM
state.
1’b1: Timeout condition reached
1’b0: No time condition reached
APB_S_PRDATA[7]
CRCERR
Received TLP with LCRC error: This signal reports that a TLP is
received, which contains an LCRC error.
APB_S_PRDATA[6]
CRCINV
Received nullified TLP: This signal indicates that a nullified TLP
is received.
APB_S_PRDATA[5]
RX_ERR_DLLP
Received DLLP with LCRC error: This signal reports that a DLLP
has been received that contains an LCRC error.
APB_S_PRDATA[4]
ERR_DLLPROT
DLL protocol error at data link layer: This signal reports a DLL
protocol error.
APB_S_PRDATA[3]
RX_ERR_FRAME
DLL framing error detected: This signal indicates that received
data cannot be considered as a DLLP or TLP, in which case, a
receive port error is generated and link retraining is initiated.
APB_S_PRDATA[2]
L2-EXIT
l2_exit information signal
APB_S_PRDATA[1]
DLUP_EXIT
dlup_exit information signal
APB_S_PRDATA[0]
HOTRST_EXIT
hotrst_exit information signal
List of Changes
The following table shows important changes made in this document for each revision.
Date
Revision 5
(December 2015)
102
Changes
Updated Table 2-15 (SAR 73409).
Updated Table 2-4 and Table 2-5 (SAR 73758).
R e vi s i o n 5
Page
63
45 and
46
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Date
Changes
Revision 4
(August 2015)
Updated Table 2-1 (SAR 69996).
Updated Figure 2-4, Figure 2-5, Figure 2-6, Figure 2-7, Figure 2-19, and
Figure 2-22 (SAR 69885).
Page
29
32, 33,
34, 36,
54, and
59
Added Table 2-55 (SAR 67187).
81
Updated Table 2-42 (SAR 67613).
74
Updated Table 2-4, Table 2-5, Table 2-6, Table 2-7, Table 2-8, and Table 2-9.
45, 46,
and 48
Updated "PCIe Fabric Interface (AXI3/AHB-Lite)" section.
34
Updated "PCIe System" section (SAR 64677).
39
Updated Figure 2-12 and Figure 2-20.
41, 56
Updated "Appendix C: SERDESIF PCIe Debug Interface" section.
101
Revision 3
(January 2015)
Consolidated SmartFusion2 and IGLOO2 User Guides.
NA
Revision 2
(July 2014)
Updated Table 2-4 (SAR 56134).
45
March 2014
Updated the chapter (SAR 49906).
Updated Figure 2-10,"Features" section, and "PCIe Base IP Core" section 
(SARs 57466 and 56868).
39,28
and 40
NA
Glossary
APB
Advanced peripheral bus
AXI3
Advanced extensible interface
EP
Endpoint
PCI Express
Peripheral component interconnect express
PCIe
PCI Express
SERDES
Serializer/de-serializer
SERDESIF
Serializer/de-serializer interface
Revision 5
103
3 – XAUI
Introduction
This chapter describes implementing XAUI in SmartFusion2 and IGLOO2 FPGA devices using the XAUI
extender block inside the SERDESIF block. XAUI is a standard for extending the 10 Gb media
independent interface (XGMII) between the media access control (MAC) and PHY layer of 10 Gb
Ethernet (10 GbE). The SmartFusion2 and IGLOO2 high speed serial block implements integrated XAUI,
which can be connected to a 10 Gb Ethernet FPGA IP core in the FPGA fabric for a complete solution.
Overview of XAUI Implementation in SmartFusion2/IGLOO2
The IGLOO2 SERDESIF block integrates the functionality of supporting multiple high speed serial
protocols, such as PCIe 2.0, XAUI, and EPCS, as shown in Figure 3-1. The SERDESIF block can be
configured in various modes, including XAUI. XAUI is a standard for extending the XGMII between the
MAC and PHY layer of 10 GbE.
JTAG I/O
SPI I/O
Multi-Standard User I/O (MISO)
SPI x 2
MMUART x 2
I2C x 2
Timer x 2
System Controller
AES256
SHA256
ECC
NRBG
SRAM-PUF
DDR User I/O
Microcontroller Subsystem (MSS) for SmartFusion2
OR
CAN
APB
Flash*Freeze
sh Freeze
HS USB
OTG ULPI
PDMA
WDT
In-Application
Programming
SYSREG
Multi-Standard
tandard User I/O (MISO)
AHB
Mi SRAM
Micro
(64x18)
AHB
TSEMAC
eSRAM
HPDMA
SMC_FIC Config
AHB
Large SRAM
(1024x18)
AXI/AHB
Math Block
MACC (18x18)
Multi-Standard User I/O (MISO)
Interrupts
FIC_1
SERDES
I/O
MSS/HPMS
DDR Controller
+ PHY
AHB Bus Matrix (ABM)
FIC_0
Large SRAM
(1024x18)
PMA LANE1
SERDES
I/O
PMA LANE2
EPCS
LANE
0:1
PCIe PCS
LANE1
PMA Control
Logic
PIPE
Controller
APB Bus
PMA Control
Logic
XAUI
Extender
PCIe PCS
LANE2
LANE[2:3] Calibration
SERDES
I/O
Micro SRAM
(64x18)
PCIe PCS
LANE0
PMA Control
Logic
LANE[0:1] Calibration
FIIC
COMM_BLK
PMA LANE0
DDR
Bridge
eNVM
RTC
FPGA
GA Fabric
SERDES
I/O
High Performance Memory Subsystem (HPMS) for IGLOO2
PMA LANE3
PMA Control
Logic
EPCS
LANE
2:3
PCIe PCS
LANE3
Math Block
MACC (18x18)
FPGA Fabric Interface
Config
AXI/AHB/XGXS
Serial Controller 0
(PCIe, XAUI/XGXS)
+ Native SERDES
Serial 0 I/O
Config
OSCs
AXI/AHB/XGXS
Serial Controller 1
(PCIe, XAUI/XGXS)
+ Native SERDES
Serial 1 I/O
Config
PLLs
AXI/AHB
Fabric DDR
Controller + PHY
Standard Cell /
SEU Immune
Flash Based /
SEU Immune
APB Slave
Register Space
Interface
XGMII/MDIO
User Gigabit
Ethernet IP
DDR User I/O
Figure 3-1 • SmartFusion2 and IGLOO2 SERDESIF Block Diagram
As an example for discussion, the block diagram for the M2GL050T device is shown in Figure 3-1. The
smaller devices have fewer SERDES channel and the larger devices have more channels.
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The XAUI implementation in SmartFusion2 and IGLOO2 devices offers the following features:
•
Full compliance with IEEE 802.3
•
IEEE 802.3ae- clause 45 MDIO interface
•
IEEE 802.3ae- clause 48 state machines
•
Pseudorandom idle insertion (PRBS Polynomial X7 + X3 + 1)
•
FPGA interface Clock frequency of 156.25 MHz
•
Double-width 64-bit single data rate (SDR) interface
•
Comma alignment function
•
Low power mode
•
PHY-XS and DTE-XS loopback
•
IEEE 802.3ae- annex 48A jitter test pattern support
•
IEEE 802.3 clause 36 8B/10B encoding compliance
•
Tolerance of lane skew up to 16 ns (50 UI)
•
IEEE 802.3 PICs compliance matrix
Device Support
Table 3-1 shows the total number of SERDESIF blocks in each SmartFusion2 and IGLOO2 device that
can be configured to support XAUI.
Table 3-1 • SERDESIF Blocks in SmartFusion2 and IGLOO2 FPGAs that support XAUI
SERDESIF
available for
XAUI
M2S/M2GL
005
M2S/M2GL
010
M2S/M2GL
025
M2S/M2GL
050
M2S/M2GL
060
M2S/M2GL
090
M2S/M2GL
150
0
1
1
Up to 2
1
1
Up to 4
Notes:
1. The specified number of SERDESIF blocks varies depending on the device package.
2. XAUI uses one entire SERDESIF (4-Lanes).
XAUI Overview
XAUI is a standard for extending the 10 Gb media independent interface (XGMII) between the MAC and
PHY layer of 10 GbE. XGMII provides a 10 Gbps pipeline; the separate transmission of clock and data
coupled with the timing requirement to latch data on both the rising and falling edges of the clock results
in a significant challenge in routing the bus more than the recommended short distance of 7 cm. Also, the
XGMII bus puts many limitations on the number of ports that can be implemented on a system line card.
To overcome these issues, IEEE 802.3ae 10 GbE Task Force developed the XAUI interface. XAUI is a
full duplex interface that uses four self-clocked serial differential links in each direction to achieve 10
Gbps data throughput. Each serial link operates at 3.125 Gbps to accommodate both data and the
overhead associated with 8B/10B coding. The self-clocked nature eliminates skew concerns between
clock and data, and extends the functional reach of the XGMII by approximately another 50 cm. Its
compact nature and robust performance makes it ideal for chip to chip, board to board, and chip to optics
module applications. The XAUI standard is fully specified in clauses 47 and 48 of the 10 GbE
specification IEEE Std. 802.3-2008.
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XAUI
XAUI has the following features:
•
Simple signal mapping to the XGMII
•
Independent transmit and receive data paths
•
Four lanes conveying the XGMII 64-bit data and control
•
Differential signaling with low voltage swing (1600 mV(p-p))
•
Self-timed interface allowing jitter control to the physical coding sublayer (PCS)
•
Shared technology with other 10 Gbps interfaces
•
Shared functionality with other 10 Gbps Ethernet block
•
Utilization of 8b/10b encoding
The conversion between the XGMII and XAUI interfaces occurs at the XGXS (XAUI extender sublayer).
SmartFusion2 and IGLOO2 XAUI
The SmartFusion2 and IGLOO2 FPGA has a integrated XAUI implementation. The SmartFusion2 and
IGLOO2 high speed interface (SERDESIF) has a XAUI IP block (XAUI Extender) and SERDES block.
Figure 3-1 on page 104 shows an application example; the XAUI IP is extending the 10 Gb soft IP in the
fabric. The XAUI IP block in SERDESIF block provides the XGXS functionality and the SERDES block
provides the physical layer. The XAUI IP block connects a 10 Gb Ethernet MAC to SERDES physical
medium attachment (PMA) logic. In addition, the XAUI IP block has a management data input/output
(MDIO) interface allowing an MDIO manageable device to program the MDIO registers. The SERDES
block is configured to PMA only mode and requires a reference clock of 156.25 MHz to operate at a line
rate of 3.125 Gbps.
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Figure 3-2 • XAUI Implementation in SmartFusion2/IGLOO2
The high speed serial interface (SERDESIF) can be configured to support multiple serial protocols.
However, when using the XAUI protocol, only one protocol can be implemented because XAUI uses all
four SERDES lanes. Table 3-2 shows the lane speed of four physical SERDES lanes when using XAUI.
Table 3-2 • XAUI Implementation in SmartFusion2 and IGLOO2
Lane0
XAUI Protocol
Single Protocol PHY
Lane1
Lane2
Lane3
Protocol
Speed
Protocol
Speed
Protocol
Speed
Protocol
Speed
XAUI
3.125G
XAUI
3.125G
XAUI
3.125G
XAUI
3.125G
The SERDESIF block in XAUI mode has a SERDES I/O pad on one side and an XGMII interface and
MDIO interface on the FPGA fabric side. Table 3-2 shows the SmartFusion2 and IGLOO2 I/O PAD in
XAUI mode.
The SmartFusion2 and IGLOO2 XAUI interface uses the "SERDESIF- I/O Signal Interface" listed in
Table 5-4 on page 175. Refer to the "XAUI IP Fabric Interface" section on page 112 for detailed
information on XGMII and MDIO interfaces on the fabric side.
Refer to device Pin Descriptions for other SERDES required pins.
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XAUI
Getting Started
This section provides an overview of how to configure a SERDESIF block in XAUI mode, and instructions
for using XAUI IP in a SmartFusion2 or IGLOO2 device.
The following sections show how to instantiate XAUI in a design by completing the following steps:
1. Using High-Speed Serial Configurator for XAUI Mode
2. Simulating SERDESIF with XAUI Mode
3. Application Example Using XAUI
Using High-Speed Serial Configurator for XAUI Mode
The High Speed Serial Interface Configurator in Libero SoC can be used to configure the SERDESIF
block in XAUI mode. Refer to Figure 3-3 for the XAUI mode setting in the high speed serial interface
configurator.
Figure 3-3 • XAUI Mode Setting in High Speed Serial Interface Configurator
Following are brief descriptions of the configuration options. Refer to the High Speed Serial Interface
Configuration User Guide for details.
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Protocol Selection
These settings are used for protocol selection:
•
Protocol 1 Type—This is the protocol setting. Select XAUI from the drop-down menu.
•
Protocol 1 PHY Reference Clock—This is the PHY reference clock selection. Refer to the
"SERDES Reference Clocks Selection" section on page 117 for details on PHY reference clock
selection.
Simulating SERDESIF with XAUI Mode
When configured in XAUI mode, the SERDESIF block will only allow the user to run simulation using the
APB3 interface. The user can read and write to the SERDESIF and SERDES register using the
simulation library. Refer to the SERDESIF BFM Simulation Guide for details for using RTL mode for
simulation. BFM mode for simulation is not supported for XAUI.
Application Example Using XAUI
To complete an application in a SmartFusion2 or IGLOO2 device, configure the appropriate settings in
the high speed serial interface generator, then generate the SERDESIF block in XAUI mode. Figure 3-4
shows the SERDESIF block in Libero SoC in XAUI mode. Libero SoC promotes the SERDES I/Os to top
level and exposes XGMII, MDIO, and the APB interface to the FPGA fabric. In addition, the SERDESIF
block exposes the clocks, resets, and PLL locks to the user.
Figure 3-4 • High Speed Serial Interface Block in XAUI Mode in Libero SoC
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XAUI
Figure 3-5 shows a complete application in a SmartFusion2 or IGLOO2 device.
SERDES
I/O PADS
SERDESIF
in XAUI Mode
MDIO
interface
XGMII
interface
Reset
and Clock
interface
APB
interface
FPGA
I/O PADS
GIGAbit Ethernet
FPGA IP
Fabric
FIC_2
MSS/HPMS
Figure 3-5 • An Application Example Using XAUI IP
XAUI IP Architecture
This section provides an overview of the XAUI IP block, covering the following topics:
•
Overview of XAUI IP Block
•
XAUI IP Fabric Interface
Overview of XAUI IP Block
Figure 3-6 shows the XAUI IP block. This module is connected to the SERDES PMA block through the
two EPCS interface blocks, and to the FPGA fabric through XGMII and MDIO interfaces. There are three
major blocks:
•
Transmit block: This block is responsible for encoding the XGMII data (using 8B/10B). The output
to the transmit block is an 80-bit interface (20 bits per lane). The PMA in the SERDES receives
this 80-bit data and transmits it to the XAUI bus.
•
Receive block: This block receives 8B/10B encoded data and four recovered clocks from an
external XAUI SERDES PMA. The receive block performs comma alignment on the data, phasealigns the four lanes of data, and performs the 8B/10B decode function.
•
Management block: The management block is the MDIO interface to the design registers.
The transmit and receive FPGA interface frequencies are set at 156.25 MHz.
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SERDESIF
XAUI Extender
Transmit Block
XGMII Interface
Lane12
EPCS
Interface
SERDES
I/O PADS
SERDES
(PMA only)
Management Block
Lane23
EPCS
Interface
MDIO Interface
Receive Block
Figure 3-6 • XAUI Extender Block Diagram
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XAUI
XAUI IP Fabric Interface
The SmartFusion2 and IGLOO2 SERDESIF in XAUI mode interfaces with the fabric and differential I/O
pads. The following tables describe the fabric interfaces:
•
MDIO Interface Signals
•
XGMII Transmit Interface Signals
•
XGMII Receive Interface Signals
•
XAUI Extender Block Miscellaneous Control Signal
•
Clock Signals in XAUI Mode
•
XAUI Extender Block Miscellaneous Control Signal
Table 3-3 • MDIO Interface Signals
Port
Type
Description
XAUI_MMD_MDC
Input
MDIO I/F clock. 40 MHz or less
XAUI_MMD_MDI
Input
MDIO data input from bidirectional pad
XAUI_MMD_MDI_ EXT
Input
Serial data output of another block that is responding to a host read transaction
XAUI_MMD_MDO
Output MDIO data output to bidirectional pad
XAUI_MMD_ MDOE
Output MDIO data output enable. This is used to control bidirectional pad. It is active
High.
XAUI_MMD_ MDOE_IN
Input
MDIO data output enable input. This is used to force MMD_MDI High in an idle
state. It is active High.
XAUI_MMD_PRTAD[4:0]
Input
A static signal that defines the port address of the XAUI extender block
instantiated. Access to the MDIO registers is granted only if the port address
specified in the MDI stream matches this input.
XAUI_MMD_ DEVID[4:0]
Input
A static signal that defines the device ID of the XAUI extender block instantiated.
Access to the MDIO registers is granted only if the device ID (DEVID) specified
in the MMD_MDI stream matches this input. For the PHY-XS, this value must be
04h. For the DTE-XS, this value must be 05h.
XAUI_VNDRRESLO[31:0] Output A general purpose register for vendor use, reset Low. The output of two 16-bit
registers (address 0x8000 and 0x8001) that are set Low on reset for general
purpose use.
XAUI_VNDRRESHI[31:0]
112
Output General purpose register for vendor use, reset High. The output of two 16-bit
registers (address 0x8002 and 0x8003) that are set High on reset for general
use.
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Table 3-4 • XGMII Transmit Interface Signals
Port
Type
XAUI_TXD[63:0]
Input
Description
Transmit data input from the XGMII. The signal has the following lane definitions:
Lane0, row0: txd[7:0]
Lane1, row0: txd[15:8]
Lane2, row0: txd[23:16]
Lane3, row0: txd[31:24]
Lane0, row1: txd[39:32]
Lane1, row1: txd[47:40]
Lane2, row1: txd[55:48]
Lane3, row1: txd[63:56]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause
46, for a complete definition.
XAUI_TXC[7:0]
Input
Transmit data lane control signals. The signal has the following lane definitions:
Lane0, row0: txc[0]
Lane1, row0: txc[1]
Lane2, row0: txc[2]
Lane3, row0: txc[3]
Lane0, row1: txc[4]
Lane1, row1: txc[5]
Lane2, row1: txc[6]
Lane3, row1: txc[7]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause
46, for a complete definition.
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Table 3-5 • XGMII Receive Interface Signals
Port
Type
Description
XAUI_RX_CLK
Output Receive clock synchronous with Rxd, clock synchronous with the output XGMII data
Rxd. Equal to the input recovered clock RX_CLKI0. This clock operates nominally at
156.25 MHz. Refer to IEEE 802.3ae, clause 46, for a complete definition.
XAUI_RXD[63:0]
Output Receive data output to the XGMII. The signal has the following lane definitions:
Lane0, row0: rxd[7:0]
Lane1, row0: rxd[15:8]
Lane2, row0: rxd[23:16]
Lane3, row0: rxd[31:24]
Lane0, row1: rxd[39:32]
Lane1, row1: rxd[47:40]
Lane2, row1: rxd[55:48]
Lane3, row1: rxd[63:56]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause 46,
for a complete definition.
XAUI_RXC[7:0]
Output Receive lane data control signals. The signal has the following lane definitions:
Lane0, row0: rxc[0]
Lane1, row0: rxc[1]
Lane2, row0: rxc[2]
Lane3, row0: rxc[3]
Lane0, row1: rxc[4]
Lane1, row1: rxc[5]
Lane2, row1: rxc[6]
Lane3, row1: rxc[7]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause 46,
for a complete definition.
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Table 3-6 • XAUI Extender Block Miscellaneous Control Signal
Port
XAUI_ LOOPBACK_OUT
XAUI_ LOOPBACK_IN
XAUI_ LOWPOWER
Type
Description
Output
Loopback mode enable out. This signal is asserted when the XAUI extender
block is placed in loopback. Typically, this signal is shunted back into the
input XAUI_ LOOPBACK_IN port. In this case, loopback is implemented in
the XAUI extender block. However, this signal can be used to control the
loopback function on a PMA in the SERDES block in place of the mxgxs
loopback function.
Input
Loopback mode enable in. When asserted, the XAUI PMA output data
signals are shunted back into the input signals. For loopback to function
appropriately, the XGMII transmit clock TX_CLK must be shunted back into
the PMA recovered clock inputs.
Output
SERDES low power status. When set to 1, the SERDES block is placed in a
low power state.
Reset and Clocks for PCIe
This section covers the functional aspects of the reset and clock circuitry inside the high speed serial
interface block for XAUI mode. It includes the following sections:
•
XAUI Mode Clocking
•
XAUI Mode Reset Network
XAUI Mode Clocking
When the SERDESIF is configured in XAUI mode, it has multiple clock inputs and outputs. This section
describes the XAUI clocking scheme.
SERDESIF Clock Network in XAUI
In XAUI mode, data is exchanged from FPGA IP in the fabric and XAUI IP. Figure 3-7 on page 116 shows
in the XAUI clocking scheme. The 156.25 MHz reference clock is used by the SERDES PMA (Tx PLL
and CDR PLL). The PLLs generate 156.25 MHz clocks and send 4Rx and 4Tx clocks through the EPCS
interface. The Lane0 Tx clock is fed into as reference clock of SPLL and XAUI extender block. This SPLL
is used to reduce the skew between the fabric and SmartFusion2 and IGLOO2 SERDESIF module.
Libero SOC automatically connects the XAUI_CLK_OUT signal with the XAUI_FDB_CLK signal in the
FPGA fabric through the global network, as shown in Figure 3-7 on page 116. The 4 Rx clocks are fed
into the XAUI extender block, where lane de-skewing is done and only one Rx clock is given out to the
FPGA fabric. The XAUI_CLK_OUT and XAUI_RX_CLK signals are used by XGMII FPGA IP. The APB
clock (APB_S_PCLK) is an asynchronous clock used for SERDESIF register access.
In XAUI only mode, the Tx clock is generated from the PMA. The lane0 Tx clock is used for this purpose.
The Rx clock for all four lanes is passed to the XGXS receiver block with gating logic in between to low
power operation.
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XAUI
TXDP
TXDN
3.125 GHz
RXDP
RXDN
3.125 GHz
Fabric
SERDESIF
SERDES
Reference Clock (156.25 MHz)
CDR
PLL
TX
PLL
APB_S_PCLK
MDD_MDC
156.25 MHz
TxClk-x4 Clks
156.25 MHz
RxClk-x4 Clks
XAUI_RXCLK
XAUI
IP
4 to 1
Mux
156.25 MHz
TxClk
EPCS_TXCLK[0]
XGMII
FPGA
IP
PLL_SERDESIF_REF
deskew
SPLL
PLL_SERDESIF_FB
deskew
GB
PLL_ACLK
XAUI_CLK_OUT
Figure 3-7 • SPLL Clocking in XAUI Mode
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Table 3-7 shows the various clocks in the XAUI mode.
Table 3-7 • Clock Signals in XAUI Mode
Clock Signal
Description
XAUI_OUT_CLK
Transmit clock to be used for the transmit data. Divided down 156.52 MHz clock from the
transmit PLL.
MMD_MDC
MDIO clock
XAUI_RX_CLK
Receive clock synchronous with Rxd, clock synchronous with the output XGMII data Rxd.
Equal to the input recovered clock RX_CLKI0. Refer to IEEE 802.3ae, clause 46, for a
complete definition.
APB_S_PCLK
PCLK for APB interface
SERDES Reference Clocks Selection
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through PLLs. Figure 3-8 shows reference clock selection in the high speed serial interface
generator available in Libero SoC. The user can choose one of the two reference clocks. The reference
clock to the four lanes can come from I/O Port0 (SERDES_x_REFCLK0) or I/O Port1
(SERDES_x_REFCLK1) I/O pads. The FAB_REF_CLK option is not available in XAUI mode. Note that
the reference clock pads are differential input. In XAUI mode, the user must choose one reference clock
for all 4 lanes. For more information, refer to the "Serializer/De-serializer" chapter on page 154.
SERDES_x_REFCLK0_P
SERDESI
REFCLK0
0
SERDES_x_REFCLK0_N
SERDES_x_REFCLK1_P
REFCLK1
1
aREFCLK[1:0]
SERDES_x_REFCLK1_N
2
LANE01_REFCLK_SEL[1:0]
0
1
SERDES
aREFCLK[3:2]
2
fab_ref_clk
(not available
in XAUI mode)
LANE23_REFCLK_SEL[1:0]
Figure 3-8 • SERDES Reference Clock for PCIe Mode
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XAUI
Table 3-8 • Reference Clock Signals for SERDES
Clock Signal
Description
REFCLK0_P, REFCLK0_N
Reference clock output of SERDES_x_REFCLK0_P and SERDES_x_REFCLK0_N
REFCLK1_P, REFCLK1_N
Reference clock output of SERDES_x_REFCLK1_P and SERDES_x_REFCLK1_N
Figure 3-9 shows reference clock selection in the high speed serial interface generator available in
Libero SoC. I/O Port0 selects REFCLK0 and I/O Port1 selects REFCLK1.
Figure 3-9 • Reference Clock Selection
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XAUI Mode Reset Network
The SmartFusion2 and IGLOO2 SERDESIF configured in XAUI mode has multiple reset inputs.
Figure 3-10 shows the reset signals and how they are connected internally. The CORE_RESET_N input
is an asynchronous reset input XAUI extender block, the XAUI_MDC_RESET input asynchronously
resets all of the MDIO registers, the XAUI_TX_RESET input resets the TX block register, and the
XAUI_RX_RESET input resets the RX block register. The XAUI IP generates several reset signals that are
used by the FPGA IP. In addition, there are several input reset signal SERDES and SERDESIF registers.
Table 3-9 on page 120 describes the reset signals and recommended connections.
Fabric
SERDESIF
PHY_RESET_N
APB_S_PRESET_N
Power-up
CORE_RESET_N
epcs_rstn[3:0]
XAUI_MDC_RESET
Reset
Glue Logic
MDC_RESET
SERDES
XAUI_TX_RESET
TX_RESET
MSTR_RESET
XAUI
Extender
XAUI_RX_RESET
RX_RESET[3:0]
XAUI_RX_RESET_OUT
epcs_ready[3:0]
RX_RESETOUT[3:0]
XAUI_TX_RESET_OUT
XAUI_MDC_RESET_OUT
Figure 3-10 • XAUI Reset Scheme
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Table 3-9 • XAUI Mode Reset Signals
Port
Type
Description
CORE_RESET_N
Input
External asynchronous reset input. Must be asserted for at least two clock
cycles of the host clock MMD_MDC for a full reset of the XAUI extender to
occur. It is active Low.
PHY_RESET_N
Input
Active Low SERDES reset. It is synchronized with the SERDES reference
clock.
XAUI_MDC_RESET_ OUT
XAUI_MDC_RESET
XAUI_TX_RESET_OUT
XAUI_TX_RESET
Output MDC synchronous reset. This reset is asynchronously asserted by
MSTR_RESET and synchronously deasserted with the XAUI_MMD_MDC
clock. Typically, this output is connected to the XAUI_MDC_RESET input. It
is active High.
Input
Output Software generated reset (register 0.15) synchronized with TX_CLK. This
signal is held High whenever low power mode is enabled. This signal is
asynchronously asserted by the software generated reset and
synchronously deasserted with EPCS_TXCLK[0]. It is active high. Typically,
this output is connected to the XAUI_TX_RESET input.
Input
XAUI_RX_RESET_ OUT[3:0]
Asynchronously resets all the MDIO registers to their default values. This pin
is connected directly to set/reset ports of all flops in the MMD_MDC clock
domain. Typically, this input is connected to the XAUI_MDC_RESET_OUT
signal.
Resets the XAUI Transmit block. This pin is connected directly to the
set/reset ports of all flops in the EPCS_TXCLK[0] clock domain. It is active
high. Typically, this is connected to the XAUI_TX_RESET_OUT signal.
Output Software generated resets (register 0.15) synchronized with the
XAUI_RX_CLK[3:0] clocks. These signals are held high whenever low
power mode is enabled. These signals are asynchronously asserted by the
software-generated reset and synchronously deasserted with the
XAUI_RX_CLK[3:0]. It is active high.
XAUI_RX_RESET
Input
Resets the XAUI extender block. These pins are connected to set/reset
ports of all flops in the corresponding XAUI_RX_CLK[3:0] clock domain.
APB_S_PRESET_N
Input
APB asynchronous reset to all SERDESIF APB registers.
Design Consideration
This section provides instruction for implementing XAUI in SmartFusion2 and IGLOO2 devices. It
includes the following sections:
120
•
Using the MDIO Interface
•
XAUI IP Block Timing Diagram
•
XAUI Mode Loopback Test Operation
•
Using MMD Status Registers
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Using the MDIO Interface
The MDIO interface allows users to access the MDIO registers. Figure 3-11 shows a system block
diagram for connecting XAUI IP and an MDIO manageable device (MMD) to a station management entity
(STA). In this case, the STA is A-XGMAC. The use of the MDIO interface is not required. If the register of
the MDIO are not required for the user application the MDIO ports can be tied off inactive.
To External Device
Fabric
SERDESIF
XAUI_MMD_MDI_EXT
10 Gig
MAC
(STA)
XAUI_MMD_MDO
XAUI_MMD_MDI
XAUI Extender
XAUI_MMD_MDOE_IN
XAUI_MMD_MDI
XAUI_MMD_MDOE_IN
XAUI_MMD_MDO
XAUI_MMD_MDOE
Figure 3-11 • MDIO System Block Diagram
Revision 5
121
XAUI
XAUI IP Block Timing Diagram
The following sections show the timing relations between clock and data for the three interfaces of the
XAUI extender.
•
Transmit Interface
•
Receive Interface
•
MMD Read Timing
•
MMD Write Timing
Refer to the DS0451: IGLOO2 and SmartFusion2 Datasheet for the detailed timing numbers.
Transmit Interface
Figure 3-12 shows the XGMII transmit timing diagram. The transmit data and control signals are source
centered on the transmit clock per requirements of IEEE 802.3ae, clause 46. Furthermore, all four lanes
of data are synchronous with a common clock.
XAUI_TX_CLK
XAUI_TXD[31:0]
S
D
XAUI_TXC[3:0]
0x1
0x0
D
D
XAUI_TXD[64:32]
XAUI_TXC[7:4]
D
D
D
D
I
0xF
D
0x0
D
D
T
I
0xC
0xF
Figure 3-12 • Transmit XGMII Interface Timing Diagram
Receive Interface
Figure 3-13 on page 123 shows the XGMII receive timing diagram. The receive data and control signals
are edge-aligned with the receive clock XAUI_RX_CLK. To be fully compliant with IEEE 802.3ae, the
data and control signals are normally source centered on XAUI_RX_CLK. However, in the SmartFusion2
and IGLOO2 FPGAs, the XAUI extender is interfaced with a FPGA 10G MAC in the fabric within the
same device, eliminating the need to source center the data. All four lanes of data are synchronous with
the common clock XAUI_RX_CLK. The user must check timing to make sure the data is captured by the
FPGA 10G MAC in the fabric.
122
R e vi s i o n 5
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XAUI_RX_CLK
XAUI_RXD[31:0]
S
D
XAUI_RXC[3:0]
0x1
0x0
D
D
XAUI_RXD[64:32]
XAUI_RXC[7:4]
D
D
D
D
I
I
0xF
D
D
D
0x0
T
0xC
I
I
0xF
Figure 3-13 • XGMII Interface Receive Timing Diagram
MMD Read Timing
Figure 3-14 shows the timing diagram for an MDIO register read. The XAUI_MMD_MDO signal is
controlled by XAUI_MMD_MDOE.
<read/read inc>
<Z>
<0>
XAUI_MMD_MDC
XAUI_MMD_MDO
XAUI_MMD_MDOE
Figure 3-14 • MDIO Interface Read Timing Diagram
MMD Write Timing
Figure 3-15 shows the timing diagram for MDIO registers. XAUI_MMD_MDOE must not be asserted
during a write operation. Refer to the IEEE 802.3ae specification, clause 45, for a complete definition.
<idle>
<0>
<0>
XAUI_MMD_MDC
XAUI_MMD_MDI
XAUI_MMD_MDOE
Figure 3-15 • MDIO Interface Read Timing Diagram
Revision 5
123
XAUI
XAUI Mode Loopback Test Operation
The XAUI extender block can be placed in loopback mode for testing purposes. It can also be placed in
multiple loopback operations.
XAUI—Near End Loopback Test
Bit 14 of Reg00 can be used to enable the loopback. When loopback mode is enabled, the transmit
output is shunted back into the receive input. For loopback mode to work appropriately, the transmit clock
is also shunted back into the receive clock inputs. The loopback test data must be fed from the XGMII
interface available to fabric.
XAUI—Far End Loopback Test
In the XAUI far end loopback test, the transmit interface of the XAUI extender block is connected to the
EPCS interface of the SERDES block. In this case, the SERDES block is put in loopback mode, where
serial data from transmit side is fed into the serial receive interface. Along with verifying the transmit and
receive block of the XAUI extender, it also tests the PMA data path validity. The XAUI_ LOOPBACK_IN
signal is used for this mode.
124
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Using MMD Status Registers
There are two MMD status registers: XS status 1 (Reg01) and XS status 2 (Reg07).
Upon the deassertion of the reset signal on the XAUI block, the initial state of the two status registers
indicate a fault condition. This initial false fault condition must be ignored, and a read operation must be
performed on the XS status 1 and XS status 2 registers to clear the false fault-status. After this, when a
real fault condition happens (for example, when a link is down), the fault register does indicate it properly,
as expected.
MDIO Register Map
Table 3-10 lists the MDIO registers.
Table 3-10 • MDIO Registers
Register Name
Register Address
Read /
Writable
Device
Address
Description
Reg00
0x0000
R/W
04h/05h
XS control 1 register
Reg01
0x0001
R
04h/05h
XS status 1 register
Reg02
0x 0002
R
04h/05h
XS device identifier register Low
Reg03
0x0003
R
04h/05h
XS device identifier register High
Reg04
0x0004
R
04h/05h
XS speed ability register
Reg05
0x0005
R
04h/05h
XS devices in package register Low
Reg06
0x0006
R
04h/05h
XS devices in package register High
–
0x0007
NA
04h/05h
Reserved
Reg07
0x0008
R
04h/05h
XS status 2
–
0x0009 to 0x000d
NA
04h/05h
Reserved
Reg08
0x000e
R
04h/05h
XS package identifier register Low
Reg09
0x000f
R
04h/05h
XS package identifier register High
–
0x0010 to 0x0017
NA
04h/05h
Reserved
Reg10
0x0018
R
04h/05h
10G XGXS lane status register
Reg11
0x0019
R/W
04h/05h
10G XGXS test control register
–
0x001a to 0x7fff
NA
04h/05h
Reserved
Reg12
0x8000
R/W
04h/05h
Vendor-specific reset Lo 1
Reg13
0x8001
R/W
04h/05h
Vendor-specific reset Lo 2
Reg14
0x8002
R/W
04h/05h
Vendor-specific reset Hi 1
Reg15
0x8002
R/W
04h/05h
Vendor-specific reset Hi 1
–
0x8004 to 0xffff
NA
04h/05h
Reserved
Revision 5
125
XAUI
Table 3-11 gives bit definitions for the XS Control 1 Register.
Table 3-11 • Reg00
Bit
Number
15
Name
Reset
Reset
Value
0x0
Description
The XAUI extender block is reset when this bit is set to 1. It returns to 0 when
the reset is complete (self-clearing).
1: Block reset
0: Normal operation
14
Loopback
0x0
The XAUI extender block loops the transmit signal back into the receiver.
0: Disable loopback
1: Enable loopback
13
Speed selection
0x1
This bit is for speed selection and is set to 1'b1 for compatibility with clause 22.
0: Unspecified
1: 10 Gbps and above
Any write to this bit is ignored.
12
Reserved
0x0
Reserved
11
Low power mode
0x0
When set to 1, the SERDES block is placed in a Low power mode. Set to 0 to
return to normal operation.
0: Normal operation
1: Low power mode
[10:7]
Reserved
0x0
Reserved
6
Speed selection
0x1
This bit is set to 1'b1 in order to make compatible with clause 22.
0: Unspecified
1: 10 Gbps and above
[5:2]
Speed selection
0x0
The speed of the PMA/PMD may be selected using bits 5 through 2.
1 x x x: Reserved
x 1 x x: Reserved
x x 1 x: Reserved
0 0 0 1: Reserved
0 0 0 0: 10 Gbps
Any write to this bit is ignored.
[1:0]
126
Reserved
0x0
–
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 3-12 gives bit definitions for the XS Status 1 register.
Table 3-12 • Reg01
Bit
Number
2
Name
PHY/DTE
transmit/receive link
status
Reset
Value
0x0
Description
When read as a one, the receive link is up.
0: Link down
1: Link up
The receive link status bit is implemented with latching low behavior.
1
Low power ability
0x1
When read as a one, it indicates that the Low power feature in
supported.
10: Low power not supported
1: Low power is supported
0
Reserved
0x0
–
Table 3-13 gives bit definitions for the XS Device Identifier Low register.
Table 3-13 • Reg02
Bit
Number
[15:0]
Name
Organizationally unique
identifier (OUI)
Reset
Value
0x0
Description
Reg02 and Reg03 provide a 32-bit value, which may constitute a
unique identifier for a particular type of SERDES. The identifier is
composed of the 3rd through 24th bits of the OUI assigned to the
device manufacturer by the IEEE, a 6-bit model number, and a 4-bit
revision number.
Reg02 sets bits [3:18] of the OUI. Bit 3 of the OUI is located in bit 15 of
the unique identifier of the register, and bit 18 of the OUI is located in bit
0 of the register.
Table 3-14 give bit definitions for the XS Device Identifier High register.
Table 3-14 • Reg03
Bit
Number
Name
Reset
Value
Description
[15:10]
OUI
0x0
Bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of the
register, and bit 24 of the OUI is located in bit 10 of the register.
[9:4]
Manufacturer model
number
0x0
Bits [5:0] of the manufacturer model number. Bit 5 of the model
number is located in bit 9 of the register, and bit 0 of the model number
is located in bit 4 of the register.
[3:0]
Revision number
0x0
Bits [3:0] of the manufacturer model number. Bit 3 of the revision
number is located in bit 3 of the register, and bit 0 of the revision
number is located in bit 0 of the register.
Revision 5
127
XAUI
Table 3-15 give bit definitions for the XS Speed Ability register.
Table 3-15 • Reg04
Bit
Number
Name
Reset
Value
Description
[15:10]
Reserved
0x0
Reserved
[9:4]
10g capable
0x1
0: Not 10g capable
0: 10g capable
Table 3-16 gives definitions for the XS Devices in Package Low register.
Table 3-16 • Reg05
Bit
Number
Name
Reset
Value
[15:6]
Reserved
0x0
5
DTE XS present
0x1
Description
Reserved
0: DTE XS not present in the package
1: DTE XS present in the package
4
PHY XS present
0x0
0: PHY XS not present in the package
1: PHY XS present in the package
3
PCS present
0x0
0: PCS not present in the package
1: PCS present in the package
2
WIS present
0x0
0: WIS not present in the package
1: WIS present in the package
1
PMD/PMA present
0x0
0: PMD/PMA not present in the package
1: PMD/PMA present in the package
0
Clause 22 register
present
0x0
0: Clause 22 registers not present in the package
1: Clause 22 registers present in the package
Table 3-17 gives bit definitions for the XS Devices in Package High register.
Table 3-17 • Reg06
Bit
Number
15
14
[13:0]
128
Name
Reset
Value
Vendor-specific device2
present
0x0
Vendor-specific device1
present
0x0
Reserved
0x0
Description
0: Vendor-specific device 2 not present
1: Vendor-specific device 2 present
0: Vendor-specific device 1 not present
1: Vendor-specific device 1 present
Reserved
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 3-18 gives bit definitions for the XS Status 2 register.
Table 3-18 • Reg07
Bit
Number
[15:14]
Name
Device present
Reset
Value
0x0
Description
10: Device responding at this address.
11: No device responding at this address.
01: No device responding at this address.
00: No device responding at this address.
[13:12]
Reserved
0x0
Reserved
11
Transmit fault
0x0
0: No transmit fault
1: Transmit fault
Latched High, clear on read
10
Receive fault
0x0
0: No receive fault
1: Receive fault
Latched High, clear on read
[9:0]
Reserved
0x0
Reserved
Table 3-19 gives bit definitions for the XS Package ID Low register
Table 3-19 • Reg08
Bit
Number
[15:0]
Name
OUI
Reset
Value
0x0
Description
Reg08 and Reg 09 provide a 32-bit value, which may constitute a unique
identifier for a particular type of package that the SERDES is instantiated
within. The identifier is composed of the 3rd through 24th bits of the OUI
assigned to the package manufacturer by the IEEE, plus a 6-bit model
number, and a 4-bit revision number. Reg08 sets bits [3:18] of the OUI. Bit 3
of the OUI is located in bit 15 unique identifier of the register, and bit 18 of the
OUI is located in bit 0 of the register.
Table 3-20 gives bit definitions for the XS Package ID High register.
Table 3-20 • Reg09
Bit
Number
Name
Reset
Value
Description
[15:10]
OUI
0x0
Bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of the register, and
bit 24 of the OUI is located in bit 10 of the register.
[9:4]
Manufacturer
model number
0x0
Bits [5:0] of the manufacturer model number. Bit 5 of the model number is
located in bit 9 of the register, and bit 0 of the model number is located in bit 4
of the register.
[3:0]
Revision number
0x0
Bits [3:0] of the manufacturer model number. Bit 3 of the revision number is
located in bit 3 of the register, and bit 0 of the revision number is located in bit
0 of the register.
Revision 5
129
XAUI
Table 3-21 gives bit definitions for the XGXS Lane Status register.
Table 3-21 • Reg10
Bit
Number
Name
Reset
Value
[15:13]
Reserved
12
PHY/DTE XGXS lane
alignment status
0x0
Pattern testing ability
0x1
11
–
Description
Reserved
0: Lanes not aligned
1: Lanes aligned
0: (PHY/DTE)XS is unable to generate test patterns
1: (PHY/DTE)XS is able to generate test patterns
10
PHY XGXS loopback
ability
[9:4]
Reserved
3
Lane3 synchronized
0x1
0: PHY XGXS does not has the ability to perform a loopback
1: PHY XGXS has the ability to perform a loopback
–
0x0
Reserved
When read as a one, this register indicates that the receive Lane3 is
synchronized.
0: Lane3 is not synchronized
1: Lane3 is synchronized
2
Lane2 synchronized
0x0
When read as a one, this register indicates that the receive Lane2 is
synchronized.
0: Lane2 is not synchronized
1: Lane2 is synchronized
1
Lane1 synchronized
0x0
When read as a one, this register indicates that the receive Lane1 is
synchronized.
0: Lane1 is not synchronized
1: Lane1 is synchronized
0
Lane0 synchronized
0x0
When read as a one, this register indicates that the receive Lane1 is
synchronized.
0: Lane0 is not synchronized
1: Lane0 is synchronized
Table 3-22 gives bit definitions for the XGXS Test Control register.
Table 3-22 • Reg11
Bit
Number
Name
[15:3]
Reserved
2
Transmit test pattern
enabled
Reset
Value
–
0x0
Description
Reserved
When this bit is set to a one, pattern testing is enabled on the transmit
path.
0: Transmit/receive test pattern disabled
1: Transmit/receive test pattern enabled
[1:0]
Test pattern select
0x0
The test pattern is used when enabled pattern testing is selected using
these bits:
00: High frequency test pattern
01: Low frequency test pattern
10: Mixed frequency test pattern
11: Reserved
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R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 3-23 gives bit definitions for the Vendor-Specific Reset Low 1 register.
Table 3-23 • Reg12
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Lo 1 0x0000 General purpose registers that are connected to the output port.
XAUI_VNDRRESLO[15:0]. Typically used for external device control.
Table 3-24 gives bit definitions for the Vendor-Specific Reset Low 2 register.
Table 3-24 • Reg13
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Lo 2 0x0000 General purpose registers that are connected to the output port.
XAUI_VNDRRESLO[31:16]. Typically used for external device control.
Table 3-25 gives bit definitions for the Vendor-Specific Reset High 1 register.
Table 3-25 • Reg14
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Hi 1 0xFFFF General purpose registers that are connected to the output port.
XAUI_VNDRRESLI[15:0]. Typically used for external device control.
Table 3-26 gives bit definitions for the Vendor-Specific Reset High 2 register.
Table 3-26 • Reg15
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Hi 2 0xFFFF General purpose registers that are connected to the output port.
XAUI_VNDRRESLI[31:16]. Typically used for external device control.
SERDES Block System Register Configurations for XAUI Mode
The SmartFusion2 and IGLOO2 SERDESIF block subsystem has three regions of configuration and
status registers:
•
SERDES Block System Register
•
Bridge Register Space
•
SERDES Block–I/O Signal Interface
These registers are accessed by the 32-bit APB bus. Refer to the “SERDESIF Block System Register”
for details. In XAUI mode, the PCIe core registers are not used. Only the SERDES block system
registers and SERDES block register are used for XAUI mode. The XAUI block also has MDIO registers,
which are accessed via MDIO interface signals.
The SERDESIF block system registers occupy 1 KB of the configuration memory map. However, in XAUI
mode, only subsets of the register are used. SERDES registers can be referenced in the “SERDESIF
Block System Register”.These registers can be updated through the 32-bit APB interface after power-up.
Revision 5
131
XAUI
List of Changes
The following table shows important changes made in this document for each revision.
Date
Revision 4
(August 2015)
Changes
Updated Table 3-1 (SAR 69996).
Updated Figure 3-3, Figure 3-4, and Figure 3-9 (SAR 69885).
Page
105
108, 109,
and 118
Updates are made to maintain the style and consistency of the document.
NA
Added "SERDES Block System Register Configurations for XAUI Mode" section.
131
Revision 3
(January 2015)
Consolidated SmartFusion2 and IGLOO2 User Guides.
NA
Revision 2
(July 2014)
No updates
NA
132
R e vi s i o n 5
4 – EPCS Interface
Introduction
This chapter describes using the EPCS interface in the SmartFusion2 and IGLOO2 FPGA SERDESIF
blocks.
The SERDESIF block integrates the functionality of supporting multiple high speed serial protocols, such
as peripheral component interconnect express (PCIe) 2.0, extended attachment unit interface (XAUI),
and EPCS interfaces as shown in Figure 4-1. The SERDESIF block can be configured in various modes,
including EPCS mode. In EPCS mode, Lane0 and Lane1 (L01) EPCS interface and Lane2 and Lane3
(L23) EPCS interface are exposed to the fabric and configures serializer/de-serializer (SERDES) in
physical media attachment (PMA) only mode. The PCIe and XAUI PCS logic in SERDES is bypassed,
however, the PCS logic can be implemented in the FPGA fabric and the EPCS interface signals of the
SERDES block can be connected. This allows any user-defined high-speed serial protocol to be
implemented in the SmartFusion2 and IGLOO2 device.
TU0570: Implementing a SmartFusion2 and IGLOO2 SERDES EPCS Protocol Design Tutorial
demonstrates the features capabilities.
SPI I/O Multi-Standard User I/O (MSIO)
JTAG I/O
SPI x 2
MMUART x 2
I2C x 2
Timer x 2
System Controller
AES256
SHA256
ECC
NRBG
SRAM-PUF
Microcontroller Subsystem (MSS) for SmartFusion2
CAN
APB
HS USB
OTG ULPI
PDMA
SYSREG
Multi-Standard User I/O (MSIO)
FPGA
GA Fabric
AHB
Mi SRAM
Micro
(64x18)
Micro SRAM
(64x18)
AHB
TSEMAC
eSRAM
HPDMA
SMC_FIC Config
AHB
Large SRAM
(1024x18)
Large SRAM
(1024x18)
AXI/AHB
Math Block
MACC (18x18)
Multi-Standard User I/O (MSIO)
Interrupts
FIC_1
SERDES
I/O
MSS/HPMS
DDR Controller
+ PHY
AHB Bus Matrix (ABM)
FIC_0
PMA LANE0
PMA Control
Logic
EPCS
LANE
0:1
LANE[0:1] Calibration
FIIC
COMM_BLK
SERDES
I/O
DDR
Bridge
eNVM
RTC
OR
PCIe PCS
LANE0
OR
High Performance Memory Subsystem (HPMS) for IGLOO2
WDT
In-Application
Programming
Flash*Freeze
sh Freeze
DDR User I/O
PMA LANE1
PCIe PCS
LANE1
PMA Control
Logic
PIPE
Controller
APB Bus
SERDES
I/O
PMA LANE2
PMA Control
Logic
PCIe PCS
LANE2
LANE[2:3] Calibration
SERDES
I/O
PMA LANE3
PMA Control
Logic
XAUI
Extender
PCIe PCS
LANE3
EPCS
LANE
2:3
Math Block
MACC (18x18)
FPGA Fabric Interface
Config
AXI/AHB/XGXS
Serial Controller 0
(PCIe, XAUI/XGXS)
+ Native SERDES
Config
OSCs
Serial 0 I/O
AXI/AHB/XGXS
Serial Controller 1
(PCIe, XAUI/XGXS)
+ Native SERDES
Serial 1 I/O
Config
PLLs
APB Slave
Register Space
Interface
AXI/AHB
Fabric DDR
Controller + PHY
Standard Cell /
SEU Immune
EPCS_LANE[0:3]
Parallel Intf
User Protocol
IP
Flash Based /
SEU Immune
DDR User I/ O
Figure 4-1 • SmartFusion2 and IGLOO2 SERDESIF Block Diagram
Features
The main features of the EPCS interface in SmartFusion2 and IGLOO2 are:
•
Up to 20-bit Rx/Tx EPCS Interface to the FPGA fabric
•
Allows the FPGA fabric to directly access the PMA block bypassing the PCIe PCS block in
SERDES and thus allow implementing any serial protocol for up to four lanes using the PCS logic
in the fabric
•
Allows the FPGA fabric to access the SERDES register through the APB interface and allows
programming various PMA settings, including programming of the SERDES Tx PLL and Rx PLLs
settings
Revision 5
133
EPCS Interface
Device Support
The SmartFusion2 or IGLOO2 family has a number of devices available. Table 4-1 shows the total
number of SERDESIF blocks available in each SmartFusion2 and IGLOO2 device that can be configured
to support the EPCS interface.
Table 4-1 • Available SERDESIF Blocks in SmartFusion2 and IGLOO2 Devices that support EPCS
M2S/M2GL
005
M2S/M2GL
010
M2S/M2GL
025
M2S/M2GL
050
M2S/M2GL
060
M2S/M2GL
090
M2S/M2GL
150
SERDESIF
available for
EPCS
0
1
1
Up to 2
1
1
Up to 4
SERDES
Lanes
0
4
4
8
4
4
16
Note: 1. The specified number of SERDESIF blocks varies depending on the device package.
2. M2S/M2GL060/090 application interfaces have dual controller capability supporting up to two x1 or x2 PCIe
endpoints within a SERDESIF.
134
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
SmartFusion2/IGLOO2 EPCS Interface
The SERDESIF block can be configured in EPCS mode.This allows the FPGA fabric to directly access
the SERDES block. The PCS logic of SERDES is bypassed in this mode to allow user-defined protocol to
be supported from the FPGA fabric. Figure 4-2 shows an application example using the EPCS interface.
Refer to Figure 4-1 on page 133 for the EPCS interface signals.
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Figure 4-2 • Application Using SERDESIF EPCS Interface
Revision 5
135
EPCS Interface
The SERDESIF block can be configured to operate in two different modes: Single-protocol mode and
Multi-protocol mode. In Single-protocol mode, the EPCS interface can be configured as x4 or x2 or x1
lane. In Multi-protocol mode, the SERDESIF block can operate using dedicated Lane2 and Lane3 in
EPCS mode, while Lane1 and Lane2 are dedicated to the PCIe protocol link implementation. Table 4-2,
Table 4-3, and Table 4-6 on page 143 show a detailed description of the EPCS interface usage in Singleprotocol and Multi-protocol mode.Multi-EPCS protocol allows up to all four Lanes to be used
independently for customized protocols such as SGMII or JESD204b.
Table 4-2 • EPCS Interface Usage in Single-Protocol and Multi-Protocol Mode
Protocol
Mode
Description
Single-protocol
EPCS Protocol
Configured to use maximum 4 lanes. In EPCS mode, the user- defined
serial protocol implemented within the FPGA fabric is connected though the
EPCS interface.
Multi-protocol
PCIe protocol and
EPCS protocol
Configured to use x2 and x1 lane in PCIe mode. (lane0 and lane1 are used
for the PCIe link). Any user-defined/other serial protocol connected to the
EPCS interface uses lane2 and lane3 for this purpose.
Multi-EPCS
–
Configure multiple independent EPCS protocols across Lane[0:1] and
Lane[2:3].
Table 4-3 • EPCS Interface and SERDES Lane Mapping in Single-Protocol Mode
Single
Protocol
EPCS Mode
Lane0
Lane1
Lane2
Lane3
EPCS
–
–
–
EPCS
EPCS
–
–
–
–
–
EPCS
–
–
EPCS
EPCS
EPCS
EPCS
EPCS
EPCS
Note: These are only examples above. Single non-bonded EPCS protocols can occupy any lanes.
Table 4-4 • EPCS Interface and SERDES Lane Mapping in Multi-Protocol Mode
PHY-MODE EPCS 
Multi- Protocol
PHYSICAL SERDES LANES/LOGICAL LANES
LANE-0
LANE-1
LANE-2
LANE-3
Protocol
Protocol
Protocol
Protocol
PCIe
*
EPCS
EPCS
PCIe
PCIe
EPCS
EPCS
*
PCIe
EPCS
EPCS
PCIe
PCIe
EPCS
EPCS
PCIe_0
PCIe_1
EPCS
EPCS
M2S/M2GL010/025/050/150
Multi Protocol
PHY – Mode
(PCIe link Non-Reversed-Mode)
Multi Protocol
PHY – Mode (PCIe link Reversed-Mode)
M2S/M2GL060/090
Multi and Dual PCIe Protocol
PHY – Mode (Non-Reversed-Mode)
136
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 4-4 • EPCS Interface and SERDES Lane Mapping in Multi-Protocol Mode (continued)
PHY-MODE EPCS 
Multi- Protocol
PHYSICAL SERDES LANES/LOGICAL LANES
LANE-0
LANE-1
LANE-2
LANE-3
Protocol
Protocol
Protocol
Protocol
Notes:
1. * refers to unused lanes.
2. When operating the EPCS mode in x2 or x4 the lanes are not bound together. The x2 and x4 nomenclature
simple indicates the number of lanes in the SERDESIF which are active. The High Speed Serial Interface
Configurator allows the user to select rate of each channel independently.
Getting Started
This section provides an overview of how to configure the SERDESIF block in EPCS mode and
instructions for using the EPCS interface.
The following sections show how to use SERDESIF in EPCS mode by completing the following steps:
•
Using High Speed Serial Interfaces Configurator in EPCS Mode
•
Simulating SERDESIF in EPCS Mode
•
Create an Application in EPCS Mode
Using High Speed Serial Interfaces Configurator in EPCS Mode
The high speed serial interfaces configurator (SERDESIF configurator) in the Libero SoC software
allows configuring the SERDESIF block with EPCS mode in Single-protocol mode or 
Multi-protocol mode. Refer to Figure 4-3 on page 138 for setting SERDESIF configurator in the EPCS
with Single-protocol mode, that shows configuring all 4 lanes in EPCS mode. Refer to Figure 4-4 on
page 139 for setting EPCS with Multi-protocol mode. EPCS data rates use a CUSTOM EPCS option
within the SERDESIF configurator as shown in Figure 4-4 on page 139. This feature allows designers to
opportunity to craft customized SERDES implementations based on reference clock and data widths.
This implementation allows for data rate targeted applications to be easily setup while the GUI
Configurator manages the limitations of the SERDESIF block.
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137
EPCS Interface
Figure 4-3 • EPCS Mode Setting (Single-protocol mode) in SERDESIF Configurator
SERDESIF EPCS_TX/RXDATA width supports a maximum data bus width of 20-bits. The SERDESIF
supports several options for the data bus widths such as 4, 5, 8, 10, 16, and 20 bit. These are all valid
options based on the data rate.
EPCS interface is always modeled as a 20-bit bus. When using less than 20-bits, the most recently
received word is nearer RxDO[19] than it is RxDO[0], so PCS words are justified starting from RxDO[19],
not RxDO[0]. Such is the case for all supported bus widths. Users need to split or slice the ports on the
module to only connect the necessary ports. For RX bus orientation is always [n-1:0]. Whereas TX, it’s
orientation is upper towards lower. User must be cautious when the width is not 20 such as a bus width of
8 for instance.
Table 4-5 • Data Bus Widths
Bus Width
RX Data Bus Description
TX Data Bus Description
20-bit
[19:0]
[19:0]
16-bit
[19:4]
[15:0]
10-bit
[19:10]
[9:0]
8-bit
[19:12]
[7:0]
5-bit
[19:15]
[4:0]
4-bit
[19:16]
[3:0]
138
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Figure 4-4 • EPCS Mode Setting (Multi-protocol mode) in SERDESIF Configurator
Revision 5
139
EPCS Interface
Figure 4-5 • EPCS Custom Speed Mode in SERDESIF Configurator
Following are the brief descriptions of the configuration options (refer to the "SERDESIF Block" chapter
on page 10 for details).
Protocol Selection
The following settings are used for protocol selection:
•
Protocol 1 or Protocol 2 Type–Select protocol settings. Select EPCS or PCIe from the drop-down
based on Single-protocol or Multi-protocol mode.
•
Number of Lanes–Select number of lanes used.
•
Speed–Select the lane speed.
•
Protocol 1 or Protocol 2 PHY reference Clock–Select the inputs for the PHY reference clock
selection. Refer to the "SERDES Reference Clock Selection" section on page 146 for details on
PHY reference clock selection.
Simulating SERDESIF in EPCS Mode
The SERDESIF block, when configured in EPCS requires the RTL simulation model which is selectable
in the High Speed Serial Interfaces Configurator. Refer to the SERDESIF BFM Simulation Guide for
details.
140
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Create an Application in EPCS Mode
A complete application in SmartFusion2 and IGLOO2 require a properly set SERDESIF Configurator and
then to generate the SERDESIF block in EPCS mode. Figure 4-6 shows SERDESIF block configured in
EPCS mode in all four lanes. Libero promotes the SERDES I/Os to top level and it exposes the EPCS
interface for each lane into the FPGA fabric; the SERDESIF block exposes the APB3 interface to the
FPGA fabric as well.
Figure 4-6 • Libero SoC Showing SERDESIF in EPCS Mode
Fabric logic or FPGA IP is required to be connected to the EPCS interface as shown in Figure 4-2 on
page 135.
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141
EPCS Interface
SERDESIF Architecture in EPCS Mode
This section provides an overview of the SERDESIF in EPCS mode. The following topics are covered:
•
SERDESIF Block in EPCS Mode
•
SERDESIF Fabric Interface in EPCS Mode
SERDESIF Block in EPCS Mode
Figure 4-7 shows the SERDESIF block internal architecture during EPCS Single-protocol mode. EPCS
mode facilitates the use of four lanes of the SERDES which are exposed to the FPGA fabric with a 20-bit
EPCS interface per lane. EPCS mode gives full control over the PLL configurations in the SERDES using
the APB interface to generate the required serial link frequencies. Figure 4-7 shows the SERDES block
in EPCS mode. The EPCS interface is suitable for running any protocol, including Ethernet MAC and
PCS in the FPGA fabric. The PMA macro is used for implementing any standard (SRIO, JESD204 and
so on) or user-defined serial protocol.
SERDES
SERDES
I/O
PMA
Ch0
PMA
Control
Logic
SERDES
I/O
PMA
Ch1
PMA
Control
Logic
APB Bus
SERDES
I/O
PMA
Ch2
SERDES
I/O
PMA
Ch3
PMA
Control
Logic
PMA
Control
Logic
Figure 4-7 • SERDES in EPCS Mode
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To Lane01
and Lane23
EPCS Interface
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
SERDESIF Fabric Interface in EPCS Mode
The SERDESIF in EPCS mode interfaces with the fabric and differential I/O pads. The following
sections list the fabric interfaces:
•
EPCS interface signals
•
APB interface signals
Table 4-6 • SERDESIF Block – EPCS Interface
Port
EPCS_0_RESET_N
EPCS_1_RESET_N
EPCS_2_RESET_N
EPCS_3_RESET_N
EPCS_0_READY
EPCS_1_READY
EPCS_2_READY
EPCS_3_READY
EPCS_0_PWRDN
EPCS_1_PWRDN
EPCS_2_PWRDN
EPCS_3_PWRDN
EPCS_0_TX_OOB
EPCS_1_TX_OOB
EPCS_2_TX_OOB
EPCS_3_TX_OOB
EPCS_0_TX_VAL
EPCS_1_TX_VAL
EPCS_2_TX_VAL
EPCS_3_TX_VAL
EPCS_0_TX_DATA[19:0]
EPCS_1_TX_DATA[19:0]
EPCS_2_TX_DATA[19:0]
EPCS_3_TX_DATA[19:0]
Type
Input
Description
Active low PHY RESET. These inputs reset the associated SERDES logic for
each lane. The resets are logically ordered with the power up signal.
Output
PHY ready: This signal is asserted when the PHY has completed the
calibration sequence for each specific lane. This signal can be used to
release the reset for the external PCS and controller, start transmitting data to
the PMA, or any other purpose.
Input
PHY power-down: This signal is used to put the PMA in power-down state
where RX CDR PLL is bypassed and other low power features are applied to
the PMA. When exiting power-down, no calibration is required and the link
can be operational much faster than when using the EPCS_X_TX_OOB or
EPCS_X_RESETN signals. These signals are active high.
Input
PHY transmit out-of-band (OOB): This signal is used to load electrical idle III
in the TX driver of the PMA macro. It can be used for serial advanced
technology attachment (SATA) as part of the sequencing for transmitting very
short OOB signaling. These signals are active high. Minimum transfer burst
size is 23 symbols.
Input
PHY transmit valid: This signal is used to transmit valid data. If deasserted,
the PMA macro is put in electrical idle 1. It can be used for protocols requiring
electrical idle (SATA) and must also be deasserted as long as
EPCS_X_READY is not asserted. This signal must be generated one clock
cycle earlier than corresponding EPCS_TXDATA signals. These signals are
active high.
Input
PHY transmit data: This signal is used to transmit data. This signal is always
20 bits per lane, but the SERDESIF only uses the number of bits selected in
the High Speed Serial Interfaces Configurator.
EPCS_0_TX_CLK
EPCS_1_TX_CLK
EPCS_2_TX_CLK
EPCS_3_TX_CLK
PHY transmit clock: This clock signal is generated by the TX PLL in the PMA
macro and must be used by the external PCS logic to provide data on
Output
EPCS_X_TX_DATA.
EPCS_0_TX_RESET_N
EPCS_1_TX_RESET_N
EPCS_2_TX_RESET_N
EPCS_3_TX_RESET_N
PHY clean active low reset on the TX clock. This signal is a clean version of
the EPCS_X_RESET_N signal, which has a clean deassertion timing versus
Output
EPCS_TXCLK.
EPCS_0_RX_CLK
EPCS_1_RX_CLK
EPCS_2_RX_CLK
EPCS_3_RX_CLK
PHY receive clock: This clock signal is generated by the RX PLL in the PMA
macro and must be used by the external PCS logic to provide data on
Output
EPCS_X_RX_DATA.
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143
EPCS Interface
Table 4-6 • SERDESIF Block – EPCS Interface (continued)
Port
EPCS_0_RX_RESET_N
EPCS_1_RX_RESET_N
EPCS_2_RX_RESET_N
EPCS_3_RX_RESET_N
EPCS_0_RX_VAL
EPCS_1_RX_VAL
EPCS_2_RX_VAL
EPCS_3_RX_VAL
Type
Description
PHY clean active low reset on EPCS_X_RX_CLK.
Output This signal is a clean version of the EPCS_X_RESET_N signal, which has a
clean deassertion timing versus EPCS_X_RX_CLK.
Output
PHY receive valid: This signal is used to signal receive valid data. It
corresponds to the two conditions completed by the PMA control logic:
•
Receiver detects incoming data (not in electrical idle)
•
CDR PLL is locked to the input bit stream in fine grain state
EPCS_0_RX_IDLE
EPCS_1_RX_IDLE
EPCS_2_RX_IDLE
EPCS_3_RX_IDLE
PHY Receive Idle: This signal is used to signal an electrical idle condition
detected by the PMA control logic. Note that this signal is generated on
Output
EPCS_X_TX_CLK of the selected lane.
EPCS_0_RXDATA[19:0]
EPCS_1_RXDATA[19:0]
EPCS_2_RXDATA[19:0]
EPCS_3_RXDATA[19:0]
PHY receive data: This signal is always 20 bits per lane and the external PCS
can use any number of these bits for its application. The SERDESIF only
Output
uses the number of bits selected in the High Speed Serial Interfaces
Configurator.
EPCS_0_TX_CLK_STABLE
EPCS_1_TX_CLK_STABLE
EPCS_2_TX_CLK_STABLE
EPCS_3_TX_CLK_STABLE
Output
EPCS_0_RX_ERR
EPCS_1_RX_ERR
EPCS_2_RX_ERR
EPCS_3_RX_ERR
144
Input
Active high to signal to indicate EPCS interface Lane_X clock is stable,
meaning when TX PLL is locked.
EPCS interface Lane_X receiver error is detected when using the external
logic. When there are many receive errors such as, invalid 8b/10b code or
disparity error, then the asynchronous signal can be used to cause the
CDRPLL to switch back to the frequency lock phase. These pins can be
hardwired to 0 and rely only on Electrical Idle detection to switch the CDR
PLL back to frequency lock state.
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Reset and Clocks
This section covers the functional aspects of the reset and clock circuitry inside the SERDESIF block in
EPCS mode. The following topics are covered:
•
EPCS Mode Clocking
•
EPCS Mode Reset Network
EPCS Mode Clocking
When the SERDESIF block is configured in EPCS mode, it has multiple clock inputs and outputs. This
section describes the EPCS clocking scheme.
SERDESIF Clock Network in EPCS
Figure 4-8 shows the SERDESIF clock network in EPCS mode.
In EPCS mode, data is exchanged between the fabric and SERDESIF. Figure 4-8 shows the
SERDESIF clock network in EPCS mode. The SERDES PMA has two PLLs (Tx PLL and CDR PLL) that
generate the required clock frequency and send 4-Rx and 4-Tx clocks for each lane through the EPCS
interface. User design is required to use these clocks within the FPGA fabric, in custom logic or FPGA IP,
to transfer data between SERDESIF and FPGA fabric. There is an additional clock (asynchronous)
dedicated to the APB interface, called APB_S_PCLK, used for accessing the SERDESIF block registers.
SERDESIF
SERDES_x_REFCLK0_P
SERDES_x_REFCLK0_N
REFCLK0
SERDES_x_REFCLK1_P
SERDES_x_REFCLK1_N
REFCLK1
reg_clk
0
1
Fabric
APB _S_PCLK
aREFCLK[1:0]
2
0
EP CS _0_RX _CL K
LANE01_REFCLK_
SEL[1:0]
1
aREFCLK[3:2]
epcs_rxclk[3:0]
EP CS _1_RX _CL K
EP CS _2_RX _CL K
2
EP CS _3_RX _CL K
LANE23_REFCLK_SEL[1:0]
EP CS _0_TX_CL K
EP CS _1_TX_CL K
epcs_txclk[3:0]
SERDES
EPCS
EP CS _2_TX_CL K
EP CS _3_TX_CL K
EPCS _FAB _ REF_CLK
Figure 4-8 • SERDESIF Clocking in EPCS Mode
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145
EPCS Interface
Table 4-7 summarizes the various clocks in EPCS mode. Table 4-7 • Clock Signals in EPCS Mode
Clock Signal
Description
aREFCLK
Reference clock for SERDES
EPCS_X_TX_CLK
EPCS interface LaneX (X = 0, 1, 2, 3) Tx Clock
EPCS_X_RX_CLK
EPCS interface LaneX (X = 0, 1, 2, 3) Rx Clock
APB_S_PCLK
PCLK for APB interface
REFCLK0_P
REFCLK0_N
Differential reference clock input I/O Port0
REFCLK1_P
REFCLK1_N
Differential reference clock input I/O Port1
EPCS_FAB_REF_CLK Fabric reference clock for SERDES PMA
SERDES Reference Clock Selection
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through the PLLs. It has three options for the reference clock. The reference clock for the four
lanes comes from the I/O Port0 (REFCLK0) or I/O Port1 (REFCLK1) I/O pads or from FPGA fabric.
Lane0 and lane1 share the same reference clock; lane2 and lane3 share the same reference clock, or
alternatively the same clock can be shared among all four lanes. The reference clock pads are
differential input.
Figure 4-9 shows the reference clock selection in the SERDESIF Configurator available in Libero. I/O
Port0 selects REFCLK0 and I/O Port1 selects REFCLK1.
Figure 4-9 • SERDES Reference Clock Using SERDESIF Configurator
EPCS Protocol 1 and Protocol 2 can use separate reference clocks using the REFCLK0 and REFCLK1
inputs. In the case of single channel protocols, the two channels cannot be adjacent because of REF
CLK sharing.
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EPCS Mode Reset Network
Figure 4-10 shows the reset network for the EPCS interface x4 lanes implementation. The resets for all
four lanes (EPCS_0_RESET_N, EPCS_1_RESET_N, EPCS_2_RESET_N, and EPCS_3_RESET_N)
are gated with the power valid signal from SmartFusion2 or IGLOO2 program control and again with
SERDES_LANEx_SOFTRESET (x = 0, 1, 2, 3).
The SERDES_LANEx_SOFTRESET signals are controlled by the "SERDESIF System Register",
SERDESIF_SOFT_RESET, (active low reset signal for each lane), which can be programmed using the
APB3 interface. On the output side, the SERDESIF block in EPCS mode generates 4 sets of reset
signals for each lane. Table 4-8 on page 147 describes the reset signals and recommended connections.
Fabric
EPCS_0_RX_RESET_N
EPCS_1_RX_RESET_N
EPCS_2_RX_RESET_N
EPCS_3_RX_RESET_N
Power-Up
SERDESIF
EPCS_0_RESET_N
SERDES_LANE0_SOFTRESET
EPCS_1_RESET_N
SERDES_LANE1_SOFTRESET
SERDES
(PMA only)
I/O PADS
EPCS_2_RESET_N
SERDES_LANE2_SOFTRESET
EPCS_3_RESET_N
SERDES_LANE3_SOFTRESET
APB_S_PRESET_N
EPCS_0_TX_RESET_N
EPCS_1_TX_RESET_N
EPCS_2_TX_RESET_N
EPCS_3_TX_RESET_N
Figure 4-10 • SERDESIF Reset Signals in EPCS Mode
Table 4-8 • SERDESIF Reset signals in EPCS Mode
Port
EPCS_X_RESET_N
Type
Input
APB_S_PRESET_N
Input
EPCS_X_Rx_RESET_N
Output
EPCS_X_Tx_RESET_N
Output
Description
EPCS interface LaneX (X = 0, 1, 2, 3) clean reset, de-asserted on
EPCS_X_RX_CLK
APB asynchronous reset to all APB registers
EPCS interface LaneX (X = 0, 1, 2, 3) reset output, de-asserted on
EPCS_X_RX_CLK
EPCS interface LaneX (X = 0, 1, 2, 3) reset output, deasserted on
EPCS_X_TX_CLK
Revision 5
147
EPCS Interface
Design Consideration
This section provides instruction for using the EPCS interface in SmartFusion2 and IGLOO2 devices.
The following topics are covered:
•
EPCS Interface: Timing Diagram
•
EPCS SERDES Calibration and External Resistor Configuration
•
Implementing SGMII Using EPCS Interface
EPCS Interface: Timing Diagram
The Tx clock and Rx clock from SERDES are sent to the EPCS interface through the EPCS_x_TX_CLK
(x = 0, 1, 2, 3) and EPCS_x_RX_CLK (x = 0, 1, 2, 3) output signals. These signals must be used as
transmit clock and receive clock by the external PCS logic. It is recommended to use either a global clock
(CLKINT) or a regional clock (RCLKINT) in the fabric for these signals.
Note: The EPCS_x_RX_CLK requires a clock resource which has low clock injection time into the fabric.
In the smaller arrays sizes of the 010 and 025 either an RCLKINT or CLKINT can be used for the
EPCS_x_RX_CLK. For the larger arrays sizes of the 050, 060, 090, and 150 an RCLKINT must be
used. The CLKINT in the larger devices produces too much delay and does not allow for hold timing
closure.
The transmit data EPCS_X_TXDATA (x = 0, 1, 2, 3) must be generated using the rising edge of
EPCS_x_TX_CLK as it is sampled by the SERDES block, as shown in Figure 4-11. To constrain the
place and route of the EPCS interface, the user needs to provide a clock constraint on the
EPCS_x_TX_CLK signal. This ensures that the setup and hold timing will be met across the interface.
TXCLK
1
EPCS_x_TX_CLK
2
EPCS_x_TX_VAL
EPCS_X_TXDATA[19:0]
First Data
Last Data
Tsetup
Thold
1: Delay introduced by the clock tree on a TxClkp
2: Clock-to-out delay and routing delay
Figure 4-11 • EPCS Transmit Interface Timing Diagram
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EPCS_x_RXDATA (x = 0, 1, 2, 3) is sampled in the FPGA Fabric using the rising edge of
EPCS_x_RX_CLK (x = 0, 1, 2, 3) as shown in Figure 4-12. To constrain the place and route of the EPCS
interface the user needs to provide a clock constraint on the EPCS_x_RX_CLK signal. This ensures that
setup and hold timing will be met across the interface.
EPCS_x_RX_CLK
EPCS_x_RXDATA[19:0]
Valid Data Window
Figure 4-12 • EPCS Receive Interface Timing Diagram
All other EPCS signals are considered asynchronous with respect to the EPCS_RX_CLK or
EPCS_TX_CLK clocks.Figure 4-13 on page 150 provides the recommended interface circuit to achieve
timing closure for high-speed designs in which the EPCS interface clocks are above 125 MHz.
Adding pipeline registers before the user logic provides the place and route tool flexibility in the
placement of these registers and allow for small routes. In addition, using the proper fabric clock routing
resources using the CLKINT an RCLKINT will allow for low skew and fast injection timing necessary to
achieve high-speed timing closure across the EPCS interface.
Revision 5
149
EPCS Interface
SERDES Lane
EPCS_#_TX_RESET_N
Tx_Intf
TXOUT
EPCS_#_TX_DATA[20:0]
From FPGA Fabric
EPCS_#_TXCLK
EPCS_#_RX_RESET_N
Rx_Intf
RXIN
EPCS_#_RX_DATA[20:0]
Delay
To FPGA Fabric
EPCS_#_RXCLK
Figure 4-13 • Detailed EPCS Interface Diagram
Figure 4-13 shows an interface diagram for using the EPCS interface to achieve both setup and hold timing closure. For more information about an example design using the EPCS interface solution as well as
constraints and simulation, refer to the TU0570: Implementing a SmartFusion2/IGLOO2 SERDES EPCS
Protocol Design - Libero SoC Tutorial.
The EPCS design should include proper clock constraints. The table below provides a good example to
properly constrain the design. The user needs to adjust the period and hierarchy accordingly.
Table 4-9 • Example EPCS Constraints
EPCS_0_TXCLK
create_clock -period 8.000 -name {EPCS_0_TX_CLK} [get_pins
{SERDES_IF_0/SERDESIF_INST:EPCS_TXCLK_0}]
EPCS_0_RXCLK
create_clock -period 8.000 -name {EPCS_0_RX_CLK} [get_pins
{SERDES_IF_0/SERDESIF_INST:EPCS_RXCLK_0}]
EPCS_1_TXCLK
create_clock -period 8.000 -name {EPCS_1_TX_CLK} [get_pins
{EPCS_SERDES_0/SERDES_IF_0/SERDESIF_INST:EPCS_TXCLK_1}]
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Table 4-9 • Example EPCS Constraints (continued)
EPCS_1_RXCLK
create_clock -period 8.000 -name {EPCS_1_RX_CLK} [get_pins
{EPCS_SERDES_0/SERDES_IF_0/SERDESIF_INST:EPCS_RXCLK_1}]
EPCS_2_TXCLK
create_clock -period 8.000 -name {EPCS_2_TX_CLK} [get_pins
{EPCS_SERDES_0/SERDES_IF_0/SERDESIF_INST:EPCS_TXCLK[0]}]
EPCS_2_RXCLK
create_clock -period 8.000 -name {EPCS_2_RX_CLK} [get_pins
{EPCS_SERDES_0/SERDES_IF_0/SERDESIF_INST:EPCS_RXCLK[0]}]
EPCS_3_TXCLK
create_clock -period 8.000 -name {EPCS_3_TX_CLK} [get_pins
{SERDES_IF_0/SERDESIF_INST:EPCS_TXCLK[1]}]
EPCS_3_RXCLK
create_clock -period 8.000 -name {EPCS_3_RX_CLK} [get_pins
{SERDES_IF_0/SERDESIF_INST:EPCS_RXCLK[1]}]
EPCS SERDES Calibration and External Resistor Configuration
An external resistor is required for the PMA hard macro in order to perform an impedance calibration
(transmit, receive, and receiver equalization). In a SERDESIF (4- lanes), two lanes share a same
external resistor (REXT) - so L0 & L1 share one and L2 & L3 share another REXT. Hence whenever any
lane is used the respective REXT resistor must be connected on the board. The external resistor input
signal needs to be connected to the SERDES_x_L01_REXT and SERDES_x_L23_REXT pads. The end
of the calibration is signaled by the PMA macro through the EPCS_READY signal. Refer to the
"SERDESIF Block" chapter on page 10 for detail.
Implementing SGMII Using EPCS Interface
SmartFusion2 and IGLOO2 support implementing SGMII using SERDESIF in EPCS mode and then
connecting it to a customer supplied or 3rd party soft IP MAC. Following are the two options to implement
SGMII:
•
Mode A:
1. Sets Protocol mode for the lane to EPCS mode using the SERDESIF configurator in Libero
SoC, and performs APB write cycles through the fabric APB interface to SGMII settings.
2. Performs PHY reset either by asserting “EPCS_X_RX_RESET_N” or
SERDES_LANEx_SOFTRESET registers to bring the PHY up again with SGMII.
•
Mode B:
1. Sets Protocol mode for the lane to EPCS1.25G mode using the SERDESIF configurator in
Libero SoC.
2. Upon power-up the lane has same settings as those for SGMII except Tx post cursor ratio
uses -3.5dB de-emphasis by default. The SGMII Tx post cursor ratio does not use any 
de-emphasis by default. The Tx post cursor ratio setting difference may or may not affect
the transmission of SGMII depending on how lossy are the board level link connections.
- If instant on is not critical for SGMII application, Mode A is the preferred solution
because it enables the capability to configure the settings such as Tx post-cursor ratio
corresponding to the board level link connections.
- In either options of all-four-lane SGMII, the lanes may use the same refclk source
running at 125 MHz. Lane0 and lane1 can share the same calibration results from
lane0, and lane2 and lane3 can share the same calibration results from lane2. When
re-calibration is performed, the two lanes in the lane pair are affected at the same time,
even though the SGMII application on each lane is regarded as independent.
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EPCS Interface
Customized EPCS Mode Settings
While the default SERDESIF registers are pre-set by the Libero software, the designer can alter these
registers using the Edit Register function of the SERDES generator. This feature allows customized
alterations to the SERDESIF capabilities. The Edit Register GUI allows access to all registers of the
SERDESIF. It also includes a configuration export and import capability for versatility and customization.
Figure 4-14 • SERDESIF Configurator Window
EPCS modes are all customizable, however some registers are locked and read-only using the Edit
Register function.
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List of Changes
The following table shows important changes made in this document for each revision.
Date
Changes
Revision 4
(August 2015)
Page
Updated Table 4-1 and Table 4-4 (SAR 69996).
134 and
136
Updated Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6, Figure 4-9, and
Figure 4-14 (SAR 69885).
138, 139,
140, 141,
146, and
152
Updated Figure 4-10 (SAR 63671).
147
Updates are made to maintain the style and consistency of the document.
NA
Updated "Introduction" section.
133
Revision 3
(January 2015)
Consolidated SmartFusion2 and IGLOO2 User Guides.
NA
Revision 2
(July 2014)
Updated Table 4-6 (SAR 57322).
143
March 2014
Updated the chapter (SARs 49906 and 50672).
NA
Glossary
Acronyms
AXI3
Advanced extensible interface
EP
Endpoint
FPGA
Field programmable gate array
PCI Express
Peripheral component interconnect express
PCIe
PCI Express
SERDES
Serializer/de-serializer
SERDESIF
Serializer/de-serializer interface
XAUI
Extended attachment unit interface
EPCS
External Physical Coding Sublayer
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5 – Serializer/De-serializer
Introduction
The high speed serial/de-serializer (SERDES) hard IP block of the SmartFusion2/IGLOO2 FPGA family
is included within the SERDESIF module. The details in this chapter include the physical hardware
capabilities of the SERDES and a description of the fixed hardware blocks of the SmartFusion2/IGLOO2
serial physical interface (PHY). For more Information on serial protocols, refer to the previous protocol
chapters in the "SERDESIF Block" chapter on page 10.
Features
•
TX macro including differential impedance matching output buffers, serializer logic, transition 
de-emphasis, and receiver detection circuitry
•
RX macro including differential CML input buffers, de-serializer logic, on-chip termination, and
continuous-time linear equalization (CTLE)
•
Clock macro including clock recovery circuitry and clock management logic
•
Configuration control and status register access
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Figure 5-1 • SmartFusion2 and IGLOO2 SERDESIF Block Diagram - SERDES/PMA Module
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Device Support
Table 5-1 lists the total number of SERDES channels available in each SmartFusion2/IGLOO2 device.
Table 5-1 • Available SERDES Blocks in SmartFusion2/IGLOO2 Devices
M2S/M2GL
005
SERDESIF
0
available
SERDES
0
Lanes
Notes:
M2S/M2GL
010
1
M2S/M2GL
025
1
M2S/M2GL
050
Up to 2
M2S/M2GL
060
1
M2S/M2GL
090
1
M2S/M2GL
150
Up to 4
4
4
8
4
4
16
1. The specified number of SERDESIF blocks varies depending on the device package.
2. M2S/M2GL060/090 application interfaces have dual controller capability supporting up to two x1 or x2 endpoints
within a SERDESIF.
SERDES Block Overview
SmartFusion2/IGLOO2 devices include up to four integrated high-speed serial interface (SERDESIF)
blocks. Details on SERDESIF can be found in "SERDESIF Block" chapter on page 10. Figure 5-1 on
page 154 shows a high level diagram of the fixed SERDESIF blocks.
Each SERDESIF block has a SERDES including four full-duplex differential channels and a fully
implemented physical media attachment (PMA). The PMA includes the TX and RX buffers, SERDES
logic, clocking, and clock recovery circuitry.
Based on application, the datapath includes a peripheral component interface express (PCIe) physical
coding sublayer (PCS), 10 gigabit attachment unit interface (XAUI) extender, or external PCS (EPCS).
The PCIe PCS contains the 8b/10b encoder/decoder, RX detection, and elastic buffer for the PCI. The
PCS layer interface is compliant to the Intel PHY interface for the PCIe architecture v2.00 specification
(PIPE). The PCIe PCS is fully configurable in terms of number of lanes and number of links. Each link is
configurable from x1, x2, or x4 with supporting power management and wakeup logic.
For XAUI applications, the datapath from the PMA passes through the 8b/10b encoder/decoder, channel
aligner, clock compensation, and XAUI state machine. The XAUI path is terminated to the FPGA fabric
as an XGXS interface. The XAUI extender core also includes an MDIO management interface.
The PCIe PCS functionality can be bypassed completely in order to use the SERDES macro for
protocols other than PCIe through an EPCS interface. In addition, the multi-lane instance can be
disassociated at power-up to distinguish between the lanes used for PCIe and the lanes used for other
protocols through the external PCS interface.
The SERDES macros terminates to the FPGA fabric by the following interfaces.
1. PIPE interface for PCIe protocol (maximum 16 bits), this also includes power management and
wake-up signals.
2. XAUI XGXS with MDIO control interface
3. EPCS interface for implementing any protocol other than PCIe (maximum 20 bits)
4. Advanced peripheral bus (APB) interface for configuration
Each SERDES macro can be configured independently at power-up in a specific mode by using the
SERDES macro registers. These registers are used to control the multi-function SERDES macro
parameters to configure the SERDES in a specific mode. Refer to Chapter 6 – SERDESIF Register
Access Map for details about setting serial protocols. Each SERDES macro can interface to several
other modules within the SERDESIF.
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Serializer/De-serializer
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Figure 5-2 • SERDES Macro Datapath
As shown in Figure 5-2, PCIe, XAUI, and EPCS modes include a specific connectivity through the
SERDES block. The SERDES block registers allow control of the parameters corresponding to PLL
frequency, baud rate, output voltage, de-emphasis, RX equalization, and parallel data path width for the
PCS logic. The initial setup of these parameters is pre-configured through the Libero SoC software.
These registers can be modified after power-up through the register space interface signals on a perlane basis or all lanes together. These registers can be accessed through the APB interface and load the
SERDES parameters after power-up. This run-time capability can be used to simply change specific
settings such as the output voltage amplitude or de-emphasis due to a high bit error rate seen on a
specific lane. The Libero software programs the appropriate registers based on the user design
requirements. Any unused SERDES block resources are configured in a powered down mode via
programming from the software. For unused SERDES, physical I/Os need to be properly terminated
based on the recommendations in DS0115: SmartFusion2 Pin Descriptions Datasheet and DS0124:
IGLOO2 Pin Descriptions Datasheet.
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PMA Macro Block
The SERDES PMA macro contains high-speed analog front-end logic as well as TX PLL and clock and
data recovery (CDR) PLL, calibration, and the voltage offset cancellation mechanism. Figure 5-3 shows a
simplified functional block diagram of the PMA macro. Each of the PMA macro blocks includes the
following three sub-functions:
•
TX Macro
•
RX Macro
•
Clock Macro
The three blocks have several primary inputs and outputs as well as control and status connections. The
control and status nodes are either ports or registers used in conjunction with the implementation.
Figure 5-3 shows a simple diagram of the functionality fixed within the PMA.
Far End
RX Detect
TX Macro
TXDP
TX Data
Serializer
Transmitter
TX Amp
Pre-and
Post-Cursor
Settings
TXDN
TX Clk
TX PLL
REXT
TX Clk
Stable
IMPEDANCE
CALIBRATOR
Clock
Macro
Reference
Clock
DIV
÷
CDR PLL
RXDP
Ref Clk
Stable
Receiver
with CTLE
RXDN
RX Clk
÷
Deserializer
RX Data
Activity
Detect
AD
RX Macro
Equalization
Control
Figure 5-3 • PMA Diagram
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Serializer/De-serializer
TX Macro
The TX macro includes a serializer which receives a 20-bit (maximum) data-word synchronous with a TX
clock, serialized into a single stream of differential transmitted data transmitted to the lane. The TX macro
supports multi-level output drive and multi-level transition (pre-and post-cursor) 3-tap de-emphasis while
maintaining proper impedance. Refer to the "SERDESIF- I/O Signal Interface" listed in Table 5-4 on
page 175 for details. The TX outputs do not support hot-swap.
TX Output Buffer
The TX macro, shown in Figure 5-4, is a high-speed, differential impedance matching output buffer. It
supports multi-level drive, pre-cursor and post-cursor transition de-emphasis, multi-level common-mode,
and calibrated output impedance. These parameters are predefined by the Libero software but can be
tuned by the designer.
SERDES_[01]_L[3:0]_VDDAIO
Emphasis
Ctrl
Emphasis driver
Pre-cursor
Pre-Driver
Far End Detect
(PCIe)
+
SERDES_x_TXDP[3:0]
Differential
Output Buffer
From Serializer
Pre-Driver
SERDES_x_TXDN[3:0]
Emphasis driver
Post-cursor
Clk
Pre-Driver
Figure 5-4 • TX Output Diagram
The TX output voltage levels, VDIFFp-p and VCM, are nominally set by the Libero software based on key
protocol parameters. The limits of these settings are dependent on the analog SERDES I/O supply. The
output voltage parameters are defined by the following equations:
158
•
VDIFFp-p = 2*|VD+ – VD-|
•
VCM= 0.5*(VD+ –VD-)
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VD+
VDIFF
VCM
VD-
Figure 5-5 • TX Output Signal Parameters
Figure 5-6 • Example TX Output Signal
The main tap of the TX output Macro is programmable and controlled by the TX_AMP_RATIO setting.
The amplitude can be set as a ratio from 100%(full-swing) to 0%. The ratio is determined as a function of
the initial lane calibration. Thus the device calibrates the link and determines an optimized impedance
and the ratio setting uses this calibration to baseline the needed amplitude. This allows flexibility to
match receiver specifications on the far-end of the link. Valid settings for TX_AMP_RATIO are between 0
and 128 whereas 128 is 100% swing.
Figure 5-7 • TX AMP RATIO Setting
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Serializer/De-serializer
TX De-Emphasis
The signal quality of a physical channel can be adjusted to match the interconnections and PCB using
the integrated de-emphasis control. The post-curser and pre-cursor nominally spans 0 dB to 20 dB.
Adjustment to these controls in conjunction with the TX amplitude allows the user to closely match the
interconnect channel.
The pre-curser and post cursor de-emphasis adjusts the magnitude of the output based on the prior bit
values effectively attenuating the successive bits. This transition emphasis compensates for the channel
losses and opens the signal eye at the far-end receiver. Figure 5-8 shows the de-emphasis settings and
pre-curser and post-cursor response of the transmit driver.
The pre-cursor and post-cursor attenuation is a function of the TX amplitude ratio setting (see
TX_AMP_RATIO) and the TX pre and post cursor ratio setting (see TX_PRE_RATIO and
TX_PST_RATIO, respectively).
The pre-cursor attenuation (de-emphasis in dB) is calculated using the formula:
dB = 20 * log (1-2*precursor ratio)
where precursor ratio is simply the TX_PRE_RATIO divided by TX_AMP_RATIO.
Similarly, post-cursor attenuation (de-emphasis in dB) is calculated using the formula:
dB = 20 * log (1-2*postcursor ratio)
where post cursor ratio is simply the TX_PST_RATIO divided by TX_AMP_RATIO.
For example, when TX_AMP_RATIO=128 and TX_PST_RATIO=21, Post Cursor Attenuation= 20*log(12*21/128). This yields -3.5dB attenuation.
Post Cursor
De-emphasis
Pre Cursor
De-emphasis
Figure 5-8 • Pre-Cursor and Post-Cursor De-Emphasis
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The TX Macro has many features that can be tuned dynamically when in operation mode. When
changing the TX control registers in real-time, the changes are not updated until the specific
UPDATE_SETTINGS register is written. Refer Table 6-116 on page 221.
Figure 5-9 • TX DEEMPHASIS RATIO Setting
RX Macro
The RX macro receives the serialized data from input receivers. The CDR circuit receives the signal and
extracts a properly timed bit clock from the data stream. The data signal is deserialized down to a lower
speed parallel, 20-bit (maximum) digital data-word (RX data). The deserialized data is synchronous to
the recovered link clock (RX clock).
RX Input Buffer
The RX macro includes an analog front-end powered by the SERDES analog power supply. It contains a
current mode, input differential buffer with on-die input impedance control. The input buffer amplifier
receives the incoming differential data signal. It translates the differential signal to internal logic levels,
with no amplitude impairments. The input buffer amplifier rejects common mode noise. The calibrated
input impedance has a typical 100-ohm differential impedance. The input impedance can be configured
as needed to match the system requirements. The RX inputs do not support hot-swap.
Jitter on the incoming data signal transfers through this stage, therefore care must be taken to ensure
both the incoming timing and amplitude are clean from impairments. The integrated linear equalizer
filters extraneous noise from the incoming signals.
SERDES_[01]_L[3:0]_VDDAIO
+
SERDES_x_RXDP[3:0]
Input Impedance
Termination
(On-die)
Differential
Input Buffer
SERDES_x_RXDN[3:0]
Linear Equalization
Figure 5-10 • RX Input Diagram
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RX Equalization
The RX macro supports a programmable continuous time-linear equalization (CTLE). The equalizer
compensates attenuated interconnections of the system printed circuit board (PCB) by effectively using a
high-pass filter component which attenuates the lower frequency components to a degree greater than
the higher frequency components. The equalizer circuitry can be tuned to compensate for the signal
distortion due to the high frequency attenuation of the physical channel of the PCB and interconnect.
The effective receiver equalization compensates for the channel loss of the board with the added
frequency response of the CTLE. The frequency response can be programmed to maximize the signal
quality of the receiver for achieving the best possible bit-error rate (BER). An under-equalized channel
does not adequately open the eye, whereas over-equalization can produce a channel with high jitter.
Correct equalization has optimal eye opening with low noise and low jitter.
The RX Macro has many features that can be tuned dynamically when in operation mode. When
changing the TX control registers in real-time, the changes will not be updated until the specific
UPDATE_SETTINGS register is written. Refer Table 6-116 on page 221.
Figure 5-11 • RX EQ RATIO Setting
AC Coupling
Each channel must be AC-coupled to remove common mode dependencies. However, AC coupling
generates baseline wander if the high-speed serial data transmission is not DC-balanced. 8B/10B
encoded data is an example of DC-balanced signaling used with PCIe and XAUI protocols. The addition
of external capacitors for AC coupling requires careful consideration. The designer should select a
capacitor knowing the requirements of the system. It is important to minimize the pattern-dependent jitter
associated with the low frequency cutoff of the AC coupling network. When NRZ data containing long
strings of identical 1's or 0's is applied to this high-pass filter, a voltage droop occurs, resulting in 
low-frequency, pattern-dependent jitter (PDJ). Off-chip AC coupling requires recommended capacitor
values such as 10 nF for 8b/10b XAUI and 75-200 nF for PCIe. These example values need to be
reviewed based on specific system requirements. Refer to the AC393: SmartFusion2 and IGLOO2 Board
Design Guidelines Application Note for further details.
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Clock Macro
The Clock macro in the PMA contains one transmit PLL (TX PLL) and one CDR PLL. Figure 5-12 shows
the overview of the clock macro with some associated signals. The TXPLL and RXCDR use a common
input pin “aRefClk”. The power supply for the TXPLL and CDR PLL is supplied from a dedicated 2.5 V
supply. Figure 5-15 on page 167 shows the required power supply connections for
SERDES_x_L01_VDDAPLL and SERDES_x_L23_VDDAPLL. These supplies are specified and used
separately from the SPLL which was mentioned in the PCIE and XAUI sections of this document.
TXDN
Pre-cursor D/E
Post-cursor D/E
TXDP
aTxD[0]
Serializer
aTxD[19]
2
÷M
aRefClk
LoopBack
Equalizer
RXDP
Equalizer
RXDN
S_CLK
TX
PLL
BIT_CLK
T_CLK
aTxClk
÷N
÷F
÷M
CDR
PLL
÷N
÷F
T_CLK
S_CLK
aLpBkNearEnd
2
aRxClk
aRxDO[19]
DeSerializer
aRxDO[0]
Figure 5-12 • Clock Macro Diagram
Note: aRefClk comes from REFCLK[0 or 1] or from fabric clock. Fabric clock only available in EPCS modes.
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Each of the PLLs (TX PLL and CDR PLL) contains the necessary dividers and output high frequency
(BitClk, S_Clk, and T_Clk) and low frequency (aTXClk and aRXClk) clocks. The TX clock (aTXclk) and
RX clock (aRXClk) are divided down and pipelined versions of the high frequency clocks BitClk and
S_Clk. The TX clock and RX clock are complementary. The exact frequencies of the clocks are
determined by the reference clock (RefClk) and divide ratio settings (M, N, and F). The divide ratio
settings—M, N, and F—can be programmed from the APB interface on the SERDESIF block. Refer to
the DS0451: IGLOO2 and SmartFusion2 Datasheet for the RefClk operating ranges.
The relationships between FREF (from RefClk clock input), FBaudClock, FBusClock, and bus width are
as shown in EQ 1 through EQ 4.
FVCO = (FREF) * M * N * F
EQ 5-1
FBaudClock = FVCO / M = (FREF) * N * F
EQ 5-2
FBusClock = FBaudClock / N = (FREF) * F
EQ 5-3
Bus width = FBaudClock / FBusClock = N
EQ 5-4
Note: FBaudClock in TX PLL is the EPCS_TX_CLK for EPCS mode, FBaudClock in CDR PLL is the
EPCS_RX_CLK for EPCS mode, and bus width is the EPCS bus width.
TX clock will only be present and at the correct frequency if all the following are true:
•
Reference clock is present and at correct frequency
•
M, N, and F are correctly set
•
TX PLL is on
•
TX clock trees are on (internal)
•
Power-down mode is off and initialization is done
The RX clock will only be present and at the correct frequency (with high frequency internal S and T
clocks aligned to the bitstream) if all of the following are true:
•
Reference clock is initially present and at the correct frequency
•
M, N, and F are correctly set
•
RX PLL is on, at correct frequency and TX clock is present (PMA controlled mode)
•
Serial bitstream is present and valid
•
De-serializer circuitry is on
•
Receivers are on
Refer to the "TX PLL and CDR PLL Operation" section on page 167 for more information on using the TX
and CDR PLL.
Note: The TX clock and RX clock do not need to be identical in frequency.
Figure 5-13 • M, N, and F Setting
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Reference Clock Inputs
Each SERDESIF consists of reference clock input pads (SERDES_x_REFCLKn_P/N). The REFCLK is
multiplexed in the clock macro, It optionally allows the reference clock to be sourced to the TX PLL
and/or the CDR PLL These are dual purpose I/Os; as they can be alternatively used as generic I/O to
MSIOD fabric only if the SERDESIF is not activated. If unused for either SERDES REFCLK or MSIOD,
they can be left floating.
The MSIOD supported REFCLKs can be used as differential or single-ended I/Os. When used
differentially, the SERDES_x_REFCLKnP/N is operational to receive clock signaling from LVDS and
HCSL type clock drivers. These input signals must be dc-coupled (no series capacitors) from the
SERDES_x_REFCLKnP/N pins to the clock driver device. If used with LVPECL clock type drivers, the
signal requires ac-coupling capacitor and termination resistors. The termination resistors must be placed
closest to the SERDES_x_REFCLKnP/N pins and used to properly bias the inputs to the correct voltage
input common-mode (VICM) and voltage input differential (VID).
AC-coupling of the SERDES_x_REFCLKnP/N cannot be used without the correct re-biasing
terminations. Refer to the DS0451: IGLOO2 and SmartFusion2 Datasheet for REFCLK input
specifications. The REFCLK inputs do not support any 3.3 V input standards and only operate at up to
2.5 V nominal. The inputs do not support hot-plug.
Table 5-2 • Reference Clock Specifications (Typical)
Reference Clock Parameter
Min
Max
Ref Clock Speed
100
160
Note: Refer to the DS0451: IGLOO2 and SmartFusion2 Datasheet for detailed specifications
Unit
MHz
Selection of a quality clock source is important for the best performance of the SERDES. The SERDES
reference clock phase noise contributes to the transmit output phase noise and can decrease receiver
jitter tolerance. Refer to the DS0451: IGLOO2 and SmartFusion2 Datasheet for more specific
information.
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SERDES Reference Clocks
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through the PLLs. The two reference clock inputs ports (REFCLK0 and REFCLK1) are
optionally connected to I/O pads, as previously discussed, or an additional reference clock source,
fab_ref_clk, coming from the fabric. The dedicated clock input pins are recommended to achieve optimal
performance. The fabric reference clock is only available for EPCS modes. Figure 5-14 shows the reference
clock selection. The fabric clock should not be sourced from any of the on-die oscillators. The user programmed
clock selection is routed to the SERDES Clock Macro RefClk input port shown above in Figure 5-6 on
page 159.
The SERDES has four lanes, the two adjacent SERDES lanes share the same reference clock, as
shown in Figure 5-14. In this scheme, lane0 and lane1 share the same reference clock input. Similarly,
lane3 and lane4 share the same reference clock.
SERDES_x_REFCLK0P
REFCLK0
0
SERDES_x_REFCLK0N
SERDES_x_REFCLK1P
REFCLK1
1
SERDES_x_REFCLK1N
aRefClk[1:0]
2
epcs_ fab_ref_clk
SERDES
0
LANE01_REFCLK_SEL[1:0]
1
2
LANE23_REFCLK_SEL[1:0]
Figure 5-14 • SERDES Reference Clock Sources
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Calibration Resource Sharing
The SERDES PMA block calibration is performed to optimize the SERDES in the system. Calibration is
done for the source impedance at the transmitter and the termination of the receiver. The calibration
circuitry is shared across channels.
Each SERDES block contains 2 external reference resistor (REXT) signals—one for lane0 and lane1,
and another for lane2 and lane3. The calibration interaction limits the combination of protocols/data rates
per channel utilization since the adjacent channels are bonded to the same calibration circuitry. For
example, if lane1 and lane0 operate and the PHY is reset on lane0, the recalibration function which
follows the reset disrupts lane1 as a consequence of the shared REXT calibration resistor. REXT
connections are required to calibrate Tx/Rx termination value and internal elements. A 1.21 k-1% resistor
must be connected on the PCB, as shown in Figure 5-15. This resistor can be a 0201 or 0402 sized
component, since the power dissipation through this resistor is less than 1mW during calibration. Refer to
the AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note for more details.
2.5 V
SERDES_x_L01(23)_VDDAPLL
25Ω
0.1 uF
4.7 uF
SERDES_x_L01(23)_REFRET
1.21 KΩ
SERDES_x_L01(23)_REXT
Note: This connection should be replicated for the SERDES_x_L23_REXT.
SmartFusion2/IGLOO2
Figure 5-15 • Calibration Resistor Connection
Example: If lane1 and lane0 are operating and the PHY is reset on lane0, the recalibration function which
follows the reset will disrupt lane1 as a consequence of the shared REXT calibration resistor.
TX PLL and CDR PLL Operation
Each PMA Clock macro has one TX PLL and CDR PLL. This section covers how to configure and use
the TX PLL and clock data CDR PLL. Operations of the PLLs are done in conjunction with reset
operations. Several reset ports are available to both PLLs based on mode. Typical PLL operations are
pre-configured by the Libero software based on protocol and option selections.
CORE_RESET_N, PHY_RESET_N, and EPCS_RESET_N[0:1] pins are defined in the "SERDESIF
Block" chapter on page 10. There are also lower level resets that are controlled by registers that can be
accessed through the APB. These resets are used for calibration and normal operation of the TX and
CDR PLLs.
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Powering the TX PLL On and Off
Powering on the TX PLL from cold start is done using the aTXPLLRstB signal, which is connected to
TXPLL_RST (bit 4 of the PHY_RESET_OVERRIDE register). In PCS driven mode (PCIe and XAUI), the
PCS deasserts aTXPLLRstB after VDD and RefClk are stable, as shown in Figure 5-16. In EPCS mode,
aTXPLLRstB is deasserted using the APB interface. The PLL starts to acquire lock after the deassertion
of aTXPLLRstB. During TXPLL reset, RefClk is bypassed and produced at the outputs of PLL. During
bypass mode, aTXClk is a divided down version of RefClk per M, N, and F settings of the TX PLL.
Proper values for RefClk frequency and M, N, F settings of TX PLL are supplied to the PLL prior to
deassertion of aTXPLLRstB. The settings must be initialized to correct values before coming out of
reset. The TX PLL output is stable when the ATXCLKSTABLE signal is asserted. This signal is routed
to the fabric in EPCS mode.
VDD
VDDIO
VDDPLL
RefClk
Unstable
Stable
aTxPLLRstB
aTXCLKSTABLE
Figure 5-16 • Transmit Clock Stabilization Timing Relationships
If the TX PLL was powered down by asserting aTXPLLRstB for deep power savings, exit from 
power-down should follow the same procedure as described for powering on the TX PLL. The TXPLL is
bypassed in this mode, and if RefClk was present while aTXPLLRstB was asserted, the outputs of the
PLL toggle with RefClk but at a divided down frequency.
While the TX PLL is operational (and in lock) it is possible to shut down both the BitClk tree and aTXClk
for intermediate power savings and faster bring-up time by the assertion of TXHF_CLKDN (bit6 of
PHY_RESET_OVERRIDE register). The TXHF_CLKDN signal, when set, disables the TX PLL VCO by
applying a static zero to the PMA aTXHfClkDnB signal. The aTXHfClkDnB signal functions to inhibit the
output buffers of the PLL without interfering with the loop, hence not affecting lock.
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Changing the TX PLL Mode of Operation
Once the TX PLL has acquired lock, any change of mode setting is accomplished by the suitable change
of M, N, and F settings of the TX PLL. Changes to the PLL settings must be made while the PLL is held
in reset. A change of mode setting does not instantaneously change the frequencies of aTXClk and
BitClock, but changes the frequencies within a few aTXClk cycles, depending on the state of the internal
PLL registers when mode change is applied. The TXPLL design does not guarantee that runt pulses or
glitches do not occur on the clocks during mode changes. So, care should be taken when changing the
PLL setting during operation mode.
Powering the CDR PLL On and Off
The sequence of operations for powering-up the CDR PLL from cold start is similar to that of the TX PLL,
using the aCDRPLLRstB signal connected to RXPLL_RST (bit 5 of PHY_RESET_OVERRIDE register),
except that proper values for CDR PLL M, N, and F have to be provided. The CDR PLL should be up and
stable and a bitstream should be present at RXDP and RXDN. If the CDR PLL was powered-down for
deep power savings, exit from power-down should follow the same sequence of operations as described
for powering-up from system cold start. A bypass operation similar to that of the TX PLL would also
result.
While the CDR PLL is operational (and in lock to RefClk) it is possible to shut down the S_CLK and
T_CLK trees for intermediate power savings and faster lock to bitstream time by the assertion of
RXHF_CLKDN (bit 7 of PHY_RESET_OVERRIDE register). The RXHF_CLKDN bit, when set, disables
the RX PLL VCO settings by applying a static zero to the PMA aRXHfClkDnb signal. The aRXClk signal
will still be functional in this case, but within specified bounds of accuracy linked to Refclk. Since S_Clk
and T_Clk are not operational, bitstream lock cannot be achieved and the PCS will park the CDR PLL in
frequency acquisition mode, which locks to RefClk.
Acquiring Bit Lock for CDR PLL
Following are the two modes of lock where the CDR PLL can be trained to the incoming bitstream:
•
PCS driven mode (PCIe and XAUI)
•
PMA driven mode (EPCS)
The steps for acquiring bit lock are similar in both modes. Bit 3 of the CR0 register (PMA driven mode)
puts the CDR PLL in PMA driven mode or PCS driven mode. In PMA driven mode,
CDR_PLL_MANUAL_CR (CDR PLL manual control register) controls the bit lock steps. Both modes of
lock require the following two steps for training the CDR PLL to the incoming bitstream for the lock:
1. Frequency lock: The frequency lock (FL) operation whereby the CDR PLL locks to the reference
clock. The sampling clock at the receiver is not aligned to the center of the data eye during this
step.
2. Phase lock: The phase lock (PL) operation whereby CDR PLL acquires phase and small
frequency deviation lock to the bitstream. The sampling clock at the receiver will be aligned to the
center of the data eye after this step. It is imperative that the bitstream be valid upon entering
phase lock. There are two further steps for phase lock:
–
Coarse phase lock, which has a higher range of frequency acquisition (± 5000 ppm of static
frequency difference). This step is always a transient step before embarking on fine phase
lock.
–
Fine phase lock, which has a lower range of frequency acquisition (± 300 ppm static
frequency difference).
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Frequency Lock
Phase Lock (coarse)
Phase Lock (fine)
0.5 µs
5 µs
CDRPLL in Lock if
Serial Data Present
0.25 µs
x
(from cold start/reset)
0.5 µs
(from FD prompt)
Start Frequency
Detection
If and when frequency difference
exceeds preset threshold, go
back to frequency acquisition.
Figure 5-17 • CDR Bit Locking
Bit 3 of the SYSTEM_SERDES_TEST_OUT (0x2074) in the SERDESIF block, also known as CDR PLL
locked on data, indicates the current state of the internal frequency detector. Bit 5 of the
SYSTEM_SERDES_TEST_OUT (0x2074) register in the SERDESIF block, also known as CDR PLL
locked (aRXClkStable), indicates when CDR is locked. However, the assertion of aRXClkStable does not
indicate lock to the bitstream. It indicates that the CDR PLL frequency is not grossly out of range of the
bitstream frequency. The only indicator for correct lock to the bitstream is detection of no errors in the
decoded stream.
Changing CDR PLL Mode of Operation
Once the CDR PLL has acquired lock, any change of mode settings is accomplished by the suitable
change of CDR PLL M, N, and F settings. A valid bitstream has to be present for the CDR PLL to
correctly bit-lock. If a change of mode setting is desired with no change in VCO frequency, a certain
amount of time is required for the CDR PLL to reacquire bit-lock. This kind of change of mode setting
does not disturb the PLL frequency lock significantly, but due to phase re-acquisition, the jitter
specifications of the PLL may be violated for a few transient bit periods, with associated loss of received
bits. If a change of mode setting is desired, resulting in a change in VCO frequency, it must be noted that
the CDR PLL has to go through the entire acquisition process, including frequency lock. The CDR PLL
does not guarantee that runt pulses or glitches will not occur on the clocks during mode changes.
Therefore, care should be taken when changing the PLL setting during operation mode.
SERDES in EPCS Mode
The SERDES block can be used in modes, other than PCIe and XAUI. For this purpose, the SERDES
block includes a EPCS interface that enables it to assign each implemented PHY lane to a different
protocol.
The SmartFusion2/IGLOO2 SERDES can operate up to 5 Gbps. The Libero software with 20-bit at 
200 Mhz targets and provides tuned and predictable automatic placement results using customized
EPCS designs up to 4 Gbps. For designs greater than 4 Gbps, the EPCS Interface lends itself to timing
concerns in both transmit and receive path across the boundary to the fabric. These interfaces require
every lane to the fabric to use careful design considerations.
•
Both setup and hold time analysis needs to be done to verify timing on this interface.
•
Proper clock connections, pipelining, and floor-planning is required to place FFs at specific
locations.
The native speed of the SmartFusion2/IGLOO2 SERDES is between 1 through 5 Gbps. Using
oversampling, each data bit is sampled in multiple clock cycles before being transmitted. For example, to
transmit a 400 Mbit/s data rate over a 1.2 Gbps serial link, each bit can be sampled three times and
spread over three clock cycles for both transmit and receiving of data. This is called 3x oversampling.
Using this technique, lower data rates can be transmitted while the SERDES PLL continues to run within
its valid operating range (1 Gbps min).
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SERDES Testing Operations
This section covers how to configure the SERDES in loopback to test the signal integrity of the SERDES
block. It also details the internal pattern generation and checking capability to assist with system debug.
Following are the sub-sections:
•
Diagnostic Loopbacks
•
Pseudo-Random Bit Sequences Pattern Generator
•
Pseudo-Random Bit Sequences Pattern Checker
•
Custom Pattern Generator and Checking
Diagnostic Loopbacks
Serial Loopbacks
Serial loopback modes are specialized configurations of the SERDES datapath where the data is folded
back to the source. Typically, a specific traffic pattern is transmitted and then compared to check for
errors. Loopback test modes fall into two broad categories: Near End and Far End.
SERDES-PMA
FPGA Fabric
PCS - PCIE
Figure 5-18 • Diagnostic Loopbacks
Near End Serial PMA Loopback
The SERDES block provides support for a serial loopback back onto itself for test purposes. When the
LPBK_EN bit (bit1 of the PRBS_CTRL register) is set, the serial data is fed back to the CDR block and
the CDR block extracts the clock and data. Loopback may be operated in full frequency mode (PLLs
active) or bypass mode (PLLs bypassed). This mode is useful when used in conjunction with the on-die
PRBS data generator and checker. In this scenario, the data can be sent and received without going 
off-chip.
PCS
Serializer
PMA
TX
De-emphasis
PRBS
Gen
RX
CDR
Deserializer
CTLE
PRBS
Chk
Figure 5-19 • Near End Serial PMA Loopback
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PCS Far End PMA RX to TX Loopback
This loopback mode (also termed meso_lpbk, shown in blue in Figure 5-20) is where received data is
recaptured by the parallel transmit clock before being sent to the PMA transmitter. The RX is sent back to
the TX and requires no PPM differences between the reference clock used by the transmit and received
data. In this case, data is usually sent to the receiver from test equipment such as a BERT (Bit error-rate
tester) and brought back out of the device TX to the BERT to be checked. Typically the tester will provide
a reference clock to the device. There will be bit errors if there is any PPM differences.
PCS
Serializer
PMA
TX
Demphasis
RX
CDR
Deserializer
CTLE
Figure 5-20 • Far End PMA RX to TX Loopback
Note: To activate far end PMA RX to TX loopback program the PCS_LOOPBACK_CTRL[2].
Pseudo-Random Bit Sequences Pattern Generator
Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of SERDES. The
SERDES block allows pattern generation using the PRBS_CTRL register. This pattern can be looped
back in the PMA and verified as explained in the "Pseudo-Random Bit Sequences Pattern Checker"
section. The following bits describe the PRBS pattern generation feature:
172
•
PRBS_GEN: This signal starts the PRBS pattern transmission.
•
PRBS_TYP[1:0]: This signal defines the type of PRBS pattern which is applied. PRBS7 when set
to 00b, PRBS11 when set to 01b, PRBS23 when set to 10b, and PRBS31 when set to 11b.
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Table 5-3 • SERDES Macro PRBS Patterns
Name
PRBS-7
Polynomial
Length of
Sequence
X6
27– 1 bits
1+
+
X7
Descriptions
Used to test channels which use 8b/10b encoding. Available for PCIe, XAUI,
and EPCS protocols.
PRBS-15
1 + X14 + X15 215 – 1 bits ITU-T Recommendation O.150, Section 5.3. PRBS-15 is often used for jitter
measurement because it is the longest pattern the Agilent DCA-J sampling
scope can handle. Available for EPCS protocols.
PRBS-23
1 + X18 + X23 223 – 1 bits ITU-T Recommendation O.150, Section 5.6. PRBS-23 is often used for 
non-8B/10B encoding scheme. One of the recommended test patterns in
the SONET specification. Available for EPCS protocols.
PRBS-31
1 + X28 + X31 231 – 1 bits ITU-T Recommendation O.150, Section 5.8. PRBS-31 is often used for 
non-8b/10b encoding schemes. A recommended PRBS test pattern for 10
GbE. Refer to the IEEE 802.3ae-2002 specification. Available for EPCS
protocols.
Note: ITU-T Recommendation O.150 provides general requirements for instrumentation for performance
measurements on digital transmission equipment.
Pseudo-Random Bit Sequences Pattern Checker
The SERDES block includes a built-in PRBS checker to test the signal integrity of the channel. Using the
internal PMA loopback or a complete external path from the transmitter to receiver, this pattern checker
allows SERDES to check the four industry-standard PRBS patterns mentioned in Table 5-3. The
PRBS_CTRL register and PRBS_ERRCNT register allow pattern checking.
•
LPBK_EN: The LPBK_EN signal, bit 1 of the PRBS_CTRL register, puts the PMA macro block in
near-end loopback (serial loopback from TX back to RX). PRBS tests can be done using the
near-end loopback of the PMA macro or using any far-end loopback implemented in the opposite
component.
•
PRBS_CHK: The PRBS_CHK signal, bit 6 of the PRBS_CTRL register, starts the PRBS pattern
checker. Refer to the PRBS_CTRL register for more information.
•
PRBS_ERRCNT: The PRBS_ERRCNT register reports the number of PRBS errors detected
when the PRBS test is applied. Refer to PRBS_ERRCNT register for more information.
Custom Pattern Generator and Checking
The SERDES block allows generation of a user-defined pattern. There is no pattern checking available
for custom patterns, including any of the non-PRBS patterns. The SERDES block allows pattern
generation using PRBS related registers. The following bits describe the custom pattern generation
feature:
•
CUSTOM_PATTERN_7_0: The custom pattern registers (register offset 0X190to 0X1CC) enable
programming of a custom pattern. Refer to the custom pattern registers (starting with
CUSTOM_PATTERN_7_0) for more information.
•
CUST_SEL (CUSTOM_PATTERN_CTRL[0]): This signal replaces the PRBS data transmitted on
the link by the custom pattern. The PRBS_SEL register must also be set for transmitting the
custom pattern on the link.
•
CUST_TYP (CUSTOM_PATTERN_CTRL[3:1]): This signal defines whether the custom pattern
generated on the link is generated by the custom pattern register or by one of the hard-coded
patterns:
–
00b: Custom pattern register
–
100b: All-zero pattern (0000…00)
–
101b: All-one pattern (1111…11)
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–
110b: Alternated pattern (1010…10)
–
111b: Dual alternated pattern (1100…1100)
•
CUST_CHK (CUSTOM_PATTERN_CTRL[4]): This bit enables the error counter.
•
CUST_SKIP (CUSTOM_PATTERN_CTRL[5]): This register is used in RX Word alignment manual
mode.
•
CUST_AUTO (CUSTOM_PATTERN_CTRL[6]): This allows the word alignment to be performed
automatically by a state machine that checks whether the received pattern is word-aligned with
the transmitted pattern and to automatically use the PMA CDR PLL skip bit function to find the
alignment.
•
CUST_ERROR (CUSTOM_PATTERN_CTRL[3:0]): When the custom pattern checker is enabled,
this status register reports the number of errors detected by the logic when the custom word
aligner is in synchronization. It starts counting only after a first matching pattern has been
detected.
•
CUST_SYNC (CUSTOM_PATTERN_CTRL[4]): This bit reports that the custom pattern is 
word- aligned.
•
CUST_STATE (CUSTOM_PATTERN_CTRL[7:5]): This register reports the current state of the
custom pattern word alignment state machine.
Reset Requirement for Testing Operations
When performing testing operations such as Loopbacks and PRBS pattern testing, it is required that a
SYSTEM_SER_SOFT_RESET (0x2008) assert/de-assert be done before and after performing these
test operations. This reset operation can use the lane specific SERDES_LANE#_SOFTRESET register
or by using the PCIE_CTLR_SOFTRESET or PCIE_CTLR_SOFTRESET registers. The resetting
operations are embedded within the SmartDebug functions therefore will be conducted as part of the
function call of the feature operations.
Using SmartDebug Utility for SERDES
The SmartDebug utility included with the Libero design software provides SERDES access that will
assist FPGA and the board designers to perform SERDES real-time signal integrity testing and tuning in
a system including SERDES control and test capabilities to assist with debugging high speed serial
designs with no extra steps.
The SmartDebug JTAG interface extends access to configure, control and observe SERDES operations
and is accessible in every SERDES design. Users simply implement their design with the Libero System
Builder to incorporate the SERDESIF block enabling SERDES access from the SmartDebug tool set.
This quickly enables designers to explore configuration options without going through FPGA
recompilation or making changes to the board. GUI displays real-time system and lane status
information. SERDES configurations are supported with TCL scripting allowing access to the entire
register map for real-time customized tuning.
TU0530: SmartFusion2 and IGLOO2 SmartDebug Hardware Design Debug Tools Tutorial demonstrates
the tools capabilities.
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SERDESIF- I/O Signal Interface
The SmartFusion2 and IGLOO2 SERDES block interfaces with differential I/O pads, the PCIe system,
and the FPGA. The following section describes these signals.
Table 5-4 • SERDESIF Block I/O – PAD Interface
Port Name
SERDES_x_RXDP0
Type
Input
SERDES_x_RXDP1
Connected
to
Description
I/O Pads
Receive data. SERDES differential positive input: 
Each SERDESIF consists of 4 RX+ signals.
SERDES_x_RXDP2
SERDES_x_RXDP3
SERDES_x_RXDN0
Input
I/O Pads
Receive data. SERDES differential negative input:
Each SERDESIF consists of 4 RX- signals.
SERDES_x_RXDN1
SERDES_x_RXDN2
SERDES_x_RXDN3
SERDES_x_TXDP0
Output
I/O Pads
Transmit data. SERDES differential positive output:
Each SERDESIF consists of 4 TX+ signals.
SERDES_x_TXDP1
SERDES_x_TXDP2
SERDES_x_TXDP3
SERDES_x_TXDN0
Output
I/O Pads
Transmit data. SERDES differential negative output:
Each SERDESIF consists of 4 TX- Signals.
SERDES_x_TXDN1
SERDES_x_TXDN2
SERDES_x_TXDN3
SERDES_x_L01_REXT
Reference
I/O Pads
External reference resistor connection to calibrate TX/RX
termination value. Each SERDESIF consists of 2 REXT
signals—one for lanes 0 and 1 and another for lane2 and
lane3.
Input
I/O Pads
Reference clock differential positive. Each SERDESIF
consists of two signals (REFCLK0_P, REFCLK1_P). These
are dual purpose I/Os; these lines can be used for MSIOD
fabric, if SERDESIF is not activated.
Input
I/O Pads
Reference clock differential negative. Each SERDESIF
consists of two signals (REFCLK0_P, REFCLK1_P). These
are dual purpose I/Os; these lines can be used for MSIOD
fabric, if SERDESIF is not activated.
SERDES_x_L23_REXT
SERDES_x_REFCLK0P
SERDES_x_REFCLK1P
SERDES_x_REFCLK0N
SERDES_x_REFCLK1N
Note: Here, x = the SERDESIF_# where # is from 0 through 3.
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List of Changes
The following table shows important changes made in this document for each revision.
Date
Changes
Revision 4
(August 2015)
Updated Table 5-1 (SAR 69996).
Updated Table 5-4 (SAR 65871) and Table 5-3.
Page
155
175, 173
Updated "Custom Pattern Generator and Checking" section.
173
Revision 3
(January 2015)
Consolidated SmartFusion2 and IGLOO2 User Guides.
NA
Revision 2
(July 2014)
No updates
NA
February 2014
Updated the chapter (SAR 49906).
NA
Glossary
Acronym
CDR
Clock data recovery
PCS
Physical coding sublayer
PHY
Physical interface
PIPE
PHY interface for the PCI Express architecture v2.0 specification
PMA
Physical media attachment
PRBS
Pseudo-random bit sequence
SERDES
Serializer/de-serializer
SERDESIF
Serializer/de-serializer interface
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6 – SERDESIF Register Access Map
Configuration of SERDESIF
The SERDESIF contains a large number of internal registers required to properly configure the
SERDESIF module. The register settings provide initial programming at power-up and most portions of
the SERDESIF block can be dynamically reconfigured while in operation. A SERDESIF APB
configuration interface is accessed through the FPGA fabric providing the resources to allow these
programming capabilities.
In SmartFusion2, the SERDESIF is not connected directly to MSS. It can be accessed from MSS through
the FPGA fabric. It contains a large number of internal registers for initialization and runtime operation.
These registers are accessed through an APB configuration bus. The APB configuration interface is
routed by the AHB bus matrix to the FPGA fabric interface to configure the SERDESIF. After initial
programming at power-up, most portions of the SERDESIF block can be dynamically reconfigured while
operating. The SERDESIF system registers can be accessed through the APB bus.
1 KB
The IGLOO2 device family is supported differently than the SmartFusion2 device family for programming
the SERDESIF and its supported serial protocols. The IGLOO2 uses a FPGA module to initialize
peripherals and access the system controller known as the HPMS. The HPMS module provides
connectivity to the AHB bus matrix allowing similar SERDESIF initialization using this FPGA IP module in
the fabric. MSS/HPMS supports the SERDESIF peripheral using the Libero SoC software to correctly
provision and program the user customized features.
SERDESIF System Register
(1 KB)
0x2000
SERDES Macro Register
Lane 3 (1 KB)
4 KB
SERDES Macro Register
Lane 2 (1 KB)
SERDES Macro Register
Lane 1 (1 KB)
4 KB
SERDES Macro Register
Lane 0 (1 KB)
0x1C00
0x1800
0x1400
0x1000
PCIe Core
Bridge Register
(4 KB)
0x0000
Figure 6-1 • SERDESIF Memory Map
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SERDESIF Register Access Map
Notes:
1. Refer to the "PCI Express" chapter on page 28 for more information on the PCIe core register.
2. Memory map offset differs from MSS and HPMS
3. Reference: UG0331: SmartFusion2 Microcontroller Subsystem User Guide or UG0448: IGLOO2
FPGA High Performance Memory Subsystem User Guide
Figure 6-2 shows the APB implementation of three region configurations and status registers. The APB is
used to interface to the FPGA fabric which enable access to these register region as an APB slave.
SERDESIF
APB 32
SERDESIF System
Register
A
P
B
APB 32
Interface
APB
DECODER
I
N
T
E
R
F
A
C
E
PCIe SYSTEM
APB 32
PCIe Core Register
SERDES
APB 32
APB to SERDES
Interface
Native
8-bit
Interface
SERDES Macro
Register
Figure 6-2 • Address Decoder Logic Block Diagram
The SERDESIF block has three regions of configuration and status registers. Configuration of the
SERDESIF is done through these registers. Configuration of top level functionality of the PCIe core,
XAUI block, and SERDES macro is also done through these registers. The three regions of configuration
and status registers shown in Figure 6-1 on page 177 are described below.
SERDESIF System Register
The SERDES block system register controls the SERDES block module for single protocol or multiprotocol support implementation. It occupies 1 KB of the configuration memory map. The physical offset
location of the SERDES block system register is 0x2000-0x23FF from the SERDES block subsystem
memory map. These registers can be accessed through the 32-bit APB interface, and the default values
of these registers can be configured using Libero SoC. These flash bits have the settings for registers
that require to be initialized quickly when the device powers up such as PLL and clock configurations,
PCIe configuration space, and resets. The flash bits are set by the Libero configuration GUI based on the
user selections, programmed into the device, and are statically set at device power-up. However, the
SERDES block system registers can be updated through the 32-bit APB interface, if required.
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Table 6-1 • Mode Settings Using the SERDESIF System APB Registers
SERDESIF System APB 
Registers
Description
CONFIG_PHY_MODE[15:12] For each lane, this signal selects the protocol default settings, which will set the reset
value of the register space.
CONFIG_PHY_MODE [15:12] - Defines lane3 settings
0000: PCIe mode lane3
0001: XAUI mode lane3
0011: Reserved
0100: Reserved
0101: EPCS mode lane3
1111: SERDES PHY lane3 is off
CONFIG_PHY_MODE[11:8] CONFIG_PHY_MODE [11:8] - Defines lane2 settings
0000: PCIe mode lane2
0001: XAUI mode lane2
0011: Reserved
0100: Reserved
0101: EPCS mode lane2
1111: SERDES PHY lane2 is off
CONFIG_PHY_MODE[7:4]
CONFIG_PHY_MODE [7:4] - Defines lane1 settings
0000: PCIe mode lane1
0001: XAUI mode lane1
0011: Reserved
0100: Reserved
0101: EPCS mode lane1
1111: SERDES PHY lane1 is off
CONFIG_PHY_MODE[3:0]
CONFIG_PHY_MODE [3:0] - Defines lane0 settings
0000: PCIe mode lane0
0001: XAUI mode lane0
0011: Reserved
0100: Reserved
0101: EPCS mode lane0
1111: SERDES PHY lane0 is off
Notes:
1. XAUI = 10 Gbps attachment unit interface
2. EPCS = External physical coding sub-layer
3. 0010: Reserved Setting for all lanes
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Table 6-1 • Mode Settings Using the SERDESIF System APB Registers (continued)
SERDESIF System APB 
Registers
CONFIG_EPCS_SEL[3:0]
Description
For each lane, one bit of this signal defines whether the external PCS interface is used
or the PCIe PCS is enabled:
0: PCIe mode
1: External PCS mode
CONFIG_EPCS_SEL [3]: External PCS selection associated with lane3
CONFIG_EPCS_SEL [2]: External PCS selection associated with lane2
CONFIG_EPCS_SEL [1]: External PCS selection associated with lane1
CONFIG_EPCS_SEL [0]: External PCS selection associated with lane0
CONFIG_LINK2LANE[3:0]
This signal is used in PCIe mode to select the association of lane to link. The four bits
refer to four lanes.
Notes:
1. XAUI = 10 Gbps attachment unit interface
2. EPCS = External physical coding sub-layer
3. 0010: Reserved Setting for all lanes
Table 6-2 • SERDESIF System Registers
Register Name
Address Register
Offset
Type
Description
SYSTEM_SER_PLL_CONFIG_
LOW (0x2000)
0x00
R/W
Sets SERDES PLL(SPLL) configuration bits (LSBs).
SYSTEM_SER_PLL_CONFIG_
HIGH (0x2004)
0x04
R/W
Sets SPLL configuration bits (MSBs).
SYSTEM_SER_SOFT_RESET
(0x2008)
0x08
R/W
PCIe controller, XAUI, and SERDES lanes soft RESET
SYSTEM_SER_INTERRUPT_
ENABLE (0x200C)
0x0C
R/W
SPLL lock interrupt enable
SYSTEM_CONFIG_AXI_AHB_
BRIDGE (0x2010)
0x10
R/W
Defines whether AXI3/AHB master interface is implemented on
the master interface to fabric.
SYSTEM_CONFIG_ECC_INTR
_ENABLE (0x2014)
0x14
R/W
Sets ECC enable and ECC interrupt enable for PCIe memories.
Reserved
0x18
R/W
Reserved
Reserved
0x1C
R/W
Reserved
SYSTEM_CONFIG_PCIE_PM
(0x2020)
0x20
R/W
Used to inform the configuration space, the slot power, PHY
reference clock, Power mode etc.
SYSTEM_CONFIG_PHY_MOD
E_0 (0x2024)
0x24
R/W
Selects the protocol default settings of the PHY.
SYSTEM_CONFIG_PHY_MOD
E_1 (0x2028)
0x 28
R/W
Selects PCS mode, link to lane settings.
SYSTEM_CONFIG_PHY_MOD
E_2 (0x202C)
0x2C
R/W
Sets the equalization calibration performed by the PMA control
logic of the lane or use the calibration result of adjacent lane.
Notes:
1. Refer to the individual register description for the reset value.
2. R/W: Read and write allowed R/O: 0 Read only
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Table 6-2 • SERDESIF System Registers (continued)
Register Name
Address Register
Offset
Type
Description
SYSTEM_CONFIG_PCIE_0
(0x2030)
0x30
R/W
Defines PCIe vendor ID and device ID for PCIe identification
registers.
SYSTEM_CONFIG_PCIE_1
(0x2034)
0x34
R/W
Defines PCIe subsystem vendor ID and subsystem device ID for
PCIe identification registers.
SYSTEM_CONFIG_PCIE_2
(0x2038)
0x38
R/W
Defines PCIe subsystem revision ID and class code.
SYSTEM_CONFIG_PCIE_3
(0x203C)
0x3C
R/W
Sets PCIe link speed.
SYSTEM_CONFIG_BAR_SIZE
_0_1 (0x2040)
0x40
R/W
Sets BAR0 and BAR1 of PCIe core register map.
SYSTEM_CONFIG_BAR_SIZE
_2_3 (0x2044)
0x44
R/W
Sets BAR2 and BAR3 of PCIe core register map.
SYSTEM_CONFIG_BAR_SIZE
_4_5 (0x2048)
0x48
R/W
Sets BAR4 and BAR5 of PCIe core register map.
SYSTEM_SER_CLK_STATUS
(0x204C)
0x4C
R/O
This register describes SPLL lock information.
Reserved
0x50
R/O
–
Reserved
0x54
R/O
–
SYSTEM_SER_INTERRUPT
(0x2058)
0x58
R/O
SPLL/FPLL lock interrupt
SYSTEM_SERDESIF_INTR_S
TATUS (0x205C)
0x5C
R/O
SECDED interrupt status for PCIe memories
Reserved
0x60
–
SYSTEM_REFCLK_SEL
(0x2064)
0x64
R/W
Reference clock selection for the four lanes of PMA.
SYSTEM_PCLK_SEL (0x2068)
0x68
R/W
PCIe core clock selection
SYSTEM_EPCS_RSTN_SEL
(0x206C)
0x6C
R/W
EPCS reset signal selection from fabric
SYSTEM_CHIP_ENABLES
(0x2070)
0x70
R/O
GEN2 enable for PCIe
SYSTEM_SERDES_TEST_OU
T (0x2074)
0x74
R/O
Status Test out output of PCIe PHY
SYSTEM_SERDES_FATC_RE
SET (0x2078)
0x78
R/W
Fabric alignment test circuit – reset input
SYSTEM_RC_OSC_SPLL_RE
FCLK_SEL (0x207C)
0x7C
R/W
Reference clock selection for SPLL
SYSTEM_SPREAD_SPECTRU
M_CLK (0x2080)
0x80
R/W
Spread spectrum clocking configuration
SYSTEM_CONF_AXI_MSTR_
WNDW_0 (0x2084)
0x84
R/W
PCIe AXI3-master window0 configuration register – 0
–
Notes:
1. Refer to the individual register description for the reset value.
2. R/W: Read and write allowed R/O: 0 Read only
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Table 6-2 • SERDESIF System Registers (continued)
Address Register
Offset
Type
Register Name
Description
SYSTEM_CONF_AXI_MSTR_
WNDW_1 (0x2088)
0x88
R/W
PCIe AXI3-master window0 configuration register – 2
SYSTEM_CONF_AXI_MSTR_
WNDW_2 (0x208C)
0x8C
R/W
PCIe AXI3-master window0 configuration register – 2
SYSTEM_CONF_AXI_MSTR_
WNDW_3 (0x2090)
0x90
R/W
PCIe AXI3-master window0 configuration register – 3
SYSTEM_CONF_AXI_SLV_W
NDW_0 (0x2094)
0x94
R/W
PCIe AXI3-slave window0 configuration register – 0
SYSTEM_CONF_AXI_SLV_W
NDW_1 (0x2098)
0x98
R/W
PCIe AXI3-slave window0 configuration register – 1
SYSTEM_CONF_AXI_SLV_W
NDW_2 (0x209C)
0x9C
R/W
PCIe AXI3-slave window0 configuration register – 2
SYSTEM_CONF_AXI_SLV_W
NDW_3 (0x20A0)
0xA0
R/W
PCIe AXI3-slave window0 configuration register – 4
SYSTEM_DESKEW_CONFIG
(0x20A4)
0xA4
R/W
PLL REF clock DESKEW register
Notes:
1. Refer to the individual register description for the reset value.
2. R/W: Read and write allowed R/O: 0 Read only
Table 6-3 • SYSTEM_SER_PLL_CONFIG_LOW (0x2000)
Bit
Number
[18:16]
Name
PLL_OUTPUT_DIVISOR
Reset
Value
0x1
Description
These bits set SPLL output divider value:
000: ÷1
001: ÷2
010: ÷4
011: ÷8
[15:6]
PLL_FEEDBACK_DIVISOR
0x2
These bits set SPLL feedback divider value (SSE = 0) (binary value +
1)
0000000000: ÷1
0000000001: ÷2
0000000010: ÷3
…
1111111111: ÷1,025
[5:0]
PLL_REF_DIVISOR
0x2
These bits set SPLL reference divider value (binary value+1):
000000: ÷1
000001: ÷2
000010: ÷3
…
111111: ÷65
Both REFCK and post-divide REFCK must be within the range
specified in the PLL datasheet.
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Table 6-4 • SYSTEM_SER_PLL_CONFIG_HIGH (0x2004)
Bit
Number
Name
Reset
Value
Description
16
PLL_PD
0x0
A power-down (PD) signal is provided for lowest quiescent current. When PD
is asserted, the PLL powers down and outputs are low. PD has precedence
over all other functions.
15
PLL_FSE
0x0
This signal chooses between internal and external input paths:
0: Feedback (FB) pin input
1: Internal feedback
FB should be tied off (High or Low) and not left floating when FSE is High. FB
should connect directly or through the clock tree to PLLOUT when FSE is
low. SSE is ineffective when FSE = 0. If the FACC source multiplexer is
configured to select a clock other than the PLL output clock, then the
fddr_pll_fse signal must be set to 1, when the PLL is powered up.
14
PLL_MODE_3V3
0x1
Analog voltage selection
1: 3.3 V
0: 2.5 V
Selects between 2.5 V and 3.3 V analog voltage operation mode (wrong
selection may cause PLL not to function, but will not damage the PLL).
13
PLL_MODE_1V2
0x1
Core voltage selection
1: 1.2 V
0: 1.0 V
Selects between 1.0 V and 1.2 V core voltage operation mode (wrong
selection may cause PLL not to function, but will not damage the PLL).
12
PLL_BYPASS
0x1
A bypass signal is provided which both powers down the PLL core and
bypasses it as that PLLOUT tracks REFCK. Bypass has precedence over
reset. Microsemi recommends that either Bypass or reset are asserted until
all configuration controls are set in the desired working value; the power
supply and reference clocks are stable within operating range, and the
feedback path is functional. Either bypass or reset may be used for powerdown IDDQ testing.
11
PLL_RESET
0x1
PLL reset signal (asserted high).
[10:7]
PLL_LOCKCNT
0xF
These bits contain lock counter value (2^ (binary value + 5)):
0000: 32
0001: 64
…
1111: 1048576
The above mentioned lock counter values represent the number of reference
cycles present before the lock is asserted or detected.
Note: All the registers are 32-bit. Bits, which are not shown in the table, are reserved.
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Table 6-4 • SYSTEM_SER_PLL_CONFIG_HIGH (0x2004) (continued)
Bit
Number
[6:4]
Name
PLL_LOCKWIN
Reset
Value
0x0
Description
These bits contain phase error window for lock assertion as a fraction of
divided reference period:
000: 500ppm
100: 8000ppm
001: 1000ppm
101: 16000ppm
010: 2000ppm
110: 32000ppm
011: 4000ppm
111: 64000ppm
Values are at typical process, voltage, and temperature (PVT) only and are
not PVT compensated.
[3:0]
PLL_FILTER_RANGE
0x9
These bits contain PLL filter range:
0000: BYPASS
0111: 18–29 MHz
0001: 1–1.6 MHz
1000: 29–46 MHz
0010: 1.6–2.6 MHz
1001: 46–75 MHz
0011: 2.6–4.2 MHz
1010: 75–120 MHz
0100: 4.2–6.8 MHz
1011: 120–200 MHz
0101: 6.8–11 MHz
0110: 11–18 MHz
Note: All the registers are 32-bit. Bits, which are not shown in the table, are reserved.
Table 6-5 • SYSTEM_SER_SOFT_RESET (0x2008)
Bit
Number
Name
Reset
Value
Description
5
SERDES_LANE3_SOFTRESET
0x1
SERDES lane3 soft reset
4
SERDES_LANE2_SOFTRESET
0x1
SERDES lane2 soft reset
3
SERDES_LANE1_SOFTRESET
0x1
SERDES lane1 soft reset
2
SERDES_LANE0_SOFTRESET
0x1
SERDES lane0 soft reset
1
XAUI_CTLR_SOFTRESET
0x1
XAUI controller soft reset
0
PCIE_CTLR_SOFTRESET
0x1
PCIe controller soft reset
Note: All the registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-6 • SYSTEM_SER_INTERRUPT_ENABLE (0x200C)
Bit
Number
Name
Reset
Value
3
FPLL_LOCKLOST_INT_ENABLE
0x0
This bit sets FPLL lock lost interrupt output enable.
2
FPLL_LOCK_INT_ENABLE
0x0
This bit sets FPLL lock interrupt output enable.
1
SPLL_LOCKLOST_INT_ENABLE
0x0
This bit sets SERDES PLL lock lost interrupt output enable.
0
SPLL_LOCK_INT_ENABLE
0x0
This bit sets SERDES PLL lock interrupt output enable.
Description
Table 6-7 • SYSTEM_CONFIG_AXI_AHB_BRIDGE (0x2010)
Bit
Number
1
Name
CFGR_AXI_AHB_MASTER
Reset
Value
0x1
Description
Defines whether AXI3/AHB slave interface is implemented on
the master interface to fabric.
0: AHB, 32-bit AHB slave implemented in fabric
1: AXI3, 64-bit AXI3 slave implemented in fabric
0
CFGR_AXI_AHB_SLAVE
0x1
Defines whether AXI3/AHB master interface is implemented
on the slave interface to fabric.
0: AHB, 32-bit AHB master implemented in fabric
1: AXI3, 64-bit AXI3 master implemented in fabric
Table 6-8 • SYSTEM_CONFIG_ECC_INTR_ENABLE (0x2014)
Bit
Number
[7:4]
Name
CFGR_PCIE_ECC_INTR_EN
Reset
Value
0x7
Description
This bit sets the ECC interrupt enable for PCIe Tx, Rx, and Rp
memories.
Bit 0
1: Rp - ECC interrupt enabled
0: ECC interrupt disabled
Bit 1
1: Rx - ECC interrupt enabled
0: ECC interrupt disabled
Bit 2
1: Tx - ECC interrupt enabled
0: ECC interrupt disabled
[3:0]
CFGR_PCIE_ECC_EN
0x7
This bit sets the ECC enable for PCIe Tx, Rx, and Rp
memories.
Bit 0
1 - Rp - ECC enabled- 1'b0: ECC – disabled
Bit-1: 1'b1 - Rx - ECC enabled- 1'b0: ECC – disabled
Bit-2: 1'b1 - Tx - ECC enabled- 1'b0: ECC – disabled
Table 6-9 • Reserved Register (0x2018)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Note: All registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-10 • Reserved Register (0x201C)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Table 6-11 • SYSTEM_CONFIG_PCIE_PM (0x2020)
Bit
Number
3
Name
CFGR_TX_SWING
Reset
Value
0x0
Description
Transmit swing: This signal is a per-link signal, which is
generated by each link PCIe. The PCS logic performs the
internal mapping of link to lanes.
Note: This signal is only for PCIe Gen2 controller, not for
PCIe GEN1 controller.
2
CFGR_L2_P2_ENABLE
0x0
L2/P2 enable.
1'b1: Enable L2/P2 (Default-L2P2-Enabled)
1'b0: Disable L2/P2
If L2/P2 is enabled, cfgr_pm_auxpwr should also be enabled.
1
CFGR_PM_AUX_PWR
0x0
Slot auxiliary power: This signal specifies whether the device
uses the slot auxiliary power source. This signal is used only
used if the core supports D3 cold.
1'b1: Auxiliary power source available. Default L2P2-Enabled.
1'b0: Auxiliary power source unavailable.
0
CFGR_SLOT_CONFIG
0x0
Slot clock configuration: This signal is used only to inform the
configuration space, if the reference clock of the PHY is same
as that of the slot.
0: Independent clock
1: Slot clock
This signal is synchronous to CLK.
Note: All registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-12 • SYSTEM_CONFIG_PHY_MODE_0 (0x2024)
Bit
Number
[15:0]
Name
CONFIG_PHY_MODE
Reset
Value
0x0
Description
For each lane, this signal selects the protocol default settings of the
PHY, which sets the reset value of the registers space. For instance,
the following mapping is associated to a four lane PHY:
phy_mode[3:0]: Mode associated to lane0
phy_mode[7:4]: Mode associated to lane1
phy_mode[11:8]: Mode associated to lane2
phy_mode[15:12]: Mode associated to lane3
PHY_MODE settings:
4'b0000 - PCIE mode
4'b0001 - XAUI mode
4'b0010 - Reserved
4'b0011 - Reserved
4'b0100 - Reserved
4'b0101 - EPCS mode
4'b1111 - SERDES PHY lane is off
Table 6-13 • SYSTEM_CONFIG_PHY_MODE_1 (0x2028)
Bit
Number
Name
Reset
Value
[11:8]
CONFIG_REG_LANE_SEL
0xF
Lane select: This signal defines which lanes are accessed and must
be one-hot encoded for read transaction. For write transaction, one
or several lanes can be written in the same time when several bits
are asserted.
[7:4]
CONFIG_LINKK2LANE
0xF
This signal is used in PCIe mode in order to select the association of
lane to link and must be one-hot encoded (each lane can be
associated only to one link).
Description
For example, a four lane PHY, which can be configured in 1 or 2 link
might have
•
pipe_lk2ln[3:0]: lane associated to link 0
•
pipe_lk2ln[7:4]: lane associated to link 1
Note: It is mandatory that this signal is static at power-up or stable
before reset de-assertion.
[3:0]
CONFIG_EPCS_SEL
0x0
For each lane, one bit of this signal defines whether the external
PCS interface is used or the PCIe PCS is enabled:
0b: PCIe mode
1b: External PCS mode
For instance, the mapping associated to a four lane PHY is:
epcs_sel[0]: External PCS selection associated to lane0
epcs_sel[1]: External PCS selection associated to lane1
epcs_sel[2]: External PCS selection associated to lane2
epcs_sel[3]: External PCS selection associated to lane3
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Table 6-14 • SYSTEM_CONFIG_PHY_MODE_2 (0x202C)
Bit
Number
[7:0]
Name
CONFIG_REXT_SEL
Reset
Value
0x0
Description
For each lane, 2 bits of this signal select whether the Tx, Rx, and Rx
equalization calibration is performed by the PMA control logic of the
lane or use the calibration result of adjacent lane (upper or lower
lanes):
00b: perform calibration using the lane calibration algorithm, which
also requires that the Rext resistor is present on board
01b: use calibration result of lower lane
10b: use calibration result of upper lane
11b: reserved
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-15 • SYSTEM_CONFIG_PCIE_0 (0x2030)
Bit
Number
Name
Reset
Value
Description
[31:16]
PCIE_DEVICE_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe device ID.
[15:0]
PCIE_VENDOR_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe vendor ID.
Table 6-16 • SYSTEM_CONFIG_PCIE_1 (0x2034)
Bit
Number
Name
Reset
Value
Description
[31:16]
PCIE_SUB_DEVICE_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe subsystem device ID.
[15:0]
PCIE_SUB_VENDOR_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe subsystem vendor ID.
Table 6-17 • SYSTEM_CONFIG_PCIE_2 (0x2038)
Bit
Number
Name
Reset
Value
Description
[31:16]
PCIE_CLASS_CODE
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe class code.
[15:0]
PCIE_REV_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe revision ID.
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-18 • SYSTEM_CONFIG_PCIE_3 (0x203C)
Bit
Number
Name
Reset
Value
Description
[5:2]
K_BRIDGE_SPEC_REV
0x0
RESERVED
1
K_BRIDGE_EMPH
0x0
RESERVED
0
K_BRIDGE_SPEED
0x0
RESERVED
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Table 6-19 • SYSTEM_CONFIG_BAR_SIZE_0_1 (0x2040)
Bit
Number
Name
[17:13] CONFIG_BAR_SIZE_1
Reset
Value
Description
0x0 These bits set the size of the BAR1 memory. For example, 32-bit BAR:
CONFIG_BAR_SIZE_1 - 5'd21 translates to BAR0 - (2 MB)
"1111_1111_1110_0000_0000_0000_0000_CONFIG_BAR_CONTROL_1"
[12:9]
CONFIG_BAR_CONTROL_1
0x0 LSB bits of BAR1 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
[8:4]
CONFIG_BAR_SIZE_0
0x0 These bits set the size of the BAR0 memory. For example, 32-bit BAR:
CONFIG_BAR_SIZE_0 - 5'd20 translates to BAR0 - (1 MB)
"1111_1111_1111_0000_0000_0000_0000_CONFIG_BAR_CONTROL_0"
[3:0]
CONFIG_BAR_CONTROL_0
0x0 LSB bits of BAR 0 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Revision 5
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Table 6-20 • SYSTEM_CONFIG_BAR_SIZE_2_3 (0x2044)
Bit
Number
Name
[17:13] CONFIG_BAR_SIZE_3
Reset
Value
Description
0x0 These bits set the size of the BAR3 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_3 - 5'd23 translates to BAR3 - (8 MB)
"1111_1111_1000_0000_0000_0000_0000_CONFIG_BAR_CONTROL_3"
[12:9] CONFIG_BAR_CONTROL_3 0x0 [3:0] LSB bits of BAR 3 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10-64-bit memory
Bit3: Prefetchable/non-prefetchable memory
[8:4]
CONFIG_BAR_SIZE_2
0x0 These bits set the size of the BAR2 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_2 - 5'd22 translates to BAR0 - (4 MB)
"1111_1111_1100_0000_0000_0000_0000_CONFIG_BAR_CONTROL_2"
[3:0]
CONFIG_BAR_CONTROL_2 0x0 [3:0] LSB bits of BAR 2 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
Table 6-21 • SYSTEM_CONFIG_BAR_SIZE_4_5 (0x2048)
Bit
Number
Name
[17:13] CONFIG_BAR_SIZE_5
Reset
Value
Description
0x0 These bits set the size of the BAR5 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_5 - 5'd25 translates to BAR5 - (32 MB)
"1111_1110_0000_0000_0000_0000_0000_CONFIG_BAR_CONTROL_5"
[12:9]
CONFIG_BAR_CONTROL_5
0x0 [3:0] LSB bits of BAR 5 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00 - 32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
[8:4]
CONFIG_BAR_SIZE_4
0x0 These bits set the size of the BAR4 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_4 - 5'd24 translates to BAR4 - (16 MB)
"1111_1111_0000_0000_0000_0000_0000_CONFIG_BAR_CONTROL_4"
[3:0]
CONFIG_BAR_CONTROL_4
0x0 [3:0] LSB bits of BAR 4 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32 bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
Note: All registers are 32-bit. Bits not shown in the table are reserved.
190
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-22 • SYSTEM_SER_CLK_STATUS (0x204C)
Bit
Number
Name
Reset
Value
Description
1
FAB_PLL_LOCK
0x0
Fabric PLL lock information, CLK_BASE, 1: LOCKED
0
PLL_LOCK
0x0
SPLL lock information, 1: LOCKED
Table 6-23 • Reserved Register (0x2050)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Name
Reset
Value
Description
Reserved
0x0
–
Table 6-24 • Reserved Register (0x2054)
Bit
Number
–
Table 6-25 • SYSTEM_SER_INTERRUPT (0x2058)
Bit
Number
Name
Reset
Value
Description
1
PLL_LOCK_INT
0x0
SPLL/FPLL lock interrupt output
0
PLL_LOCKLOST_INT
0x0
SPLL/FPLL lock lost interrupt output
Table 6-26 • SYSTEM_SERDESIF_INTR_STATUS (0x205C)
Bit
Number
[2:0]
Reset
Value
Name
SERDESIF_INTR_STATUS
0x0
Description
ECC interrupt status for PCIe memories
Table 6-27 • Reserved Register (0x2060)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-28 • SYSTEM_REFCLK_SEL (0x2064)
Bit
Number
[3:2]
Name
LANE23_REFCLK_SEL
Reset
Value
Description
0x0 Reference clock selection for lane2 and lane3 of PMA:
00: Selects refclk_io0 clock for lane2 and lane3 as reference clock
01: Selects refclk_io1 clock for lane2 and lane3 as reference clock
10: Reserved
11: Selects fab_ref_clk clock for lane2 and lane3 as reference clock
[1:0]
LANE01_REFCLK_SEL
0x0 Reference clock selection for lane0 and lane1 of PMA:
00: Selects refclk_io0 clock for lane0 and lane1 as reference clock
01: Selects refclk_io1 clock for lane0 and lane1 as reference clock
10: Reserved
11: Selects fab_ref_clk clock for lane0 and lane1 as reference clock
Revision 5
191
SERDESIF Register Access Map
Table 6-29 • SYSTEM_PCLK_SEL (0x2068)
Bit
Number
[5:4]
Name
Reset
Value
PIPE_PCLKIN_LANE23_SEL
0x0
Description
PIPE clock input selection for lane2 and lane3, can be selected
from one of pipeclk_out[3:0]:
00: Selects pipeclk_out[0] clock as pipeclk_in for lane2 and lane3.
01: Selects pipeclk_out[1] clock as pipeclk_in for lane2 and lane3.
10: Selects pipeclk_out[2] clock as pipeclk_in for lane2 and lane3.
11: Selects pipeclk_out[3] clock as pipeclk_in for lane2 and lane3.
[3:2]
PIPE_PCLKIN_LANE01_SEL
0x0
PIPE clock input selection for lane0 and lane1, can be selected
from one of pipeclk_out[3:0]:
00: Selects pipeclk_out[0] clock as pipeclk_in for lane0 and lane1.
01: Selects pipeclk_out[1] clock as pipeclk_in for lane0 and lane1.
10: Selects pipeclk_out[2] clock as pipeclk_in for lane0 and lane1.
11: Selects pipeclk_out[3] clock as pipeclk_in for lane0 and lane1.
[1:0]
PCIE_CORECLK_SEL
0x0
PCIe core clock selection. PCIe core clock can be selected from
one of pipeclk_out[3:0]:
00: Selects pipeclk_out[0] clock as PCIe core clock.
01: Selects pipeclk_out[1] clock as PCIe core clock.
10: Selects pipeclk_out[2] clock as PCIe core clock.
11: Selects pipeclk_out[3] clock as PCIe core clock.
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-30 • SYSTEM_EPCS_RSTN_SEL (0x206C)
Bit
Number
[3:0]
Name
FABRIC_EPCS_RSTN_SEL
Reset
Value
0x0
Description
EPCS reset signal selection from FABRIC
Table 6-31 • SYSTEM_CHIP_ENABLES (0x2070)
Bit
Number
0
Name
GEN2_SUPPORTED
Reset
Value
0x1
Description
GEN2 enable for PCIe:
1: GEN2 enabled
0: GEN2 disabled
192
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-32 • SYSTEM_SERDES_TEST_OUT (0x2074)
Bit
Number
[31:0]
Name
SERDES_TEST_OUT
Reset
Value
0x0
Description
Status TESTOUT output of PCIe PHY.
SERDES_TEST_OUT[31:24] - Debug signal for lane3
SERDES_TEST_OUT[23:16] - Debug signal for lane2
SERDES_TEST_OUT[15:80] - Debug signal for lane1
SERDES_TEST_OUT[7:0] - Debug signal for lane0
Bit[0]: Tx PLL reset - Active low signals
Bit[1]: Rx PLL reset - Active low signals
Bit[2]: Activity detected
Bit[3]: CDR PLL locked on data
Bit[4]: Tx PLL locked
Bit[5]: Rx PLL locked
Bit[7:6]: reserved
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-33 • SYSTEM_SERDES_FATC_RESET (0x2078)
Bit
Number
0
Name
Reset
Value
SERDES_FATC_RESET
0x1
Description
Fabric alignment test circuit - reset input
Table 6-34 • SYSTEM_RC_OSC_SPLL_REFCLK_SEL (0x207C)
Bit
Number
0
Name
Reset
Value
RC_OSC_REFCLK_SEL
0x1
Description
This bit sets RC OSC as reference clock selection for SPLL.
Table 6-35 • SYSTEM_SPREAD_SPECTRUM_CLK (0x2080)
Bit
Number
[7:3]
Name
PLL_SERDESIF_SSMF
Reset
Value
0x0
Description
Spread spectrum clocking configuration register for feedback divider.
[2:1]
PLL_SERDESIF_SSMD
0x0
Spread spectrum clocking configuration register for reference divider.
0
PLL_SERDESIF_SSE
0x0
Spread spectrum clocking configuration register.
Table 6-36 • SYSTEM_CONF_AXI_MSTR_WNDW_0 (0x2084)
Bit
Number
[31:0]
Name
Reset
Value
CONF_AXI_MSTR_WNDW_0
0x0
Description
PCIe AXI3-master Window0 configuration register – 0
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-37 • SYSTEM_CONF_AXI_MSTR_WNDW_1 (0x2088)
Bit
Number
[31:0]
Name
Reset
Value
CONF_AXI_MSTR_WNDW_1
0x0
Description
PCIe AXI3-master Window0 configuration register – 1
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Revision 5
193
SERDESIF Register Access Map
Table 6-38 • SYSTEM_CONF_AXI_MSTR_WNDW_2 (0x208C)
Bit
Number
[31:0]
Name
CONF_AXI_MSTR_WNDW_2
Reset
Value
0x0
Description
PCIe AXI3-master Window0 configuration register – 2
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-39 • SYSTEM_CONF_AXI_MSTR_WNDW_3 (0x2090)
Bit
Number
[3:0]
Name
CONF_AXI_MSTR_WNDW_3
Reset
Value
0x0
Description
PCIe AXI3-master Window0 configuration register – 3
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-40 • SYSTEM_CONF_AXI_SLV_WNDW_0 (0x2094)
Bit
Number
[31:0]
Name
CONF_AXI_SLV_WNDW_0
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 0
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-41 • SYSTEM_CONF_AXI_SLV_WNDW_1 (0x2098)
Bit
Number
[31:0]
Name
CONF_AXI_SLV_WNDW_1
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 1
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-42 • SYSTEM_CONF_AXI_SLV_WNDW_2 (0x209C)
Bit
Number
[31:0]
Name
CONF_AXI_SLV_WNDW_2
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 2
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-43 • SYSTEM_CONF_AXI_SLV_WNDW_3 (0x20A0)
Bit
Number
[3:0]
Name
CONF_AXI_SLV_WNDW_3
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 3
Note: All registers are 32-bit. Bits not shown in the table are reserved.
194
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-44 • SYSTEM_DESKEW_CONFIG (0x20A4)
Bit
Number
[3:2]
Name
Reset
Value
DESKEW_PLL_FDB_CLK
0x0
Description
These bits set the PLL FEEDBACK clock DESKEW register. Delay
cells addition in the path of FEEDBACK clock to PLL.
00: Bypass delay cells
01: Add 1-cells
10: Add 2-cells
11: Add 3-cells
[1:0]
DESKEW_PLL_REF_CLK
0x0
These bits set the PLL REF clock DESKEW register. Delay cells
addition in the path of REFERENCE clock to PLL.
00: Bypass delay cells
01: Add 1-cells
10: Add 2-cells
11: Add 3-cells
SERDES Macro Register
The SERDES macro register map contains control and status information for the SERDES block and
lanes. Each block uses 256 register bytes. However, these 256 bytes are mapped to 1 KB to make 32-bit
APB output. The APB-to-SERDES programming interface bridge is implemented to convert the system
32-bit APB bus transactions into appropriate 8 bits. Since the SmartFusion2 and IGLOO2 devices map
the 4 SERDES lanes into 1KB blocks., the overall register map size is 4 KB. The physical offset location
of the SERDES macro registers from the SERDESIF system memory map is as follows:
•
0x1000-0x13FF - 1 KB - SERDES programming interface (Lane0)
•
0x1400-0x17FF - 1 KB - SERDES programming interface (Lane1)
•
0x1800-0x1BFF - 1 KB - SERDES programming interface (Lane2)
•
0x1C00-0x1FFF - 1 KB - SERDES programming interface (Lane3)
The SERDESIF system register memory map occupies 1 KB of configuration memory map. Physical
offset location of the SERDESIF system registers is 0x2000-0x23FF from the SERDESIF block memory
map. Table 6-2 on page 180 describes the SERDESIF system registers.
The 1 Kbyte register space can be divided between the protocol-specific read/write register and generic
purpose register.
•
Configuration PHY registers (offset 0x000 to 0x03C): These 16 registers are protocol-specific,
with a reset value depending on the selected protocol, according to CONFIG_PHY_MODE
register settings. For example, PLL_F_PCLK_RATIO register may have different reset values for
PCIe and XAUI mode. PCIe Gen1 features are configured using these 16 8-bit registers.
•
PCIe 5 Gbps PHY registers (offset 0x040 to 0X0BC): These 32 registers are specific to the PCIe
protocol when running at 5 Gbps.
•
SERDES Electrical Parameter registers (offset 0X0C0 to 0X18C): These 48 registers are
internally reported values of parameters programmed inside the SERDES block. These register
descriptions are reserved for factory testing only.
•
SERDES Testing registers (offset 0X190 to 0x1FC): These registers are used for testing the
SERDES block. These register descriptions are reserved for factory testing only.
•
SERDES Recompute register (offset 0x200): This register is a command register that requires
PMA control logic to recompute the SERDES parameter based on the new set of register values
programmed.
•
SERDES PRBS Error Counter registers (offset 0x204 to 0x400): There are 14 registers that are
used for bit error rate testing. These registers are for lane0, lane1, lane2, or lane3 and the
only difference between lane0, lane1, lane2, and lane3 is the base address specifying which
lane it is for. The rest of the register spaces are unused.
Revision 5
195
SERDESIF Register Access Map
Table 6-45 lists the SERDES Macro register mapping including reset values. Unused lanes will default to
0x00 values.
Table 6-45 • SERDES Macro Lane Registers
Register Name
CR0
Address
Offset (Hex)
0x000
Reset
Value
0x80
Type
Description
RW Lane Control register 0
ERRCNT_DEC
0x004
0x20
RW
Clock count for error counter decrement
RXIDLE_MAX_ERRCNT_THR
0x008
0x48 or
0xF8
RW
Error counter threshold – RX0 idle detect
maximum latency
Reset value for PCIe mode: 0x48
IMPED_RATIO
0x00C
0x6D
RW
Reset value for other mode: 0xF8
TX impedance ratio
PLL_F_PCLK_RATIO
0x010
0x24,
RW
PLL F settings and PCLK ratio
0x34, or
0x00
Reset value for PCIe mode:
0x24: 16-bit pipe interface and 250 MHz
PCLK
0x34: 16-bit pipe interface and other PCLK
0x24: 8-bit pipe interface
PLL_M_N
0x014
0x04,
RW
0x13, or
0x69
CNT250NS_MAX
0x018
0x7C,
Reset value for other modes: 0x00
PLL M and N settings
Reset value for PCIe mode: 0x04
Reset value for XAUI mode: 0x13
RW
Reset value for EPCS mode: 0x69
250 ns timer base count
Reset value for PCIe mode: 0x7C Reset
value for XAUI mode: 0x27
0x27, or
0x1F
RE_AMP_RATIO
0x01C
0x00
RW
Reset value for EPCS mode: 0x1F
RX equalization amplitude ratio
RE_CUT_RATIO
0x020
0x00
RW
RX equalization cut frequency
TX_AMP_RATIO
0x024
0x6D
RW
TX_PST_RATIO
0x028
0x15 or
0x00
RW
TX amplitude ratio (Gen 1 PCIe and lower
data rates)
TX post-cursor ratio
Reset value for PCIe mode: 0x15
Reset value for XAUI mode: 0x15
TX_PRE_RATIO
0x02C
0x00
RW
Reset value for EPCS mode: 0x00
TX pre-cursor ratio
ENDCALIB_MAX
0x030
0x10
RW
End of calibration counter
CALIB_STABILITY_COUNT
0x034
0x38
RW
Calibration stability counter
POWERDOWN
0x038
0x00
RW
Power-down feature
RX_OFFSET_COUNT
0x03C
0x70
RW
RX offset counter
PLL_F_PCLK_RATIO_5GBPS
(PCIe Gen2 Protocol Only)
0x040
0x24
RW
PLL F settings and PCLK ratio (in PCIe 5
Gbps speed)
PLL_M_N_5GBPS (PCIe Gen2
Protocol Only)
196
or
0x04
0x044
0x09
R e vi s i o n 5
0x24: 16-bit pipe
RW
0x04: 8-bit pipe
PLL M and N settings (in PCIe 5 Gbps
speed)
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-45 • SERDES Macro Lane Registers (continued)
Address
Offset (Hex)
0x048
Reset
Value
0x7C
TX_PST_RATIO_DEEMP0_FULL
0x050
0x15
TX_PRE_RATIO_DEEMP0_FULL
0x054
0x00
TX_PST_RATIO_DEEMP1_FULL
0x058
0x20
TX_PRE_RATIO_DEEMP1_FULL
0x05C
0x00
TX_AMP_RATIO_MARGIN0_FULL
0x060
0x80
TX_AMP_RATIO_MARGIN1_FULL
0x064
0x78
TX_AMP_RATIO_MARGIN2_FULL
0x068
0x68
TX_AMP_RATIO_MARGIN3_FULL
0x06C
0x60
TX_AMP_RATIO_MARGIN4_FULL
0x070
0x58
TX_AMP_RATIO_MARGIN5_FULL
0x074
0x50
TX_AMP_RATIO_MARGIN6_FULL
0x078
0x48
TX_AMP_RATIO_MARGIN7_FULL
0x07C
0x40
RE_AMP_RATIO_DEEMP0
0x080
0x00
RE_CUT_RATIO_DEEMP0
0x084
0x00
Type
Description
RW 250 ns timer base count (in PCIe 5 Gbps
speed)
RW TX Post-Cursor ratio with TXDeemp = 0, Full
swing, Gen2 speeds
RW TX pre-cursor ratio TXDeemp = 0, full swing,
Gen2 speeds
RW TX post-cursor ratio with TXDeemp = 1, Full
swing, Gen2 speeds
RW TX pre-cursor ratio TXDeemp = 1, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 0, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 1, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 2, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 3, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 4, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 5, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 6, full swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 7, full swing,
Gen2 speeds
RW RX equalization amplitude ratio TXDeemp =
0
RW RX equalization cut frequency TXDeemp = 0
RE_AMP_RATIO_DEEMP1
0x088
0x00
RW
RE_CUT_RATIO_DEEMP1
0x08C
0x00
RW
TX_PST_RATIO_DEEMP0_HALF
0x090
0x15
RW
TX_PRE_RATIO_DEEMP0_HALF
0x094
0x00
RW
TX_PST_RATIO_DEEMP1_HALF
0x098
0x20
RW
TX_PRE_RATIO_DEEMP1_HALF
0x09C
0x00
RW
TX_AMP_RATIO_MARGIN0_HALF
0x0A0
0x50
RW
TX_AMP_RATIO_MARGIN1_HALF
0x0A4
0x58
RW
TX_AMP_RATIO_MARGIN2_HALF
0x0A8
0x48
RW
TX_AMP_RATIO_MARGIN3_HALF
0x0AC
0x40
RW
TX_AMP_RATIO_MARGIN4_HALF
0x0B0
0x38
RW
TX_AMP_RATIO_MARGIN5_HALF
0x0B4
0x30
RW
Register Name
CNT250NS_MAX_5GBPS
Revision 5
RX equalization amplitude ratio TXDeemp =
1
RX equalization cut frequency TXDeemp = 1
TX post-cursor ratio with TXDeemp = 0, half
swing
TX pre-cursor ratio TXDeemp = 0, half swing
TX post-cursor ratio with TXDeemp = 1, half
swing
TX pre-cursor ratio TXDeemp = 1, half swing
TX amplitude ratio TXMargin = 0, half swing,
Gen2 speeds
TX amplitude ratio TXMargin = 1, half swing,
Gen2 speeds
TX amplitude ratio TXMargin = 2, half swing,
Gen2 speeds
TX amplitude ratio TXMargin = 3, half swing,
Gen2 speeds
TX amplitude ratio TXMargin = 4, half swing,
Gen2 speeds
TX Amplitude ratio TXMargin = 5, half swing,
Gen2 speeds
197
SERDESIF Register Access Map
Table 6-45 • SERDES Macro Lane Registers (continued)
Register Name
TX_AMP_RATIO_MARGIN6_HALF
Address
Offset (Hex)
0x0B8
Reset
Value
0x28
TX_AMP_RATIO_MARGIN7_HALF
0x0BC
0x20
PMA_STATUS
0x0C0
0x80
PRBS_CTRL
0x190
0x00
PRBS_ERRCNT
0x194
0x00
RO
PRBS error counter register
PHY_RESET_OVERRIDE
0x198
0x00
RW
PHY reset override register
PHY_POWER_OVERRIDE
0x19C
0x00
RW
PHY power override register
CUSTOM_PATTERN_7_0
0x1A0
0x00
RW
Custom pattern byte 0
CUSTOM_PATTERN_15_8
0x1A4
0x00
RW
Custom pattern byte 1
CUSTOM_PATTERN_23_16
0x1A8
0x00
RW
Custom pattern byte 2
CUSTOM_PATTERN_31_24
0x1AC
0x00
RW
Custom pattern byte 3
Type
Description
RW TX amplitude ratio TXMargin = 6, half swing,
Gen2 speeds
RW TX amplitude ratio TXMargin = 7, half swing,
Gen2 speeds
RO PMA status register- correct read back value
= 0x80
RW PRBS control register
Note: Registers 49-99 are factory reserved for testing purposes.
CUSTOM_PATTERN_39_32
0x1B0
0x00
RW
Custom pattern byte 4
CUSTOM_PATTERN_47_40
0x1B4
0x00
RW
Custom pattern byte 5
CUSTOM_PATTERN_55_48
0x1B8
0x00
RW
Custom pattern byte 6
CUSTOM_PATTERN_63_56
0x1BC
0x00
RW
Custom pattern byte 7
CUSTOM_PATTERN_71_64
0x1C0
0x00
RW
Custom pattern byte 8
CUSTOM_PATTERN_79_72
0x1C4
0x00
RW
Custom pattern byte 9
CUSTOM_PATTERN_CTRL
0x1C8
0x00
RW
Custom pattern control
CUSTOM_PATTERN_STATUS
0x1CC
0x00
RO
Custom pattern status register
PCS_LOOPBACK_CTRL
0x1D0
0x00
RW
PCS loopback control
GEN1_TX_PLL_CCP
0x1D4
0x06
RW
Gen1 transmit PLL current charge pump
GEN1_RX_PLL_CCP
0x1D8
0x66
RW
Gen1 receive PLL current charge pump
GEN2_TX_PLL_CCP
0x1DC
0x06
RW
Gen2 receive PLL current charge pump
GEN2_RX_PLL_CCP
0x1E0
0x66
RW
Gen2 receive PLL current charge pump
CDR_PLL_MANUAL_CR
0x1E4
0x00
RW
CDR PLL manual control
UPDATE_SETTINGS
0x200
0x00
WO
Update settings command register
PRBS_ERR_CYC_FIRST_7_0
0x280
0x00
RO
PRBS_ERR_CYC_FIRST_15_8
0x284
0x00
RO
PRBS_ERR_CYC_FIRST_23_16
0x288
0x00
RO
PRBS_ERR_CYC_FIRST_31_24
0x28C
0x00
RO
PRBS_ERR_CYC_FIRST_39_32
0x290
0x00
RO
PRBS first
bits[7:0]
PRBS first
bits[15:8]
PRBS first
bits[23:16]
PRBS first
bits[31:24]
PRBS first
bits[39:32]
198
R e vi s i o n 5
error cycle counter register
error cycle counter register
error cycle counter register
error cycle counter register
error cycle counter register
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-45 • SERDES Macro Lane Registers (continued)
Register Name
PRBS_ERR_CYC_FIRST_47_40
Address
Offset (Hex)
0x294
Reset
Value
0x00
PRBS_ERR_CYC_FIRST_49_48
0x298
0x00
PRBS_ERR_CYC_FIRST_7_0
0x2A0
0x00
Type
Description
RO PRBS first error cycle counter register
bits[47:40]
RO PRBS first error cycle counter register bits
[49:48]
RO PRBS last error cycle counter register
bits[7:0]
Note: Registers 129 to 159 are not used.
PRBS_ERR_CYC_FIRST_15_8
0x2A4
0x00
RO
PRBS_ERR_CYC_FIRST_23_16
0x2A8
0x00
RO
PRBS_ERR_CYC_FIRST_31_24
0x2AC
0x00
RO
PRBS_ERR_CYC_FIRST_39_32
0x2B0
0x00
RO
PRBS_ERR_CYC_FIRST_47_40
0x2B4
0x00
RO
PRBS_ERR_CYC_FIRST_49_48
0x2B8
0x00
RO
Revision 5
PRBS last
bits[15:8]
PRBS last
bits[23:16]
PRBS last
bits[31:24]
PRBS last
bits[39:32]
PRBS last
bits[47:40]
PRBS last
bits[49:48]
error cycle counter register
error cycle counter register
error cycle counter register
error cycle counter register
error cycle counter register
error cycle counter register
199
SERDESIF Register Access Map
SERDES Block Register Bit Definitions
The following tables give bit definitions for the registers of the SERDES block registers.
The published register syntax is prefixed by LANEn (where n is 0:3). The register bit is appended to the
block register name.
Example: LANE0_CR0.AUTOSHIFT
Table 6-46 • CR0
Bit
Number
Name
7
AUTO_SHIFT
Reset
Value
Description
0x1 Defines whether the electrical idle 1 pattern is automatically
shifted in the SERDES macro after loading the drive pattern.
When set to 1, electrical idle I or Drive mode can be entered
within a single aTXClkp clock cycle. When set to 0, 23 clock
cycles are required to dynamically switch between electrical
idle I and Drive mode. In general, this bit is always set to 1.
Unused lanes are set to 0.
6
FORCE_RX_DETECT
0x0 Forces the result of PCIe receiver detect operation to be
always detected. This register can be used on unreliable
results of RX detect operations. When set to 1, the result of
the PCIe receiver detect operation is always positive and thus
makes the PHY non-compliant to PCIe.
[5:4]
CDR_REFERENCE
0x0 Defines the CDR reference PLL mode. By default, these two
bits must be set to 00 when RefClk is used for the CDR
reference clock.
3
PMA_DRIVEN_MODE
0x0 Puts the CDR PLL in PMA driven mode. When set to 0, the
PCS driven mode is selected for locking the SERDES CDR
circuitry and when set to 1, PMA driven mode is used.
2
CDR_PLL_DELTA
0x0 Defines the frequency comparator threshold value to switch
from fine grain locking to frequency lock and thus control the
input signal of the PMA macro when CDR is configured in
PMA driven mode, and the equivalent function when the PMA
is configured in PCS driven mode. When set to 0, the RX clock
and TX clock must be in a 0.4% difference range; 0.8% when
set to 1.
1
SIGNAL_DETECT_THRESHOLD
0x0 Defines the Schmitt trigger signal detection threshold used to
detect electrical idle on RX. When set to 0, threshold is 
125 mV (±40%), and when set to 1, threshold is 180 mV
(±33%).
0
TX_SELECT_RX_FEEDBACK
0x0 Must be set to 0 when RefClk is used for TX PLL. Set to 1
when the CDR PLL is used as TX PLL reference clock.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Table 6-47 • ERRCNT_DEC
Bit
Reset
Number
Name
Value
Description
[7:0]
ERRCNT_DEC 0x20 In PCS driven mode, the PMA control logic counts the number of errors detected
by the PCS logic in order to decide to switch back to frequency lock mode of the
CDR PLL. This counter is used to decrement the error counter every
16*errcnt_dec[7:0] aTXClk clock cycles.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
200
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Table 6-48 • RXIDLE_MAX_ERRCNT_THR
Bit
Number
[7:4]
Name
RXIDLE_MAX
Reset Value
0x4-PCIe
0xF-others
[3:0]
ERRCNT_THR
0x8
Description
Defines the number of clock cycles required before the activity
detected output of the PMA macro and reports either electrical idle
or valid input data. This register must be set to at least 3 because
the activity detected signal is considered as metastable by the PCS
logic.
In PCS driven mode, the PMA control logic counts the number of
errors detected by the PCS logic in order to decide to switch back
to frequency lock mode of the CDR PLL. This register defines the
error counter threshold value after which the CDR PLL switches
Note: This register can be reprogrammed any time during operation.
Table 6-49 • IMPED_RATIO
Bit
Number
[7:0]
Name
IMPED_RATIO
Reset Value
0x8
Description
Fine-tunes the impedance ratio of the PMA macro with a nominal
value of 100 , corresponding to a multiplication factor of 1, which
is encoded 8'd128. A 150  impedance corresponds to 2/3 ratio,
encoded 8'd85.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Table 6-50 • PLL_F_PCLK_RATIO
Bit
Number
[7:6]
Name
Reserved
[5:4]
DIV_MODE0
[3:0]
F
Reset Value
PCIe mode: 0x0
XAUI mode:0x0
EPCS mode:0x0
PCIe mode: 0x3
XAUI mode: 0x0
EPCS mode: 0x0
Description
Defines the ratio between PCLK and aTXClk. PCLK is used by the
PCIe PCS logic as well as by the majority of the PMA control logic
and thus is also useful for other protocols in order to reduce the
amount of logic requiring a high aTXClk frequency. In non-PCIe
mode, this register is only useful if pipe_pclkout is used by any
logic. A value of 00 is used for divide-by-1, 10 for divide by-2 and 11
for divide-by-4.
Defines the aRXF[3:0] and aTXF[3:0] settings of the PMA macro.
The same F value is applied to both RX and TX PLL.
PCIe mode: 0x4
XAUI mode: 0x0
EPCS mode: 0x0
Note: This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under
reset.
Revision 5
201
SERDESIF Register Access Map
Table 6-51 • PLL_M_N
Bit
Number
7
Name
CNT250NS_MAX[8]
Reset Value
Description
PCIe mode: 0x0 This bit is concatenated to the Reg06 register as an MSB to
XAUI mode: 0x0 define the 250 ns base time.
EPCS mode: 0x0
[6:5]
M[1:0]
PCIe mode: 0x0 Defines the TX PLL M values and CDR PLL M value settings of
XAUI mode: 0x0 the PMA macro. For PCIe, it corresponds to the Gen1 settings.
EPCS mode: 0x1 The same M value is applied to both RX and TX PLL.
[4:0]
N[4:0]
PCIe mode: 0x4 Defines the TX PLL N values and CDR PLL N value settings of
XAUI mode: 0x13 the PMA macro. For PCIe, it corresponds to the Gen1 settings.
EPCS mode: 0x9 The same N value is applied to both RX and TX PLL.
Note: This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under
reset.
Table 6-52 • CNT250NS_MAX
Bit
Number
[7:0]
Name
CNT250NS_MAX
Reset Value
Description
PCIe mode: 0x7C Defines the base count of a 250 ns event based on the aTXClk
XAUI mode: 0x27 clock. This counter is used by the CDR PLL in PCS driven
mode and also by the PMA control logic for operations such as
EPCS mode: 0x20
receiver detect and electrical idle 2 and 3 states. In the case of
a non-integer value, the base count should be rounded up.
This register must be set correctly for all protocols.
Note: This register must only be reprogrammed when the PHY is under reset for proper operation. It impacts the PCSdriven CDR PLL mode as well as calibration and thus has no effect after calibration is completed (PMA is ready)
or if the PHY CDR PLL is used in PMA driven mode.
Table 6-53 • RE_AMP_RATIO
Bit
Number
[7:0]
Name
RE_AMP_RATIO
Reset Value
0x00
Description
Defines the RX equalization amplitude ratio where the
maximum value of 8’d128 corresponds to 100%. If RX
equalization is not used, this register can be set to zero.
Note: This register can be reprogrammed during normal operation but the effect will only appear when the parameters
for the SERDES receiver are updated (at the end of calibration or when UPDATE_SETTINGS is programmed.
Table 6-54 • RE_CUT_RATIO
Bit
Number
[7:0]
Name
RE_CUT_RATIO
Reset Value
0x00
Description
Defines the RX equalization cut frequency ratio, used in the
computation of Rn[3:0] and Rd[3:0] equalization settings of the
PMA macro. The encoding of this register is such that 
(Rn + Rd) = (RE_CUT_RATIO)/256*W_SETTING where
W_SETTING is the result of RX equalization calibration.
Note: This register can be reprogrammed during normal operation but the effect will only appear when the parameters
for the SERDES receiver are updated (at the end of calibration or when UPDATE_SETTINGS is programmed).
202
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Table 6-55 • TX_AMP_RATIO
Bit
Number
[7:0]
Name
TX_AMP_RATIO
Reset Value
Description
0x80
Implements the TX amplitude ratio used by the TX driver. A value of
128 corresponds to 100% (full voltage); a value of 0 corresponds to
0%. Values higher than 128 are forbidden. For PCIe, this register is
used for Gen1 speed only.
Note: This register can be reprogrammed during normal operation but the effect will only appear when the parameters
for the SERDES transmitter are updated (at the end of calibration, on entry or exit of TX electrical idle I or when
UPDATE_SETTINGS is programmed).
Table 6-56 • TX_PST_RATIO
Bit
Number
[7:0]
Name
TX_PST_RATIO
Reset Value
Description
0x15
Defines the TX post-cursor ratio for the Gen1 speed used for selecting
the de-emphasis of the switching bit versus non-switching bit. A value
of 128 corresponds to 100% (full voltage); a value of 0 corresponds to
0%. A value of –3.5 dB corresponds to 8’d21 encoding.
Note: This register can be reprogrammed during normal operation but the effect will only appear when the parameters
for the SERDES transmitter are updated (at the end of calibration, on entry or exit of TX Electrical Idle I or when
UPDATE_SETTINGS is programmed).
Table 6-57 • TX_PRE_RATIO
Bit
Number
[7:0]
Name
TX_PRE_RATIO
Reset Value
Description
0x00
Defines the TX pre-cursor ratio for the Gen1 speed used for selecting
the de-emphasis of the switching bit versus non-switching bit. A value
of 128 corresponds to 100% (full voltage); a value of 0 corresponds to
0%.
Note: This register can be reprogrammed during normal operation but the effect appears only when the parameters for
the SERDES transmitter are updated (at the end of calibration, on entry or exit of TX electrical idle I or when
UPDATE_SETTINGS is programmed).
Table 6-58 • ENDCALIB_MAX
Bit
Number
[7:0]
Name
ENDCALIB_MAX
Reset Value
Description
0x10
Defines the amount of time in microseconds required by the PMA to
settle its electrical level after loading electrical idle 1 in the TX driver at
the end of calibration. All operations are automatically performed by
the PMA control logic but that the SERDES transmitter can start driving
data on the link immediately after the end of calibration. By default
(except if forbidden by protocol) a 10 µs delay between end of
Calibration and Mission mode is set (but any value might work as well).
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Revision 5
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SERDESIF Register Access Map
Table 6-59 • CALIB_STABILITY_COUNT
Bit
Number
Name
[7:5]
CALIB_SETTLE_MAX
Reset
Value
0x1
[4:0]
0x18
CALIB_STABLE_MAX
Description
Defines the amount of time in microseconds required by the PMA to
settle its electrical level after loading electrical idle 1 in the TX driver at
the end of calibration. Note that all operation is automatically performed
by the PMA control logic but that the SERDES transmitter can start
driving data on the link immediately after end of calibration. By default,
except if forbidden by protocol, a 10 µs delay between end of
calibration and mission mode is set (but any value might work as well).
This register defines the number of clock cycles before which the
impedance calibrator results (aZCompOp = 1, impedance calibrator
result is greater than nominal; and aZCompOp = 0, impedance
calibrator result is less than nominal) signal can be checked for stability
after impedance calibration control values (aZCalib) modification.
aZCompOp = 1, when Impedance calibrator result > nominal
0, when Impedance calibrator result < nominal
This is used for TX, RX, and RX equalization calibration.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Table 6-60 • POWERDOWN
Bit
Number
Name
[7:6]
RXIDLE_MSB
Reset
Value
0x0
5
FORCE_SIGNAL
0x0
4
FORCE_IDLE
0x0
3
NO_FCMP
0x0
204
Description
These bits are used as the most significant bits (MSBs) of the activity
detector logic, to specify that no activity has been detected during up to
61 aTXClkp clock cycles. These bits are the two MSBs; the
rxidle_max[3:0] field of Reg02 represents the least significant bit (LSB)
part.
When this bit is set, the PHY disables the Idle detection circuitry and
forces signal detection on the receiver. This bit is generally always set
to disable (0) unless the activity detector logic must be bypassed. In that
case, the PMA control logic always reports activity detected on the link
(when set to 1). This bit can be used, for instance, if the activity detector
of the SERDES PMA hard macro does not work for the selected
protocol (as outside range of functionality).
When this bit is set, the PHY disables the Idle detection circuitry and
forces electrical Idle detection on the receive side. By default, this bit is
generally cleared and might be set only for very specific conditions or
testing such as generating a fake loss of signal to the PCS or MAC
layer, forcing a retraining of word aligner or any training state machine.
As long as this bit is set, the activity detector logic of the PMA control
logic reports that no signal is detected on the receive side. If CDR PLL
PCS driven mode is selected, the CDR PLL will be directed in lock to
the reference clock state, leading to potential wrong data received by
the SERDES (because the CDR PLL is not locked to incoming data).
When set, this bit disables the frequency comparator logic of the PCS
driven CDR PLL control logic. When not set, the frequency comparator
logic is no longer part of the condition for going from fine-grain lock state
to frequency acquisition. This mode locks to the refclk.
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-60 • POWERDOWN (continued)
Bit
Number
Name
2
PMFF_ALL
Reset
Value
0x0
1
CDR_ERR
0x0
0
CDR_P1
0x0
Description
Used with PCIe only, this register when set disables the function that
waits for every active lane to have valid data to transmit before
generating a global read enable. This bit is intended to be used in case
of any issue with this function. When set, each lane might start
transmitting data with one 500 MHz clock uncertainty (corresponding to
5 or 10 bits time, depending on the speed of the link). Even if violating
the protocol requirement, the PCIe standard is strong enough to
support this non-compliance.
When set, this register disables the error counter internally of the CDR
PLL state machine, which switches back the CDR PLL to frequency
mode acquisition when the number of errors counted is higher than the
predefined error threshold. This bit is intended for disabling this function
in the case of any issue with the PHY. This is available for all SERDES
modes.
Defines the state of the CDR PLL when the PHY is in P1 Low power
mode.
When set to zero, the CDR PLL is put in reset and low power, enabling
maximum power savings. When the opposite component sends the
TS1 ordered set to drive the link in recovery, only the
PIPE_RXELECIDLE signal is deasserted at the PIPE interface and the
PHY waits for the controller to change the pipe_powerdown[1:0] signal
back to P0 before retraining the CDR PLL (~6 µs) and sending received
data to the controller.
When set to 1, the CDR PLL is kept alive in Frequency lock mode in the
P1 state, which enables a faster recovery time from the P1 state but
which also consumes more power (all RX logic is kept alive and
consumes power in the P1 state). This register must not be set for
applications which remove the reference clock in P1 mode (generally
associated with the CLKREQ# signal, express card application, and
more generally power sensitive application).
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready), except for bit 2, which can only be modified under reset condition.
Table 6-61 • RX_OFFSET_COUNT
Bit
Number
Name
[7:5]
RXOFF_SETTLE_MAX
Reset
Value
0x3
Description
Defines the number of clock cycles before which the aRXDNullDat
signal can be checked for stability after aRXDNull[3:0] modification. This
is used also for aRXD, aRXT, and Schmitt trigger calibration. The value
of this register expresses a number of (2*N+1) PCLK clock cycles.
[4:0]
RXOFF_STABLE_MAX 0x10 Defines the number of clock cycles where the aRXDNullDat signal is
checked for stability.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Revision 5
205
SERDESIF Register Access Map
Table 6-62 • PLL_F_PCLK_RATIO_5GBPS (PCIe Gen2 Protocol Only)
Bit
Number
[7:6]
Reserved
Name
Reset
Value
0x0
Description
[5:4]
DIV_MODE1
0x2
Defines the ratio between PCLK and aTXClk for the PCIe
Gen2 protocol.
[3:0]
F
0x4
Defines the F setting for the TX PLL and CDR PLL of the
PMA macro for the PCIe Gen2 protocol.
Note: This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under
reset.
Table 6-63 • PLL_M_N_5GBPS (PCIe Gen2 Protocol Only)
Bit
Number
Name
7
CNT250NS_MAX_5G BPS[8]
Reset
Value
0x0
Description
Defines bit 7 and bit 6 of the cnt250ns_max counter
mentioned in Reg18.
[6:5]
M
0x0
Defines the TX PLL M values and CDR PLL M value settings
of the PMA macro for the PCIe Gen2 protocol.
[4:0]
N
0x9
Defines the TX PLL N values and CDR PLL N value settings
of the PMA macro for the PCIe Gen2 protocol.
Note: This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under
reset.
Table 6-64 • CNT250NS_MAX_5GBPS
Bit
Number
Name
[7:0]
CNT250NS_MAX_5GBPS[7:0]
Reset
Value
0x7C
Description
This register defines the base count of a 250 ns event
EPCS-0x00 based on the aTXClk clock. This counter is used by the
CDR PLL in PCS driven mode.
Note: This register must only be reprogrammed when PHY is under reset for proper operation. It impacts the PCSdriven CDR PLL mode as well as calibration. Thus, it has no effect after calibration is completed (PMA is ready)
or if the PHY CDR PLL is used in PMA driven mode.
206
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The following registers in Table 6-65 through Table 6-88 on page 211 can be reprogrammed during normal
operation but the effect appears when the parameters for the SERDES transmitter are updated (on entry
or exit of TX electrical idle I, when UPDATE_SETTINGS is programmed, or when any of the PIPE
TXSwing, TXDeemp, or TXMargin signals is modified).
Table 6-65 • TX_PST_RATIO_DEEMP0_FULL
Bit
Number
Name
[7:0]
TX_PST_RATIO_DEEMP0_FULL
Reset
Value
Description
Defines the TX post-cursor ratio used for selecting the
0x15
EPCS-0x00 de-emphasis of the switching bit versus non-switching bit.
A value of 128 corresponds to 100% (full voltage); a value
of 0 corresponds to 0%. A value of –3.5 dB corresponds
to 8’d21 encoding.
Table 6-66 • TX_PRE_RATIO_DEEMP0_FULL
Bit
Reset
Number
Name
Value
Description
[7:0]
TX_PRE_RATIO_DEEMP0_FULL 0x00 Defines the TX pre-cursor ratio used for selecting the 
de-emphasis of the switching bit versus non-switching bit. A
value of 128 corresponds to 100% (full voltage); a value of 0
corresponds to 0%.
Table 6-67 • TX_PST_RATIO_DEEMP1_FULL
Bit
Reset
Number
Name
Value
Description
[7:0]
TX_PST_RATIO_DEEMP1_FULL 0x20 Defines the TX post-cursor ratio for the Gen2 speed used for
selecting the de-emphasis of the switching bit versus nonswitching bit. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. A value of –3.5 dB
corresponds to 8’d21 encoding.
Table 6-68 • TX_PRE_RATIO_DEEMP1_FULL
Bit
Reset
Number
Name
Value
Description
[7:0]
TX_PRE_RATIO_DEEMP1_FULL 0x00 Defines the TX pre-cursor ratio for the Gen2 speed used for
selecting the de-emphasis of the switching bit versus 
non-switching bit. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%.
Table 6-69 • TX_AMP_RATIO_MARGIN0_FULL
Bit
Reset
Number
Name
Value
Description
[7:0]
TX_AMP_RATIO_MARGIN0_FULL 0x80 This register implements the TX amplitude ratio used by the
TX driver. A value of 128 corresponds to 100% (full voltage); a
value of 0 corresponds to 0%. Values higher than 128 are
forbidden.
Revision 5
207
SERDESIF Register Access Map
Table 6-70 • TX_AMP_RATIO_MARGIN1_FULL
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN1_FULL
Reset
Value
0x78
Description
Implements the TX amplitude ratio used by the TX driver.
A value of 128 corresponds to 100% (full voltage); a value
of 0 corresponds to 0%. Values higher than 128 are
forbidden.
Table 6-71 • TX_AMP_RATIO_MARGIN2_FULL
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN2_FULL
Reset
Value
0x68
Description
Implements the TX amplitude ratio used by the TX driver.
A value of 128 corresponds to 100% (full voltage); a value
of 0 corresponds to 0%. Values higher than 128 are
forbidden.
Table 6-72 • TX_AMP_RATIO_MARGIN3_FULL
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN3_FULL
Reset
Value
0x60
Description
Implements the TX amplitude ratio used by the TX driver.
A value of 128 corresponds to 100% (full voltage); a value
of 0 corresponds to 0%. Values higher than 128 are
forbidden.
Table 6-73 • TX_AMP_RATIO_MARGIN4_FULL
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN4_FULL
Reset
Value
0x58
Description
Implements the TX amplitude ratio used by the TX driver.
A value of 128 corresponds to 100% (full voltage); a value
of 0 corresponds to 0%. Values higher than 128 are
forbidden.
Table 6-74 • TX_AMP_RATIO_MARGIN5_FULL
Bit
Number
[7:0]
208
Name
TX_AMP_RATIO_MARGIN5_FULL
Reset
Value
0x50
Description
Implements the TX amplitude ratio used by the TX driver.
A value of 128 corresponds to 100% (full voltage); a value
of 0 corresponds to 0%. Values higher than 128 are
forbidden.
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-75 • TX_AMP_RATIO_MARGIN6_FULL
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN6_FULL
Reset
Value
0x48
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-76 • TX_AMP_RATIO_MARGIN7_FULL
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN7_FULL
Reset
Value
0x40
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-77 • TX_PST_RATIO_DEEMP0_HALF
Bit
Number
[7:0]
Name
TX_PST_RATIO_DEEMP0_HALF
Reset
Value
0x15
Description
Defines the TX post-cursor ratio for the Gen2 speed
used for selecting the de-emphasis of the switching bit
versus non-switching bit. A value of 128 corresponds to
100% (full voltage); a value of 0 corresponds to 0%. A
value of –3.5 dB corresponds to 8’d21 encoding.
Table 6-78 • TX_PRE_RATIO_DEEMP0_HALF
Bit
Number
[7:0]
Name
TX_PRE_RATIO_DEEMP0_HALF
Reset
Value
0x00
Description
Defines the TX pre-cursor ratio for the Gen2 speed
used for selecting the de-emphasis of the switching bit
versus non-switching bit. A value of 128 corresponds to
100% (full voltage); a value of 0 corresponds to 0%.
Table 6-79 • TX_PST_RATIO_DEEMP1_HALF
Bit
Number
[7:0]
Name
TX_PST_RATIO_DEEMP1_HALF
Reset
Value
0x20
Description
Defines the TX post-cursor ratio for the Gen2 speed
used for selecting the de-emphasis of the switching bit
versus non-switching bit. A value of 128 corresponds to
100% (full voltage); a value of 0 corresponds to 0%. A
value of –3.5 dB corresponds to 8’d21 encoding.
Revision 5
209
SERDESIF Register Access Map
Table 6-80 • TX_PRE_RATIO_DEEMP1_HALF
Bit
Number
[7:0]
Name
TX_PRE_RATIO_DEEMP1_HALF
Reset
Value
0x00
Description
Defines the TX pre-cursor ratio for the Gen2 speed
used for selecting the de-emphasis of the switching bit
versus non-switching bit. A value of 128 corresponds to
100% (full voltage); a value of 0 corresponds to 0%.
Table 6-81 • TX_AMP_RATIO_MARGIN0_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN0_HALF
Reset
Value
0x50
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-82 • TX_AMP_RATIO_MARGIN1_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN1_HALF
Reset
Value
0x58
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-83 • TX_AMP_RATIO_MARGIN2_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN2_HALF
Reset
Value
0x48
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-84 • TX_AMP_RATIO_MARGIN3_HALF
Bit
Number
[7:0]
210
Name
TX_AMP_RATIO_MARGIN3_HALF
Reset
Value
0x40
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-85 • TX_AMP_RATIO_MARGIN4_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN4_HALF
Reset
Value
0x38
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-86 • TX_AMP_RATIO_MARGIN5_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN5_HALF
Reset
Value
0x30
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-87 • TX_AMP_RATIO_MARGIN6_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN6_HALF
Reset
Value
0x28
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Table 6-88 • TX_AMP_RATIO_MARGIN7_HALF
Bit
Number
[7:0]
Name
TX_AMP_RATIO_MARGIN7_HALF
Reset
Value
0x20
Description
Implements the TX amplitude ratio used by the TX
driver. A value of 128 corresponds to 100% (full
voltage); a value of 0 corresponds to 0%. Values higher
than 128 are forbidden.
Revision 5
211
SERDESIF Register Access Map
The following registers in Table 6-89 through Table 6-92 can be reprogrammed during normal operation
but the effect appears when the parameters for the SERDES transmitter are updated (on entry or exit of
TX electrical idle I, when UPDATE_REGISTER is programmed, or when any of the PIPE TXSwing,
TXDeemp, or TXMargin signals is modified).
Table 6-89 • RE_AMP_RATIO_DEEMP0
Bit
Number
[7:0]
Name
RE_AMP_RATIO_DEEMP0
Reset
Value
0x00
Description
Defines the RX Equalization amplitude ratio where the
maximum value is 8’d128, corresponding to 100%. If RX
equalization is not used, this register can be set to zero.
Note: This register must only be reprogrammed when the PHY
is under reset for proper operation.
Table 6-90 • RE_CUT_RATIO_DEEMP0
Bit
Number
[7:0]
Name
RE_CUT_RATIO_DEEMP0
Reset
Value
0x00
Description
Defines the RX equalization cut frequency ratio, used in the
computation of Rn[3:0] and Rd[3:0] equalization settings of the
PMA macro. The encoding of this register is such that
(Rn + Rd) = (RE_CUT_RATIO)/256*W_SETTING,
W_SETTING being the result of the RX equalization
calibration.
Table 6-91 • RE_AMP_RATIO_DEEMP1
Bit
Number
[7:0]
Name
RE_AMP_RATIO_DEEMP1
Reset
Value
0x00
Description
Defines the RX equalization amplitude ratio where the
maximum value is 8’d128, corresponding to 100%. If RX
equalization is not used, this register can be set to zero.
Note: This register must only be reprogrammed when the PHY
is under reset for proper operation.
Table 6-92 • RE_CUT_RATIO_DEEMP1
Bit
Number
[7:0]
Name
RE_CUT_RATIO_DEEMP1
Reset
Value
0x00
Description
Defines the RX equalization cut frequency ratio, used in the
computation of Rn[3:0] and Rd[3:0] equalization settings of the
PMA macro. The encoding of this register is such that
(Rn+Rd) = (RE_CUT_RATIO)/256*W_SETTING,
W_SETTING being the result of RX equalization calibration.
212
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Table 6-93 • PMA_STATUS
Bit
Number
7
Name
PMA_RDY
Reset
Value
0x01
[6:0]
Description
This read-only register indicates that the PMA has completed it internal
calibration sequence after power-up and PHY reset de-assertion.
Reserved
Table 6-94 • PRBS_CTRL
Bit
Number
7
6
Name
Reset
Value
Description
Unused
PRBS_CHK
0x0
When set, this signal starts the PRBS pattern checker. It can be set at the
same time as the PRBS generator while the PRBS checker logic waits for
256 clock cycles and CDR being in lock state to enable the PRBS pattern
comparison (allowing a total latency of 256 cycles to loop back the
transmitted data).
[5:4]
Reserved
[3:2]
PRBS_TYP[1:0]
0x0
1
LPBK_EN
0x0
0
PRBS_GEN
0x0
Defines the type of PRBS pattern which is applied. PRBS7 when set to 00,
PRBS11 when set to 01, PRBS23 when set to 10, PRBS31 when set to 11.
When set, the PMA is put in near-end loopback (serial loopback from TX
back to RX). PRBS tests can be done using the near-end loopback of the
PMA, some load board, or any far-end loopback implemented in the
opposite component. When near-end loopback bit is set, the idle detector
always reports valid data, enabling the PCS driven CDR PLL locking logic to
lock on input data.
When set, this signal starts the PRBS pattern transmission.
Note: This register can be programmed any time but has functional impact because it can configure the SERDES in
loopback or generate the PRBS pattern.
Table 6-95 • PRBS_ERRCNT
Bit
Number
[7:0]
Name
PRBS_ERRCNT[7:0]
Reset
Value
0x00
Description
This test reports the number of PRBS errors detected when the
PRBS test is applied.
This register is automatically cleared when the PRBS_EN
register is cleared (requiring testing the value of this register
when the test is running).
The PRBS error counter saturates at 254 errors, the 255 count
value corresponding to an error code where the CDR PLL is
not locked to incoming data. When such an error code is
detected, the PRBS test must wait for a longer time for the CDR
PLL to synchronize on input data before enabling the PRBS
checker or simply timeout, reporting that no data has been
received at all.
Note: The PRBS error counter logic also counts errors when
the PRB Sinvariant (all zero value) is obtained,
considering input data as error data.
Revision 5
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SERDESIF Register Access Map
Table 6-96 • PHY_RESET_OVERRIDE
Bit
Number
7
Name
RXHF_CLKDN
Reset
Value
0x0
6
TXHF_CLKDN
0x0
When set, this signal disables the TX PLL VCO by applying a static zero
to the PMA aTXHfClkDnb signal.
5
RXPLL_RST
0x0
When set, this signal resets the RX PLL settings by applying a static zero
to the PMA aCdrPllRstb signal.
4
TXPLL_RST
0x0
When set, this signal initializes the TX PLL settings by applying a static
zero to the PMA aTXPllRstb signal.
3
RXPLL_INIT
0x0
When set, the signal initializes the RX PLL settings by applying a static
one to the PMA aRXPllDivInit signal.
2
TXPLL_INIT
0x0
When set, this signal initializes the TX PLL settings by applying a static
one to the PMA aTXPllDivInit signal.
1
RX_HIZ
0x0
When set, this signal forces the RX driver to hiZ, applying a static one to
the PMA aForceRXHiZ signal.
0
TX_HIZ
0x0
When set, this signal forces the TX driver to hiZ, applying a static one to
the PMA aForceTXHiZ signal.
Description
When set, this signal disables the RX PLL VCO settings by applying a
static zero to the PMA aRXHfClkDnb signal.
Note: This register can be programmed any time but has functional impact on the SERDES because it can put the
PLL under reset or place part of the SERDES in Low power mode, bypassing the functional mode.
Table 6-97 • PHY_POWER_OVERRIDE
Bit
Number
[7:1]
0
Name
Reset
Value
Description
Unused
RX_PWRDN
0x0
When set, this register forces the RX PMA logic to be in Power-down
mode.
Note: This register can be programmed any time but has functional impact on the SERDES because it can powerdown the receiver part of the SERDES, bypassing the functional mode.
Table 6-98 • CUSTOM_PATTERN_7_0
Bit
Number
[7:0]
Reset
Value
0x00
Description
Enables bit 7 to bit 0 to program a custom pattern instead of the
implemented PRBS generator/checker. The PRBS mode must
still be selected to transmit this custom pattern on the transmit line
but this mode enables the generation of any repeated sequence
of data. It can be used, for instance, for single lane PCIe
compliance pattern generation (for the purpose of an eye diagram
compliance check) or can even be looped back to the receiver to
check if any error is detected on the line. In the latter case, the
PMA hard macro function is used to perform a word alignment
function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
214
Name
CUSTOM_PATTERN[7:0]
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Table 6-99 • CUSTOM_PATTERN_15_8
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [15:8]
Reset
Value
0x00
Description
Enables bit 15 to bit 8 to program a custom pattern instead of
the implemented PRBS generator/checker. The PRBS mode
must still be selected to transmit this custom pattern on the
transmit line, but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA hard macro
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-100 • CUSTOM_PATTERN_23_16
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [23:16]
Reset
Value
0x00
Description
Enables bit 23 to bit 16 to program a custom pattern instead
of the implemented PRBS generator/checker. PRBS mode
must still be selected to transmit this custom pattern on the
transmit line but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even be
looped back to the receiver to check if any error is detected
on the line. In the latter case, the PMA hard macro function is
used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-101 • CUSTOM_PATTERN_31_24
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [31:24]
Reset
Value
0x00
Description
This register enables bit 31 to bit 24 to program a custom
pattern instead of the implemented PRBS generator/checker.
PRBS mode must still be selected to transmit this custom
pattern on the transmit line, but this mode enables the
generation of any repeated sequence of data. It can be used,
for instance, for single lane PCIe compliance pattern
generation (for the purpose of an eye diagram compliance
check) or can even be looped back to the receiver to check if
any error is detected on the line. In the latter case, the PMA
hard macro function is used to perform word alignment
function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Revision 5
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SERDESIF Register Access Map
Table 6-102 • CUSTOM_PATTERN_39_32
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [39:32]
Reset
Value
0x00
Description
Enables bit 39 to bit 32 to program a custom pattern instead
of the implemented PRBS generator/checker. PRBS mode
must still be selected to transmit this custom pattern on the
transmit line, but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA hard macro
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-103 • CUSTOM_PATTERN_47_40
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [47:40]
Reset
Value
0x00
Description
Enables bit 47 to bit 40 to program a custom pattern instead
of the implemented PRBS generator/checker. PRBS mode
must still be selected to transmit this custom pattern on the
transmit line, but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for purpose
of eye diagram compliance check) or can even be looped
back to the receiver to check if any error is detected on the
line. In the latter case, the PMA hard macro function is used
to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-104 • CUSTOM_PATTERN_55_48
Bit
Number
[7:0]
Reset
Value
0x00
Description
Enables bit 55 to bit 48 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern on
the transmit line but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even be
looped back to the receiver to check if any error is detected
on the line. In the latter case, the PMA hard macro function is
used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
216
Name
CUSTOM_PATTERN [55:48]
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Table 6-105 • CUSTOM_PATTERN_63_56
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [63:56]
Reset
Value
0x00
Description
Enables bit 63 to bit 56 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern
on the transmit line but this mode enables the generation of
any repeated sequence of data. It can be used, for instance,
for single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA hard macro
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-106 • CUSTOM_PATTERN_71_64
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [71:64]
Reset
Value
0x00
Description
Enables bit 71 to bit 64 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern
on the transmit line but this mode enables the generation of
any repeated sequence of data. It can be used, for instance,
for single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA hard macro
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-107 • CUSTOM_PATTERN_79_72
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [79:72]
Reset
Value
0x00
Description
Enables bit 79 to bit 72 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern on
the transmit line but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA hard macro
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Revision 5
217
SERDESIF Register Access Map
Table 6-108 • CUSTOM_PATTERN_CTRL
Bit
Number
7
RSVD
6
CUST_AUTO
0x0
5
CUST_SKIP
0x0
4
CUST_CHK
0x0
[3:1]
CUST_TYP
0x0
Name
Reset
Value
Description
When this register is set, the word alignment is performed automatically
by a state machine that checks whether the received pattern is wordaligned with the transmitted pattern and automatically use the PMA CDR
PLL skip bit function to find the alignment. Once the word alignment is
detected, the custom pattern checker is now word-aligned and the
custom pattern checker can be enabled for detecting and counting any
error over time.
This register is used in RX word alignment manual mode. The custom
pattern requires word alignment in order to be checked by the receiver
(as opposed to a PRBS pattern, which does not require this word
alignment function). In Manual mode, read the CUST_SYNC register in
order to check whether the word is aligned. If not in Manual mode, a one
bit skip is to the CDR PLL must be done by writing one then zero in this
register (and repeat this sequence until the receiver is aligned).
Enables the error counter. When clear, it also resets the error counter.
Thus, the error counter must be checked before clearing this register.
Defines whether the custom pattern generated on the link is generated
by the custom pattern register or by one of the hard-coded patterns:
000: Custom pattern register
100: All-zero pattern (0000…00)
101: All-one pattern (1111…11)
110: Alternated pattern (1010…10)
111: Dual alternated pattern (1100…1100)
When set, this signal replaces the PRBS data transmitted on the link by
the custom pattern. The PRBS_SEL register must also be set for
transmitting the custom pattern on the link.
Note: This register can be programmed any time but has functional impact on the SERDES because it can directly
activate some part of the SERDES (aRXSkipBit), changing the current bitstream reception (thus creating
alignment errors).
0
CUST_SEL
0x0
Table 6-109 • CUSTOM_PATTERN_STATUS
Bit
Number
[7:5]
Name
CUST_STATE
Reset
Value
0x0
4
CUST_SYNC
0x0
[3:0]
CUST_ERROR[3:0]
0x0
218
Description
Reports the current state of the custom pattern word alignment state
machine. It can be useful for debug purposes (Refer verilog code).
Reports that the custom pattern is word-aligned.
When the custom pattern checker is enabled, this status register reports
the number of errors detected by the logic when the custom word
aligner is in synchronization (it starts counting only after a first matching
pattern has been detected. The word alignment status can be checked
through (cust_state==3’b101) or CUST_SYNC register asserted.
R e vi s i o n 5
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
Table 6-110 • PCS_LOOPBACK_CTRL
Bit
Number
[7:4]
–
Name
Reset
Value
–
Description
Unused
3
MESO_SYNC
0x0
2
MESO_LPBK
0x0
1
Reserved
0x0
Is read-only and reports whether the mesochronous clock alignment
state machine has completed its process, having thus aligned the CDR
receive clock to the transmit clock.
When set, this register enables Mesochronous loopback mode, which
forces PMA received data to be re-transmitted on the PMA TX
interface. This mode requires that no PPM exists between RX data and
TX data (thus, both sides of the link use the same reference clock) and
also performs alignment of the CDR clock to the transmit clock using
the PMA CDR PLL skip bit functionality. This alignment is automatically
performed by a state machine when this loopback register is set.
–
0
Reserved
0x0
–
Table 6-111 • GEN1_TX_PLL_CCP
Bit
Number
[7:3]
–
[2:0]
ATXICP_RATE0[2:0]
Name
Reset
Value
–
Description
Reserved
0x0
Defines the TX PLL charge pump current when the PMA is running in
PCIe Gen1 speed or in any other protocol. This register is R/W in order
to enable changing the default value by register programming, which is
expected to be performed before reset deassertion.
Note: This register can be programmed when the PHY is under reset.
Revision 5
219
SERDESIF Register Access Map
Table 6-112 • GEN1_RX_PLL_CCP
Bit
Number
7
Reserved
[6:4]
ARXCDRICP_RATE0[2:0]
0x0
3
Reserved
0x0
[2:0]
ARXICP_RATE0[2:0]
0x0
Name
Reset
Value
0x0
Description
Reserved
Defines the RX PLL charge pump current when the PMA is
frequency locked and running in PCIe Gen1 speed or in any
other protocol. This register is R/W in order to enable changing
the default value by register programming, which is expected to
be performed before reset deassertion.
Reserved
Defines the RX PLL charge pump current when the PMA is
CDR locked and running in PCIe Gen1 speed or in any other
protocol. This register is R/W in order to enable changing the
default value by register programming, which is expected to be
performed before reset deassertion.
Note: This register can be programmed when the PHY is under reset.
Table 6-113 • GEN2_TX_PLL_CCP
Bit
Number
7
Reserved
[6:4]
ATXICP_RATE1[2:0]
Name
Reset
Value
0x0
Description
Reserved
Defines the TX PLL charge pump current when the PMA is
running in PCIe Gen2 speed. This register is R/W in order to
enable changing the default value by register programming,
which is expected to be performed before reset deassertion.
Note: This register can be programmed when the PHY is under reset and is implemented only if PCIe Gen2 is
supported by the PHY.
0x0
Table 6-114 • GEN2_RX_PLL_CCP
Bit
Number
7
Reserved
[6:4]
ARXCDRICP_RATE1[2:0]
0x0
Defines the RX PLL charge pump current when the PMA is
frequency locked and running in PCIe Gen2 speed. This register
is R/W in order to enable changing the default value by register
programming, which is expected to be performed before reset
deassertion.
3
Reserved
0x0
Reserved
[2:0]
ARXICP_RATE1[2:0]
0x0
Defines the RX PLL charge pump current when the PMA is CDR
locked and running in PCIe Gen2 speed. This register is R/W in
order to enable changing the default value by register
programming, which is expected to be performed before reset
deassertion
Name
Reset
Value
0x0
Description
Reserved
Note: This register can be programmed when the PHY is under reset and is implemented only if PCIe Gen2 is
supported by the PHY.
220
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Table 6-115 • CDR_PLL_MANUAL_CR
Bit
Number
[7:3]
Reserved
2
FINE_GRAIN
0x0
In PCS-driven mode when this register is set, it enables forcing
the CDR PLL state machine in fine grain state. In this state, the
CDR PLL locks on receive data, making RX data and RX
CLOCKP valid on the PMA interface.
1
COARSE_GRAIN
0x0
0
FREQ_LOCK
0x0
When set, this register enables forcing the CDR PLL state
machine when used in PCS driven mode (see Reg00 bit 3 set to
0) in coarse grain state. In this state, the CDR PLL performs a
coarse grain lock on receive data, enabling adjustment of its
clock up to 5000 PPM.
When set, this register enables forcing the CDR PLL state
machine when used in PCS-driven mode (see Reg00 bit 3 set to
0) in frequency lock state. In this state, the CDR PLL does not
lock on receive data but on the reference clock.
Name
Reset
Value
0x0
Description
Reserved
Table 6-116 • UPDATE_SETTINGS
Bit
Number
[7:0]
Name
UPDATE_SETTINGS[7:0]
Reset
Value
0x00
Description
Is a transient register (read always reports 0) where writing a 1
in bit 0 will trigger a new computation of PMA settings based on
the value written in register space registers. Note that for PCIe,
Microsemi recommends not using this command register when
the link is not transitioning to low power state or changing rate.
Note: This register can be programmed any time, except during calibration, and triggers the RX/TX shift load logic to
load new programmed settings into the SERDES. Thus, it must be written to 0x01 only after a coherent set of
register programming has been programmed.
Table 6-117 • PRBS_ERR_CYC_FIRST_7_0
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[7:0]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[7:0].
This read-only register reports on which clock cycle the error
counter has first been incremented after the PRBS error
counter is enabled. It is a 50-bit counter, enabling performance
of bit error rate testing (BERT).
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Revision 5
221
SERDESIF Register Access Map
Table 6-118 • PRBS_ERR_CYC_FIRST_15_8
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[15:8]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[15:8].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of bit error rate testing (BERT).
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-119 • PRBS_ERR_CYC_FIRST_23_16
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[23:16]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[23:16].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-120 • PRBS_ERR_CYC_FIRST_31_24
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[31:24]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[31:24].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-121 • PRBS_ERR_CYC_FIRST_39_32
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[39:32]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[39:32].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number errors detected might give information
about bursts of errors or distributed errors, but statistics might also be required. The test can be rerun several
times with different test periods.
222
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Table 6-122 • PRBS_ERR_CYC_FIRST_47_40
Bit
Number
[7:2]
Reserved
[1:0]
PRBS_ERR_CYC_FIRST[47:40]
Name
Reset
Value
0x0
0x0
Description
Reserved
PRBS last error cycle counter register bits [47:40].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of bit error rate testing (BERT).
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-123 • PRBS_ERR_CYC_FIRST_49_48
Bit
Number
[7:2]
Reserved
[1:0]
PRBS_ERR_CYC_FIRST[49:48]
Name
Reset
Value
0x0
0x0
Description
Reserved
PRBS last error cycle counter register bits[49:48].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-124 • PRBS_ERR_CYC_FIRST_7_0
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[7:0]
Reset
Value
0x0
Description
PRBS last error cycle counter register bits [7:0].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Revision 5
223
SERDESIF Register Access Map
Table 6-125 • PRBS_ERR_CYC_FIRST_15_8
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[15:8]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[15:8].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of bit error rate testing (BERT).
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-126 • PRBS_ERR_CYC_FIRST_23_16
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[23:16]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits [23:16].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-127 • PPRBS_ERR_CYC_FIRST_31_24
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[31:24]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[31:24].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-128 • PRBS_ERR_CYC_FIRST_39_32
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[39:32]
Reset
Value
0x0
Description
PRBS last error cycle counter register bits[39:32].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of bit error rate testing (BERT).
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
224
R e vi s i o n 5
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Table 6-129 • PRBS_ERR_CYC_FIRST_47_40
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[47:40]
Reset
Value
0x0
Description
PRBS last error cycle counter register bits[47:40].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of bit error rate testing (BERT).
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-130 • PRBS_ERR_CYC_FIRST_49_48
Bit
Number
[7:2]
Reserved
0x0
Reserved
[1:0]
PRBS_ERR_CYC_LAST[49:48]
0x0
PRBS last error cycle counter register bits[49:48].
Name
Reset
Value
Description
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
List of Changes
The following table shows important changes made in this document for each revision.
Date
Changes
Revision 5
(December 2015)
Updated Table 6-96 (SAR 71077).
Revision 4
(August 2015)
Updated Table 6-28 (SAR 65917) and Table 6-110.
Page
214
191, 219
Updated "SERDESIF System Register" section
178
Removed Table 6-45: SERDESIF System Registers in EPCS Mode and Table 6-46:
Protocol Setting System Register for XAUI Mode
NA
Revision 3
(January 2015)
Consolidated SmartFusion2 and IGLOO2 User Guides.
NA
Revision 2
(July 2014)
No updates
NA
Revision 1
(March 2014)
The chapter was added.
NA
Revision 5
225
List of Changes
The following table shows important changes made in this document for each revision.
Date
Revision 5
(December 2015)
Revision 4
(August 2015)
Changes
Updated Table 2-15 (SAR 73409).
Updated Table 2-4 and Table 2-5 (SAR 73758).
Page
63
45 and 46
Updated Table 6-32 in "SERDESIF Register Access Map" Chapter (SAR
71619).
193
Updated Table 6-96 in "SERDESIF Register Access Map" Chapter (SAR
71077).
214
Updated the User Guide (SARs 64677, 65871, 67613, 67187, 63671, 65917,
69885, and 69996).
NA
Updated "SERDESIF Block" Chapter.
" List of
Changes" on
page 27
Updated "PCI Express" Chapter.
"List of
Changes" on
page 102
Updated "XAUI" Chapter.
"List of
Changes" on
page 132
Updated "EPCS Interface" Chapter.
"List of
Changes" on
page 153
Updated "Serializer/De-serializer" Chapter.
"List of
Changes" on
page 176
Updated "SERDESIF Register Access Map" Chapter.
"List of
Changes" on
page 225
Revision 3
(January 2015)
SmartFusion2 and IGLOO2 User Guides are consolidated in this revision
(SARs 56737, 59646, 58292, 62283, 57915, 58472, 59157, 60283, 59773,
60437, 54009, 61529, 60510, and 59645).
NA
Revision 2
(July 2014)
Updated the User Guide (SARs 57190, 57466, 56868, 57466, 56134, and
57322).
NA
Revision 1
(March 2014)
Updated the User Guide (SARs 49906, 55434, 54010, 50698, and 50672)
NA
Revision 5
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UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
The following table shows important changes made in this document for each revision.
Date
Revision 4
(June 2014)
Revision 3
(April 2013)
Revision 2
(November 2012)
Revision 1
(November 2012)
Changes
Page
Updated the User Guide (SARs 49906, 55434, 54010, 50698, 50672).
NA
Updated "SERDESIF Block" Chapter (SARs 57190, 56868).
10
Updated "PCI Express" Chapter (SARs 58293, 56134, 57424, 56868).
28
Updated "EPCS Interface" Chapter (SAR 57322).
133
Updated "SERDESIF Register Access Map" Chapter (SAR 58405).
177
Restructured the user guide (SAR 47394).
NA
Updated "SERDESIF Block" Chapter (SAR 44571).
10
Updated "Serializer/De-serializer" Chapter (SAR 44572).
154
Updated "Serializer/De-serializer" Chapter (SAR 42156).,
154
Updated "Serializer/De-serializer" Chapter (SAR 42155).
154
Updated the user guide (SAR 42443).
NA
Updated "SERDESIF Block" Chapter (SAR 42912).
10
Updated "Serializer/De-serializer" Chapter (SAR 42156).
154
Updated "Serializer/De-serializer" Chapter (SAR 42155).
154
Updated the user guide (SAR 42443).
NA
Updated "SERDESIF Block" Chapter (SAR 42912).
10
Revision 5
227
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
For Microsemi SoC Products Support, visit 
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected].
Revision 5
228
UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select
Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR
web page.
Revision 5
229
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
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custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and
has approximately 3,600 employees globally. Learn more at www.microsemi.com.
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Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
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Fax: +1 (949) 215-4996
E-mail: [email protected]
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rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
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hereunder and any other products sold by Microsemi have been subject to limited testing and should not
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other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
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50200447-5/12.15