256 K × 4-Bit Dynamic RAM Low Power 256 K × 4-Bit Dynamic RAM HYB 514256B/BJ-50/-60/-70 HYB 514256BL/BJL-50/-60/-70 Advanced Information 262 144 words by 4-bit organization • Fast access and cycle time 50 ns access time 95 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) • Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) • Low power dissipation max. 495 mW active (-50 version) max. 440 mW active (-60 version) max. 385 mW active (-70 version) max. 5.5 mW standby max. 1.1 mW standby for L-version • • • • • • • Single + 5 V (± 10 %) supply with a built-in VBB generator Output unlatched at cycle end allows twodimensional chip selection Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability All inputs, outputs and clocks TTL-compatible 512 refresh cycles/8 ms 512 refresh cycles/64 ms for L-version only Plastic Packages: P-DIP-20-2, P-SOJ-26/20-1 Ordering Information Type Ordering Code Package Description HYB 514256B-50 Q67100-Q1044 P-DIP-20-2 DRAM (access time 50ns) HYB 514256B-60 Q67100-Q530 P-DIP-20-2 DRAM (access time 60 ns) HYB 514256B-70 Q67100-Q433 P-DIP-20-2 DRAM (access time 70 ns) HYB 514256BJ-50 Q67100-Q1054 P-SOJ-26/20-1 DRAM (access time 50 ns) HYB 514256BJ-60 Q67100-Q536 P-SOJ-26/20-1 DRAM (access time 60 ns) HYB 514256BJ-70 Q67100-Q537 P-SOJ-26/20-1 DRAM (access time 70 ns) HYB 514256BL-50 on request P-DIP-20-2 DRAM (access time 50 ns) HYB 514256BL-60 Q67100-Q542 P-DIP-20-2 DRAM (access time 60 ns) HYB 514256BL-70 Q67100-Q543 P-DIP-20-2 DRAM (access time 70 ns) HYB 514256BJL-50 on request P-SOJ-26/20-1 DRAM (access time 50 ns) HYB 514256BJL-60 Q67100-Q608 P-SOJ-26/20-1 DRAM (access time 60 ns) HYB 514256BJL-70 Q67100-Q607 P-SOJ-26/20-1 DRAM (access time 70 ns) Semiconductor Group 55 01.95 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM The HYB 514256B/BJ/BL/BJL is the new generation dynamic RAM organized as 262 144 words by 4-bit. The HYB 514256B/BJ/BL/BJL utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514256B/BJ/BL/BJL to be packaged in a standard plastic P-DIP-20-2,or plastic P-SOJ-26/20-1. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. These HYB 514256BL/BJL are specially selected for battery backup applications. Pin Definitions and Functions Pin No. Function A0-A8 Address Inputs RAS Row Address Strobe OE Output Enable I/O1-I/O4 Data Input/Output CAS Column Address Strobe WE Read/Write Input VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 56 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM Pin Configuration (top view) P-SOJ-26/20-1 Semiconductor Group P-DIP-20-2 57 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM Block Diagram Semiconductor Group 58 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 ˚C Storage temperature range......................................................................................– 55 to + 150 ˚C Soldering temperature ............................................................................................................260 ˚C Soldering time .............................................................................................................................10 s Input/output voltage ........................................................................................................ – 1 to + 7 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation..................................................................................................................... 0.6 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 % Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 6.5 V 1) Input low voltage VIL – 1.0 0.8 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current, any input (0 V ≤ VIN ≤ 6.5 V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ VCC) IO(L) – 10 10 µA 1) Average VCC supply current: -50 version -60 version -70 version (RAS, CAS, address cycling: tRC = tRC min.) ICC1 – – – 90 80 70 mA mA mA 2) 3) Standby VCC supply current (RAS = CAS = VIH) ICC2 – 2 mA – Average VCC supply current, RAS only mode: -50 version -60 version -70 version (RAS cycling: CAS = VIH : tRC = tRC min.) – – – 90 80 70 mA mA mA 2) Semiconductor Group 2) 3) 2) 3) ICC3 59 2) 2) HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM DC Characteristics (cont’d) TA = 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 % Parameter Symbol Average VCC supply current, fast page mode: -60 version -70 version -50 version (RAS = VIL , CAS, address cycling: tPC = tPC min.) ICC4 Standby VCC supply current L-Version (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current, CAS-before-RAS refresh mode: -50 version -60 version -70 version (RAS, CAS cycling: tRC = tRC min.) ICC6 For L-version only: Battery backup current: average power supply current, battery backup mode: (CAS = CAS before RAS cycling or 0.2 V, OE = VCC – 0.2 V WE = VCC – 0.2 V or 0.2 V, A0 to A8 = VCC – 0.2 V or 0.2 V, I/O1 to I/O4 = VCC – 0.2 V or 0.2 V or open, tRC = 125 µs, tRAS = tRAS min. ~ 1 µs) Semiconductor Group ICC7 60 Limit Values min. max. Unit Test Condition – – – 70 60 50 mA mA mA 2) 3 – – 1 200 mA µA 1) – – – 90 80 70 mA mA mA 2) 300 µA 2) – 2) 3) 2) 3) 1) 2) 2) HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM AC Characteristics 4) 13) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. Random read or write cycle time tRC 95 – 110 – 130 – ns Read-modify-write cycle time tRWC 140 – 160 – 185 – ns Fast page mode cycle time tPC 35 – 40 – 45 – ns 80 – 90 – 100 – ns Fast page mode read-modify- tPRWC write cycle time Access time from RAS 6) 11) tRAC – 50 – 60 – 70 ns Access time from CAS 6) 11) tCAC – 15 – 15 – 20 ns tAA – 25 – 30 – 35 ns tCPA – 30 – 35 – 40 ns tCLZ 0 – 0 – 0 – ns tOFF 0 15 0 20 0 20 ns tT 3 50 3 50 3 50 ns RAS precharge time tRP 35 – 40 – 50 – ns RAS pulse width tRAS 50 10.000 60 10.000 70 10.000 ns RAS pulse width (fast page mode) tRASP 50 100.000 60 100.000 70 100.000 ns RAS hold time tRSH 15 – 15 – 20 – ns CAS hold time tCSH 50 – 60 – 70 – ns CAS pulse width tCAS 15 10.000 15 10.000 20 10.000 ns RAS hold time from CAS precharge (Fast Page Mode) tRHCP 30 – 35 – 45 – ns CAS precharge to WE delay time (FPM RMW) tCPWD 55 – 60 – 65 – ns tRCD 20 35 20 45 20 50 RAS to column address delay tRAD 12) time 15 25 15 30 15 35 ns Access time from column address Access time from CAS precharge 6) 12) 6) 12) 4) CAS to output in low-Z Output buffer turn-off delay 7) Transition time (rise and fall) RAS to CAS delay time 5) 11) CAS to RAS precharge time tCRP 5 – 5 – 5 – ns CAS precharge time tCP 10 – 10 – 10 – ns Semiconductor Group 61 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM AC Characteristics (cont’d) 4) 13) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 10 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 10 – 15 – 15 – ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns tRCH 0 – 0 – 0 – ns tRRH 0 – 0 – 0 – ns Write command hold time tWCH 10 – 10 – 15 – ns Write command pulse width tWP 10 – 10 – 15 – ns Write command to RAS lead time tRWL 15 – 15 – 20 – ns Write command to CAS lead time tCWL 15 – 15 – 20 – ns 8) Read command hold time Read command hold time referenced to RAS 8) Data setup time 9) tDS 0 – 0 – 0 – ns Data hold time 9) tDH 10 – 15 – 15 – ns Refresh period tREF – 8 – 8 – 8 ms Refresh period L-version tREF – 64 – 64 – – ms Write command setup time 10) tWCS 0 – 0 – 0 – ns CAS to WE delay time 10) tCWD 40 – 45 – 50 – ns RAS to WE delay time 10) tRWD 75 – 90 – 100 – ns Column address to WE delay tAWD 10) time 50 – 60 – 65 – ns CAS setup time (CAS-before- tCSR RAS cycle) 5 – 5 – 5 – ns CAS hold time (CAS-beforeRAS cycle) tCHR 10 – 15 – 15 – ns RAS to CAS precharge time tRPC 0 – 0 – 0 – ns Semiconductor Group 62 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM AC Characteristics (cont’d) 4) 13) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. CAS precharge time (CASbefore-RAS counter test cycle) tCPT 25 – 30 – 40 – ns OE access time tOEA – 15 – 15 – 20 ns RAS hold time referenced to OE tROH 10 – 10 – 10 – ns Output buffer turn-off delay time from OE tOEZ 0 15 0 20 0 20 ns Data to CAS low delay 14) tDZC 0 – 0 – 0 – ns 15) tDZO 0 – 0 – 0 – tCDD 15 – 20 – 20 – ns tODD 15 – 20 – 20 – ns CAS high to data delay OE high to data delay 15) OE to data delay 15) Capacitance TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A8) CI1 – 5 pF Input capacitance (RAS, CAS, WE, OE) CI2 – 7 pF Output capacitance (I/O1 ... I/O4) C5O – 7 pF Semiconductor Group 63 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM Notes : 1) All voltages are referenced to VSS . 2) ICC1 , ICC3 , ICC4 , ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 6) Measured with a load equivalent to 2 TTL loads and 100 pF. 7) tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open-circuit conditions and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-modify-write cycles. 10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle; if tRWD ≥ tRWD (min.), tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and I/O will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) AC measurements assume tT = 5ns. 14) Either tDZC or tDZO must be satisfied. 15) Either tCDD or tODD must be satisfied. Semiconductor Group 64 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM Waveforms tRC tRAS RAS V IH VIL tCSH V IH VIL tRAD tASR A0 - A8 V IH VIL tRAL tCAH tASC tASR Column Address Row Address Row Address tRCH tRAH tRCS WE OE tRRH V IH VIL tAA tOEA V IH VIL tCDD tDZC tODD tDZO V I/O1-I/O4 IH (Inputs) V IL tCAC tCLZ V I/O1-I/O4 OH (Outputs) V OL Hi Z tOFF tOEZ Valid Data Out tRAC “H” or “L” Read Cycle Semiconductor Group tCRP tRSH tCAS tRCD CAS tRP 65 Hi Z HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRC tRAS RAS V IH VIL tCSH tRCD tRSH tCAS V IH CAS VIL tRAD tASR A0 - A8 V IH VIL OE tASR Column Address Row Address tWCS V IH Row Address tCWL t WP VIL tWCH tRWL V IH VIL tDS V I/O1-I/O4 IH (Inputs) V IL tDH Valid Data In V I/O1-I/O4 OH (Outputs) V Hi Z OL “H” or “L” Write Cycle (Early Write) Semiconductor Group 66 tCRP tRAL tCAH tASC tRAH WE tRP . HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRC tRAS RAS V IH VIL tCSH tRCD VIL tRAD tASR A0 - A8 V IH VIL tCAH tASC tRAL tASR tCWL tRWL tWP V IH VIL tOEH OE V IH VIL tODD tDZO tDZC V I/O1-I/O4 IH (Inputs) V IL tDS tDH tOEZ Valid Data tCLZ tOEA V I/O1-I/O4 OH (Outputs) V OL Hi-Z Hi-Z “H” or “L” Write Cycle (OE Controlled Write) Semiconductor Group 67 . Row Address Column Address Row Address tRAH WE tCRP tRSH tCAS V IH CAS tRP HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRWC tRP tRAS RAS V IH VIL tCSH tRSH tCAS tRCD CAS V IH tCRP VIL tCAH tRAH A0 - A8 V IH VIL tASR tASC tASR Column Address Row Address Row Address tCWL tRWL tAWD tRAD tCWD tRWD tWP V IH WE VIL tAA tOEA tRCS tOEH V IH OE VIL tDZO tDS tDZC tDH V IH Valid Data in I/O1-I/O4 (Inputs) VIL tCLZ tCAC tOEZ V I/O1-I/O4 OH (Outputs) VOL Data Out “H” or “L” tRAC Read-Write (Read-Modify-Write) Cycle Semiconductor Group tODD 68 Semiconductor Group Fast Page Mode Read-Modify-Write Cycle 69 IH IH IH IH IH V IH V IL V V IL V V IL V V IL V V IL OL I/O1-I/O4 OH (Outputs) V V I/O1-I/O4 (Inputs) V IL OE WE A0-A8 CAS RAS V tASR tRAC tCAS tAA tOEA tCAC Data In tDS tOEH tCAC tCLZ tOEZ tWP tDS tDH Data In tODD Data Out tOEA tAWD tCPA tAA tDZC tCAS tPRWC tCPWD tCWD tCAH Column Address tASC tCP tCWL tWP tOEZ tDH tODD Data Out tAWD tRWD tCWD Column Address tASC tCAH tDZC tCLZ tDZO tRCS “H” or “L” Row Address tRAH tRAD tRCD tCSH tRASP tOEH tDZC tCWL tAWD tAA tCLZ tCPA tRAL Data Out tDS tOEZ tDH tOEH tRWL tCWL tWP Data In tODD tCPWD tCWD tOEA Column Address tASC tCAH tCAS tRSH tCRP Row Address tASR tRP HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRASP tRP V IH RAS VIL tCP tCAS V IH CAS VIL tASR A0-A8 VIL tCAS tCAS tCRP tCSH tRAH V IH tRHCP tRSH tPC tRCD tCAH tASC Row Addr tASC Column Address tCAH tCAH tASR tASC Column Address Column Address tRAD Row Address tRCH tRCH tRCS tRCS tRCS tCPA tAA tCPA tAA tOEA V IH WE VIL tAA tOEA V IH OE VIL tOEA V tCAC tRAC tCLZ tOFF tOEZ tCAC tOFF tCLZ tOEZ V I/O1-I/O4 OH (Outputs) V Valid Data Out OL “H” or “L” Fast Page Mode Read Cycle Semiconductor Group 70 tODD tODD tODD tCDD tDZO tDZO tDZO I/O1-I/O4 IH (Inputs) V IL tDZC tDZC tDZC tRRH Valid Data Out tCAC tCLZ tOFF tOEZ Valid Data Out HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRASP tRP V IH RAS VIL tPC tCAS tRCD VIL tRAL tRAH tCAH tASC tASR A0-A8 V IH VIL Row Addr Column Address OE tASC tCAH Column Address tWCS tWCH tWP V IH tASC tCAH Column Address tCWL tRWL tWCS tCWL tWCS tCWL tRAD WE tCRP tCP V IH CAS tRSH tCAS tCAS tWCH tWP tWCH tWP tDH tDH VIL V IH VIL tDH tDS V I/O1-I/O4 IH (Inputs) V IL Valid Data In tDS tDS Valid Data In Valid Data In V I/O1-I/O4 OH (Outputs) V HI-Z OL “H” or “L” Fast Page Mode Early Write Cycle Semiconductor Group 71 tASR Row Address HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRC tRAS RAS tRP V IH VIL tCRP tRPC V IH CAS VIL tRAH tASR tASR A0-A8 V IH Row Address VIL Row Address V I/O1-I/O4 OH (Outputs) V HI-Z OL “H” or “L” RAS-Only Refresh Cycle Semiconductor Group 72 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRC tRP RAS tRP tRAS V IH VIL tCRP tRPC tCSR CAS V IH VIL tRPC tCHR tCP tWRP tWRH WE V IH VIL tOEZ OE V IH VIL tCDD V I/O1-I/O4 IH (Inputs) V IL tODD V I/O1-I/O4 OH (Outputs)VOL HI-Z tOFF “H” or “L” CAS-Before-RAS Refresh Cycle Semiconductor Group 73 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRC tRC RAS tRP tRAS V IH tRP tRAS VIL tRCD tRSH tCRP tCHR CAS V IH tRAD VIL tASC tRAH tASR A0-A8 V IH VIL tWRP Column Address Row Addr Row Address tRRH tRCS WE OE tASR tWRH tCAH V IH VIL tAA tOEA V IH VIL tDZC tCDD tDZO tODD V I/O1-I/O4 IH (Inputs) V IL tOFF tCAC tCLZ tOEZ tRAC V I/O1-I/O4 OH (Outputs) V Valid Data Out OL “H” or “L” Hidden Refresh Cycle (Read) Semiconductor Group 74 HI-Z HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM tRC tRC tRP RAS tRAS V IH WE OE tRSH tCHR tCRP V IH VIL tRAD tRAH tASC tCAH tASR A0-A8 tRP VIL tRCD CAS tRAS V IH VIL Row Addr tASR Row Address Column Address tWCS tWCH tWP V IH VIL V IH VIL tDS tDH V IH I/O1-I/O4 (Inputs) V IL Valid Data V I/O1-I/O4 OH (Outputs) V HI-Z OL “H” or “L” Hidden Refresh Cycle (Early Write) Semiconductor Group 75 HYB 514256B/BL/BJ/BJL-50/-60/-70 256 K × 4-DRAM V RAS V IL tCHR tCSR V CAS V IL V tWRP V tASR Row Address Column Address IL tRCS tWRH V tRAL tCAH tASC IH Read Cycle WE tRSH tCAS tCPT IH V A0-A8 tRP tRAS IH tAA tCAC tRRH tRCH IH IL tOEA OE V V I/O1-I/O4 (Inputs) IH IL V V tDZC tDZO IH IL tOFF tCLZ I/O1-I/O4 (Outputs) V OH V OL Write Cycle V Valid Data Out tWCS tWRP tRWL tCWL V IH tWCH IL V OE IH IL tDH tDS I/O1-I/O4 (Inputs) I/O1-I/O4 (Outputs) V V IH V IH V IL V V I/O1-I/O4 (Inputs) I/O1-I/O4 (Outputs) HI-Z tRCS tWRH tAA tWP tOEA tOEH IH IL V tCWL tRWL tAWD tCWD tCAC IL V V tWRP IH V OE Valid Data In IL Read-Modify-Write Cycle WE tOEZ tWRH V WE tCDD tODD tDS tDZC tDZO tDH IH Data In IL tCLZ V OH V OL D.Out HI-Z “H” or “L” Semiconductor Group tODD tOEZ tCAC 76 HI-Z