8-Channel, 24-Bit, Simultaneous Sampling ADC AD7779 Data Sheet FEATURES 8-channel, 24-bit simultaneous sampling analog-to-digital converter (ADC) Single-ended or true differential inputs Programmable gain amplifier (PGA) per channel (gains of 1, 2, 4, and 8) Low dc input current: ±4 nA Up to 16 kSPS output data rate (ODR) per channel Programmable ODRs and bandwidth Sample rate converter (SRC) for coherent sampling Sampling rate resolution up to 15.2 μSPS Low latency sinc3 filter path Adjustable phase synchronization Internal 2.5 V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution successive approximation (SAR) ADC for system and chip diagnostics Power supply Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital input/output (I/O) supply: 1.8 V to 3.6 V Performance temperature range: –40°C to +105°C Functional temperature range: –40°C to +125°C Performance Combined ac and dc performance 108 dB signal-to-noise ratio (SNR)/dynamic range at 16 kSPS in high resolution mode −109 dB total harmonic distortion (THD) ±7 ppm integral nonlinearity (INL) ±40 μV offset error ±0.1% gain error ±10 ppm/°C typical temperature coefficient APPLICATIONS Circuit breakers General-purpose data acquisition Electroencephalography (EEG) Industrial process control Each channel contains an ADC modulator and a sinc3, low latency digital filter. An SRC is provided to allow fine resolution control over the AD7779 ODR. This control can be used in applications where the ODR resolution is required to maintain coherency with 0.01 Hz changes in the line frequency. The SRC is programmable through the serial port interface (SPI). The AD7779 implements two different interfaces: a data output interface and SPI control interface. The ADC data output interface is dedicated to transmitting the ADC conversion results from the AD7779 to the processor. The SPI interface is used to write to and read from the AD7779 configuration registers and for the control and reading of data from the SAR ADC. The SPI interface can also be configured to output the Σ-Δ conversion data. The AD7779 includes a 12-bit SAR ADC. This ADC can be used for AD7779 diagnostics without having to decommission one of the Σ-Δ ADC channels dedicated to system measurement functions. With the use of an external multiplexer, which can be controlled through the three general-purpose inputs/outputs pins (GPIOs), and signal conditioning, the SAR ADC can be used to validate the Σ-Δ ADC measurements in applications where functional safety is required. In addition, the AD7779 SAR ADC includes as an internal multiplexer to sense internal nodes. The AD7779 contains a 2.5 V reference and reference buffer. The reference has a typical temperature coefficient of 10 ppm/°C. The AD7779 offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a higher dynamic range while consuming 10.75 mW per channel; low power mode consumes just 3.37 mW per channel at a reduced dynamic range specification. The specified operating temperature range is −40°C to +105°C, although the device is operational up to +125°C. GENERAL DESCRIPTION The AD7779 is an 8-channel, simultaneous sampling ADC. There are eight full sigma-delta (Σ-Δ) ADCs on chip. The AD7779 provides an ultralow input current to allow direct sensor connection. Each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor outputs into the full-scale ADC input range, maximizing the Rev. 0 dynamic range of the signal chain. The AD7779 accepts VREF from 1 V up to 3.6 V. The analog inputs accept unipolar (0 V to VREF) or true bipolar (±VREF/2 V) analog input signals with 3.3 V or ±1.65 V analog supply voltages, respectively. The analog inputs can be configured to accept true differential or single-ended signals to match different sensor output configurations. Note that throughout this data sheet, certain terms are used to refer to either the multifunction pins or a range of pins. The multifunction pins, such as DCLK0/SDO, are referred to either by the entire pin name or by a single function of the pin, for example, DCLK0, when only that function is relevant. In the case of ranges of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7779 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 -Δ Output Data............................................................................. 49 Applications ....................................................................................... 1 ADC Conversion Output—Header and Data ........................ 49 General Description ......................................................................... 1 Sample Rate Converter (SRC) (SPI COntrol MOde) ............ 50 Revision History ............................................................................... 3 Data Output Interface ................................................................ 51 Functional Block Diagram .............................................................. 4 Calculating the CRC Checksum .............................................. 56 Specifications..................................................................................... 5 Register Summary .......................................................................... 57 DOUTx Timing Characterististics ............................................. 9 Register Details ............................................................................... 61 SPI Timing Characterististics ................................................... 10 Channel 0 Configuration Register ........................................... 61 Synchronization Pins and Reset Timing Characteristics ...... 11 Channel 1 Configuration Register ........................................... 61 SAR ADC Timing Characterististics ....................................... 12 Channel 2 Configuration Register ........................................... 62 GPIO SRC Update Timing Characterististics......................... 12 Channel 3 Configuration Register ........................................... 62 Absolute Maximum Ratings.......................................................... 13 Channel 4 Configuration Register ........................................... 63 Thermal Resistance .................................................................... 13 Channel 5 Configuration Register ........................................... 63 ESD Caution ................................................................................ 13 Channel 6 Configuration Register ........................................... 64 Pin Configuration and Function Descriptions ........................... 14 Channel 7 Configuration Register ........................................... 64 Typical Performance Characteristics ........................................... 17 Disable Clocks to ADC Channel Register .............................. 65 Terminology .................................................................................... 30 Channel 0 Sync Offset Register ................................................ 65 RMS Noise and Resolution............................................................ 31 Channel 1 Sync Offset Register ................................................ 65 High Resolution Mode............................................................... 31 Channel 2 Sync Offset Register ................................................ 66 Low Power Mode ........................................................................ 31 Channel 3 Sync Offset Register ................................................ 66 Theory of Operation ...................................................................... 32 Channel 4 Sync Offset Register ................................................ 66 Analog Inputs .............................................................................. 32 Channel 5 Sync Offset Register ................................................ 66 Transfer Function ....................................................................... 33 Channel 6 Sync Offset Register ................................................ 67 Core Signal Chain....................................................................... 34 Channel 7 Sync Offset Register ................................................ 67 Capacitive PGA........................................................................... 34 General User Configuration 1 Register ................................... 67 Internal Reference and Reference Buffers ............................... 34 General User Configuration 2 Register ................................... 68 Integrated LDOs ......................................................................... 35 General User Configuration 3 Register ................................... 69 Clocking and Sampling.............................................................. 35 Data Output Format Register ................................................... 69 Digital Reset and Synchronization Pins .................................. 35 Main ADC Meter and Reference Mux Control Register ...... 70 Digital Filtering ........................................................................... 36 Global Diagnostics Mux Register............................................. 71 Shutdown Mode.......................................................................... 36 GPIO Configuration Register ................................................... 72 Controlling the AD7779 ............................................................ 37 GPIO Data Register.................................................................... 72 Pin Control Mode ....................................................................... 37 Buffer Configuration 1 Register ............................................... 72 SPI Control .................................................................................. 39 Buffer Configuration 2 Register ............................................... 73 Digital SPI Interface ................................................................... 42 Channel 0 Offset Upper Byte Register..................................... 73 Diagnostics and Monitoring ......................................................... 45 Channel 0 Offset Middle Byte Register ................................... 73 Self Diagnostics Error ................................................................ 45 Channel 0 Offset Lower Byte Register ..................................... 74 Monitoring Using the AD7779 SAR ADC (SPI Control Mode) ........................................................................................... 46 Channel 0 Gain Upper Byte Register ....................................... 74 Σ-Δ ADC Diagnostics (SPI Control Mode) ............................ 48 Channel 0 Gain Middle Byte Register ..................................... 74 Channel 0 Gain Lower Byte Register ....................................... 74 Rev. 0 | Page 2 of 97 Data Sheet AD7779 Channel 1 Offset Upper Byte Register .....................................75 Channel 6 Gain Lower Byte Register ....................................... 83 Channel 1 Offset Middle Byte Register ....................................75 Channel 7 Offset Upper Byte Register ..................................... 84 Channel 1 Offset Lower Byte Register .....................................75 Channel 7 Offset Middle Byte Register .................................... 84 Channel 1 Gain Upper Byte Register........................................75 Channel 7 Offset Lower Byte Register ..................................... 84 Channel 1 Gain Middle Byte Register ......................................76 Channel 7 Gain Upper Byte Register ....................................... 84 Channel 1 Gain Lower Byte Register........................................76 Channel 7 Gain Middle Byte Register ...................................... 85 Channel 2 Offset Upper Byte Register .....................................76 Channel 7 Gain Lower Byte Register ....................................... 85 Channel 2 Offset Middle Byte Register ....................................76 Channel 0 Status Register .......................................................... 85 Channel 2 Offset Lower Byte Register .....................................77 Channel 1 Status Register .......................................................... 86 Channel 2 Gain Upper Byte Register........................................77 Channel 2 Status Register .......................................................... 86 Channel 2 Gain Middle Byte Register ......................................77 Channel 3 Status Register .......................................................... 87 Channel 2 Gain Lower Byte Register........................................77 Channel 4 Status Register .......................................................... 87 Channel 3 Offset Upper Byte Register .....................................78 Channel 5 Status Register .......................................................... 88 Channel 3 Offset Middle Byte Register ....................................78 Channel 6 Status Register .......................................................... 88 Channel 3 Offset Lower Byte Register .....................................78 Channel 7 Status Register .......................................................... 89 Channel 3 Gain Upper Byte Register........................................78 Channel 0/Channel 1 DSP Errors Register.............................. 89 Channel 3 Gain Middle Byte Register ......................................79 Channel 2/Channel 3 DSP Errors Register.............................. 90 Channel 3 Gain Lower Byte Register........................................79 Channel 4/Channel 5 DSP Errors Register.............................. 90 Channel 4 Offset Upper Byte Register .....................................79 Channel 6/Channel 7 DSP Errors Register.............................. 91 Channel 4 Offset Middle Byte Register ....................................79 Channel 0 to Channel 7 Error Register Enable Register........ 91 Channel 4 Offset Lower Byte Register .....................................80 General Errors Register 1 ........................................................... 92 Channel 4 Gain Upper Byte Register........................................80 General Errors Register 1 Enable .............................................. 92 Channel 4 Gain Middle Byte Register ......................................80 General Errors Register 2 ........................................................... 93 Channel 4 Gain Lower Byte Register........................................80 General Errors Register 2 Enable .............................................. 93 Channel 5 Offset Upper Byte Register .....................................81 Error Status Register 1 ................................................................ 94 Channel 5 Offset Middle Byte Register ....................................81 Error Status Register 2 ................................................................ 94 Channel 5 Offset Lower Byte Register .....................................81 Error Status Register 3 ................................................................ 95 Channel 5 Gain Upper Byte Register........................................81 Decimation Rate (N) MSB Register ......................................... 95 Channel 5 Gain Middle Byte Register ......................................82 Decimation Rate (N) LSB Register ........................................... 95 Channel 5 Gain Lower Byte Register........................................82 Decimation Rate (IF) MSB Register ......................................... 96 Channel 6 Offset Upper Byte Register .....................................82 Decimation Rate (IF) LSB Register .......................................... 96 Channel 6 Offset Middle Byte Register ....................................82 SRC Load Source and Load Update Register .......................... 96 Channel 6 Offset Lower Byte Register .....................................83 Outline Dimensions ........................................................................ 97 Channel 6 Gain Upper Byte Register........................................83 Ordering Guide ........................................................................... 97 Channel 6 Gain Middle Byte Register ......................................83 REVISION HISTORY 2/16—Revision 0: Initial Version Rev. 0 | Page 3 of 97 AD7779 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD1x VCM REF_OUT REFx+ REFx– AVDD2 COMMONMODE VOLTAGE AREGxCAP ANALOG LDO IOVDD DREGCAP DIGITAL LDO 2.5V REF AIN0+ AIN0– XTAL1 CLOCK MANAGER XTAL2/MCLK SYNC_IN SYNC_OUT START 280mV p-p EXT_REF PGA Σ-∆ ADC SINC3/ SRC FILTER Σ-∆ ADC SINC3/ SRC FILTER GAIN OFFSET GAIN OFFSET GAIN OFFSET DCLK DRDY INT_REF AIN1+ AIN1– PGA REFERENCES DATA OUTPUT INTERFACE DOUT3 DOUT2 DOUT1 DOUT0 AIN2+ AIN2– PGA Σ-∆ ADC SINC3/ SRC FILTER PGA Σ-∆ ADC SINC3/ SRC FILTER GAIN OFFSET GAIN OFFSET GAIN OFFSET REFERENCES AIN3+ AIN3– REFERENCES AIN4+ AIN4– PGA Σ-∆ ADC SINC3/ SRC FILTER PGA Σ-∆ ADC SINC3/ SRC FILTER REFERENCES AIN5+ AIN5– REFERENCES AIN6+ AIN6– RESET FORMAT1 FORMAT0 HARDWARE MODE CONFIGURATION PGA Σ-∆ ADC SINC3/ SRC FILTER GAIN OFFSET PGA Σ-∆ ADC SINC3/ SRC FILTER GAIN OFFSET REFERENCES AUXAIN+ AUXAIN– MODE3/ALERT MODE2/GPIO2 MODE1/GPIO1 MODE0/GPIO0 ALERT/CS SPI INTERFACE REFERENCES AIN7+ AIN7– REGISTER MAP AND LOGIC CONTROL DCLK2/SCLK DCLK1/SDI DCLK0/SDO AD7779 SAR ADC AVSSx AVDD4 CONVST_SAR Figure 1. Rev. 0 | Page 4 of 97 13295-001 DIAGNOSTIC INPUTS Data Sheet AD7779 SPECIFICATIONS AVDD1x = +1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND (single-supply operation), AVDD2x − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V AVSSx (internal/external), master clock (MCLK) = 8192 kHz for high resolution mode and 4096 kHz for low power mode, ODR = 16 kHz for high resolution mode and 4 kHz for low power mode; all specifications at TMIN to TMAX, unless otherwise noted. Table 1. Parameter ANALOG INPUTS Differential Input Voltage Range Single-Ended Input Voltage Range AINx± Common-Mode Input Range Absolute AINx± Voltage Limits DC Input Current Single-Ended Differential Input Current Drift AC Input Capacitance PGA Gain Settings Bandwidth REFERENCE Internal Initial Accuracy Temperature Coefficient Reference Load Current, IL DC Power Supply Rejection Load Regulation, ∆VOUT/∆IL Voltage Noise Voltage Noise Density Turn On Settling Time External Input Voltage Buffer Headroom REFx− Input Voltage Average REFx± Input Current Test Conditions/Comments Min Typ VREF = (REFx+ − REFx−) AVSSx + 0.10 (AVDD1x + AVSSx)/2 AVSSx + 0.10 HP, MCLK = 8192 kHz Low power mode, MCLK = 4096 kHz HP, MCLK = 8192 kHz Low power mode, MCLK = 4096 kHz Max Unit ±VREF/PGAGAIN 0 to VREF/PGAGAIN AVDD1x − 0.10 V V V AVDD1x − 0.10 ±4 ±1.5 nA nA ±1.5 ±0.6 nA nA 50 8 pA/°C pF 1, 2, 4, or 8 Small signal, high resolution mode Small signal, low power mode Large signal, high resolution mode Large signal, low power mode REF_OUT, TA = 25°C 2.5 − 0.2% 2.5 ±10 −10 Line regulation MHz 512 5 kHz kHz 1.5 kHz 2.5 + 0.2% V ppm/°C mA dB μV/mA μV rms nV/√Hz ms +10 95 100 6.8 273.5 1.5 eN p-p, 0.1 Hz to 10 Hz eN, 1 kHz, 2.5 V reference 100 nF VREF = (REFx+ − REFx−) 2 1 AVSSx + 0.1 2.5 AVSSx Current per channel Reference buffer disabled, high resolution mode Reference buffer precharge mode (pre-Q), high resolution mode Reference buffer disabled, low power mode Reference buffer pre-Q, low power mode Rev. 0 | Page 5 of 97 AVDD1x AVDD1x − 0.1 AVDD1x – REFx+ V V 18 μA/V 600 nA/V 4.5 μA/V 100 nA/V AD7779 Parameter TEMPERATURE RANGE Specified Performance Functional2 TEMPERATURE SENSOR Accuracy DIGITAL FILTER RESPONSE (SINC3) Group Delay Data Sheet Test Conditions/Comments Reference buffer enabled, high resolution mode Reference buffer enabled, low power mode Min TMIN to TMAX TMIN to TMAX −40 −40 CLOCK SOURCE Frequency Duty Cycle Σ-Δ ADC Speed and Performance Resolution Output Data Rate (ODR) No Missing Codes AC Accuracy Dynamic Range 16 kSPS 4 kSPS 1 kSPS THD SINAD SFDR Intermodulation Distortion (IMD) DC Power Supply Rejection DC Common-Mode Rejection Ratio Crosstalk Unit nA/V nA/V +105 +125 ±2 °C °C °C See the SRC Group Delay section See the Settling Time section See the SRC Bandwidth section See the SRC Bandwidth section −0.1 dB −3 dB Decimation Rate Max 5 Settling Time Pass Band Typ 10 High resolution mode Low power mode 128 64 4095.99 4095.99 High resolution mode Low power mode 0.655 1.3 45:55 8.192 4.096 55:45 MHz MHz % 16 8 Bits kSPS kSPS Bits 50:50 24 High resolution mode Low power mode 24 Shorted inputs, PGAGAIN = 1 High resolution mode High resolution mode Low power mode Low power mode −0.5 dBFS, high resolution mode −0.5 dBFS, low power mode fIN = 60 Hz High resolution mode, 16 kSPS, PGAGAIN = 1 fA = 50 Hz, fB = 51 Hz, high resolution mode fA = 50 Hz, fB = 51 Hz, low power mode AVDD1x = 3.3 V 108 116 106 116 −109 −105 106 132 dB dB dB dB dB dB dB dB −125 dB −105 dB −90 dB dB −120 dB 80 Rev. 0 | Page 6 of 97 Data Sheet Parameter DC ACCURACY INL AD7779 Test Conditions/Comments Min Endpoint method, PGAGAIN = 1 Other PGA gains Offset Error Offset Error Drift vs. time Offset Matching Gain Error Gain Drift vs. Temperature Gain Matching SAR ADC Speed and Performance Resolution Analog Input Range Analog Input Common-Mode Range Analog Input Leakage Current Throughput DC Accuracy INL DNL Offset Gain AC Performance SNR THD VCM PIN Output Load Current, IL Load Regulation, ∆VOUT/∆IL Short-Circuit Current LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Input Currents LOGIC OUTPUTS3 Output High Voltage, VOH Output Low Voltage, VOL Leakage Current Output Capacitance Σ-Δ ADC Data Output Coding Typ Max Unit ±7 ±3 ±40 ±0.5 −2 ±15 ±15 ±125 ppm of FSR ppm of FSR μV μV/°C μV/ 1000 hrs μV % FS ppm/°C % 25 ±0.1 ±45 ±0.1 PGAGAIN = 1 12 AVSS4 + 0.1 AVSS4 + 0.1 (AVDD4 + AVSS4)/2 ±5 AVDD4 − 0.1 AVDD4 − 0.1 Bits V V 256 nA kSPS Differential mode 1.5 No missing codes (12-bit) 1 12 LSB LSB LSB LSB 66 −81 dB dB (AVDD1x + AVSSx)/2 1 12 5 V −0.99 1 kHz 1 kHz +1 mA mV/mA mA 0.7 × IOVDD 0.4 0.1 −10 IOVDD ≥ 3 V, ISOURCE = 1 mA 2.3 ≤ IOVDD < 3 V, ISOURCE = 500 μA IOVDD < 2.3 V, ISOURCE = 200 μA IOVDD ≥ 3 V, ISINK = 2 mA 2.3 ≤ IOVDD < 3 V, ISINK = 1 mA IOVDD < 2.3 V, ISINK = 100 μA Floating state Floating state +10 0.8 × IOVDD 0.8 × IOVDD 0.8 × IOVDD 0.4 0.4 0.4 +10 −10 SAR ADC Data Output Coding Rev. 0 | Page 7 of 97 10 Twos complement Binary V V V μA V V V V V V μA pF AD7779 Parameter POWER SUPPLIES AVDD1x – AVSSx IAVDD1x4, 5 AVDD2x – AVSSx IAVDD2x Data Sheet Test Conditions/Comments All Σ-Δ channels enabled AVSSxv − DGND IOVDD − DGND IIOVDD Power Dissipation6 High Resolution Mode Low Power Mode Power-Down Typ Max Unit 3.6 V 17 4.5 22.7 6.1 mA mA 19 5 25.5 6.8 mA mA 13 3.5 17.8 4.8 3.6 9.45 3.7 AVDD1x mA mA V mA mA V 2 10 0 3.6 10.7 4.4 mA μA V V mA mA 133 44 mW mW μW 3.0 Reference buffer pre-Q, VCM enabled, internal reference enabled High resolution mode Low power mode Reference buffer enabled, VCM enabled, internal reference enabled High resolution mode Low power mode Reference buffer disabled, VCM disabled, internal reference disabled High resolution mode Low power mode 2.2 High resolution mode Low power mode 9 3.5 AVDD4 – AVSSx IAVDD4 Min AVDD1x – 0.3 SAR enabled SAR disabled 1.7 1 −1.8 1.8 High resolution mode Low power mode Internal buffers bypassed, internal reference disabled, internal oscillator disabled, SAR disabled 16 kSPS 4 kSPS All ADCs disabled 1 8 3 86 27 530 AVSSx is used to refer to the following pins: AVSS1A, AVSS1B, AVSS2B, and AVSS2A. This term is used throughout the data sheet. At temperatures higher than 105°C, the device can be operated normally, though slight degradation on the maximum/minimum specifications is expected because these specifications are only guaranteed up to 105°C. See the Typical Performance Characteristics section for plots showing the typical performance of the device at high temperatures. 3 The SDO pin and the DOUTx pin are configured in the default mode of strength. 4 AVDD1x = 3.3 V, AVSSx = GND = ground, IOVDD = 1.8 V, CMOS clock. 5 Disabling either the VCM pin or the internal reference results in a 40 μA typical current consumption reduction. 6 Power dissipation is calculated using the maximum supply voltage, 3.6 V. 2 Rev. 0 | Page 8 of 97 Data Sheet AD7779 DOUTx TIMING CHARACTERISTISTICS AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V internal/external, MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Test Conditions/Comments 50:50 Min 0.655 60 60 Typ MCLK/2 MCLK/2 122 122 15 15 5 5 20 20 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. t1 t2 t3 MCLK DCLK t4 t6 t5 t8 t7 t9 DRDY DOUTx LSB MSB MSB – 1 t10 t11 Figure 2. Data Interface Timing Diagram Rev. 0 | Page 9 of 97 LSB + 1 LSB 13295-002 1 Description1 MCLK Frequency MCLK Low Time MCLK High Time DCLKx High Time DCLKx Low Time MCLK Falling Edge to DCLK Rising Edge MCLK Falling Edge to DCLK Falling Edge DCLKx Rising Edge to DRDY Rising Edge DCLKx Rising Edge to DRDY Falling Edge DOUTx Setup Time DOUTx Hold Time Max 8.192 Unit MHz ns ns ns ns ns ns ns ns ns ns AD7779 Data Sheet SPI TIMING CHARACTERISTISTICS AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 3. Parameter t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22A t22B t23 t24 t25 Test Conditions/Comments 50:50 Min 7 7 10 10 10 10 10 5 5 30 49 10 10 30 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. t19 CS t15 t16 t17 t13 t14 t18 SCLK t20 SDI MSB t22A SDO MSB – 1 t12 LSB + 1 LSB t21 MSB t22B MSB – 1 LSB + 1 t24 t23 Figure 3. SPI Control Interface Timing Diagram Rev. 0 | Page 10 of 97 LSB t25 13295-003 1 Description1 SCLK Period SCLK Low Time SCLK High Time SCLK Rising Edge to CS Falling Edge CS Falling Edge to SCLK Rising Edge SCLK Rising Edge to CS Rising Edge CS Rising Edge to SCLK Rising Edge Minimum CS High Time SDI Setup Time SDI Hold Time CS Falling Edge to SDO Enable (SPI = Mode 0) SCLK Falling Edge to SDO Enable (SPI = Mode 1) SDO Setup Time SDO Hold Time CS Rising Edge to SDO Disable Typ Max 30 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet AD7779 SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 4. Parameter t26 t27 t28 t29 t30 tINIT_ tINIT_ t31 tPOWER_UP SYNC_IN RESET Test Conditions/Comments 16 kSPS, HP mode 16 kSPS, HP mode Min 10 MCLK MCLK 10 MCLK 145 225 2 × MCLK tPOWER_UP is not shown in Figure 4 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. MCLK START t26 t27 SYNC_OUT t28 SYNC_IN t29 t30 DRDY tINIT_SYNC_IN RESET t31 tINIT_RESET Figure 4. Synchronization Pins and Reset Control Interface Timing Diagram Rev. 0 | Page 11 of 97 Typ 2 13295-004 1 Description1 START Setup Time START Hold Time MCLK Falling Edge to SYNC_OUT Falling Edge SYNC_IN Setup Time SYNC_IN Hold Time SYNC_IN Rising Edge to First DRDY RESET Rising Edge to First DRDY RESET Hold Time Start Time Max Unit ns ns ns ns ns μs μs ns ms AD7779 Data Sheet SAR ADC TIMING CHARACTERISTISTICS AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 5. Description1 Conversion Time Acquisition Time2 Delay Time Throughput Data Parameter t32 t33 t34 t35 1 2 Min 1 500 50 Typ Max 3.4 Unit μs ns ns kSPS 256 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. Direct mode enabled. If deglitch mode is enabled, add 1.5/MCLK. CS t33 t32 t34 13295-005 CONVST_SAR t35 Figure 5. SAR ADC Timing Diagram GPIO SRC UPDATE TIMING CHARACTERISTISTICS AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter t36 t37 t37 t38 t39 t40 Min 10 MCLK 2 × MCLK 20 5 MCLK All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. MCLK GPIO2 t36 t37 GPIO1 t38 GPIO0 t39 t40 Figure 6. GPIOs for SRC Update Timing Diagram Rev. 0 | Page 12 of 97 13295-006 1 Description1 GPIO2 Setup Time GPIO2 Hold Time High Resolution Mode Low Power Mode MCLK Rising Edge to GPIO1 Rising Edge Time GPIO0 Setup Time GPIO0 Hold Time Typ Max Unit ns ns ns ns ns Data Sheet AD7779 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Any Supply Pin to AVSSx AVSSx to DGND AREGxCAP to AVSSx DREGCAP to DGND IOVDD to DGND IOVDD to AVSSx AVDD4 to AVSSx Analog Input Voltage REFx± Input Voltage AUXAIN± Digital Input Voltage to DGND Digital Output Voltage to DGND XTAL1 to DGND AINx±, AUXAIN±, and Digital Input Current Operating Temperature Range Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering ESD Field Induced Charged Device Model (FICDM) Rating −0.3 V to +3.96 V −1.98 V to +0.3 V −0.3 V to +1.98 V −0.3 V to +1.98 V −0.3 V to +3.96 V −0.3 V to +5.94 V AVDD1x − 0.3 V to 3.96 V AVSSx − 0.3 V to AVDD1x + 0.3 V or 3.96 V (whichever is less) AVSSx − 0.3 V to AVDD1x + 0.3 V or 3.96 V (whichever is less) AVSSx − 0.3 V to AVDD4 + 0.1 V or 3.96V (whichever is less) DGND − 0.3 V to IOVDD + 0.3 V or 3.96 V (whichever is less) DGND − 0.3 V to IOVDD + 0.3 V or 3.96 V (whichever is less) DGND − 0.3 V to DREGCAP + 0.3 V or 1.98 V (whichever is less) ±10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 8. Thermal Resistance Package Type1 64-Lead LFCSP No Thermal Vias1 49 Thermal Vias1 1 θJA θJB ΨJT ΨJB Unit 30.43 22.62 N/A2 3.17 0.13 0.09 6.59 3.19 °C/W °C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. 2 N/A means not applicable. ESD CAUTION −40°C to +125°C 150°C −65°C to +150°C 260°C 2 kV 500 V Rev. 0 | Page 13 of 97 AD7779 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AUXAIN– AUXAIN+ AVDD4 AVSS4 AVSS2A AREG1CAP AVDD2A VCM CLK_SEL FORMAT0 FORMAT1 AVSS3 AVDD2B AREG2CAP AVSS2B REF_OUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD7779 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AIN4– AIN4+ AIN5– AIN5+ AVSS1B AVDD1B REF2– REF2+ AIN6– AIN6+ AIN7– AIN7+ RESET SYNC_IN SYNC_OUT START NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSSx. 13295-007 CONVST_SAR ALERT/CS DCLK2/SCLK DCLK1/SDI DCLK0/SDO DGND DREGCAP IOVDD DOUT3 DOUT2 DOUT1 DOUT0 DCLK DRDY XTAL1 XTAL2/MCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AIN0– AIN0+ AIN1– AIN1+ AVSS1A AVDD1A REF1– REF1+ AIN2– AIN2+ AIN3– AIN3+ MODE0/GPIO0 MODE1/GPIO1 MODE2/GPIO2 MODE3/ALERT Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic AIN0− AIN0+ AIN1− AIN1+ AVSS1A Type Analog input Analog input Analog input Analog input Supply Direction Input Input Input Input Supply 6 AVDD1A Supply Supply 7 REF1− Reference Input 8 9 10 11 12 13 REF1+ AIN2− AIN2+ AIN3− AIN3+ MODE0/GPIO0 Reference Analog input Analog input Analog input Analog input Digital I/O Input Input Input Input Input I/O 14 MODE1/GPIO1 Digital I/O I/O 15 MODE2/GPIO2 Digital I/O I/O 16 MODE3/ALERT Digital I/O I/O 17 CONVST_SAR Digital input Input Description Analog Input Channel 0, Negative. Analog Input Channel 0, Positive. Analog Input Channel 1, Negative. Analog Input Channel 1, Positive. Negative Front-End Analog Supply for Channel 0 to Channel 3, Typical at −1.65 V (Dual Supply) and AGND (Single Supply). Connect all the AVSSx pins to the same potential. Positive Front-End Analog Supply for Channel 0 to Channel 3, Typical at AVSSx + 3.3 V. Connect this pin to AVDD1B. Negative Reference Input 1 for Channel 0 to Channel 3, Typical at AVSSx. Connect all the REFx− pins to the same potential. Positive Reference Input 1 for Channel 0 to Channel 3, Typical at REF1− + 2.5 V. Analog Input Channel 2, Negative. Analog Input Channel 2, Positive. Analog Input Channel 3, Negative. Analog Input Channel 3, Positive. Mode 0 Input Pin in Pin Control Mode (MODE0). See Table 18 for more details. Configurable General-Purpose Input/Output 0 in SPI Control Mode (GPIO0). If not in use, connect this pin to DGND or IOVDD. Mode 1 Input Pin in Pin Control Mode (MODE1). See Table 18 for more details. Configurable General-Purpose Input/Output 1 in SPI Control Mode (GPIO1). If not in use, connect this pin to DGND or IOVDD. Mode 2 Input Pin in Pin Control Mode (MODE2). See Table 18 for more details. Configurable General-Purpose Input/Output 2 in SPI Control Mode (GPIO2). If not in use, connect this pin to DGND or IOVDD. Mode 3 Input Pin in Pin Control Mode (MODE3). See Table 18 for more details. Alert Output Pin in SPI Control Mode (ALERT). Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table 17 for more details. This pin also functions as the start for the SAR conversion in SPI control mode. Rev. 0 | Page 14 of 97 Data Sheet AD7779 Pin No. 18 Mnemonic ALERT/CS Type Digital input Direction Input 19 DCLK2/SCLK Digital input Input 20 DCLK1/SDI Digital input Input 21 DCLK0/SDO Digital output Output 22 23 24 DGND DREGCAP IOVDD Supply Supply Supply Supply Output Supply 25 DOUT3 Digital output I/O 26 DOUT2 Digital output I/O 27 28 29 30 31 DOUT1 DOUT0 DCLK DRDY XTAL1 Digital output Digital output Digital output Digital output Clock Output Output Output Output Input 32 XTAL2/MCLK Clock Input 33 START Digital input Input 34 SYNC_OUT Digital output Input 35 SYNC_IN Digital input Input 36 RESET Digital input Input 37 38 39 40 41 42 AIN7+ AIN7− AIN6+ AIN6− REF2+ REF2− Analog input Analog input Analog input Analog input Reference Reference Input Input Input Input Input Input 43 AVDD1B Supply Supply 44 AVSS1B Supply Supply 45 46 47 48 AIN5+ AIN5− AIN4+ AIN4− Analog input Analog input Analog input Analog input Input Input Input Input Description Alert Output Pin in Pin Control Mode (ALERT). Chip Select Pin in SPI Control Mode (CS). DCLK Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 19 for more details. SPI Clock in SPI Control Mode (SCLK). DCLK Frequency Selection Pin 1 in Pin Control Mode (DCLK1). See Table 19 for more details. SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the device is configured in pin control mode with the SPI as the data output interface. DCLK Frequency Selection Pin 0 in Pin Control Mode (DCLK0). See Table 19 for more details. SPI Data Output in SPI Control Mode (SDO). Digital Ground. Digital LDO Output. Decouple this pin to DGND with a 1 μF capacitor. Digital Levels Input/Output and Digital LDO (DLDO) Supply from 1.8 V to 3.6 V. IOVDD must not be lower than DREGCAP. Data Output Pin 3. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. Data Output Pin 2. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. Data Output Pin 1. Data Output Pin 0. Data Output Clock. Data Output Ready Pin. Crystal 1 Input Connection. If CMOS is used as a clock source, tie this pin to DGND. See Table 16 for more details. Crystal 2 Input Connection (XTAL2). See Table 16 for more details. CMOS Clock (MCLK). See Table 16 for more details. Synchronization Pulse. This pin is used to synchronize internally an external START asynchronous pulse with MCLK. The synchronize signal is shift out by the SYNC_OUT pin. If not in use, tie this pin to DGND. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details. Synchronization Signal. This pin generates a synchronous pulse generated and driven by hardware (via the START pin) or by software (GENERAL_USER_ CONFIG_2, Bit 0). If this pin is in use, it must be wired to the SYNC_IN pin. See the Phase Adjustment and the Digital Reset and Synchronization Pins section for more details. Reset for the Internal Digital Block and Synchronize for Multiple Devices. See the Digital Reset and Synchronization Pins section for more details. Asynchronous Reset Pin. This pin resets all registers to their default value. It is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. Analog Input Channel 7, Positive. Analog Input Channel 7, Negative. Analog Input Channel 6, Positive. Analog Input Channel 6, Negative. Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2− + 2.5 V. Negative Reference Input 2 for Channel 4 to Channel 7, Typical at AVSSx. Connect all the REFx− pins to the same potential. Positive Front-End Analog Supply for Channel 4 to Channel 7. Connect this pin to AVDD1A. Negative Front-End Analog Supply for Channel 4 to Channel 7, typical at −1.65 V (Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins together. Analog Input Channel 5, Positive. Analog Input Channel 5, Negative. Analog Input Channel 4, Positive. Analog Input Channel 4, Negative. Rev. 0 | Page 15 of 97 AD7779 Data Sheet Pin No. 49 Mnemonic REF_OUT Type Reference Direction Output 50 51 52 53 54 55 56 57 AVSS2B AREG2CAP AVDD2B AVSS3 FORMAT1 FORMAT0 CLK_SEL VCM Supply Output Supply Supply Input Input Input Output 58 AVDD2A Supply Supply Supply Supply Digital input Digital input Digital input Analog output Supply 59 60 61 62 63 64 AREG1CAP AVSS2A AVSS4 AVDD4 AUXAIN+ AUXAIN− EPAD Supply Supply Supply Supply Analog input Analog input Supply Output Input Supply Supply Input Input Input Input Description 2.5 V Reference Output. Connect a 100 nF capacitor on this pin if using the internal reference. Negative Analog Supply. Connect all the AVSSx pins together. Analog LDO Output 2. Decouple this pin to AVSS2B with a 1 μF capacitor. Positive Analog Supply. Connect this pin to AVDD2A. Negative Analog Ground. Connect all the AVSSx pins together. Output Data Frame 1. See Table 17 for more details. Output Data Frame 0. See Table 17 for more details. Select Clock Source. See Table 16 for more details. Common-Mode Voltage Output, Typical at (AVDD1 + AVSSx)/2. Analog Supply from 2.2 V to 3.6 V. AVSS2x must not be lower than AREGxCAP. Connect this pin to AVDD2B. Analog LDO Output 1. Decouple this pin to AVSS with a 1 μF capacitor. Negative Analog supply. Connect all the AVSSx pins together. Negative SAR Analog Supply and Reference. Connect all AVSSx pins together. Positive SAR Analog Supply and Reference Source. Positive SAR Analog Input Channel. Negative SAR Analog Input Channel. Exposed Pad. Connect the exposed pad to AVSSx. Rev. 0 | Page 16 of 97 Data Sheet AD7779 TYPICAL PERFORMANCE CHARACTERISTICS 8 8 TEMPERATURE = 25°C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 6 4 4 2 Figure 8. INL vs. Input Voltage and Channel at 8 kSPS, High Resolution Mode, AVSSx (VCM is the Voltage on the VCM Pin) 2.48 13295-019 2.12 1.77 1.06 0.70 0 0.35 –0.35 INPUT VOLTAGE (V) Figure 11. INL vs. Input Voltage and Channel at 2 kSPS, Low Power Mode, AVSSx 6 8 TEMPERATURE = 25°C VREF = 2.5V DIFFERENTIAL VIN × GAIN VCM = (AVDD1x + AVSSx) ÷ 2 4 TEMPERATURE = 25°C DIFFERENTIAL VIN × GAIN VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 6 4 2 2 INL (ppm) 0 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –2 0 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –2 –4 –4 –6 INPUT VOLTAGE (V) 13295-012 2.48 2.12 1.77 1.41 1.06 0.70 0.35 0 –0.35 –0.70 –1.06 –1.41 –1.77 –2.48 13295-009 2.48 2.12 1.77 1.41 1.06 0.70 0.35 0 –0.35 –0.70 –1.06 –1.41 –1.77 –2.12 –2.48 INPUT VOLTAGE (V) Figure 9. INL vs. Input Voltage and PGA Gain at 8 kSPS, High Resolution Mode, AVSSx –2.12 –8 –6 Figure 12. INL vs. Input Voltage and PGA Gain at 2 kSPS, Low Power Mode, AVSSx 6 10 GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 4 GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 8 6 4 INL (ppm) 2 0 TA = –40°C TA = +25°C TA = +105°C TA = +125°C –2 2 0 TA = –40°C TA = +25°C TA = +105°C TA = +125°C –2 –4 –6 –4 –8 Figure 10. INL vs. Input Voltage and Temperature at 8 kSPS, High Resolution Mode, AVSSx Rev. 0 | Page 17 of 97 2.48 2.12 1.77 1.41 1.06 0.70 0.35 0 –0.35 –0.70 –1.06 –1.41 –1.77 –2.12 INPUT VOLTAGE (V) Figure 13. INL vs. Input Voltage and Temperature at 2 kSPS, High Resolution Mode, AVSSx 13295-013 INPUT VOLTAGE (V) 13295-010 2.48 2.12 1.77 1.41 1.06 0.70 0.35 0 –0.35 –0.70 –1.06 –1.41 –1.77 –2.12 –10 –2.48 –6 –2.48 INL (ppm) –0.70 –2.48 2.48 INPUT VOLTAGE (V) 13295-016 2.12 1.77 1.06 0.70 0 0.35 –0.35 –0.70 –1.06 –1.41 –8 –1.77 –8 –2.12 –6 –2.48 –6 –1.06 –4 –1.41 –4 –2 –1.77 –2 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 0 –2.12 0 1.41 INL (ppm) CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 1.41 INL (ppm) 2 INL (ppm) TEMPERATURE = 25°C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 6 AD7779 Data Sheet 15 15 TEMPERATURE = 25°C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VCM = (AVDD1x + AVSSx) ÷ 2 10 10 5 VREF VREF VREF VREF VREF VREF –5 –10 –15 –3.6 –2.6 –1.6 = 3.3V = 3.0V = 2.5V = 2.0V = 1.5V = 1.0V –0.6 0.4 1.4 INPUT VOLTAGE (V) VREF VREF VREF VREF VREF VREF –5 –10 2.4 3.4 –15 –3.6 Figure 14. INL vs. Input Voltage and Reference Voltage (VREF) at 8 kSPS, High Resolution Mode, AVSSx –2.6 –1.6 = 3.3V = 3.0V = 2.5V = 2.0V = 1.5V = 1.0V –0.6 0.4 1.4 INPUT VOLTAGE (V) 2.4 3.4 Figure 17. INL vs. Input Voltage and Reference Voltage (VREF) at 2 kSPS, Low Power Mode, AVSSx 10 10 TEMPERATURE = 25°C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V 8 6 TEMPERATURE = 25°C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V 8 6 4 4 2 2 INL (ppm) 0 VCM = 1.35V VCM = 1.65V VCM = 1.95V –2 –4 0 VCM = 1.35V VCM = 1.65V VCM = 1.95V –2 –4 Figure 15. INL vs. Input Voltage and VCM at 8 kSPS, High Resolution Mode 2.48 13295-018 2.12 1.77 1.41 1.06 0.70 0 0.35 –0.35 –0.70 –1.06 2000 1600 1400 1000 Rev. 0 | Page 18 of 97 8388772 8388730 8388688 8388646 8388604 8388562 ADC CODE Figure 19. Noise Histogram at 2 kSPS, Low Power Mode 13295-225 ADC CODE Figure 16. Noise Histogram at 8 kSPS, High Resolution Mode 8388436 0 8388394 0 8388352 200 8388310 400 200 13295-022 400 8388300 8388314 8388328 8388342 8388356 8388370 8388384 8388398 8388412 8388426 8388440 8388454 8388468 8388482 8388496 8388510 8388524 8388538 8388552 8388566 8388580 8388594 600 8388268 800 600 8388226 800 1200 8388184 1000 8388142 1200 8388520 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1400 VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 TEMPERATURE = 25°C GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1800 8388478 VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 TEMPERATURE = 25°C SAMPLE CODE 1600 –1.41 INPUT VOLTAGE (V) Figure 18. INL vs. Input Voltage and VCM at 2 kSPS, Low Power Mode 2000 1800 –1.77 –2.48 2.48 INPUT VOLTAGE (V) 13295-015 2.12 1.77 1.41 1.06 0.70 0 0.35 –0.35 –0.70 –1.06 –1.41 –1.77 –2.12 –8 –10 –2.48 –8 –10 –2.12 –6 –6 8388100 INL (ppm) 0 13295-017 INL (ppm) 0 13295-014 INL (ppm) 5 SAMPLE COUNT TEMPERATURE = 25°C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VCM = (AVDD1x + AVSSx) ÷ 2 Data Sheet AD7779 5.0 10 4.5 9 4.0 8 VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 NOISE (µV rms) 2.5 2.0 6 5 4 3 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1.0 0.5 0 –40 25 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 2 1 105 125 TEMPERATURE (°C) 0 –40 25 105 13295-029 3.0 1.5 VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 7 13295-026 NOISE (µV rms) 3.5 125 TEMPERATURE (°C) Figure 20. Noise vs. Temperature at 8 kSPS, High Resolution Mode Figure 23. Noise vs Temperature at 2 kSPS, Low Power Mode 6 5.0 4.5 5 4.0 3.0 2.5 2.0 1.5 VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 TEMPERATURE = 25°C DECIMATION = 256 1.0 0.5 2 VREF = 2.5V VCM = (AVDD1x + AVSSx) ÷ 2 TEMPERATURE = 25°C DECIMATION = 256 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1 CLOCK FREQUENCY (Hz) 3980920 13295-035 3750760 3520600 3290440 3060280 2830120 2599960 2369800 2139640 1909480 1679320 1449160 988840 1219000 758680 298360 7961840 13295-032 7501520 7041200 6580880 6120560 5660240 5199920 4739600 4279280 3818960 3358640 2898320 2438000 1977680 1517360 596720 CLOCK FREQUENCY (Hz) Figure 21. Noise vs. Clock Frequency, High Resolution Mode, Decimation = 256 Figure 24. Noise vs. Clock Frequency at 2 kSPS, Low Power Mode, Decimation = 256 120 400 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 100 350 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 300 NOISE (nV/√Hz) 80 60 40 250 200 150 100 20 100 2000 4000 8000 1600 ODR (Hz) Figure 22. Noise vs. ODR, High Resolution Mode 0 500 1000 2000 4000 ODR (Hz) Figure 25. Noise vs. ODR, Low Power Mode Rev. 0 | Page 19 of 97 8000 13295-098 0 50 13295-097 NOISE (nV/√Hz) 3 0 1057040 0 4 528520 NOISE (µV rms) 3.5 NOISE (µV rms) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 Data Sheet Figure 29. FFT Plot, Low Power Mode, Input Frequency (fIN) = 50 Hz, 8192 Samples, AVSSx (This Plot is a Close Up Perspective of the Original Data) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 13295-021 FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. FFT Plot, Low Power Mode, Input Frequency (fIN) = 1 kHz, 8192 Samples, AVSSx Figure 27. FFT Plot, High Resolution Mode, Input Frequency (fIN) = 1 kHz, AVSSx –100 –100 VIN = –0.5dBFS VREF = 2.5V TEMPERATURE = 25°C –105 VIN = –0.5dBFS VREF = 2.5V TEMPERATURE = 25°C –105 –110 THD (dB) –110 –115 –120 GAIN = GAIN = GAIN = GAIN = 1 2 4 8 –115 –120 –125 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –130 –130 Figure 28. THD vs. Input Frequency at 8 kSPS, High Resolution Mode Rev. 0 | Page 20 of 97 INPUT FREQUENCY (Hz) Figure 31. THD vs. Input Frequency at 2 kSPS, Low Power Mode 13295-036 13295-033 INPUT FREQUENCY (Hz) 10 70 130 190 250 310 370 460 530 590 650 710 770 840 900 960 1066 1198 1352 1484 1616 1748 1880 2012 –135 –135 10 90 170 250 330 410 490 570 650 730 810 890 970 1355 1923 2491 3059 3627 4266 4905 5544 6112 6751 7390 7958 THD (dB) VREF = 2.5V TEMPERATURE = 25°C DIFFERENTIAL INPUT = –0.5dBFS VCM = (AVDD1x + AVSSx) ÷ 2 INPUT FREQUENCY = 1kHz 8192 SAMPLES 4kSPS GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 13295-024 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 13295-023 FREQUENCY (Hz) AMPLITUDE (dB) VREF = 2.5V TEMPERATURE = 25°C DIFFERENTIAL INPUT = –0.5dBFS VCM = (AVDD1x + AVSSx) ÷ 2 INPUT FREQUENCY = 1kHz 16384 SAMPLES 16kSPS 0 277.343750 554.687500 832.031250 1109.37500 1386.71875 1664.06250 1941.40625 2218.75000 2496.09375 2773.43750 3050.78125 3328.12500 3605.46875 3882.81250 4160.15625 4437.50000 4714.84375 4992.10875 5269.53125 5546.87500 5824.21875 6101.56250 6378.90625 6656.25000 6933.59375 7210.93750 7488.28125 7765.62500 AMPLITUDE (dB) Figure 26. FFT Plot at 16 kSPS, High Resolution Mode, Input Frequency (fIN) = 50 Hz, AVSSx (This Plot is a Close Up Perspective of the Original Data) –125 VREF = 2.5V TEMPERATURE = 25°C DIFFERENTIAL INPUT = –0.5dBFS VCM = (AVDD1x + AVSSx) ÷ 2 INPUT FREQUENCY = 50Hz 8192 SAMPLES 4kSPS GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 0 31.25 62.50 93.75 125.00 156.25 187.50 218.75 250.00 281.25 312.50 343.75 375.00 406.25 437.50 468.75 500.00 531.25 562.50 593.75 625.00 656.25 687.5 718.75 750.00 781.25 812.50 843.75 875.00 906.25 937.50 968.75 AMPLITUDE (dB) 996.093750 FREQUENCY (Hz) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 13295-020 937.500000 878.906250 820.312500 761.718750 703.125000 644.531250 585.937500 527.343750 468.750000 410.156250 351.562500 292.968750 234.375000 175.781250 117.187500 0 VREF = 2.5V TEMPERATURE = 25°C DIFFERENTIAL INPUT = –0.5dBFS VCM = (AVDD1x + AVSSx) ÷ 2 INPUT FREQUENCY = 50Hz 16384 SAMPLES 16kSPS GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 0 66.40625 132.81250 199.21875 265.62500 332.03125 398.43750 464.84375 531.25000 597.65625 664.06250 730.46875 796.87500 863.28125 929.68750 996.09375 1062.50000 1128.90625 1195.31250 1261.71875 1328.12500 1394.53125 1460.93750 1527.34375 1593.75000 1660.15625 1726.56250 1792.96875 1859.37500 1925.78125 1992.18750 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 58.593750 AMPLITUDE (dB) AD7779 Data Sheet AD7779 –100 –100 INPUT FREQUENCY = 50Hz VREF = 2.5V TEMPERATURE = 25°C –105 –110 –120 1 2 4 8 –120 –130 –130 –135 –135 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 13295-034 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 32. THD vs. Input Voltage at 2 kSPS, High Resolution Mode (Input Frequency = 50 Hz) 13295-037 –140 –140 Figure 35. THD vs. Input Voltage at 500 SPS, Low Power Mode –90 –90 –100 THD (dB) –105 –110 –105 –110 –120 –120 –125 –125 REFERENCE VOLTAGE (V) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 13295-038 –115 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 –115 REFERENCE VOLTAGE (V) Figure 33. THD vs. Reference Voltage at 8 kSPS, High Resolution Mode (Input Frequency = 50 Hz) –100 –100 INPUT FREQUENCY = 50Hz VREF = 2.5V INPUT VOLTAGE = –0.5dBFS TEMPERATURE = 25°C DECIMATION = 256 –102 –104 –106 Figure 36. THD vs. Reference Voltage at 2 kSPS, Low Power Mode (Input Frequency = 50 Hz) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 INPUT FREQUENCY = 50Hz VREF = 2.5V INPUT VOLTAGE = 5V p-p TEMPERATURE = 25°C DECIMATION = 256 –102 –104 –106 THD (dB) –108 –110 –112 –110 –112 –114 –114 –116 –116 235840 665920 1096000 1216000 1336000 1456000 1576000 1696000 1816000 1936000 2056000 2176000 2296000 2416000 2536000 2656000 2776000 2896000 3016000 3136000 3256000 3376000 3496000 3616000 3736000 3856000 3976000 4096000 7823010 7301490 6779970 13295-039 MCLK FREQUENCY (Hz) 6258450 5736930 5215410 4693890 4172370 3650850 3129330 2607810 2086290 1564770 655000 –118 –120 1043250 -118 –120 Figure 34. THD vs. MCLK Frequency, High Resolution Mode, Input Frequency (fIN) = 50 Hz, Decimation = 256 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –108 FREQUENCY (Hz) 13295-042 –100 INPUT FREQUENCY = 50Hz INPUT VOLTAGE = 5V p-p TEMPERATURE = 25°C GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –95 13295-041 INPUT FREQUENCY = 50Hz INPUT VOLTAGE = ±VREF TEMPERATURE = 25°C GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –95 THD (dB) = = = = –125 –125 THD (dB) GAIN GAIN GAIN GAIN –115 THD (dB) THD (dB) –110 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –115 INPUT FREQUENCY = 50Hz VREF = 2.5V TEMPERATURE = 25°C –105 Figure 37. THD vs. MCLK Frequency, Low Power Mode, Input Frequency (fIN) = 50 Hz, Decimation = 256 Rev. 0 | Page 21 of 97 AD7779 Data Sheet 125 125 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 115 110 110 SNR (dB) 115 105 VIN = 0dBFS VREF = 2.5V TEMPERATURE = 25°C 105 100 95 95 90 90 85 1 2 4 8 16 ODR (kHz) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 85 0.5 8 120 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 110 DYNAMIC RANGE (dB) 110 100 90 80 100 90 80 70 70 8000 PGA GAIN Figure 39. Dynamic Range vs. PGA Gain, High Resolution Mode, ODR = 8 kSPS 13295-090 60 13295-089 60 2000 PGA GAIN Figure 42. Dynamic Range vs. PGA Gain, Low Power Mode, ODR = 2 kSPS 0 0 TEMPERATURE = 25°C VIN = 0V VREF = 2.5V AVDD1x = 3.3V OFFSET ERROR (µV) –10 –20 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 –30 –40 TEMPERATURE = 25°C VIN = 0V VREF = 2.5V AVDD1x = 3.3V –10 –50 –20 –30 –40 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 –50 –60 2 4 PGA GAIN 8 –70 13295-044 1 Figure 40. Offset Error vs. PGA Gain, High Resolution Mode, AVDD1x = 3.3 V 1 2 4 PGA GAIN 8 13295-047 DYNAMIC RANGE (dB) 4 Figure 41. SNR vs. ODR at 2 kSPS, Low Power Mode (AVDDx = 3.6 V, AVSS = 1.8 V, IOVDD = 3.6 V) 120 OFFSET ERROR (µV) 2 ODR (kHz) Figure 38. SNR vs. ODR at 8 kSPS, High Resolution Mode (AVDDx = 3.6 V, AVSS = 1.8 V, IOVDD = 3.6 V) –60 1 13295-043 100 INPUT FREQUENCY = 50Hz VIN = 0dBFS VREF = 2.5V INPUT VOLTAGE = 5V p-p TEMPERATURE = 25°C 120 13295-040 SNR (dB) 120 Figure 43. Offset Error vs. PGA Gain, Low Power Mode, AVDD1x = 3.3 V Rev. 0 | Page 22 of 97 Data Sheet AD7779 0 0 –5 –5 –10 OFFSET ERROR (µV) –15 –20 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 TEMPERATURE = 25°C VIN = 0V VREF = 2.5V –25 –30 TEMPERATURE = 25°C VIN = 0V VREF = 2.5V –15 –20 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –25 –30 –35 –35 –45 3.0 13295-051 3.3 3.6 SUPPLY SETTING 3.6 13295-054 –40 –40 3.0 1000 13295-058 OFFSET ERROR (µV) –10 3.3 SUPPLY SETTING Figure 44. Offset Error vs. Supply Setting, High Resolution Mode Figure 47. Offset Error vs. Supply Setting, Low Power Mode 30 35 AVDD1x = 3.3V 30 20 GAIN ERROR DRIFT (ppm) OFFSET DRIFT (µV) 25 10 0 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 –10 –20 20 15 10 5 0 –5 –30 –10 –15 13295-045 115.991 124.589 95.349 105.439 87.104 78.593 70.920 62.669 54.035 45.142 35.461 26.714 9.272 18.298 0.073 –13.506 –22.232 –30.430 –37.624 –40 0 500 TIME (Hours) TEMPERATURE (°C) Figure 48. Gain Error Drift vs. Time Figure 45. Offset Drift vs. Temperature, AVDD1x = 3.3 V 0.017 0.008 0 –0.008 –0.017 –0.035 –0.035 3.0 3.3 AVDD1x SUPPLY (V) 3.6 Figure 46. Gain Error vs. AVDD1x Supply, High Resolution Mode TEMPERATURE = 25°C GAIN = 1 –0.017 –0.026 –0.043 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 –0.008 –0.026 13295-056 GAIN ERROR (%) 0 TEMPERATURE = 25°C GAIN = 1 –0.043 3.0 3.3 AVDD1x SUPPLY (V) Figure 49. Gain Error vs. AVDD1x Supply, Low Power Mode Rev. 0 | Page 23 of 97 3.6 13295-059 0.008 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 GAIN ERROR (%) 0.017 AD7779 0.005 0 0.005 0 –0.005 –0.011 –0.017 –0.011 –0.017 –0.023 –0.029 –0.029 –0.035 –0.035 105 125 –0.400 –40 1.5 REFERENCE VOLTAGE DRIFT (mV) 0.07 0.06 HIGH RESOLUTION LOW POWER 0.05 0.04 0.03 0.02 0.01 1 2 4 8 PGA GAIN UNIT 1 UNIT 2 UNIT 3 UNIT 4 UNIT 5 UNIT 6 UNIT 7 1.0 0.5 0 –0.5 –1.0 –1.5 –40 13295-052 –20 Figure 51. Channel Gain Mismatch, High Resolution Mode, AVDD1x = 3.3 V 20 40 60 80 100 120 Figure 54. Internal Reference Voltage Drift 0.008 0.010 0.006 0.008 VREF = 2.5V VIN = –0.5dBFS GAIN = 1 AVDD1x = 3.3V 0.006 TUE (% OF INPUT) 0.004 0.002 VREF = 2.5V VIN = –0.5dBFS GAIN = 1 AVDD1x = 3.3V 0 0.004 0.002 0 –0.002 –0.002 Rev. 0 | Page 24 of 97 110 125 90 100 80 70 60 50 40 30 20 0 10 –10 –30 TEMPERATURE (°C) Figure 55. TUE (as % of Input) vs. Temperature, Low Power Mode, AVDD1x = 3.3 V 13295-085 TEMPERATURE (°C) Figure 52. Total Unadjusted Error (TUE) (as % of Input) vs. Temperature, High Resolution Mode, AVDD1x = 3.3 V –40 13295-082 110 –0.004 125 90 100 80 70 60 50 40 30 20 0 10 –10 –20 –30 –0.004 –40 TUE (% OF INPUT) 0 TEMPERATURE (°C) –20 0 125 Figure 53. Gain Error vs. Temperature, Low Power Mode, AVDD1x = 3.3 V TEMPERATURE = 25°C AVDD1x = 3.3V 0.08 105 TEMPERATURE (°C) Figure 50. Gain Error vs Temperature, High Resolution Mode, AVDD1x = 3.3 V 0.09 25 13295-099 25 TEMPERATURE (°C) GAIN ERROR (%) –0.005 –0.023 –0.400 –40 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 AVDD1x = 3.3V 0.011 13295-057 GAIN ERROR (%) 0.017 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 13295-060 AVDD1x = 3.3V 0.011 GAIN ERROR (%) 0.017 Data Sheet Data Sheet 1.5 0.6 AINx+ VCM = 1.95V AINx– VCM = 1.95V AINx+ VCM = 1.35V AINx– VCM = 1.35V 1.0 VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 0.5 0.4 0.5 0 –0.5 –1.0 0.3 0.2 0.1 0 AINx+ VCM = 1.95V AINx– VCM = 1.95V AINx+ VCM = 1.35V AINx– VCM = 1.35V –0.1 –1.5 –0.2 –2.5 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 VREF = 2.5V VIN = 2.5V AVDD1 = 3.3V –0.3 1.5 –0.4 – 2.5 –2.0 2.0 2.5 DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–)) 13295-076 –2.0 Figure 56. Input Current vs. Differential Input Voltage, High Resolution Mode –0.5 0 0.5 1 1.5 2 2.5 Figure 59. Input Current vs. Differential Input Voltage, Low Power Mode 4 115.991 124.589 95.349 105.439 87.104 78.593 0.4 VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 0.5 0 –0.5 –1.0 –1.5 0.3 0.2 AINx+ – AINx– VCM = 1.95V AINx+ – AINx– VCM = 1.35V 0.1 0 –0.1 –0.2 –0.3 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–)) 2.5 Figure 58. Differential Input Current vs. Differential Input Voltage, High Resolution Mode –0.5 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–)) 2.5 Figure 61. Differential Input Current vs. Differential Input Voltage, Low Power Mode Rev. 0 | Page 25 of 97 13295-093 –0.4 13295-091 –2.0 –2.5 70.920 0.5 AINx+ – AINx– VCM = 1.95V AINx+ – AINx– VCM = 1.35V DIFFERENTIAL INPUT CURRENT (nA) 1.0 62.669 Figure 60. Absolute Input Current vs. Temperature, Low Power Mode 2.0 1.5 54.035 –40.000 TEMPERATURE (°C) Figure 57. Absolute Input Current vs. Temperature, High Resolution Mode 13295-083 TEMPERATURE (°C) 13295-080 115.991 124.589 95.349 105.439 87.104 78.593 70.920 62.669 54.035 45.142 35.461 26.714 9.272 18.298 –0.073 –8.000 –16.000 –24.000 –32.000 –6 –40.000 –5 –6 45.142 –4 –5 35.461 –4 AIN0+ AIN0– AIN2+ AIN2– –3 26.714 –3 –2 9.272 AIN0+ AIN0– AIN2+ AIN2– –2 18.298 –1 0 –1 –0.073 0 1 –16.000 1 2 –24.000 2 –32.000 ABSOLUTE INPUT CURRENT (nA) 3 VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 3 –8.000 VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 4 ABSOLUTE INPUT CURRENT (nA) –1.0 DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–)) 5 DIFFERENTIAL INPUT CURRENT (nA) –1.5 13295-079 INPUT CURRENT (nA) INPUT CURRFENT (nA) AD7779 AD7779 Data Sheet 8 10 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 7 6 5 7 DIFFERENTIAL INPUT CURRENT (nA) VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 4 3 2 5 4 3 2 1 1 13295-094 115.991 124.589 95.349 105.439 87.104 78.593 70.920 62.669 54.035 45.142 35.461 26.714 9.272 18.298 –0.073 –8.000 GAIN 1 GAIN 2 GAIN 4 GAIN 8 AVDD1x = 3.3V VCM = 1.65V + 100mV p-p 13295-062 13.000 8250.088 16487.177 24724.265 32961.353 41198.442 49435.530 57672.618 65909.707 74146.795 82383.883 90620.971 98858.060 107095.148 115332.236 123569.325 131806.413 140043.501 148280.590 156517.678 164754.766 172991.855 181228.943 189466.031 197782.322 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 INPUT FREQUENCY (Hz) Figure 63. CMRR vs. Input Frequency at 8 kSPS, High Resolution Mode, AVDD1x = 3.3 V, VCM = 1.65 V + 100 mV p-p GAIN 1 GAIN 2 GAIN 4 GAIN 8 0 TEMPERATURE = 25°C AVDD1x = 3.3V + 100mV p-p –20 –40 –40 –60 –60 AC PSRR (dB) –80 –100 –120 TEMPERATURE = 25°C AVDD1x = 3.3V + 100mV p-p –80 –100 –120 –140 –160 –160 INPUT FREQUENCY (Hz) –180 13295-063 10 380962 761914 1142866 1523818 1904770 2285722 2666674 3047626 3428578 3809530 4190482 4571434 4952386 5333338 5714290 6095242 6476194 6857146 7238098 7619050 8000002 8390478 8790477 9190477 9590477 9990476 –140 –180 GAIN 1 GAIN 2 GAIN 4 GAIN 8 Figure 64. AC PSRR vs. Input Frequency at 8 kSPS, High Resolution Mode, AVDD1x = 3.3 V + 100 mV p-p VCM = 1.65V + 100mV p-p INPUT FREQUENCY (Hz) 13295-066 AC PSRR (dB) –20 10 380962 761914 1142866 1523818 1904770 2285722 2666674 3047626 3428578 3809530 4190482 4571434 4952386 5333338 5714290 6095242 6476194 6857146 7238098 7619050 8000002 8390478 8790477 9190477 9590477 9990476 0 Figure 66. CMRR vs. Input Frequency at 2 kSPS, Low Power Mode, AVDD1x = 3.3 V, VCM = 1.65 V + 100 mV p-p Figure 67. AC PSRR vs. Input Frequency at 2 kSPS, Low Power Mode, AVDD1x = 3.3 V + 100 mV p-p Rev. 0 | Page 26 of 97 13295-065 AVDD1x = 3.3V VCM = 1.65V + 100mV p-p INPUT FREQUENCY (Hz) –16.000 TEMPERATURE (°C) Figure 65. Differential Input Current vs. Temperature, Low Power Mode CMRR (dB) GAIN 1 GAIN 2 GAIN 4 GAIN 8 13.000 6903.641 13794.282 20684.924 27575.565 34466.206 41356.847 48247.488 55138.130 62028.771 68919.412 75810.053 82700.694 89591.335 96481.977 103372.618 110263.259 117153.900 124044.541 130935.183 137825.824 144756.066 151646.708 158576.950 165507.193 172437.435 179367.678 186297.920 193228.163 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –40.000 13295-092 115.991 124.589 95.349 105.439 87.104 78.593 70.920 62.669 54.035 45.142 35.461 26.714 9.272 18.298 –0.073 –8.000 –16.000 –24.000 –32.000 –40.000 TEMPERATURE (°C) Figure 62. Differential Input Current vs. Temperature, High Resolution Mode –24.000 0 0 CMRR (dB) VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 6 –32.000 DIFFERENTIAL INPUT CURRENT (nA) 9 Data Sheet AD7779 0 0 –10 GAIN = GAIN = GAIN = GAIN = –20 –40 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 –60 –30 ATTENUATION (dB) ATTENUATION (dB) –20 –80 1 2 4 8 –40 –50 –60 –70 –80 –100 –90 –100 FREQUENCY (Hz) FREQUENCY (Hz) Figure 68. Filter Profiles at 8 kSPS, High Resolution Mode 20 18 Figure 71. Filter Profiles at 2 kSPS, Low Power Mode 6 AVDD1 AVDD2 AVDD4 IOVDD AVDD1 AVDD2 AVDD4 IOVDD 5 ALL CHANNELS ENABLED SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16 13295-087 25 344 663 982 1301 1620 1939 2258 2577 2896 3215 3534 3853 4172 4491 4810 5129 5448 5767 6086 6405 6724 7043 7362 7681 13295-086 25 664 1303 1942 2581 3220 3859 4498 5137 5776 6415 7054 7693 8332 8971 9610 10249 10888 11527 12166 12805 13444 14083 14722 15361 –120 14 12 10 8 6 4 ALL CHANNELS ENABLED 4 3 2 1 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) Figure 69. Supply Current vs. Supply Voltage at 8 kSPS, High Resolution Mode SUPPLY CURRENT (mA) 20 AVDD1 AVDD2 AVDD4 IOVDD 7 6 10 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Figure 72. Supply Current vs. Supply Voltage at 2 kSPS, Low Power Mode ALL CHANNELS ENABLED 15 2.2 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 25 0 2.0 13295-064 0 2.0 13295-067 2 AVDD1 AVDD2 AVDD4 IOVDD ALL CHANNELS ENABLED 5 4 3 2 5 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 0 –40 13295-069 0 –40 Figure 70. Supply Current vs. Temperature at 8 kSPS, High Resolution Mode –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 13295-072 1 Figure 73. Supply Current vs. Temperature at 2 kSPS, Low Power Mode Rev. 0 | Page 27 of 97 Data Sheet 300 600 200 400 200 REF1– REF1+ REF2– REF2+ 0 –200 –400 100 0 –200 –300 –400 –500 –800 –600 13295-096 TEMPERATURE (°C) –35.263 –29.594 –22.185 –15.223 –7.366 –0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 –600 Figure 74. Reference Input Current vs. Temperature, High Resolution Mode TEMPERATURE (°C) Figure 77. Reference Input Current vs. Temperature, Low Power Mode 80 250 70 SHUTDOWN SUPPLY CURRENT (µA) SHUTDOWN SUPPLY CURRENT (µA) REF1– REF1+ REF2– REF2+ –100 13295-095 REFERENCE INPUT CURRENT (nA) 800 –35.263 –29.594 –22.185 –15.223 –7.366 –0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 REFERENCE INPUT CURRENT (nA) AD7779 60 50 40 AVDD1 AVDD2 AVDD4 IOVDD 30 20 10 200 AVDD1 AVDD2 AVDD4 IOVDD 150 100 50 0 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLATGE (V) –50 –40 13295-074 14 AVDD1 AVDD2 AVDD4 12 30 25 20 15 10 40 60 80 100 120 AVDD1 AVDD2 AVDD4 10 8 6 4 2 5 2.0 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) 3.2 3.4 3.6 0 1.8 13295-068 0 1.8 20 Figure 78. Shutdown Supply Current vs. Temperature POWER CONSUMPTION (mW) POWER CONSUMPTION (mW) 35 0 TEMPERATURE (°C) Figure 75. Shutdown Supply Current vs. Supply Voltage 40 –20 Figure 76. Power Consumption per Channel vs. Supply Voltage at 8 kSPS, High Resolution Mode 2.0 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) 3.2 3.4 3.6 13295-071 –10 1.8 13295-078 0 Figure 79. Power Consumption per Channel vs. Supply Voltage at 2 kSPS, Low Power Mode Rev. 0 | Page 28 of 97 Data Sheet 90 25 AVDD1 AVDD2 AVDD4 AVDD1 AVDD2 AVDD4 70 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 80 AD7779 60 50 40 30 20 20 15 10 5 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 0 –40 13295-070 0 –40 Figure 80. Power Dissipation vs. Temperature at 8 kSPS, High Resolution Mode –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 13295-073 10 Figure 81. Power Dissipation vs. Temperature at 2 kSPS, Low Power Mode Rev. 0 | Page 29 of 97 AD7779 Data Sheet TERMINOLOGY the ±2.5 V range). The last transition (from 011 … 110 to 011 … 111) occurs for an analog voltage 1½ LSB below the nominal full scale (2.49999 V for the ±2.5V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at fullscale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− at frequency, fS. CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. DNL error is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) Error Integral noninearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale input signal to the rms noise measured for an input. The value for dynamic range is expressed in decibels. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale frequency sweep sine wave signal to all seven nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure is given for worst case scenarios across all eight channels of the AD7779. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa and nfb, where m, n = 0,1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7779 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the secondorder terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. Gain Error The first transition (from 100 … 000 to 100 … 001) occurs at a level ½ LSB above nominal negative full scale (−2.49999 V for Gain Error Drift Gain error drift is the ratio of the gain error change due to a temperature change of 1°C and the full-scale range (2N). It is expressed in parts per million. Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is LSB (V) = 2VREF 2N The LSB referred to the input is 2 VREF PGAGAIN LSB (VIN) = 2N Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in the power supply voltage from the nominal value. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Offset Error Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of 1°C and the full-scale code range (2N). It is expressed in μV/°C. Rev. 0 | Page 30 of 97 Data Sheet AD7779 RMS NOISE AND RESOLUTION It is important to note that the effective resolution is calculated using the rms noise; 16,384 consecutives samples were used to calculate the rms noise. Table 10 through Table 12 show the dynamic range (DR), rms noise (RTI), effective number of bits (ENOB), and effective resolution (ER) of the AD7779 for various output data rates and gain settings. The numbers given are for the bipolar input range with an external 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. Effective Resolution = log2(Input Range/RMS Noise) ENOB = (DR − 1.78)/6 HIGH RESOLUTION MODE Table 10. DR (dB) and RTI (μVRMS) for High Resolution Mode Gain Decimation Rate 128 256 512 1024 2048 Output Data Rate (SPS) 16000 8000 4000 2000 1000 f−3dB (Hz) 5029.99 2521.99 1267.99 640.99 327.49 1 2 DR 108.28 112.5 116.12 119.5 122.37 RTI 6.80 4.12 2.70 1.87 1.33 DR 105.13 110.21 114.7 118.3 121.55 4 RTI 4.80 2.63 1.59 1.07 0.74 8 DR 101 106.8 111.6765 115.82 119 RTI 3.95 2.01 1.11 0.70 0.49 DR 95.86 102 107.61 112 115.5 RTI 3.46 1.72 0.93 0.57 0.38 Table 11. ENOB and ER for High Resolution Mode Gain Decimation Rate 128 256 512 1024 2048 Output Data Rate (SPS) 16000 8000 4000 2000 1000 f−3dB (Hz) 5029.99 2521.99 1267.99 640.99 327.49 1 ENOB 17.75 18.46 19.06 19.62 20.1 2 ER 19.49 20.21 20.82 21.35 21.84 ENOB 17.23 18.08 18.82 19.42 19.97 4 ER 18.99 19.86 20.58 21.16 21.69 ENOB 16.54 17.51 18.32 19.01 19.54 8 ER 18.27 19.25 20.10 20.76 21.28 ENOB 15.68 16.71 17.64 18.37 18.96 ER 17.46 18.47 19.36 20.08 20.66 LOW POWER MODE Table 12. DR and RTI (μVRMS) for Low Power Mode Gain Decimation Rate 64 128 256 512 Output Data Rate (SPS) 8000 4000 2000 1000 f−3dB (Hz) 2521.99 1267.99 640.99 327.49 DR 100 106 112 116 1 RTI 19.1 8.82 4.53 2.89 2 DR 96 103 108.5 114 4 RTI 13.4 6.18 3.03 1.77 DR 92 98.5 106 111 8 RTI 11.2 5.2 2.32 1.24 DR 87 94 100.5 107 RTI 10.3 4.65 2.05 1.04 Table 13. ENOB and ER for Low Power Mode Gain Decimation Rate 64 128 256 512 Output Data Rate (SPS) 8000 4000 2000 1000 f−3dB (Hz) 2521.99 1267.99 640.99 327.49 1 ENOB 16.37 17.37 18.37 19.04 2 ER 18.00 19.11 20.07 20.72 ENOB 15.71 16.87 17.79 18.71 Rev. 0 | Page 31 of 97 4 ER 17.51 18.63 19.65 20.43 ENOB 15.04 16.12 17.37 18.21 8 ER 16.77 17.87 19.04 19.94 ENOB 14.21 15.37 16.46 17.54 ER 15.89 17.04 18.22 19.20 AD7779 Data Sheet THEORY OF OPERATION The AD7779 is an 8-channel, simultaneously sampling, low noise, 24-bit -Δ ADC with integrated digital filtering per channel and SRC. Due to the high oversampling rate, this technique spreads the quantization noise from 0 to fCLKIN/2 (in the case of the AD7779, fCLKIN relates to the external clock); therefore, the noise energy contained in the band of interest is reduced (see Figure 82). To further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (see Figure 83). The digital filter that follows the modulator removes the large out of band quantization noise (see Figure 84). For more information on basic and advanced concepts of -Δ ADCs, see MT-022 and MT-023. Digital filtering has certain advantages over analog filtering. Because digital filtering occurs after the analog-to-digital conversion process, it can remove noise injected during the conversion. Analog filtering cannot remove noise injected during conversion. fICLK\2 Figure 82. -∆ ADC Operation, Reduction of Noise Energy Contained in the Band of Interest (Linear Scale X-Axis) NOISE SHAPING BAND OF INTEREST fICLK\2 Figure 83. -∆ ADC Operation, Majority of Noise Energy Shifted Out of the Band of Interest (Linear Scale X-Axis) DIGITAL FILTER CUTOFF FREQUENCY BAND OF INTEREST fICLK\2 Figure 84. -∆ ADC Operation, Removal of Noise Energy from the Band of Interest (Linear Scale X-Axis) The -Δ ADC starts the conversions of the input signal after the supplies generated by the internal LDOs become stable. An external signal is not required to generate the conversions. ANALOG INPUTS The AD7779 can be operated in bipolar or unipolar modes and accepts true differential, pseudo differential, and single-ended input signals, as shown in Figure 85 through Figure 88. Table 14 summarizes the maximum differential input signal and dynamic range for the different input modes. Table 14. Input Signal Modes Input Signal Mode True differential Pseudo differential Single-ended PGA Gain All gains All gains All gains 13295-101 The AD7779 employs a -Δ conversion technique to convert the analog input signal into an equivalent digital word. The overview of the -Δ technique is that the modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, fCLKIN. BAND OF INTEREST 13295-102 The AD7779 offers two operation modes: high resolution mode, which offers up to 16 kSPS, and low power mode, which offers up to 8 kSPS. In low power mode, the specifications are guaranteed up to 4 kSPS, with performance degradation expected at ODRs higher than 4 kSPS. 13295-100 QUANTIZATION NOISE Maximum Differential Signal ±(VREF/PGAGAIN) ±(VREF/PGAGAIN) VREF/PGAGAIN Rev. 0 | Page 32 of 97 Maximum Peak-to-Peak Signal 2 × VREF/PGAGAIN 2 × VREF/PGAGAIN VREF/PGAGAIN Data Sheet AD7779 BIPOLAR OR UNIPOLAR TRUE DIFFERENTIAL AVDD1x – 0.1V AVSSx + 0.1V Figure 85. -∆ ADC Input Signal Configuration, True Differential (AVDD1x + AVSSx)/2 –0.4125 –0.8250 VREF = 2.5V AVDD1x = 1.65V AVSSx = –1.65V –1.6500 1 2 4 PGA GAIN –1.2375 8 The AD7779 provides a common-mode voltage pin (AVDD1x + AVSSx)/2), VCM, for the single-supply, pseudo differential, or true differential input configurations. AVDD1x – 0.1V VREF /PGAGAIN TRANSFER FUNCTION AINx+ AINx+ The AD7779 can operate with up to a 3.6 V reference, typical at 2.5 V, and converts the differential voltage between the analog inputs (AINx+ and AINx−) into a digital output. The ADC converts the voltage difference between the analog input pins (AINx+ − AINx−) into a digital code on the output. The 24-bit conversion result is in MSB first, twos complement format, as shown in Table 15 and Figure 90. 13295-104 PSEUDO DIFFERENTIAL 0.4125 Figure 89. Maximum Common-Mode Voltage Range for a Maximum Differential Input Signal BIPOLAR OR UNIPOLAR VCM TRUE DIFFERENTIAL PSEUDO DIFFERENTIAL 0.8250 13295-103 AINx+ VCM AINx+ VREF /PGAGAIN 1.2375 13295-107 COMMON-MODE VOLTAGE (V) 1.6500 AVSSx + 0.1V Figure 86. -∆ ADC Input Signal Configuration, Pseudo Differential BIPOLAR SINGLE-ENDED Table 15. Output Codes and Ideal Input Voltages for PGA = 1× VREF /PGAGAIN AINx+ AINx+ 13295-105 AVSSx + 0.1V Figure 87. -∆ ADC Input Signal Configuration, Single-Ended Bipolar Condition FS − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FS + 1 LSB −FS Analog Input (AINx+ − AINx−), VREF = 2.5 V +2.499999702 V +298 nV 0V −298 nV −2.499999702 V −2.5 V Digital Output Code, Twos Complement (Hex) 0x7FFFFF 0x000001 0x000000 0xFFFFFF 0x800001 0x800000 AINx+ AINx+ + 0.1V Figure 88. -∆ ADC Input Signal Configuration, Single-Ended Unipolar The input signal common mode is not limited, but keep the absolute input signal voltage on any AINx± pin between AVSSx + 100 mV and AVDD1x – 100 mV; otherwise, the input signal linearity degrades and, if the signal voltage exceeds the absolute maximum signal rating, damages the device. Figure 89 shows the maximum and minimum voltage commonmode range at different PGA gains for a maximum differential input voltage. Rev. 0 | Page 33 of 97 011 ... 111 011 ... 110 011 ... 101 100 ... 010 100 ... 001 100 ... 000 –FSR –FSR + 1LSB –FSR + 0.5LSB +FSR – 1LSB +FSR – 1.5LSB ANALOG INPUT Figure 90. Transfer Function 13295-108 ADC CODE (TWOS COMPLEMENT) VREF /PGAGAIN 13295-106 SINGLE-ENDED UNIPOLAR AD7779 Data Sheet MCLK START SYNC_OUT SYNC_IN RESET PGA GAIN 1, 2, 4, 8 AINx+ DIGITAL FILTER SINC3 SRC Σ-∆ MODULATOR AINx– ESD PROTECTION GAIN SCALING AND OFFSET CORRECTION DRDY CONVERSION DATA INTERFACE DOUTx SCLK SIGNAL CHAIN FOR CHANNEL x CONTROL BLOCK FORMAT0 AND FORMAT1 CONTROL OPTION PIN OR SPI MODE0 TO MODE3 SPI CONTROL 13295-109 PIN CONTROL CS SCLK SDO SDI Figure 91. Top Level Core Signal Chain CORE SIGNAL CHAIN Each -Δ ADC channel on the AD7779 has an identical signal path from the analog input pins to the digital output pins. Figure 91 shows a top level implementation of this signal chain. Prior to each -Δ ADC, a PGA maps sensor outputs into the ADC inputs, providing low input current in dc (±4 nA, input current, and ±1.5 nA differential input current), an 8 pF input capacitance in ac, and configurable gains of 1, 2, 4, and 8. See the AN-1392 for more information. Each ADC channel has its own -Δ modulator, which oversamples the analog input and passes the digital representation to the digital filter block. The data is filtered, scaled for gain and offset, and is then output on the data interface. To minimize power consumption, the channels can be individually disabled. for the maximum common-mode voltage at maximum differential input signals. INTERNAL REFERENCE AND REFERENCE BUFFERS The AD7779 integrates a 2.5 V, 10 ppm/°C typical, voltage reference that is disabled at power-up. The buffered reference is available at Pin 49 and offers up to 10 mA of continuous current. A 100 nF capacitor is required if the reference is enabled. In applications where a low noise reference is required, it is recommended to add a low-pass filter (LPF) with a cutoff frequency (fCUTOFF) below 10 Hz to the REF_OUT pin. Connect the output of this filter to REFx+, and connect AVSSx to REFx−. In this scenario, config-ure the -Δ reference as external. An example of performance with and without the output filter is shown in Figure 92. 115 CAPACITIVE PGA VREF = INTERNAL REFERENCE fCUTOFF = 10Hz Each -Δ ADC has a dedicated PGA, offering gain ranges of 1, 2, 4, and 8. This PGA reduces the need for an external input buffer and allows the user to amplify small sensor signals to use the full dynamic range of the AD7779. SNR (dB) 105 The PGA maximize the signal chain dynamic range for small sensor output signals. The AD7779 uses chopping of the PGA to minimize offset and offset drift in the input amplifier, reducing the 1/f noise as well. For the AD7779, the chopping frequency is set to 64 kHz for high resolution mode, and 16 kHz for low power mode (see the AN1131 for more information). The chopping tone is rejected by the SINC filter. To minimize intermodulation effects that may cause image in the band of interest, it is recommended to limit the input signal bandwidth to 2/3 of the chop frequency. The capacitive PGA common-mode voltage does not depend on the gain, and can be any value as long as the input signal voltage is within AVSSx + 100 mV to AVDD1x – 100 mV. See Figure 89 95 75 0.05 0.50 1.00 2.00 DIFFERENTIAL INPUT VOLTAGE (V) 2.50 13295-110 85 Figure 92. SNR Adding External LPF with VREF = Internal Reference and fCUTOFF = 10 Hz The AD7779 can be used with an external reference connected between the REFx+ and REFx− pins. Recommended reference voltage sources for the AD7779 include the ADR441 and ADR4525 family of low noise, high accuracy voltage references. Rev. 0 | Page 34 of 97 Data Sheet AD7779 DCLK DIVIDER 1, 2, 4, 8, 16, 32, 64, 128 MCLK MCLK DIVIDER HIGH RESOLUTION MODE: MCLK/4 LOW POWER MODE: MCLK/8 MOD_MCLK DCLKx PGA ADC MODULATOR SINC FILTER AINx– DATA INTERFACE CONTROL DRDY DOUT3 TO DOUT0 DEC RATES = ×128, ×256, ×512, ×1024, ×2048, ×4095.99 13295-111 AINx+ Figure 93. Clock Generation on the AD7779 The reference buffers can be operated in three different modes: buffer enabled mode, buffer bypassed mode, and buffer precharged mode. In buffer enabled mode, the buffer is fully enabled, minimizing the current requirements from the external references. Note that the buffer output voltage headroom is ±100 mV from the rails. In buffer bypassed mode, the external reference is directly connected to the ADC reference capacitors; the reference must provide enough current to correctly charge the internal ADC reference capacitors. In this mode of operation, a degradation in crosstalk is expected because the ADC channels are not isolated from each other. CLOCKING AND SAMPLING The AD7779 includes eight -Δ ADC cores. Each ADC receives the same master clock signal. The AD7779 requires a maximum external MCLK frequency of 8192 kHz for high resolution mode and 4096 kHz for low power mode. The MCLK is internally divided by 4 in high performance mode and by 8 in low power mode to produce the modulator MCLK (MOD_MCLK) signal used as the modulator sampling clock for the ADCs. The MCLK can be decreased to accommodate lower ODRs if the minimum ODR selected by the SINC filter is not low enough. If the external clock is lower than 250 kHz, set the CLK_QUAL_DIS bit (in SPI control mode only). Buffer precharged (pre-Q) mode is the default operation mode. It is a hybrid mode where the internal reference buffers are connected during the initial acquisition time to precharge the internal ADC reference capacitors. During the final phase of the acquisition, the reference is connected directly to the ADC capacitors. This mode has some benefits compared to the buffer enabled and buffer bypassed modes. In buffer precharged mode, The AD7779 integrates an internal oscillator clock that initializes the internal registers at power-up. The CLK_SEL pin defines the external clock used after initialization (see Table 16). CLK_SEL State 0 Clock Source CMOS 1 Crystal the reference current requirements are minimized compared to buffer bypassed mode the noise contribution from the internal reference buffers is removed (compared to buffer enabled mode) In buffer precharged mode, the headroom/footroom of the buffer reference is not applicable because the reference sets the final voltage in the ADC reference capacitors. INTEGRATED LDOs The AD7779 has three internal LDOs to regulate the internal supplies: two LDOs for the analog block and one LDO for the digital core. The internal LDOs requires an external 1 μF decoupling capacitor on the DREGCAP, AREG1CAP, and the AREG2CAP pins. The LDO slew rate may be low because it depends on the main supply slew rate; therefore, a hardware reset generated by pulsing the RESET pin at power-up is required to guarantee that the digital block initializes correctly. Table 16. Clock Sources Connection Input to XTAL2/MCLK, IOVDD logic level. XTAL1 must be tied to DGND. Connected between XTAL1 and XTAL2/MCLK. The MCLK signal generates the DCLK output signal, which in turn clocks the -Δ conversion data from the AD7779, as shown in Figure 93. DIGITAL RESET AND SYNCHRONIZATION PINS An external pulse in the SYNC_IN pin generates the internal reset of the digital block; this pulse does not affect the data programmed in the internal registers. A pulse in this pin is required in two cases as follows: Rev. 0 | Page 35 of 97 After updating one or more registers directly related to the sinc3 filter. These are power mode, offset, gain, and phase compensation. To synchronize multiple devices. AD7779 Data Sheet The pulse in the SYNC_IN pin must be synchronous with MCLK. DIGITAL FILTERING There are two different ways to achieve a synchronous pulse if the controller/processor cannot generate it as follows: The SYNC_IN and SYNC_OUT pins must be externally connected if internal synchronization is used. The digital filter implements three main notches, one at the maximum ODR (16 kHz or 8 kHz, depending on the power mode) and another two at the ODR frequency selected to stop noise aliasing into the pass band. Figure 95 shows the typical filter transfer function for the high resolution and low power modes using a decimation rate of 256 samples. 0 If multiple AD7779 devices must be synchronized, the SYNC_OUT pin of one device can be connected to multiple devices. This synchronization method requires the use of a common MCLK signal for all the AD7779 devices connected, as shown in Figure 94. If the START pin is not used, tie it to DGND. –20 –30 ASYNCHRONOUS PULSE –40 –50 –60 –70 –80 AD7779 –90 START SYNCHRONIZATION LOGIC SYNC_OUT –100 0 8 16 24 32 FREQUENCY (kHz) DIGITAL FILTER 13295-113 MCLK LOW POWER MODE DECIMATION = 256 HIGH RESOLUTION MODE DECIMATION = 256 –10 Figure 95. Sinc3 Frequency Response SYNC_IN The sample rate converter featured allows fine tuning of the decimation rate, even for noninteger multiples of the decimation rate. See the Sample Rate Converter (SRC) section for more information on filter profiles for noninteger decimation rates. AD7779 START MCLK SYNCHRONIZATION LOGIC SYNC_OUT SHUTDOWN MODE NC The AD7779 can be placed in shutdown mode by pulling AVDD2 to ground and connecting 1 MΩ resistance, pulled low, to XTAL2. In this mode, the average current consumption is reduced to 1 mA, as shown in Figure 96. DIGITAL FILTER SYNC_IN 1.0 IAVDD1x IAVDD2x IAVDD4x IIOVDD AD7779 SYNCHRONIZATION LOGIC SYNC_OUT SUPPLY CURRENT (mA) START MCLK NC DIGITAL FILTER SYNC_IN 13295-112 MCLK Figure 94. Multiple AD7779 Synchronization AVDDx = 3.3V IOVDD = 3.3V 0.5 0 –0.5 –40 10 60 TEMPERATURE (°C) Figure 96. Shutdown Current Rev. 0 | Page 36 of 97 125 13295-114 Applying an asynchronous pulse on the START pin, which is then internally synchronized with the external MCLK clock, and the resulting synchronous signal is output on the SYNC_OUT pin. Triggering the SYNC_OUT internally. When the AD7779 is configured in SPI control mode, toggling Bit 0 in the GEN_USER_CONFIG_2 register generates a synchronous pulse that is output on the SYNC_OUT pin. GAIN (dB) The AD7779 offers a low latency sinc3 filter. Most precision -Δ ADCs use sinc3 filters because the sinc3 filter offers a low latency path for applications requiring low bandwidth signals, for example, in control loops or where application specific postprocessing is required. The digital filter adds notches at multiples of the sampling frequency. Data Sheet AD7779 CONTROLLING THE AD7779 The AD7779 can be controlled using either pin control mode or SPI control mode. Pin control mode allows the AD7779 to be hardwired to predefined settings that offer a subset of the overall functionality of the AD7779. In this mode, the SRC and diagnostic features or extended errors source are not available. Controlling the AD7779 over the SPI interface allows the user access to the full monitoring, diagnostic, and -Δ control functionality. SPI control offers additional functionality such as offset, gain, and phase correction per channel, in addition to access to the flexible SRC to achieve a coherent sampling. See Table 17 for more details about these different configurations. PIN CONTROL MODE In pin control mode, the AD7779 is configured at power-up based on the level of the mode pins, MODE 0, MODE1, MODE2, and MODE3. These four pins set the following functions on the AD7779: the mode of operation, the decimation rate/ODR, the PGA gain, and the reference source, as shown in Table 18. Due to the limited number of mode pins and the number of options available, the PGA gain control is grouped into blocks of 4, and the ODR is selected for the maximum value defined by the decimation rate; ODR (kHz) = 2048/decimation for high resolution mode, and ODR (kHz) = 512/decimation for low power mode. Depending on the mode selected, the device is configured to use an external or an internal reference. The conversion data can be read back using the SPI interface or the data output interface, as shown in Table 17. If the data output interface is used to read back the data from the conversions, the number of DOUTx lines enabled and the number of clocks required for the -Δ data transfer are determined by the logic level of the CONV_SAR, FORMAT0, and FORMAT1 pins. In this case, the DCLK2, DCLK1, and DCLK0 pins select the -Δ output interface and control the DCLKx divide function, which is a submultiple of MCLK, as shown in Table 19. The DCLKx divide function sets the frequency of the data output interface DCLKx signal. The DCLK minimum frequency depends on the decimation rate and operation mode. See the Data Output Interface section for more details about the minimum DCLKx frequency. All the pins that define the AD7779 configuration mode are reevaluated each time the SYNC_IN pin is pulsed. The typical connection diagram for pin control mode is shown in Figure 97. Table 17. Format of the Data Interface CONV_SAR State 1 0 FORMAT1 0 0 1 1 0 FORMAT0 0 1 1 1 0 Control Mode Pin Pin Pin SPI Pin 0 1 Pin 1 1 0 1 Pin SPI Data Output Mode SPI output SPI output SPI output Defined in Register 0x014 DOUT0, Channel 0 to Channel 1 DOUT1, Channel 2 to Channel 3 DOUT2, Channel 4 to Channel 5 DOUT3, Channel 5 to Channel 7 DOUT0, Channel 0 to Channel 3 DOUT1, Channel 4 to Channel 7 DOUT0, Channel 0 to Channel 7 Defined in Register 0x014 Table 18. Pin Mode Options Pin State MODE3 0 0 0 0 0 0 0 MODE2 0 0 0 0 1 1 1 MODE1 0 0 1 1 0 0 1 MODE0 0 1 0 1 0 1 0 Decimation Rate 1024 512 256 128 256 512 256 Power Mode High resolution High resolution High resolution High resolution High resolution High resolution High resolution Rev. 0 | Page 37 of 97 PGA Gain Channel Channel 0 to Channel 4 to Channel 3 Channel 7 1 1 1 1 1 1 1 1 1 2 1 4 1 4 Reference Type External External External External External External External AD7779 Data Sheet Pin State MODE3 0 1 1 1 1 1 1 1 1 MODE2 1 0 0 0 0 1 1 1 1 MODE1 1 0 0 1 1 0 0 1 1 Decimation Rate 128 512 256 128 512 256 128 128 256 MODE0 1 0 1 0 1 0 1 0 1 Power Mode High resolution High resolution High resolution High resolution Low power Low power Low power Low power Low power PGA Gain Channel Channel 0 to Channel 4 to Channel 3 Channel 7 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reference Type External Internal Internal Internal External External External Internal Internal Table 19. DCLKx Selection for Pin Control Mode DCLK2/SCLK 0 0 0 0 1 1 1 1 State DCLK0/SDO 0 1 0 1 0 1 0 1 DCLK1/SDI 0 0 1 1 0 0 1 1 MCLK Divider 1 2 4 8 16 32 64 128 EXTERNAL REFERENCE AVDD 3.3V AVDD3.3V AVSSx AVDD1x REFx+ VCM VCM AVDD3.3V AVSSx AVSSx AVSSx REFx– AVDD4 REF_OUT AVDD2x AREGxCAP BUFFER AVSSx IOVDD 2V TO 3.6V AVSSx IOVDD AD7779 BUFFER DREGCAP SYNC_IN SYNC_OUT START RESET DRDY AIN0+ PGA AIN7+ 24-BIT Σ-∆ ADC PGA AIN7– DCLK DOUT0 DOUT1 DOUT2 DOUT3 ADC DATA SERIAL INTERFACE AIN0– SINC3/SRC CS SCLK SDO SPI CONTROL INTERFACE SDI SPI/SPORT SLAVE INTERFACE FPGA OR DSP SPI MASTER INTERFACE CLK_SEL XTAL1 XTAL2 MODE3 TO MODE0 CONVST_SAR DCLK2 TO DCLK0 FORMAT1 AND FORMAT0 13295-115 AVSSx CLOCK SOURCE Figure 97. Pin Mode Connection Diagram with External Reference Rev. 0 | Page 38 of 97 Data Sheet AD7779 AVDD 3.3V AVDD3.3V AVSSx AVSSx REFx+ AVDD1x VCM VCM AVSSx REFx– REF_OUT BUFFER AVDD4 IOVDD 2V TO 3.6V AVSSx AVSSx AVDD2x AREGxCAP AD7779 BUFFER IOVDD DREGCAP SYNC_IN SYNC_OUT START RESET DRDY AIN0+ PGA ADC DATA SERIAL INTERFACE AIN0– AIN7+ 24-BIT Σ-∆ ADC PGA AIN7– DCLK DOUT0 DOUT1 DOUT2 DOUT3 SINC3/SRC SPI CONTROL INTERFACE DIAGNOSTIC INPUTS CS SCLK SDO SDI FULL BUFFER 12-BIT SAR ADC MUX AUXAIN– AVSSx GPIO2 TO GPIO0 CONVST_SAR XTAL1 FPGA OR DSP SPI MASTER INTERFACE CLK_SEL XTAL2 FORMAT1 IOVDD FORMAT0 IOVDD 13295-116 AUXAIN+ SPI/SPORT SLAVE INTERFACE CLOCK SOURCE Figure 98. SPI Control Mode Connection Diagram with Internal Reference SPI CONTROL The second option for control and monitoring the AD7779 is via the SPI interface. This option allows access to the full functionality on the AD7779, including access to the SAR converter, phase synchronization, offset and gain adjustment, diagnostics and the SRC. To use the SPI control, set the FORMAT0 and FORMAT1 pins to logic high. In this mode, the SPI interface can also be used to read the -Δ conversation data by setting the SPI_SLAVEMODE_EN bit. The typical connection diagram for SPI control mode is shown in Figure 98. Functionality Available in SPI Mode SPI control of the AD7779 offers the super set of the functions and diagnostics. The SPI Control Functionality section describes the functionality and diagnostics offered when in SPI control mode. Offset and Gain Correction Offset and gain registers are available for system calibration. The gain register is preprogrammed during final production for a PGA gain of 1, but can be overwritten with a new value if required. The gain register is 24 bits long and is split across three registers, CHx_GAIN_UPPER_BYTE, CHx_GAIN_MID_BYTE, and CHx_GAIN_LOWER_BYTE, which set the gain on a per channel basis. The gain value is relative to 0x555555, which represents a gain of 1. The offset register is 24 bits long and is spread across three byte registers, CHx_OFFSET_UPPER_BYTE, CHx_OFFSET_MID_ BYTE, and CHx_OFFSET_LOWER_BYTE. The default value is 0x000000 at power-up. Program the offset as a twos complement, signed 24-bit number. If the channel gain is set to its nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by −4/3 LSBs. As an example of calibration, the offset measured is −200 LSB (with both AINx± pins connected to the same potential). An offset adjustment of −150 changes the digital output by −150 × (−4/3) = 200 LSBs (gain value = 0x555555), representing this number as two complement, 0xFFFFFF – 0x96 + 1 = 0xFFFF70. CHx_OFFSET_UPPER_BYTE = 0xFF CHx_OFFSET_MID_BYTE = 0xFF CHx_OFFSET_LOWER_BYTE = 0x70 Note that the offset compensation is performed before the gain compensation. The gain is programmed during final testing for PGAGAIN = 1. The gain register values can be overwritten; however, after a reset or power cycle, the gain register values revert to the hard coded programmed factory setting. If the gain required is 0.75 of the nominal value (0x555555), the value that must be programmed is 0x555555 × 0.75 = 0x400000 Then, an LSB of the offset register adjustment changes the digital output by −4/3 × 0.75 = 1 LSB. Rev. 0 | Page 39 of 97 CHx_GAIN_UPPER_BYTE = 0x40 CHx_GAIN_MID_BYTE = 0x00 CHx_GAIN_LOWER_BYTE = 0x00 AD7779 Data Sheet SPI Control Functionality Global Control Functions Table 20. Phase Adjustment vs. Decimation Rate The following list details the global control functions of the AD7779: High resolution and low power modes of operation Output data rate: sample rate converter (SRC) VCM buffer power-down Internal/external reference selection Enable, precharged, or bypassed reference buffer modes Internal reference power-down SAR diagnostic mux SAR power-down GPIO write/read SPI SAR conversion readback SPI slave mode—read -Δ results SDO and DOUT drive strength DOUT mode DCLK division Internal LDO bypassed CRC protection: enabled or disabled Per Channel Functions The following list details the per channel functions of the AD7779: Phase Adjustment Compensation ×1 ×2 ×4 ×8 ×16 Decimation Rate ≤255 ≤511 ≤1023 ≤2047 ≤4095 The maximum phase delay cannot be equal to or greater than the decimation rate. If this is the case, the value changes internally to the decimation rate value minus 1. As an example, the phase mismatch between Channel 0 and Channel 1 is 5°, and the ODR is 5 kSPS in high resolution mode. In this case, the decimation ration is 2048 kHz/5 kHz = 409.6, which means that the offset register value is multiplied internally by 2. Assuming an input signal of 50 Hz, the number of MOD_ MCLK pulses required to sample a full period is 2048 kHz/ 50 Hz = 40960 > 360°/40960 = 8.78 × 103°. If a 5° delay is required, the number of MOD_MCLK delays must be 569 (5°/0.00878°) because the offset register is multiplied by 2; the final offset register value is 409.6/2 − 569/2, which gives a negative value. In this case, if the offset value programmed to the register is higher than 204 (for example, 210 × 2 = 420), the value is internally changed to 408, resulting in a phase compensation of 408 × 0.00878° = 3.58°. PGA Gain PGA gain. -Δ channel power-down. Phase delay: synchronization phase offset per channel. Calibration of offset. Calibration of gain. -Δ input signal mux. Channel error register. PGA gain. The PGA gain can be selected individually by appropriately selecting Bits[7:6] in the CHx_CONFIG register, as shown in Table 21. Table 21. PGA Gain Settings via CHx_CONFIG Phase Adjustment The AD7779 phase delay can be adjusted to compensate for phase mismatches between channels due to sensors or signal channel phase errors connected to the AD7779. Achieve phase adjustment by programming the CHx_SYNC_OFFSET register. This programming delays the synchronization signal by a certain number of modulator clocks, MOD_CLKs, to individually initiate the digital filter for each -Δ ADC. The phase adjustment register is read during the pulse; consequently, any further changes on the register have no effect unless a pulse is generated (see the Digital Reset and Synchronization Pins section for more information on how to generate a pulse in the pin). The phase offset register is multiplied internally by a factor that depends on the decimation rate, as shown in Table 20. CHx_CONFIG, Bits[7:6] Setting 00 01 10 11 PGA Gain Setting ×1 ×2 ×4 ×8 If the -Δ reference is updated, it is recommended to apply a pulse on the SYNC_IN pin to remove invalid samples during the transition of the reference Decimation The decimation defines the sampling frequency as follows: In high resolution mode, the sampling frequency = MCLK/ (4 × decimation) In low power mode, the sampling frequency = MCLK/ (8 × decimation) Refer to the Sample Rate Converter (SRC) section for more information. Rev. 0 | Page 40 of 97 Data Sheet AD7779 GPIO Pins If the AD7779 operates in SPI control mode, the mode pins operate as GPIO pins, as shown in Figure 99. The GPIO pins can be configured as inputs or outputs in any order. -∆ Reference Configuration The AD7779 can operate with internal or external references. In addition, for diagnostic purposes, the analog supply can be used as a reference, as shown in Table 22. GPIO0 GPIO1 In addition, the GPIO pins can be used to externally trigger a new decimation rate. Refer to the Sample Rate Converter (SRC) section for more information about this functionality. Table 22. -Δ References REGISTER MAP 13295-117 GPIO2 Figure 99. GPIO Pin Functionality Configuration control and readback of the GPIO pins are dealt with by Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 = output) and the GPIO_DATA register. Among other uses, the GPIOs can control an external mux connected to the auxiliary inputs of the SAR ADC. Use this mux to verify the results on the -Δ ADCs. Setting for ADC_MUX_CONFIG, Bits[7:6] 00 01 10 11 Channel 0 to Channel 3 REF1+/REF1− Internal reference AVDD1A/AVSS1A REF1−/REF1+ Channel 4 to Channel 7 REF2+/REF2− Internal reference AVDD1B/AVSS1B REF2−/REF2+ Reference buffer operation is described in Table 23. The selected reference and buffer operation mode affect all channels. If the -Δ reference is updated, it is recommended to apply a pulse on the SYNC_IN pin to remove invalid samples during the transition of the reference. Table 23. Reference Buffer Operation Modes Reference Buffer Operation Mode Enabled Precharged Disabled REFx+ BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0 BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1 BUFFER_CONFIG_1, Bit 4 = 0 Rev. 0 | Page 41 of 97 REFx− BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0 BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1 BUFFER_CONFIG_1, Bit 3 = 0 AD7779 Data Sheet Table 24. Additional Disable Power-Down Blocks Block VCM Reference Buffer Internal Reference Buffer -∆ Channel SAR Internal Oscillator Register GENERAL_USER_CONFIG_1, Bit 5 BUFFER_CONFIG_1, Bits[4:3] GENERAL_USER_CONFIG_1, Bit 4 CH_DISABLE, Bits[7:0] GENERAL_USER_CONFIG_1, Bit 3 GENERAL_USER_CONFIG_1, Bit 2 Power Modes The AD7779 offers different power modes to improve the power efficiency, high resolution and low power mode, which can be controlled via GENERAL_USER_CONFIG_1, Bit 6. To further reduce the power, additional blocks can be disabled independently, as described in Table 24. If the power mode changes, a pulse on the SYNC_IN pin is required. LDO Bypassing The internal LDOs can be individually bypassed and an external supply can be applied directly to AREG1CAP, AREG2CAP, or DREGCAP pins. Table 25 shows the absolute minimum and maximum supplies for these pins, as well as the associated register used to bypass the regulator. Table 25. LDO Bypassing LDO AREG1CAP AREG2CAP DREGCAP BUFFER_CONFIG_2, Bits[2:0]1 1XX X1X XX1 Supply Max (V) Min (V) 1.9 1.85 1.9 1.85 1.98 1.65 The SPI interfaces operates in Mode 0 and Mode 3, CPOL = 0, CPHA = 0 (Mode 0) or CPOL = 1, CPHA = 1 (Mode 3). In pin control mode, the SDI can be used to read back the -Δ results, depending on the level of the CONV_SAR pin, as described in Table 17. In SPI control mode, the SPI interface transfers data into the onchip registers while the SDO pin reads back data from the on-chip registers or reads the SAR or the -Δ conversions results, depending on the selected operation mode. The SDO data source in SPI control mode is defined by the GENERAL_USER_CONFIG_2 and GENERAL_USER_ CONFIG_3 registers, as described in Table 26. Table 26. SPI Operation Mode in SPI Control Mode GENERAL_USER_ CONFIG_2, Bit 5 Setting 0 0 1 GENERAL_USER_ CONFIG_3, Bit 4 Setting 0 1 X Mode Internal register -∆ data conversion SAR conversion In SPI control mode, there are four different levels of I/O strength on the SDO pin, which can be selected in GENERAL_USER_ CONFIG_2, Bits[4:3], as described in Table 27. X means don’t care. DIGITAL SPI INTERFACE The SPI serial interface on the AD7779 consists of four signals: CS, SDI, SCLK and SDO. A typical connection diagram of the SPI interface is shown in Figure 100. DSP/FPGA AD7779 Notes Enable by default Precharge mode by default Disable by default All channels enable Disable by default Enable by default CS SCLK Table 27. SDO Strength GENERAL_USER_CONFIG_2, Bits[4:3] Setting 0 0 0 1 1 0 1 1 Mode Nominal Strong Weak Extra strong SCLK is the serial clock input for the device. All data transfers (on either SDO or SDI) occur with respect to this SCLK signal. SDI 13295-118 SDO Figure 100. SPI Control Interface—AD7779 is the SPI Slave, Digital Signal Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master Rev. 0 | Page 42 of 97 Data Sheet AD7779 To ensure that the register write is successful, it is recommended to read back the register and verify the checksum. The SPI interface can operate in multiples of eight bits. For example, in SPI control mode, if the SDO pin is used to read back the data from the internal register or the SAR ADC, the data frame is 16 bits wide (CRC disabled), as shown in Figure 101, or 24 bits wide (CRC enabled), as shown in Figure 102. In this case, the controller can generate one frame of 16 bits/24 bits (with and without the CRC enabled), or 2/3 frames of 8 bits (with and without the CRC enabled). When the SDO pin is used to read back the data from the -Δ channels, 64 bits must be read back from the controller (in this case, the controller can generate a frame of 64 bits—either 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits). For CRC checksum calculations, the following polynomial is always used: x8 + x2 + x + 1. See the SPI Control Mode Checksum section for more information. SPI Read/Write Register Mode (SPI Control Mode) The AD7779 has on-board registers to configure and control the device. The registers have 7-bit addresses—the 7-bit register address on the SDI line selects the register for the read/write function. The 7-bit register address follows the R/W bit in the SDI data. The 8 bits on the SDI line following the 7-bit register address are the data to be written to the selected register if the SPI is a write transfer. Data on the SDI line is clocked into the AD7779 on the rising edge of SCLK, as shown in Figure 3. SPI CRC—Checksum Protection (SPI Control Mode) The AD7779 has a checksum mode that improves SPI interface robustness in SPI control mode. Using the checksum ensures that only valid data is written to a register and allows data read from the device to be validated. The SPI CRC can be enabled by setting the SPI_CRC_TEST_EN bit. If an error occurs during a register write, the SPI_CRC_ERR is set in the error register. The data on the SDO line during the SPI transfer contains the 8-bit 0010 0000 header: 8 bits of register data in the case of a read (R) operation, or 8 zeros in the case of a write (W) operation. Enabling the SPI_CRC_TEST_EN bit results in a CRC checksum being performed on all the R/W operations. When SPI_ CRC_TEST_EN is enabled, an 8-bit CRC word is appended to every SPI transaction for SAR and register map operations. For more information on -Δ readback operations, see the CRC Header section. With the CRC disabled, the basic data frame on the SDI line during the transfer is 16 bits long, as shown in Figure 101. When the CRC is enabled, a minimum frame length of 24 SCLKs is required on SPI transfers. The 24 bits of data on the SDO line consist of an 8-bit header (0010 0000), 8 bits of data, and an 8-bit CRC (see Figure 102). CS SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 0 0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 13295-119 SCLK Figure 101. 16-Bit SPI Transfer—CRC Disabled CS SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 SDO 0 0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 Figure 102. 24-Bit SPI Transfer—CRC Enabled Rev. 0 | Page 43 of 97 13295-120 SCLK AD7779 Data Sheet SPI SAR Diagnostic Mode (SPI Control Mode) to the device, which is ignored because the SDO pin is used to shift out the content of the SAR ADC. Setting Bit 5 in the GENERAL_USER_CONFIG_2 register configures the SDO line to shift out data from the SAR ADC conversions, as described in Table 26. If consecutives conversion are performed in the SAR ADC, read back the result from the previous conversion before a new conversion is generated. Otherwise, the results are corrupted. In SAR mode, the AD7779 internal registers can be written to, but any readback command is ignored because the SDO data frame is dedicated to shift out the conversion results from the SAR ADC. -∆ Data, ADC Mode In pin control mode, the SPI interface can be used to read back the -Δ conversions as described in Table 17. In SPI control mode, the SPI interface reads back the -Δ conversions by setting GENERAL_USER_CONFIG_3, Bit 4, as described in Table 26; in this mode, the AD7779 internal register can be written to, but any readback command is ignored because the SDO data frame is dedicated to shifting out the conversion results from the -Δ ADCs. To avoid unwanted writes to the internal register, it is recommended to send a readback command, for example, 0x8000, to the device, which is ignored because the SDO pin is used to shift out the content of the -Δ ADC. To exit this mode of operation, reset Bit 5 in the GENERAL_ USER_CONFIG_2 register. The data on the SDO line during the SPI transfer contains a 4-bit 0010 header and 12 bits of the SAR conversion result if the CRC is disabled. When the CRC is enabled, a minimum frame length of 24 SCLKs is required on SPI transfers. The 24 bits of data on the SDO line consist of a 4-bit header (0010), 12 bits of data, and an 8-bit CRC, as shown in Figure 103. The SDO pin data can be read back in any multiple of 8 bits, for example, as 64 bits, 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits. Per the SPI read/write register mode (see the SPI Read/Write Register Mode section), the SDI line contains the R/W bit, a 7-bit register address, 8 bits of data, and an 8-bit CRC (if enabled). To avoid unwanted writes to the internal register while the SAR conversions are read back through the SDO line, it is recommended to send a readback command, for example, 0x8000, SPI Software Reset Keeping the SDI pin high during 64 consecutives clocks generates a software reset. CS SCLK R/W A6 A5 A4 SDO 0 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR I CRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 11 10 9 8 7 6 5 4 3 2 1 0 Figure 103. SAR ADC/Diagnostic Mode—CRC Enabled Rev. 0 | Page 44 of 97 13295-121 SDI Data Sheet AD7779 DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR The AD7779 includes self diagnostic features to guarantee the correct operation. If an error is detected, the ALERT pin is pulled high to generate an external interruption to the controller. In addition, the header of the -Δ output data contains a bit used to inform the controller of a chip error (see the ADC Conversion Output—Header and Data section). Both the ALERT pin and the bit (status header) are automatically cleared if the error is no longer present. The errors related to the SPI interface do not recover automatically; read back the appropriate register to clear the error, resetting both the ALERT pin and the bit. If an error detector is manually disabled, it does not generate an internal error and, consequently, the register map or the ALERT pin and bit are not triggered. There are different sources of errors, as described in Table 28. In pin control code, it is not possible to check the error source, and some sources of error are not enabled. In SPI control mode, check the source of an error by reading the appropriate register bit. The STATUS_REG_x register bits identify the register that generates an error, as summarized in Table 28. Table 28. Register Error Source Bit Name ERR_LOC_GEN2 ERR_LOC_GEN1 ERR_LOC_CH7 ERR_LOC_CH6 ERR_LOC_CH5 ERR_LOC_CH4 ERR_LOC_CH3 ERR_LOC_CH2 ERR_LOC_CH1 ERR_LOC_CH0 ERR_LOC_SAT_CH6_7 ERR_LOC_SAT_CH4_5 ERR_LOC_SAT_CH2_3 ERR_LOC_SAT_CH0_1 the EXT_MCLK_SWITCH_ERR bit is set in the general error register, GEN_ERR_REG_2. If EXT_MCLK_SWITCH_ERR is set, this means that the device is operating off the internal oscillator. To use a slow external clock (<265 kHz), set the CLK_QUAL_ DIS bit. Setting this bit also clears the error bit. If the external clock is between 132 kHz and 265 kHz, depending on the internal synchronization between internal oscillator and external clock, the error may not trigger. However, it is still recommended to set the CLK_QUAL_DIS bit. If a slow clock is not in use and the error triggers, a reset is required. Reset Detection The AD7779 general error register contains a RESET_DETECTED bit. This bit is asserted if a reset pulse is applied to the AD7779 and is cleared by reading the general error register. This bit indicates that the power-on reset (POR) initialized correctly on the device. In addition, this pin can be used to detect an unexpected device reset or glitch on the RESET pin. To reset this error signal in SPI control mode, toggle the SYNC_IN pin or read from the general error register, GEN_ERR_REG_2. To reset this error signal in pin control mode, toggle the SYNC_IN pin. Internal LDO Status Register Source GEN_ERR_REG_2 GEN_ERR_REG_1 CH7_ERR_REG CH6_ERR_REG CH5_ERR_REG CH4_ERR_REG CH3_ERR_REG CH2_ERR_REG CH1_ERR_REG CH0_ERR_REG CH6_7_SAT_ERR CH4_5_SAT_ERR CH2_3_SAT_ERR CH0_1_SAT_ERR The AD7779 has three internal LDOs to regulate the internal analog and digital supply rails. The LDOs have internal power supply monitors. Internal comparators monitor and flag errors with these supplies after they pass a predetermined limit. The ALDO1_PSM_ERR, ALDO2_PSM_ERR, and DLDO_PSM_ ERR bits indicate either an LDO malfunction, or, if the LDOs are bypassed, an incorrect external supply. The internal analog and digital voltage monitors can be disabled by appropriately selecting the LDO_PSM_TEST_EN bits. Use the SAR ADC to verify the error. In addition, STATUS_REG_x has a bit that indicates if any internal error bit is set. This bit clears if the error is no longer present and the register is read back. Additionally, the levels of the internal monitors can be manually triggered to check if the detector works correctly by appropriately setting the bits in the LDO_PSM_TRIP_TEST_EN register. These bits increase the comparator window threshold above the LDO outputs, forcing the comparator to trigger. ROM and MEMMAP CRC The INIT_COMPLETE bit in the STATUS_REG_3 indicates that the device is initialized correctly. This bit is not an error but an indicator. If an error is found at power-up during the ROM verification, or if the internal memory map is corrupted, the AD7779 generates an error and sets MEMMAP_CRC_ERR or ROM_ CRC_ERR, depending on the source of the error. General Errors MCLK Switch Error (SPI Control Mode) The checker can be disabled by clearing the MEMMAP_ CRC_TEST_EN and ROM_CRC_TEST_EN bits. After power-up, the AD7779 initiates a clocking handover sequence to pass clocking control to the external oscillator, or the CMOS clock. In SPI mode, if an error occurs in the handover, The device must be reset if any of these errors trigger. Rev. 0 | Page 45 of 97 AD7779 Data Sheet -∆ ADC Errors Reference Detect (SPI Control Mode) Output Saturation In SPI control mode, the AD7779 includes on-chip circuitry to detect if there is a valid reference for conversions or calibrations. If the voltage between the selected REFx+ and REFx– pins goes below 0.7 V, the AD7779 detects that it no longer has a valid reference. CHx_ERR_REF_DET can be interrogated to identify the affected channel, which clears the bit register if the error is no longer present. The voltage detector can be disable by clearing the REF_DET_TEST_EN bit. Use the -Δ ADC diagnostic or the SAR ADC to verify the error. Overvoltage and Undervoltage Events The AD7779 includes on-chip overvoltage/undervoltage circuitry on each analog input pin. When the voltage on an analog input pin goes above AVDD1x + 0.04 mV, the CHx_ ERR_AINx_OV bit is set. The error disappears if the input voltage falls below AVDD1x – 40 mV. An output saturation event can occur when gain and offset calibration causes the output from the digital filter to clip at either positive or negative full scale. The output does not wrap. Reading the CHx_ERR_OUTPUT_SAT bit clears the bit if the error corrects itself. The detection can be disabled by clearing OUTPUT_SAT_ TEST_EN bit. SPI Transmission Errors (SPI Control Mode) All SPI errors clear after reading GEN_ERR_REG_1, which contains the SPI errors. These errors are not recovered automatically and, consequently, the ALERT pin and the ALERT bit remain set until the error register is read back. CRC Checksum Error If an undervoltage event occurs (AVSSx – 40 mV), the CHx_ ERR_AINx_UV bit is set. The error disappears if the input voltage increases to AVSSx + 0.04 V. If the CRC checksum is enabled by setting the SPI_CRC_ TEST_EN bit, an error bit, SPI_CRC_ERR, is raised if the CRC message does not match the message computed by the AD7779 internal CRC block. If the CRC message does not match the internally computed message, the register is not updated. SCLK Counter The CHx_ERR_AINM_UV, CHx_ERR_AINM_OV, CHx_ERR_ AINP_UV, and CHx_ERR_AINP_OV bits can be read back to verify the affected channel input, which clears the bit register if the error is no longer present. The overvoltage and undervoltage detection can be disabled independently by clearing the AINM_ UV_TEST_EN, AINM_OV_TEST_EN, AINP_UV_TEST_EN, or AINP_OV_TEST_EN bits. If the number of clocks generated by the controller is not a multiple of 8 after CS is pulled high, an error bit, SPI_CLK_ COUNT_ERR is raised. The last command multiple of 8 is executed; however, the SCLK counter can be disabled by setting the SPI_CLK_COUNT_TEST_EN bit. The input voltage can be checked independently with the SAR ADC. When an invalid register is trying to read back, the SPI_INVALID_ READ_ERR bit is set. Modulator Saturation The invalid readback address detection can be disabled by setting the SPI_INVALID_READ_TEST_EN bit. The AD7779 includes modulator saturation detection on each of the -Δ ADCs. If 20 consecutive codes for the modulator are either all 1s or 0s, this is flagged as a modulator saturation event. Reading the CHx_ERR_MOD_SAT register clears the bit if the error corrects itself. Modulator saturation detection can be disabled by clearing the MOD_SAT_TEST_EN bit. Note that the modulator input voltage is attenuated internally, which means that a modulator output of all 1s or 0s represents a modulator that is out of bounds and that a RESET pulse is required. Filter Saturation TheAD7779 includes digital filter saturation detection on each -Δ ADC channel. This detection indicates that the filter output is out of bounds, which represents an output code approximately 20% higher than positive or negative full scale. Reading the CHx_ERR_ FILTER_SAT bit clears the bit if the error corrects itself. The detection can be disabled by clearing FILTER_SAT_TEST_ EN bit. Invalid Read Invalid Write When an invalid register is trying to write, the SPI_INVALID_ WRITE_ERR bit is set. The invalid write address detection can be disabled by setting the SPI_INVALID_WRITE_TEST_EN bit. MONITORING USING THE AD7779 SAR ADC (SPI CONTROL MODE) The AD7779 contains an on-chip SAR ADC for chip diagnostics, system diagnostics, or measurement verification. The SAR ADC has a 12-bit resolution. The AVDD4 and AVSS4 pins operate in complete independence of the -Δ ADC supplies and, therefore, can be used for chip diagnostics in systems where functional safety is important. The reference for the SAR conversion process is taken from the SAR ADC supply voltage (AVDD4/ AVSS4) and, therefore, the SAR analog input range is from AVSS4 to AVDD4. The SAR ADC has a maximum throughput rate of 256 kSPS. The CONVST_SAR pin initiates a conversion on the SAR ADC. The maximum allowable frequency of the CONVST_SAR pin is Rev. 0 | Page 46 of 97 Data Sheet AD7779 256 kHz. If consecutives conversion are performed in the SAR ADC, read back the result from the previous conversion before a new conversion is generated. Otherwise, the results are corrupted. The SAR ADC is only available in SPI control mode. To read conversion results from the SAR ADC, set the SAR_DIAG_ MODE_EN bit. After this bit is set, all data shift out from the SDO pin are from the SAR ADC register, as shown in Figure 104. The CONVST_SAR signal can be internally deglitched to avoid false triggers. Table 29. SAR Synchronization and Deglitching CONVST_ DEGLITCH_DIS 11 10 Effect on CONVST_SAR CONVST_SAR goes directly to the SAR CONVST_SAR reaches the SAR when it is 1.5 MCLK cycles wide Increase the acquisition time by 1.5/MCLK when the deglitch circuitry is enabled. Prior to the SAR ADC, the AD7779 contains an internal multiplexer. This multiplexer can be configured over the SPI interface to set the inputs to the SAR ADC to be either internal circuit nodes in the case of diagnostics or to select the external AUXAIN+ and AUXAIN− pins. Along with converting external voltages, the SAR ADC can be used to monitor the internal nodes on the AVDD, IOVDD, and DGND pins, and can monitor the DLDO and ALDO outputs. Some voltages are internally attenuated by 6, and the resulting voltage is applied to the SAR ADC, as shown in Table 30. This is useful because variations in the power supply voltage can be monitored. The input multiplexer of the SAR is controlled by the GLOBAL_ MUX_CONFIG register, and the different inputs available are described in Table 30. The SAR ADC also contains an ADC driver amplifier, as shown in Figure 105. This amplifier settles the SAR input to 12-bit accuracy within the t33 time. This driver amplifier helps minimize the kickback from the SAR converter to the global diagnostic mux input circuit nodes. the AD7779 has three available GPIO ports controlled via the SPI interface. The GPIO pins can be used to control an external, dual 8:1 multiplexer, which in turn is used to sample the eight -Δ channels. Use this diagnostic in applications where functional safety is required. This diagnostic aids in removing the need for a secondary external ADC to validate primary measurements on the -Δ channels. Temperature Sensor The internal die temperature can be measured with an error of ±2°C. DVBE is proportional to the temperature measured referred to 25°C. Temperature (°C) = DVBE 0.6 V 2 mV Table 30. SAR Mux Inputs SAR Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Positive Signal AUXAIN+ DVBE REF1+ REF2+ REF_OUT VCM AREG1CAP AREG2CAP DREGCAP AVDD1A AVDD1B AVDD2A AVDD2B IOVDD AVDD4 DGND DGND DGND AVDD4 REF1+ REF2+ AVSSx Negative Signal AUXAIN− AVSSx REF1− REF2− AVSSx AVSSx AVSSx AVSSx DGND AVSSx AVSSx AVSSx AVSSx DGND AVSSx AVSSx AVSSx AVSSx AVSSx AVSSx AVSSx AVDD4 Attenuation ÷ 6 No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No No Yes Use the auxiliary inputs, AUXAIN+ and AUXAIN−, to validate the -Δ measurements. While operating in SPI control mode, SDI SDO SET BIT 5 GENERAL_USER_CONFIG_2 REG WRITE TO ADC MUX REGISTER WRITE TO ADC MUX REGISTER ADC CONVERSION RESULT REG ADC CONVERSION RESULT REG Figure 104. Configuring the AD7779 to Operate the SPI to Read from the SAR ADC Rev. 0 | Page 47 of 97 13295-123 CS AD7779 Data Sheet AVDD4 AVSS4 DEGLITCH CONVST_SAR AUXAIN+ REF AUXAIN– MUX SAR ADC FIFO CONTROL LOGIC SPI ON-CHIP DIAGNOSTICS 13295-122 SAR DRIVER Figure 105. SAR ADC Configuration and Control Table 31. -Δ Diagnostic Input 0 1 2 3 4 5 6 7 8 9 Voltage Floating Floating 280 mV differential signal External reference, positive/negative External reference, negative/positive External reference, negative/ negative Internal reference, positive/negative Internal reference, negative/positive Internal reference, positive/ positive External reference, positive/ positive Recommended Voltage Reference Not applicable Not applicable Internal/External External External External Internal Internal Internal External Notes/Result Not applicable Not applicable PGA gain calibration Positive full scale Negative full scale Zero scale Positive Full scale Negative full scale Zero scale Zero scale Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) There are two different ways to enable the diagnostic mux: The AD7779 -Δ ADC diagnostic functions are accessible through the SPI interface. The internal mux placed before the PGA has different inputs, allowing the user to select a zero-scale, positive full-scale, or negative full-scale input to the -Δ ADC, which can be converted to verify the correct operation of the -Δ ADC channel. The diagnostic mux control signals are shared across all the -Δ channels. Depending on the diagnostic selected, connect the Δ ADC reference to a different reference source to guarantee that the conversion is within the measurable range. Setting the CHx_RX bit. This bit enables the input -Δ mux. The multiplexer inputs are described in Table 31. The reference used during the conversions are controlled by the REF_MUX_CTRL bits. Setting CHx_REF_MONITOR. This bit has the same effect as enabling the CHx_RX bit and selects the VDD1x/ AVSSx supplies as the main reference. If the AINx± pin is connected to AVSSx, the input range is outside range (AVSSx + 100 mV); therefore, results may differ slightly from the expected value. The inputs can be used alternatively to calibrate gain and offset errors. Rev. 0 | Page 48 of 97 Data Sheet AD7779 ADC CONVERSION OUTPUT—HEADER AND DATA The AD7779 -Δ conversion results are output on the DOUT0 to DOUT3 pins or over the SPI, depending on the selected interface. If the DOUTx interface is selected, the AD7770 acts as the master in the transmission. If the SPI interface is selected, the controller is the master. The DRDY signal indicates the end of conversion independently of the interface selected to read back the -Δ conversion. When the SPI is used to read back the -Δ conversion, if a new conversion is completed (DRDY falling edge) before the previous conversion is read back, the results from previous conversion are overwritten and, consequently, the previous conversion data is corrupted. For each channel, the width is 32 bits long: 8 bits for the header and 24 bits for the -Δ conversion, as shown in Figure 106. HEADER N 8-BITS ADC DATA N 13295-124 N–1 24-BITS CHANNEL NUMBER CHANNEL NUMBER In pin control mode, the header is fixed to the CRC while in SPI mode, and can be selected between CRC or error headers. CRC CRC CRC Table 32. Channel ID Channel 0 1 2 3 4 5 6 7 Channel ID 2 0 0 0 0 1 1 1 1 Channel ID 1 0 0 1 1 0 0 1 1 Channel ID 0 0 1 0 1 0 1 0 1 Table 33. 8-Bit CRC, Header Configuration (Channel 2) CE 0 1 0 The CRC header is the header generated in pin control mode or in SPI mode if DOUT_HEADER_FORMAT is set. Channel 2 Header CRC7 CRC6 CRC5 CRC4 Table 34. 8-Bit CRC, Header Configuration (Channel 3) CRC Header The chip error bit is set high if an error is detected in any channel, as explained in the General Errors section. The chip error bit remains 1 until the error disappears. CRC Figure 107. CRC Header Figure 106. ADC Output—8-Bit Header + 24-Bit Conversion Data As shown in Figure 107, the header consists of a chip error bit, three bits for the ADC channel, as shown in Table 32, and four bits for the CRC. CHANNEL NUMBER The CRC generated is eight bits long; the CRC 4 MSBs are placed on the header for the first channel in the pairing and the 4 LSBs on the header of the second channel in the pairing, as shown in Table 33. If a channel is disabled, the 24-bit output data for this channel is 0x000000. DRDY DOUTx CHIP ERROR 13295-200 -Δ OUTPUT DATA CE 0 1 Channel 3 Header 1 CRC3 CRC2 CRC1 CRC0 ERROR Header (SPI Control Mode) In SPI control mode, the default header can be replaced by an error header. If the -Δ conversion is read back through the SPI interface, disable the CRC by clearing the SPI_CRC_TEST_EN bit. If the DOUTx interface is used, clear the DOUT_HEADER_ FORMAT bit. The error header provides information of common error sources specific for each channel, as shown in Table 35. Modulator and filter errors are indicated even if the checker for this error has been specifically disabled, as described in the -Δ ADC Errors section. Table 35. Status Header Output Bits 7 Name Alert 6:4 3 2 CH_ID_[2:0] RESET_DETECTED MODULATOR_SATURATE 1 FILTER_SATURATE 0 AIN_OV_UVERROR Description This bit is set high if any of the enabled diagnostic functions have detected an error, including an external clock not detected, a memory map bit flip, or an internal CRC error. This bit is not channel specific. The bit clears if the error is no longer present. These bits indicate which ADC channel the following conversion data came from (see Table 32). This bit indicates if a reset condition occurs. This bit is not channel specific. This bit indicates that the modulator output 20 consecutive 0s or 1s. The bit resets automatically after the error is no longer present. This bit indicates that the filter output is out of bounds. The bit resets automatically after the error is no longer present. This bit indicates that there is an AINx± overvoltage/undervoltage condition on the inputs. This bit is set until the appropriate register is read back and the error is no longer present. Rev. 0 | Page 49 of 97 AD7779 Data Sheet SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) The AD7779 implements a patented featured called the SRC on each -Δ channel, which allows the user to configure the output data rate or sampling frequency to any desired value, including noninteger values. The SRC achieves fine resolution control over the -Δ ADC ODR, up to 15.2 μSPS. In applications where the ODR must change based on changes in the input signal to maintain sampling coherency, the SRC provides fine control over the ODR. For example, to achieve the highest classification standard, Class A, in power quality applications, coherency must be maintained for 0.01 Hz changes in the input power line. The SRC can be used to achieve this sampling frequency accuracy. If SRC_LOAD_SOURCE is set, the ODR update is controlled externally by the GPIO0 pin. Apply a pulse in the GPIO2 pin, which is then internally synchronized with the external MCLK clock, and the resultant synchronous signal is output on the GPIO1 pin. The GPIO1 and GPIO0 pins must be externally connected. If multiple AD7779 must be synchronized, the GPIO1 pin of one device can be connected to multiple devices. This synchronization method requires the use of a common MCLK signal for all the AD7779 devices connected, as shown in Figure 108. PULSE AD7779 GPIO2 MCLK In the pin control mode, the ODR is fixed per the predefined pin control options. Consequently, a noninteger number cannot be selected, as shown in Table 17. SYNCHRONIZATION LOGIC GPIO1 DIGITAL FILTER GPIO0 To set the ODR, the user must program up to four registers, depending on the decimation value: two registers to program the integer value, N (the effective decimation rate), and two registers to program the decimal value, IF (the inter-polation factor). AD7779 GPIO2 MCLK The integer value registers are SRC_N_MSB, Bits[3:0] and SRC_N_LSB, Bits[7:0]. The decimal part value registers are SRC_IF_MSB, Bits[7:0] and SRC_IF_LSB, Bits[7:0]. MCLK SYNCHRONIZATION LOGIC GPIO1 NC DIGITAL FILTER GPIO0 As an example, if an output data rate of 2.8 kHz is required, which equates to HP mode = 2048/2.8 = 731.428 Low power mode = 512/2.8 = 182.857 AD7779 GPIO2 MCLK The register values for HP mode are as follows: SYNCHRONIZATION LOGIC GPIO1 NC DIGITAL FILTER 731d = 0x2DB SRC_N_MSB[3:0] = 0x02 SRC_N_LSB[7:0] = 0xDB 0.428d = 0.428 × 216 = 28049d = 0x6D91 SRC_IF_MSB[7:0] = 0x6D SRC_IF_LSB[7:0] = 0x91 GPIO0 13295-125 Figure 108. Hardware ODR Update SRC Bandwidth The ODR can be updated on the fly, but a new ODR is effective in three conversion cycles of the -Δ ADCs. This guarantees a smooth transition with no conversion results out of range. There are two different ways to change the ODR after a new value is written in the SRC registers: via software or via hardware, depending on SRC_UPDATE, Bit 7. If the SRC_LOAD_SOURCE bit is clear, the new ODR value is updated by setting the SRC_LOAD_UPDATE bit to 1. This bit must be held high for at least two MLCK periods; return the bit to 0 before attempting another update. The SINC filter architecture allows the user to select a noninteger value as the decimation range This versatility means that the filter notches must be adjusted dynamically: two notches at the variable frequency, and one fixed notch to remove the PGA chopping tone. Consequently, the traditional formula for the −0.1 dB and −3 dB bandwidth must be adjusted depending on the selected decimation rate. The bandwidth transfer function is not linear but can be approximated by using a linear function. Rev. 0 | Page 50 of 97 Data Sheet AD7779 Figure 109 and Figure 110 show the correction factor for the −0.1 dB and −3 dB bandwidth, respectively. In low power mode, the offset must be divided by 4. For example, when the ODR = 1000, the −0.1 dB point is SRC Group Delay The SRC group delay depends on the selected ODR and the power mode, and is defined by the following equation: Group delay = BW = 0.0581 × 1000 + 2 .9271 = 59 Hz 4 1000 –0.1dB FREQUENCY (Hz) 800 700 600 y = 0.0581x + 2.9271 Settling Time 500 The settling time is defined by the contribution of all the internal stages, the filter delay, and the block calibration. 400 300 The filter delay is defined as 3/ODR. In some extreme cases, as when an external pulse is applied, this value may increase to 4/ODR. 200 0 2 4 6 8 10 ODR (kHz) 12 14 16 18 13295-126 100 Figure 109. −0.1 dB Correction Factor tMCLK is the modulator period and is 488 ns in high resolution mode and 1.9 μs in low power mode. 5 4 DATA OUTPUT INTERFACE y = 0.3135x + 13.99 3 2 1 1 3 5 7 9 11 ODR (kHz) 13 Figure 110. −3 dB Correction Factor 15 17 13295-127 –3dB FREQUENCY (kHz) In high resolution mode, the calibration delay is defined as 62 × tMCLK, with a maximum error of 2 × tMCLK. In low power mode, the calibration delay is defined as 121 × tMCLK, with a maximum error of 4 × tMCLK. 6 0 SRC _ N ODR where: PM is a value that depends on the power mode, either 64 for high resolution mode or 32 for low power mode. SRC_N is the integer value of the programmed ODR. ODR is the programmed output data rate. 900 0 PM SRC _ N The -Δ output data interface is defined by theCONV_SAR, FORMAT0, and FORMAT1 pins in pin control mode at power-up. The FORMATx pins cannot be changed dynamically. Table 18 shows the available options for pin control mode. If the device is configured in SPI control mode, the SPI_SLAVE_MODE_ EN bit enables the SPI interface to transmit the -Δ ADC conversion results, as shown in Table 26. DOUT3 to DOUT0 Data Interface Standalone Mode In standalone mode, the AD7779 interface acts as a master. There are three different DOUT configurations, configurable through the FORMATx pins in pin control mode, as shown in Figure 111 through Figure 113, or via the DOUT_FORMAT bits, Bits[7:6], in SPI control mode, as described in Table 36. Figure 114, Figure 115, and Figure 116 show the expected data outputs for different DOUTx output modes. Rev. 0 | Page 51 of 97 AD7779 Data Sheet Table 36. DOUTx Channels DOUT_FORMAT Bits/ FORMATx Pins 00 Number of DOUTx Lines Enabled 4 01 2 10 1 Associated Channels DOUT0—Channel 0 and Channel 1 DOUT1—Channel 2 and Channel 3 DOUT2—Channel 4 and Channel 5 DOUT3—Channel 6 and Channel 7 DOUT0—Channel 0, Channel 1, Channel 2, and Channel 3 DOUT1—Channel 4, Channel 5, Channel 6, and Channel 7 DOUT0—Channel 0, Channel 1, Channel 2, Channel 3, Channel 4, Channel 5, Channel 6, and Channel 7 AD7779 DRDY DCLK FORMAT0 FORMAT1 CH 1 0 CH 3 0 CH 5 CH 7 DGND DOUT0 CH 0 CH 1 DOUT1 CH 0 CH 1 DOUT2 CH 0 CH 1 DOUT3 CH 0 CH 1 13295-128 00 DOUT0: CH 0, DOUT1: CH 2, DOUT2: CH 4, DOUT3: CH 6, DAISY-CHAINING IS NOT POSSIBLE IN THIS FORMAT Figure 111. FORMATx Pin Configuration—FORMAT0 = 0, FORMAT1 = 0 AD7779 DRDY DCLK IOVDD CH 0, CH 1, CH 2, CH 3 OUTPUT ON DOUT0 CH 4, CH 5, CH 6, CH 7 OUTPUT ON DOUT1 DOUT0 CH 0 CH 1 CH 2 CH 3 FORMAT0 FORMAT1 1 0 DOUT1 CH 4 CH 5 CH 6 CH 7 DGND DAISY-CHAINING IS POSSIBLE IN THIS FORMAT 13295-129 01 Figure 112. FORMATx Pin Configuration—FORMAT0 = 1, FORMAT1 = 0 AD7779 DRDY DCLK DGND 10 FORMAT0 FORMAT1 0 1 DOUT0 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 IOVDD DAISY-CHAINING IS POSSIBLE IN THIS FORMAT Figure 113. FORMATx Pin Configuration—FORMAT0 = 0, FORMAT1 = 1 Rev. 0 | Page 52 of 97 13295-130 CH 0 TO CH 7 OUTPUT ON DOUT0 Data Sheet AD7779 DCLK SAMPLE N SAMPLE N + 1 DOUT0 CH0-S0 CH1-S0 CH0-S1 CH1-S1 DOUT1 CH2-S0 CH3-S0 CH2-S1 CH3-S1 DOUT0 CH4-S0 CH5-S0 CH4-S1 CH5-S1 DOUT1 CH6-S0 CH7-S0 CH6-S1 CH7-S1 13295-131 DRDY Figure 114. FORMAT0 = 0, FORMAT1 = 0—Each DOUTx Outputs Two ADC Conversions (S0 Means Sample 0 and S1 Means Sample 1) DCLK SAMPLE N SAMPLE N + 1 DRDY DOUT0 CH0-S0 CH1-S0 CH2-S0 CH3-S0 CH0-S1 CH1-S1 CH2-S1 CH3-S1 DOUT1 CH4-S0 CH5-S0 CH6-S0 CH7-S0 CH4-S1 CH5-S1 CH6-S1 CH7-S1 13295-132 DOUT2 DOUT3 Figure 115. FORMAT0 = 0, FORMAT1 = 1—Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1 (S0 Means Sample 0 and S1 Means Sample 1) DCLK SAMPLE N SAMPLE N + 1 SAMPLE N + 2 DRDY DOUT0 CH0-S0 CH1-S0 CH2-S0 CH...-S0 CH6-S0 CH7-S0 CH0-S1 CH1-S1 CH2-S1 CH...-S1 CH6-S1 CH7-S2 CH0-S2 CH1-S2 CH2-S2 CH...-S2 CH6-S2 CH7-S2 CH0-S3 DOUT1 13295-133 DOUT2 DOUT3 Figure 116. FORMAT0 = 1, FORMAT1 = 0—Channel 0 to Channel 7 Output on DOUT0 Only (S0 Means Sample 0 and S1 Means Sample 1) Rev. 0 | Page 53 of 97 AD7779 Data Sheet Digital Reset and Synchronization Pins section for more information. Daisy-Chain Mode Daisy-chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple ADCs from separate AD7779 devices. In daisy-chain configuration, only one device has direct connection between the DOUTx interface and the digital host. For the AD7779, daisychain capability is implemented by cascading DOUT0 and DOUT1 through a number of devices, or by just using DOUT0 (this depends on the selected DOUTx mode). The ability to daisy chain devices and the limit on the number of devices that can be handled by the chain is dependent on the selected DOUTx mode and the decimation rate employed. This feature is especially useful for reducing the component count and wiring connections in, for example, isolated multiconverter applications or for systems with a limited interfacing capacity. For daisy-chain operation, there are two different configurations possible, as described in Table 37. Using the DOUTx = 10 mode DOUT2 acts as input pins, as shown in Figure 117. In this case, the DOUT0 pin of the AD7779 devices is cascaded to the DOUT2 pin of the next device in the chain. Data readback is analogous to clocking a shift register where data is clocked on the rising edge of DCLK. When operating in daisy-chain mode, it is required that all AD7779 devices in the chain are correctly synchronized. See the Table 37. DOUTx Modes in Daisy-Chain Operation DOUT_FORMAT Bits/ FORMATx Pins 01 Number of DOUTx Lines Enabled 2 10 1 Associated Channels DOUT0—Channel 0 to Channel 3 and DOUT2 DOUT1—Channel 4 to Channel 7 and DOUT3 DOUT2—input channel DOUT3—input channel DOUT0—Channel 0 to Channel 7 and DOUT2 DOUT2—Input Channel U2 U2 DOUT2/DIN0 DOUT0 DOUT2/DIN0 DOUT0 DCLK DRDY U2 DOUT0 U1 DOUT2/DIN0 U1 DOUT0 0 0 0 0 0 U2 S0 CH0 TO CH7 0 U2 S1 CH0 TO CH7 0 U2 S0 CH0 TO CH7 U2 S0 CH0 TO CH7 U2 S0 CH0 TO CH7 U2 S1 CH0 TO CH7 U2 S1 CH0 TO CH7 U2 S0 CH0 TO CH7 U1 S0 CH0 TO CH7 U1 S0 CH0 TO CH7 U1 S1 CH0 TO CH7 U2 S3 CH0 TO CH7 U1 S1 CH0 TO CH7 13295-134 U2 DOUT2/DIN0 Figure 117. Daisy-Chain Connection Mode, FORMAT0 = 1, FORMAT1 = 0 (S0 Means Sample 0 and S1 Means Sample 1); When Connected in Daisy-Chain Mode, DOUT2 Acts as an Input Pin, Represented by DIN0 Rev. 0 | Page 54 of 97 Data Sheet AD7779 Minimum DCLKx Frequency Select the DCLKx frequency ratio in such a way that the data is completely shifted out before a new conversion is completed, otherwise the previous conversion is overwritten and the transmission becomes corrupt. The minimum DCLKx frequency ratio is defined by the decimation rate, the operation mode, and the lines enabled on the DOUT3 to DOUT0 data interface as described in the following equations: In standalone mode, High Resolution Mode − DCLKMIN_RATIO < Decimation/ (8 × CHANNELS_PER_DOUT ) Low Power Mode − DCLKMIN_RATIO < Decimation/ (4 × CHANNELS_PER_DOUT) In daisy-chain mode, There are maximum achievable ODRs and minimum DCLKx frequencies required for a given DOUTx pin configuration, as shown in Table 39 and Table 40. Table 39. Maximum ODRs and Minimum DCLKx Frequencies in High Resolution Mode Decimation Rate 4095 2048 1024 512 256 128 ODR (kSPS) 0.500122 1 2 4 8 16 Minimum DCLKx (kHz) 1 DOUTx 2 DOUTx 4 DOUTx 128 64 32 256 128 64 512 256 128 1024 512 256 2048 1024 512 4096 2048 1024 Table 40. Maximum ODRs and Minimum DCLK Frequencies in Low Power Mode High Resolution Mode − DCLKMIN_RATIO< Decimation/ (8 × Devices × DOUTx Channels) Low Power Mode − DCLKMIN_RATIO< Decimation/ (4 × Devices × DOUTx Channels) As an example, when operating in master interface mode, DOUTx = 01, the DOUT0 and DOUT1 pins shift out four Σ-Δ channels each and, assuming a maximum output rate in high resolution mode, the decimation = 128. DCLKMIN < 128/ (8 × 4) = 4 If the DCLKMIN_RATIO is selected above the necessary minimum, a Logic 0 is continuously transmitted until a new sample is available. An example in daisy-chain mode, assuming DOUTx = 01, and with three devices connected and a decimation rate of 256 in high resolution mode, is as follows: DCLKMIN_RATIO < 256/(8 × 3 × 4) = 2.66 = 2 Decimation Rate 2048 1024 512 256 128 ODR (kSPS) 0.25 0.5 1 2 4 Minimum DCLK (kHz) 1 DOUT 2 DOUT 4 DOUT 64 32 16 128 64 32 256 128 64 512 256 128 1024 512 256 If the AD7779 operates in SPI control mode, it is possible to adjust the DOUTx strength, which can be selected in the DOUT_DRIVE_STR bits, as described in Table 41. Table 41. DOUTx Strength 0 0 1 1 GENERAL_USER_CONFIG2, Bits[2:1] 0 1 0 1 Mode Nominal Strong Weak Extra strong The different ratios are summarized in Table 38. SPI Interface Table 38. Available DCLK Ratios DCLK_CLK_DIV (SPI Control Mode), DCLKx (Pin Control Mode) 000 001 010 011 100 101 110 111 DCLKx Ratio 1 2 4 8 16 32 64 128 The SPI interfaces gives the user flexibility to read the conversion from the -Δ ADC where the processor or microcontroller is the master. When a new conversion is completed, the DRDY signal is toggled to indicate that data can be accessed. When DRDY toggles, the internal channel counter is reset and the next SPI read is from Channel 0 again. Conversely, after the last channel data is read, all succeding reads before the next DRDY signal are from Channel 7 (LSB). Rev. 0 | Page 55 of 97 Data Sheet CS SDO CH0_HEADER _+_CH0_8_BITS_MSB CH0_16_BITS_LSB 13295-135 AD7779 CS SDO CH0_HEADER _+_CH0_16_BITS_MSB CH0_8_BITS_LSB_+_CH1_HEADER_+CH1_8_BITS_MSB 13295-136 Figure 118. SPI Readback, 16 Bits per Frame Figure 119. SPI Readback, 24 Bits per Frame The SPI operates in multiples of 8 bits per frame; Figure 118 shows a readback example in 16 bits per frames, whereas Figure 119 shows a readback in 24 bits per frame. Note that if the device is configured in SPI control mode, the AD7779 generates a software reset if the SDI pin is sampled high for 64 consecutive clocks. To avoid a reset or unwanted register writes, it is recommended to transfer a 0x8000 command, which generates a readback command that is ignored by the device, as explained in the SPI Software Reset section. CALCULATING THE CRC CHECKSUM The AD7779 implements two different CRC checksum generators, one for the -Δ results and another for the SPI control mode. The AD7779 uses a CRC polynomial to calculate the CRC checksum value. The 8-bit CRC polynomial used is x8 + x2 + x + 1. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An XOR (exclusive OR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum. As an example of CRC calculation for 12-bit data is shown in Table 42. Table 42. Example CRC Calculation for 12-Bit Data1 Data Polynomial CRC 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 0 -∆ CRC Checksum The CRC message is calculated internally by the AD7779 on ADC pairs. The CRC is calculated using the ADC output data from two ADCs and Bits[7:4] from the header. Therefore, 56 bits are used to calculate the 8-bit CRC. This CRC is split between the two channel headers. The CRC data covers channel pairings as follows: Channel 0 and Channel 1, Channel 2 and Channel 3, Channel 4 and Channel 5, Channel 6 and Channel 7. To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 1s. The CRC is calculated from 56 bits across two consecutive/ channel pairings (Channel 0 and Channel 1, Channel 2 and Channel 3, Channel 4 and Channel 5, Channel 6 and Channel 7). The 56 bits consist of the chip error, the 3 bits for the first ADC pairing channel, and the 24 bits of data of each pairing channel. For example, for the second channel pairing, Channel 2 and Channel 3, 56 bits = chip error + 3 ADC channel bits (010) + 24 data bits (Channel 2) + chip error + 3 ADC channel bits (011) + 24 data bits (Channel 3) SPI Control Mode Checksum The CRC message is calculated internally by the AD7779. The data transferred to the AD7779 uses the R/W bit, a 7-bit address, and 8 bits of data for the CRC calculation. The CRC calculated and appended to the data that it is shifted out uses a 0010 0000 header and 8 bits of data for the register readback, as well as the 0010 header and 12 bits of SAR conversion data for the SAR readback transfers. This table represents the division of the data; blank cells are for formatting purposes. Rev. 0 | Page 56 of 97 Data Sheet AD7779 REGISTER SUMMARY Table 43. AD7779 Register Summary Reg. 0x000 Name CH0_CONFIG Bits [7:0] 0x001 CH1_CONFIG [7:0] CH1_GAIN 0x002 CH2_CONFIG [7:0] CH2_GAIN 0x003 CH3_CONFIG [7:0] CH3_GAIN 0x004 CH4_CONFIG [7:0] CH4_GAIN 0x005 CH5_CONFIG [7:0] CH5_GAIN 0x006 CH6_CONFIG [7:0] CH6_GAIN 0x007 CH7_CONFIG [7:0] CH7_GAIN 0x008 CH_DISABLE [7:0] 0x009 CH0_SYNC_ OFFSET CH1_SYNC_ OFFSET CH2_SYNC_ OFFSET CH3_SYNC_ OFFSET CH4_SYNC_ OFFSET CH5_SYNC_ OFFSET CH6_SYNC_ OFFSET CH7_SYNC_ OFFSET GENERAL_ USER_ CONFIG_1 [7:0] GENERAL_ USER_ CONFIG_2 GENERAL_ USER_ CONFIG_3 DOUT_FORMA T [7:0] ADC_MUX_ CONFIG GLOBAL_MUX_ CONFIG GPIO_CONFIG GPIO_DATA BUFFER_ CONFIG_1 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 0x01A BUFFER_ CONFIG_2 Bit 7 Bit 6 CH0_GAIN CH7_ DISABLE CH6_ DISABLE Bit 5 CH0_REF_ MONITOR CH1_REF_ MONITOR CH2_REF_ MONITOR CH3_REF_ MONITOR CH4_REF_ MONITOR CH5_REF_ MONITOR CH6_REF_ MONITOR CH7_REF_ MONITOR CH5_DISABLE Bit 4 CH0_RX Bit 3 Bit 2 Bit 1 RESERVED Bit 0 Reset 0x00 R/W /W R CH1_RX RESERVED 0x00 R/W CH2_RX RESERVED 0x00 R/W CH3_RX RESERVED 0x00 R/W CH4_RX RESERVED 0x00 R/W CH5_RX RESERVED 0x00 R/W CH6_RX RESERVED 0x00 R/W CH7_RX RESERVED 0x00 R/W 0x00 R/W 0x00 R/W CH4_DISABLE CH3_ DISABLE CH0_SYNC_OFFSET CH2_ DISABLE CH1_ DISABLE CH0_ DISABLE [7:0] CH1_SYNC_OFFSET 0x00 R/W [7:0] CH2_SYNC_OFFSET 0x00 R/W [7:0] CH3_SYNC_OFFSET 0x00 R/W [7:0] CH4_SYNC_OFFSET 0x00 R/W [7:0] CH5_SYNC_OFFSET 0x00 R/W [7:0] CH6_SYNC_OFFSET 0x00 R/W [7:0] CH7_SYNC_OFFSET 0x00 R/W 0x24 R/W SPI_SYNC 0x09 R/W [7:0] POWERALL_ CH_DIS_ MODE MCLK_ EN RESERVED PDB_VCM PDB_ REFOUT_ BUF SAR_DIAG_ MODE_EN PDB_ SAR SDO_DRIVE_STR PDB_ RC_OSC SOFT_RESET DOUT_DRIVE_STR [7:0] CONVST_ DEGLITCH_DIS RESERVED SPI_SLAVE_ MODE_EN RESERVED CLK_ QUAL_DIS 0x80 R/W [7:0] DOUT_FORMAT DOUT_ HEADER_ FORMAT RESERVED DCLK_CLK_DIV RESERVED 0x20 R/W [7:0] REF_MUX_CTRL 0x00 R/W RESERVED 0x00 R/W GPIO_OP_EN GPIO_WRITE_DATA RESERVED 0x00 0x00 0x38 R/W R/W R/W 0xC0 R/W [7:0] [7:0] [7:0] [7:0] [7:0] MTR_MUX_CTRL RESERVED GLOBAL_MUX_CTRL RESERVED RESERVED REFBUFP_ PREQ REFBUFN_ PREQ RESERVED GPIO_READ_DATA REF_BUF_ POS_EN RESERVED Rev. 0 | Page 57 of 97 REF_ BUF_ NEG_EN PDB_ALDO 1_OVRDRV PDB_ ALDO2_ OVRDRV PDB_ DLDO_ OVRDRV AD7779 Reg. 0x01C 0x01D 0x01E 0x01F 0x020 0x021 0x022 0x023 0x024 0x025 0x026 0x027 0x028 0x029 0x02A 0x02B 0x02C 0x02D 0x02E 0x02F 0x030 0x031 0x032 0x033 0x034 0x035 0x036 0x037 0x038 0x039 0x03A Name CH0_OFFSET_ UPPER_BYTE CH0_OFFSET_ MID_BYTE CH0_OFFSET_ LOWER_BYTE CH0_GAIN_ UPPER_BYTE CH0_GAIN_ MID_BYTE CH0_GAIN_ LOWER_BYTE CH1_OFFSET_ UPPER_BYTE CH1_OFFSET_ MID_BYTE CH1_OFFSET_ LOWER_BYTE CH1_GAIN_ UPPER_BYTE CH1_GAIN_ MID_BYTE CH1_GAIN_ LOWER_BYTE CH2_OFFSET_ UPPER_BYTE CH2_OFFSET_ MID_BYTE CH2_OFFSET_ LOWER_BYTE CH2_GAIN_ UPPER_BYTE CH2_GAIN_ MID_BYTE CH2_GAIN_ LOWER_BYTE CH3_OFFSET_ UPPER_BYTE CH3_OFFSET_ MID_BYTE CH3_OFFSET_ LOWER_BYTE CH3_GAIN_ UPPER_BYTE CH3_GAIN_ MID_BYTE CH3_GAIN_ LOWER_BYTE CH4_OFFSET_ UPPER_BYTE CH4_OFFSET_ MID_BYTE CH4_OFFSET_ LOWER_BYTE CH4_GAIN_ UPPER_BYTE CH4_GAIN_ MID_BYTE CH4_GAIN_ LOWER_BYTE CH5_OFFSET_ UPPER_BYTE Data Sheet Bits [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CH0_OFFSET_ALL[23:16] Bit 1 Bit 0 Reset 0x00 R/W R/W [7:0] CH0_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH0_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH0_GAIN_ALL[23:16] 0x00 R/W [7:0] CH0_GAIN_ALL[15:8] 0x00 R/W [7:0] CH0_GAIN_ALL[7:0] 0x00 R/W [7:0] CH1_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH1_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH1_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH1_GAIN_ALL[23:16] 0x00 R/W [7:0] CH1_GAIN_ALL[15:8] 0x00 R/W [7:0] CH1_GAIN_ALL[7:0] 0x00 R/W [7:0] CH2_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH2_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH2_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH2_GAIN_ALL[23:16] 0x00 R/W [7:0] CH2_GAIN_ALL[15:8] 0x00 R/W [7:0] CH2_GAIN_ALL[7:0] 0x00 R/W [7:0] CH3_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH3_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH3_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH3_GAIN_ALL[23:16] 0x00 R/W [7:0] CH3_GAIN_ALL[15:8] 0x00 R/W [7:0] CH3_GAIN_ALL[7:0] 0x00 R/W [7:0] CH4_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH4_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH4_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH4_GAIN_ALL[23:16] 0x00 R/W [7:0] CH4_GAIN_ALL[15:8] 0x00 R/W [7:0] CH4_GAIN_ALL[7:0] 0x00 R/W [7:0] CH5_OFFSET_ALL[23:16] 0x00 R/W Rev. 0 | Page 58 of 97 Data Sheet Reg. 0x03B AD7779 Bits [7:0] 0x04C Name CH5_OFFSET_ MID_BYTE CH5_OFFSET_ LOWER_BYTE CH5_GAIN_ UPPER_BYTE CH5_GAIN_ MID_BYTE CH5_GAIN_ LOWER_BYTE CH6_OFFSET_ UPPER_BYTE CH6_OFFSET_ MID_BYTE CH6_OFFSET_ LOWER_BYTE CH6_GAIN_ UPPER_BYTE CH6_GAIN_ MID_BYTE CH6_GAIN_ LOWER_BYTE CH7_OFFSET_ UPPER_BYTE CH7_OFFSET_ MID_BYTE CH7_OFFSET_ LOWER_BYTE CH7_GAIN_ UPPER_BYTE CH7_GAIN_ MID_BYTE CH7_GAIN_ LOWER_BYTE CH0_ERR_REG [7:0] RESERVED CH0_ERR_ AINM_UV 0x04D CH1_ERR_REG [7:0] RESERVED CH1_ERR_ AINM_UV 0x04E CH2_ERR_REG [7:0] RESERVED CH2_ERR_ AINM_UV 0x04F CH3_ERR_REG [7:0] RESERVED CH3_ERR_ AINM_UV 0x050 CH4_ERR_REG [7:0] RESERVED CH4_ERR_ AINM_UV 0x051 CH5_ERR_REG [7:0] RESERVED CH5_ERR_ AINM_UV 0x052 CH6_ERR_REG [7:0] RESERVED CH6_ERR_ AINM_UV 0x03C 0x03D 0x03E 0x03F 0x040 0x041 0x042 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04A 0x04B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CH5_OFFSET_ALL[15:8] Bit 2 Bit 1 Bit 0 Reset 0x00 R/W R/W [7:0] CH5_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH5_GAIN_ALL[23:16] 0x00 R/W [7:0] CH5_GAIN_ALL[15:8] 0x00 R/W [7:0] CH5_GAIN_ALL[7:0] 0x00 R/W [7:0] CH6_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH6_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH6_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH6_GAIN_ALL[23:16] 0x00 R/W [7:0] CH6_GAIN_ALL[15:8] 0x00 R/W [7:0] CH6_GAIN_ALL[7:0] 0x00 R/W [7:0] CH7_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH7_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH7_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH7_GAIN_ALL[23:16] 0x00 R/W [7:0] CH7_GAIN_ALL[15:8] 0x00 R/W [7:0] CH7_GAIN_ALL[7:0] 0x00 R/W Rev. 0 | Page 59 of 97 CH0_ ERR_ AINM_ OV CH1_ ERR_ AINM_ OV CH2_ ERR_ AINM_ OV CH3_ ERR_ AINM_ OV CH4_ER R_ AINM_O V CH5_ ERR_ AINM_ OV CH6_ ERR_ AINM_ OV CH0_ ERR_AINP_ UV CH0_ERR_ AINP_OV CH0_ERR_ REF_DET 0x00 R CH1_ ERR_AINP_ UV CH1_ERR_ AINP_OV CH1_ERR_ REF_DET 0x00 R CH2_ ERR_AINP_ UV CH2_ERR_ AINP_OV CH2_ERR_ REF_DET 0x00 R CH3_ ERR_AINP_ UV CH3_ERR_ AINP_OV CH3_ERR_ REF_DET 0x00 R CH4_ ERR_AINP_ UV CH4_ERR_A INP_OV CH4_ERR_ REF_DET 0x00 R CH5_ ERR_AINP_ UV CH5_ERR_ AINP_OV CH5_ERR_ REF_DET 0x00 R CH6_ ERR_AINP_ UV CH6_ERR_ AINP_OV CH6_ERR_ REF_DET 0x00 R AD7779 Data Sheet Reg. 0x053 Name CH7_ERR_REG Bits [7:0] 0x054 CH0_1_SAT_ ERR [7:0] RESERVED CH1_ERR_ MOD_SAT CH1_ERR_ FILTER_SAT 0x055 CH2_3_SAT_ ERR [7:0] RESERVED CH3_ERR_ MOD_SAT CH3_ERR_ FILTER_SAT 0x056 CH4_5_SAT_ ERR [7:0] RESERVED CH5_ERR_ MOD_SAT CH5_ERR_ FILTER_SAT 0x057 CH6_7_SAT_ ERR [7:0] RESERVED CH7_ERR_ MOD_SAT CH7_ERR_ FILTER_SAT 0x058 CHX_ERR_ REG_EN [7:0] MOD_SAT_ TEST_EN AINM_UV_ TEST_EN 0x059 GEN_ERR_ REG_1 [7:0] OUTPUT_ FILTER_ SAT_ SAT_ TEST_EN TEST_ EN RESERVED MEMMAP_ CRC_ERR ROM_CRC_ ERR 0x05A GEN_ERR_ REG_1_EN [7:0] RESERVED MEMMAP_ CRC_TEST_EN ROM_CRC_ TEST_EN 0x05B [7:0] RESERVED [7:0] RESERVED [7:0] RESERVED RESET_ DETECTED RESET_ DETECT_EN CHIP_ERROR EXT_MCLK_ SWITCH_ERR RESERVED 0x05D GEN_ERR_ REG_2 GEN_ERR_ REG_2_EN STATUS_REG_1 0x05E STATUS_REG_2 [7:0] RESERVED CHIP_ERROR ERR_LOC_ GEN2 0x05F STATUS_REG_3 [7:0] RESERVED CHIP_ERROR INIT_ COMPLETE 0x060 0x061 0x062 0x063 0x064 SRC_N_MSB SRC_N_LSB SRC_IF_MSB SRC_IF_LSB SRC_UPDATE [7:0] [7:0] [7:0] [7:0] [7:0] 0x05C Bit 7 Bit 6 Bit 5 RESERVED Bit 4 CH7_ERR_ AINM_UV ERR_LOC_ CH4 Bit 3 CH7_ ERR_ AINM_ OV CH1_ ERR_ OUTPUT_ SAT CH3_ ERR_ OUTPUT_ SAT CH5_ ERR_ OUTPUT_ SAT CH7_ ERR_ OUTPUT_ SAT AINM_ OV_ TEST_EN Bit 1 CH7_ERR_ AINP_OV Bit 0 CH7_ERR_ REF_DET Reset 0x00 R/W R CH0_ERR_ MOD_SAT CH0_ERR_ FILTER_SAT CH0_ERR_ OUTPUT_ SAT 0x00 R CH2_ERR_ MOD_SAT CH2_ERR_ FILTER_SAT CH2_ERR_ OUTPUT_ SAT 0x00 R CH4_ERR_ MOD_SAT CH4_ERR_ FILTER_SAT CH4_ERR_ OUTPUT_ SAT 0x00 R CH6_ERR_ MOD_SAT CH6_ERR_ FILTER_SAT CH6_ERR_ OUTPUT_ SAT 0x00 R AINP_UV_ TEST_EN AINP_OV_ TEST_EN REF_DET_ TEST_EN 0xFE R/W SPI_ INVALID_ WRITE_ERR SPI_CRC_ ERR 0x00 R SPI_CRC_ SPI_ TEST_EN INVALID_ WRITE_ TEST_EN ALDO2_ DLDO_ PSM_ERR PSM_ERR LDO_PSM_TRIP_TEST_EN 0x3E R/W 0x00 R 0x3C R/W ERR_ LOC_CH2 ERR_LOC_ CH1 ERR_LOC_ CH0 0x00 R ERR_ LOC_CH7 ERR_LOC_ CH6 ERR_LOC_ CH5 0x00 R ERR_ LOC_SAT_ CH4_5 ERR_ LOC_SAT_ CH2_3 ERR_LOC_ 0x00 SAT_CH0_1 R SPI_ SPI_ INVALID_ CLK_ COUNT_ READ_ERR ERR SPI_ SPI_ INVALID_ CLK_ COUNT_ READ_ TEST_EN TEST_EN REALDO1_ SERVED PSM_ERR LDO_PSM_TEST_EN ERR_ LOC_ CH3 ERR_ LOC_ GEN1 ERR_ LOC_ SAT_ CH6_7 RESERVED SRC_ LOAD_ SOURCE Bit 2 CH7_ ERR_ AINP_UV SRC_N_ALL[11:8] SRC_N_ALL[7:0] SRC_IF_ALL[15:8] SRC_IF_ALL[7:0] RESERVED Rev. 0 | Page 60 of 97 SRC_ LOAD_ UPDATE 0x00 0x80 0x00 0x00 0x00 R/W R/W R/W R/W R/W Data Sheet AD7779 REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER Address: 0x000, Reset: 0x00, Name: CH0_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH0_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH0_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH0_RX (R/W) Channel Meter Mux RX Mode Table 44. Bit Descriptions for CH0_CONFIG Bits Bit Name [7:6] CH0_GAIN Settings Description Reset Access AFE Gain 0x0 R/W 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH0_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH0_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Description Reset Access AFE Gain 0x0 R/W CHANNEL 1 CONFIGURATION REGISTER Address: 0x001, Reset: 0x00, Name: CH1_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH1_GAIN (R/W) AFE Gain 00: Gain = 1. 01: Gain = 2. 10: Gain = 4. 11: Gain = 8. [2:0] RESERVED [3] RESERVED [5] CH1_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH1_RX (R/W) Channel Meter Mux RX Mode Table 45. Bit Descriptions for CH1_CONFIG Bits Bit Name [7:6] CH1_GAIN Settings 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH1_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH1_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Rev. 0 | Page 61 of 97 AD7779 Data Sheet CHANNEL 2 CONFIGURATION REGISTER Address: 0x002, Reset: 0x00, Name: CH2_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH2_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH2_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH2_RX (R/W) Channel Meter Mux RX Mode Table 46. Bit Descriptions for CH2_CONFIG Bits Bit Name [7:6] CH2_GAIN Settings Description Reset Access AFE Gain 0x0 R/W 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH2_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH2_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Description Reset Access AFE Gain 0x0 R/W CHANNEL 3 CONFIGURATION REGISTER Address: 0x003, Reset: 0x00, Name: CH3_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH3_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH3_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH3_RX (R/W) Channel Meter Mux RX Mode Table 47. Bit Descriptions for CH3_CONFIG Bits Bit Name [7:6] CH3_GAIN Settings 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH3_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH3_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Rev. 0 | Page 62 of 97 Data Sheet AD7779 CHANNEL 4 CONFIGURATION REGISTER Address: 0x004, Reset: 0x00, Name: CH4_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH4_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH4_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH4_RX (R/W) Channel Meter Mux RX Mode Table 48. Bit Descriptions for CH4_CONFIG Bits Bit Name [7:6] CH4_GAIN Settings Description Reset Access AFE Gain 0x0 R/W 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH4_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH4_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Description Reset Access AFE Gain 0x0 R/W CHANNEL 5 CONFIGURATION REGISTER Address: 0x005, Reset: 0x00, Name: CH5_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH5_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH5_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH5_RX (R/W) Channel Meter Mux RX Mode Table 49. Bit Descriptions for CH5_CONFIG Bits Bit Name [7:6] CH5_GAIN Settings 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH5_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH5_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Rev. 0 | Page 63 of 97 AD7779 Data Sheet CHANNEL 6 CONFIGURATION REGISTER Address: 0x006, Reset: 0x00, Name: CH6_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH6_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH6_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH6_RX (R/W) Channel Meter Mux RX Mode Table 50. Bit Descriptions for CH6_CONFIG Bits Bit Name [7:6] CH6_GAIN Settings Description Reset Access AFE Gain 0x0 R/W 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH6_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH6_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Description Reset Access AFE Gain 0x0 R/W CHANNEL 7 CONFIGURATION REGISTER Address: 0x007, Reset: 0x00, Name: CH7_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH7_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH7_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH7_RX (R/W) Channel Meter Mux RX Mode Table 51. Bit Descriptions for CH7_CONFIG Bits Bit Name [7:6] CH7_GAIN Settings 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 8 5 CH7_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH7_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W Rev. 0 | Page 64 of 97 Data Sheet AD7779 DISABLE CLOCKS TO ADC CHANNEL REGISTER Address: 0x008, Reset: 0x00, Name: CH_DISABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH7_DISABLE (R/W) Channel 7 Disable [0] CH0_DISABLE (R/W) Channel 0 Disable [6] CH6_DISABLE (R/W) Channel 6 Disable [1] CH1_DISABLE (R/W) Channel 1 Disable [5] CH5_DISABLE (R/W) Channel 5 Disable [2] CH2_DISABLE (R/W) Channel 2 Disable [4] CH4_DISABLE (R/W) Channel 4 Disable [3] CH3_DISABLE (R/W) Channel 3 Disable Table 52. Bit descriptions for CH_DISABLE Bits Bit Name 7 Settings Description Reset Access CH7_DISABLE Channel 7 Disable 0x0 R/W 6 CH6_DISABLE Channel 6 Disable 0x0 R/W 5 CH5_DISABLE Channel 5 Disable 0x0 R/W 4 CH4_DISABLE Channel 4 Disable 0x0 R/W 3 CH3_DISABLE Channel 3 Disable 0x0 R/W 2 CH2_DISABLE Channel 2 Disable 0x0 R/W 1 CH1_DISABLE Channel 1 Disable 0x0 R/W 0 CH0_DISABLE Channel 0 Disable 0x0 R/W CHANNEL 0 SYNC OFFSET REGISTER Address: 0x009, Reset: 0x00, Name: CH0_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_SYNC_OFFSET (R/W) Channel Sync Offset Table 53. Bit Descriptions for CH0_SYNC_OFFSET Bits Bit Name [7:0] CH0_SYNC_OFFSET Settings Description Reset Access Channel Sync Offset 0x0 R/W Description Reset Access Channel Sync Offset 0x0 R/W CHANNEL 1 SYNC OFFSET REGISTER Address: 0x00A, Reset: 0x00, Name: CH1_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_SYNC_OFFSET (R/W) Channel Sync Offset Table 54. Bit Descriptions for CH1_SYNC_OFFSET Bits Bit Name [7:0] CH1_SYNC_OFFSET Settings Rev. 0 | Page 65 of 97 AD7779 Data Sheet CHANNEL 2 SYNC OFFSET REGISTER Address: 0x00B, Reset: 0x00, Name: CH2_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_SYNC_OFFSET (R/W) Channel Sync Offset Table 55. Bit Descriptions for CH2_SYNC_OFFSET Bits Bit Name [7:0] CH2_SYNC_OFFSET Settings Description Reset Access Channel Sync Offset 0x0 R/W Description Reset Access Channel Sync Offset 0x0 R/W CHANNEL 3 SYNC OFFSET REGISTER Address: 0x00C, Reset: 0x00, Name: CH3_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_SYNC_OFFSET (R/W) Channel Sync Offset Table 56. Bit Descriptions for CH3_SYNC_OFFSET Bits Bit Name [7:0] CH3_SYNC_OFFSET Settings CHANNEL 4 SYNC OFFSET REGISTER Address: 0x00D, Reset: 0x00, Name: CH4_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_SYNC_OFFSET (R/W) Channel Sync Offset Table 57. Bit Descriptions for CH4_SYNC_OFFSET Bits Bit Name [7:0] CH4_SYNC_OFFSET Settings Description Reset Access Channel Sync Offset 0x0 R/W Description Reset Access Channel Sync Offset 0x0 R/W CHANNEL 5 SYNC OFFSET REGISTER Address: 0x00E, Reset: 0x00, Name: CH5_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_SYNC_OFFSET (R/W) Channel Sync Offset Table 58. Bit Descriptions for CH5_SYNC_OFFSET Bits Bit Name [7:0] CH5_SYNC_OFFSET Settings Rev. 0 | Page 66 of 97 Data Sheet AD7779 CHANNEL 6 SYNC OFFSET REGISTER Address: 0x00F, Reset: 0x00, Name: CH6_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_SYNC_OFFSET (R/W) Channel Sync Offset Table 59. Bit Descriptions for CH6_SYNC_OFFSET Bits Bit Name [7:0] CH6_SYNC_OFFSET Settings Description Reset Access Channel Sync Offset 0x0 R/W Description Reset Access Channel Sync Offset 0x0 R/W CHANNEL 7 SYNC OFFSET REGISTER Address: 0x010, Reset: 0x00, Name: CH7_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_SYNC_OFFSET (R/W) Channel Sync Offset Table 60. Bit Descriptions for CH7_SYNC_OFFSET Bits Bit Name [7:0] CH7_SYNC_OFFSET Settings GENERAL USER CONFIGURATION 1 REGISTER Address: 0x011, Reset: 0x24, Name: GENERAL_USER_CONFIG_1 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 0 [7] ALL_CH_DIS__MCLK_EN (R/W) If all SD channels are disabled, setting this bit high allows DCLK to continue toggling [1:0] SOFT_RESET (R/W) Soft Reset 00: No Effect. 01: No Effect. 10: 2nd write. 11: 1st write. [6] POWERMODE (R/W) Power Mode 0: Low Power (1/4) 1: High Resolution. [2] PDB_RC_OSC (R/W) PowerDown signal for internal oscillator. Active Low [5] PDB_VCM (R/W) PowerDown VCM Buffer. Active Low [3] PDB_SAR (R/W) PowerDown SA. Active Low [4] PDB_REFOUT_BUF (R/W) PowerDown Internal Reference Output Buffer. Active Low Table 61. Bit Descriptions for GENERAL_USER_CONFIG_1 Bits Bit Name 7 ALL_CH_DIS_MCLK_EN 6 POWERMODE Settings Description Reset Access If all Σ-Δ channels are disabled, setting this bit high allows DCLK to continue toggling. 0x0 R/W Power Mode. 0x0 R/W 0 Low power (1/4). 1 High resolution. 5 PDB_VCM Power Down VCM Buffer. Active low. 0x1 R/W 4 PDB_REFOUT_BUF Power Down Internal Reference Output Buffer. Active low. 0x0 R/W 3 PDB_SAR Power Down SAR. Active low. 0x0 R/W 2 PDB_RC_OSC Power Down Signal for Internal Oscillator. Active low. 0x1 R/W Rev. 0 | Page 67 of 97 AD7779 Bits Bit Name [1:0] SOFT_RESET Data Sheet Settings Description Reset Access Soft Reset 0x0 R/W Description Reset Access 00 No effect 01 No effect 10 2nd write 11 1st write GENERAL USER CONFIGURATION 2 REGISTER Address: 0x012, Reset: 0x09, Name: GENERAL_USER_CONFIG_2 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 [7] RESERVED [0] SPI_SYNC (R/W) SYNC pulse generated thru SPI 0: This signal is ANDed with the value on STARTb pin in the control m odule, generate a pulse in /SYNC_IN pin. 1: This bit is ANDed with the value on STARTb pin in the control module. [6] RESERVED [5] SAR_DIAG_MODE_EN (R/W) Sets SPI interface to read back SAR result on SDO [2:1] DOUT_DRIVE_STR (R/W) DOUT Drive Strength 00: Nom inal. 01: Strong. 10: Weak. 11: Extra Strong. [4:3] SDO_DRIVE_STR (R/W) SDO Drive Strength 00: Nom inal. 01: Strong. 10: Weak. 11: Extra Strong. Table 62. Bit Descriptions for GENERAL_USER_CONFIG_2 Bits Bit Name [7:6] RESERVED Reserved. 0x0 R/W 5 SAR_DIAG_MODE_EN Sets SPI Interface to Read Back SAR Result on SDO. 0x0 R/W [4:3] SDO_DRIVE_STR SDO Drive Strength. 0x1 R/W 0x0 R/W 0x1 R/W [2:1] 0 Settings 00 Nominal. 01 Strong. 10 Weak. 11 Extra strong. DOUT_DRIVE_STR DOUTx Drive Strength. 00 Nominal. 01 Strong. 10 Weak. 11 Extra strong. SPI_SYNC SYNC Pulse Generated Through SPI. 0 This signal is AND’ed with the value on the START pin in the control module and generates a pulse in the SYNC_IN pin. 1 This bit is AND’ed with the value on START pin in the control module. Rev. 0 | Page 68 of 97 Data Sheet AD7779 GENERAL USER CONFIGURATION 3 REGISTER Address: 0x013, Reset: 0x80, Name: GENERAL_USER_CONFIG_3 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:6] CONVST_DEGLITCH_DIS (R/W) Disable deglitching of CONVST pin 00: Reserved. 01: Reserved. 10: CONVST_SAR Deglitch 1.5 MCLK. 11: No deglitch circuit. [0] CLK_QUAL_DIS (R/W) Disables the clock qualifier check if the user requires to use an MCLK signal < 265kHz. [1] RESERVED [3:2] RESERVED [5] RESERVED [4] SPI_SLAVE_MODE_EN (R/W) Enable to SPI slave mode to read back ADC on SDO Table 63. Bit descriptions for GENERAL_USER_CONFIG_3 Bits [7:6] Bit Name CONVST_DEGLITCH_DIS Settings Description Disable deglitching of CONVST_SAR pin 00 Reserved. 01 Reserved. 10 CONVST_SAR Deglitch 1.5 MCLK. 11 No deglitch circuit. Reset 0x2 Access R/W 5 RESERVED Reserved. 0x0 R/W 4 SPI_SLAVE_MODE_EN Enable to SPI slave mode to read back ADC on SDO 0x0 R/W [3:2] RESERVED Reserved. 0x0 R/W 1 RESERVED Reserved. 0x0 R/W 0 CLK_QUAL_DIS Disables the clock qualifier check if the user requires to use an MCLK signal <265 kHz. 0x0 R/W Description Reset Access Data Out Format. 0x0 R/W DATA OUTPUT FORMAT REGISTER Address: 0x014, Reset: 0x20, Name: DOUT_FORMAT 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 [7:6] DOUT_FORMAT (R/W) Data out format 00: 4 DOUT Lines. 01: 2 DOUT Lines. 10: 1 DOUT Lines. 11: 1 DOUT Lines. [0] RESERVED [5] DOUT_HEADER_FORMAT (R/W) Dout header format 0: Status Header. 1: CRC Header. [4] RESERVED [3:1] DCLK_CLK_DIV (R/W) Divide MCLK 000: Divide by 1. 001: Divide by 2. 010: Divide by 4. 011: Divide by 8. 100: Divide by 16. 101: Divide by 32. 110: Divide by 64. 111: Divide by 128. Table 64. Bit Descriptions for DOUT_FORMAT Bits Bit Name [7:6] DOUT_FORMAT Settings 00 4 DOUT lines 01 2 DOUT lines 10 1 DOUT lines 11 1 DOUT lines Rev. 0 | Page 69 of 97 AD7779 Data Sheet Bits Bit Name Settings 5 DOUT_HEADER_FORMAT Description Reset Access DOUT Header Format 0x1 R/W 0 Status header 1 CRC header 4 RESERVED Reserved. 0x0 R/W [3:1] DCLK_CLK_DIV Divide MCLK 0x0 R/W 0x0 R/W Description Reset Access SD ADC Reference Mux 0x0 R/W 0x0 R/W 0 RESERVED 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 Reserved. MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER Address: 0x015, Reset: 0x00, Name: ADC_MUX_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] REF_MUX_CTRL (R/W) SD ADC Reference Mux 00: External Reference REFx+/REFx01: Internal Reference. 10: External Supply AVDD1x/AVSSx. 11: External Reference REFx-/REFx+. [1:0] RESERVED [5:2] MTR_MUX_CTRL (R/W) SD ADC Meter Mux 0010: 280m V. 0011: External Reference REFx+/REFx0100: External Reference REFx-/REFx+. 0101: External Reference REFx-/REFx0110: Internal Reference +/0111: Internal Reference -/+. 1000: Internal Reference +/+. 1001: External Reference REFx+/REFx+. Table 65. Bit Descriptions for ADC_MUX_CONFIG Bits Bit Name [7:6] REF_MUX_CTRL [5:2] Settings 00 External reference REFx+/REFx− 01 Internal reference. 10 External supply AVDD1x/AVSSx. 11 External reference REFx−/REFx+. MTR_MUX_CTRL SD ADC Meter Mux 0010 280 mV 0011 External reference REFx+/REFx− 0100 External reference REFx−/REFx+ 0101 External reference REFx−/REFx− 0110 Internal reference +/− 0111 Internal reference −/+ Rev. 0 | Page 70 of 97 Data Sheet Bits [1:0] Bit Name AD7779 Settings Description 1000 Internal reference +/+ 1001 External reference REFx+/REFx+ RESERVED Reserved. Reset Access 0x0 R/W GLOBAL DIAGNOSTICS MUX REGISTER Address: 0x016, Reset: 0x00, Name: GLOBAL_MUX_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:3] GLOBAL_MUX_CTRL (R/W) Global SAR diagnostics mux control 00000: AUXAin+ AUXAin00001: DVBE AVSSx. 00010: REF1P REF1N. ... 10011: REF1+ AVSSx. 10100: REF2+ AVSSx. 10101: AVSSx AVDD4. Attenuated. [2:0] RESERVED Table 66. Bit Descriptions for GLOBAL_MUX_CONFIG Bits Bit Name [7:3] GLOBAL_MUX_CTRL [2:0] RESERVED Settings Description Reset Access Global SAR Diagnostics Mux Control. 0x0 R/W 0x0 R/W 00000 AUXAIN+/AUXAIN−. 00001 DVBE/AVSSx. 00010 REF1+/REF1−. 10011 REF2+/REF2−. 10100 REF_OUT/AVSSx. 10101 VCM/AVSSx. 10110 AREG1CAP/AVSSx. 10111 AREG2CAP/AVSSx. 11000 DREGCAP/DGND. 11001 AVDD1A/AVSSx. 11010 AVDD1B/AVSSx. 11011 AVDD2A/AVSSx. 11100 AVDD2B/AVSSx. 11101 IOVDD/DGND. 11110 AVDD4/AVSSx. 11111 DGND/AVSS1A. 10000 DGND/AVSS1B. 10001 DGND/AVSSx. 10010 AVDD4/AVSSx. 10011 REF1+/AVSSx. 10100 REF2+/AVSSx. 10101 AVDD4/AVSSx. Attenuated. Reserved. Rev. 0 | Page 71 of 97 AD7779 Data Sheet GPIO CONFIGURATION REGISTER Address: 0x017, Reset: 0x00, Name: GPIO_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:3] RESERVED [2:0] GPIO_OP_EN (R/W) GPIO input/output Table 67. Bit Descriptions for GPIO_CONFIG Bits Bit Name [7:3] [2:0] Settings Description Reset Access RESERVED Reserved. 0x0 R/W GPIO_OP_EN GPIO Input/Output 0x0 R/W Description Reset Access GPIO DATA REGISTER Address: 0x018, Reset: 0x00, Name: GPIO_DATA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [2:0] GPIO_WRITE_DATA (R/W) Value sent to GPIO pins [5:3] GPIO_READ_DATA (R) Data read from GPIO pins Table 68. Bit Descriptions for GPIO_DATA Bits Bit Name Settings [7:6] RESERVED Reserved. 0x0 R/W [5:3] GPIO_READ_DATA Data Read from the GPIO Pins 0x0 R [2:0] GPIO_WRITE_DATA Value Sent to the GPIO Pins 0x0 R/W BUFFER CONFIGURATION 1 REGISTER Address: 0x019, Reset: 0x38, Name: BUFFER_CONFIG_1 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 [7] RESERVED [0] RESERVED [6] RESERVED [1] RESERVED [5] RESERVED [2] RESERVED [4] REF_BUF_POS_EN (R/W) Reference buffer pos itive enable [3] REF_BUF_NEG_EN (R/W) Reference buffer negative enable Table 69. Bit Descriptions for BUFFER_CONFIG_1 Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 REF_BUF_POS_EN Reference Buffer Positive Enable 0x1 R/W 3 REF_BUF_NEG_EN Reference Buffer Negative Enable 0x1 R/W [2:0] RESERVED Reserved 0x0 R/W Rev. 0 | Page 72 of 97 Data Sheet AD7779 BUFFER CONFIGURATION 2 REGISTER Address: 0x01A, Reset: 0xC0, Name: BUFFER_CONFIG_2 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 [7] REFBUFP_PREQ (R/W) Reference buffer positive precharge enable [0] PDB_DLDO_OVRDRV (R/W) DRegCap Overdrive Enable. [1] PDB_ALDO2_OVRDRV (R/W) AReg2Cap Overdrive Enable [6] REFBUFN_PREQ (R/W) Reference buffer negative precharge enable [2] PDB_ALDO1_OVRDRV (R/W) AReg1Cap Overdrive Enable [5:3] RESERVED Table 70. Bit Descriptions for BUFFER_CONFIG_2 Bits Bit Name 7 Settings Description Reset Access REFBUFP_PREQ Reference Buffer Positive Precharge Enable 0x1 R/W 6 REFBUFN_PREQ Reference Buffer Negative Precharge Enable 0x1 R/W [5:3] RESERVED Reserved. 0x0 R/W 2 PDB_ALDO1_OVRDRV AREG1CAP Overdrive Enable 0x0 R/W 1 PDB_ALDO2_OVRDRV AREG2CAP Overdrive Enable 0x0 R/W 0 PDB_DLDO_OVRDRV DREGCAP Overdrive Enable 0x0 R/W Description Reset Access Combined Offset Register Channel 0 0x0 R/W Description Reset Access Combined Offset Register Channel 0 0x0 R/W CHANNEL 0 OFFSET UPPER BYTE REGISTER Address: 0x01C, Reset: 0x00, Name: CH0_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_OFFSET_ALL[23:16] (R/W) Com bined Offset register Channel 0 Table 71. Bit Descriptions for CH0_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH0_OFFSET_ALL[23:16] Settings CHANNEL 0 OFFSET MIDDLE BYTE REGISTER Address: 0x01D, Reset: 0x00, Name: CH0_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_OFFSET_ALL[15:8] (R/W) Com bined Offs et regis ter Channel 0 Table 72. Bit Descriptions for CH0_OFFSET_MID_BYTE Bits Bit Name [7:0] CH0_OFFSET_ALL[15:8] Settings Rev. 0 | Page 73 of 97 AD7779 Data Sheet CHANNEL 0 OFFSET LOWER BYTE REGISTER Address: 0x01E, Reset: 0x00, Name: CH0_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_OFFSET_ALL[7:0] (R/W) Com bined Offs et regis ter Channel 0 Table 73. Bit Descriptions for CH0_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH0_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 0 0x0 R/W Description Reset Access Combined Gain Register Channel 0 0x0 R/W Description Reset Access Combined Gain Register Channel 0 0x0 R/W Description Reset Access Combined Gain Register Channel 0 0x0 R/W CHANNEL 0 GAIN UPPER BYTE REGISTER Address: 0x01F, Reset: 0x00, Name: CH0_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 0 Table 74. Bit Descriptions for CH0_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH0_GAIN_ALL[23:16] Settings CHANNEL 0 GAIN MIDDLE BYTE REGISTER Address: 0x020, Reset: 0x00, Name: CH0_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 0 Table 75. Bit Descriptions for CH0_GAIN_MID_BYTE Bits Bit Name [7:0] CH0_GAIN_ALL[15:8] Settings CHANNEL 0 GAIN LOWER BYTE REGISTER Address: 0x021, Reset: 0x00, Name: CH0_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 0 Table 76. Bit Descriptions for CH0_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH0_GAIN_ALL[7:0] Settings Rev. 0 | Page 74 of 97 Data Sheet AD7779 CHANNEL 1 OFFSET UPPER BYTE REGISTER Address: 0x022, Reset: 0x00, Name: CH1_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 1 Table 77. Bit Descriptions for CH1_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH1_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 1 0x0 R/W Description Reset Access Combined Offset Register Channel 1 0x0 R/W CHANNEL 1 OFFSET MIDDLE BYTE REGISTER Address: 0x023, Reset: 0x00, Name: CH1_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 1 Table 78. Bit Descriptions for CH1_OFFSET_MID_BYTE Bits Bit Name [7:0] CH1_OFFSET_ALL[15:8] Settings CHANNEL 1 OFFSET LOWER BYTE REGISTER Address: 0x024, Reset: 0x00, Name: CH1_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 1 Table 79. Bit Descriptions for CH1_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH1_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 1 0x0 R/W Description Reset Access Combined Gain Register Channel 1 0x0 R/W CHANNEL 1 GAIN UPPER BYTE REGISTER Address: 0x025, Reset: 0x00, Name: CH1_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 1 Table 80. Bit Descriptions for CH1_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH1_GAIN_ALL[23:16] Settings Rev. 0 | Page 75 of 97 AD7779 Data Sheet CHANNEL 1 GAIN MIDDLE BYTE REGISTER Address: 0x026, Reset: 0x00, Name: CH1_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 1 Table 81. Bit Descriptions for CH1_GAIN_MID_BYTE Bits Bit Name [7:0] CH1_GAIN_ALL[15:8] Settings Description Reset Access Combined Gain Register Channel 1 0x0 R/W Description Reset Access Combined Gain Register Channel 1 0x0 R/W CHANNEL 1 GAIN LOWER BYTE REGISTER Address: 0x027, Reset: 0x00, Name: CH1_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 1 Table 82. Bit Descriptions for CH1_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH1_GAIN_ALL[7:0] Settings CHANNEL 2 OFFSET UPPER BYTE REGISTER Address: 0x028, Reset: 0x00, Name: CH2_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 2 Table 83. Bit Descriptions for CH2_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH2_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 2 0x0 R/W Description Reset Access Combined Offset Register Channel 2 0x0 R/W CHANNEL 2 OFFSET MIDDLE BYTE REGISTER Address: 0x029, Reset: 0x00, Name: CH2_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 2 Table 84. Bit Descriptions for CH2_OFFSET_MID_BYTE Bits Bit Name [7:0] CH2_OFFSET_ALL[15:8] Settings Rev. 0 | Page 76 of 97 Data Sheet AD7779 CHANNEL 2 OFFSET LOWER BYTE REGISTER Address: 0x02A, Reset: 0x00, Name: CH2_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 2 Table 85. Bit Descriptions for CH2_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH2_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 2 0x0 R/W Description Reset Access Combined Gain Register Channel 2 0x0 R/W Description Reset Access Combined Gain Register Channel 2 0x0 R/W Description Reset Access Combined Gain Register Channel 2 0x0 R/W CHANNEL 2 GAIN UPPER BYTE REGISTER Address: 0x02B, Reset: 0x00, Name: CH2_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 2 Table 86. Bit Descriptions for CH2_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH2_GAIN_ALL[23:16] Settings CHANNEL 2 GAIN MIDDLE BYTE REGISTER Address: 0x02C, Reset: 0x00, Name: CH2_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 2 Table 87. Bit Descriptions for CH2_GAIN_MID_BYTE Bits Bit Name [7:0] CH2_GAIN_ALL[15:8] Settings CHANNEL 2 GAIN LOWER BYTE REGISTER Address: 0x02D, Reset: 0x00, Name: CH2_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 2 Table 88. Bit Descriptions for CH2_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH2_GAIN_ALL[7:0] Settings Rev. 0 | Page 77 of 97 AD7779 Data Sheet CHANNEL 3 OFFSET UPPER BYTE REGISTER Address: 0x02E, Reset: 0x00, Name: CH3_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 3 Table 89. Bit descriptions for CH3_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH3_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 3 0x0 R/W Description Reset Access Combined Offset Register Channel 3 0x0 R/W CHANNEL 3 OFFSET MIDDLE BYTE REGISTER Address: 0x02F, Reset: 0x00, Name: CH3_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 3 Table 90. Bit Descriptions for CH3_OFFSET_MID_BYTE Bits Bit Name [7:0] CH3_OFFSET_ALL[15:8] Settings CHANNEL 3 OFFSET LOWER BYTE REGISTER Address: 0x030, Reset: 0x00, Name: CH3_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 3 Table 91. Bit Descriptions for CH3_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH3_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 3 0x0 R/W Description Reset Access Combined Gain Register Channel 3 0x0 R/W CHANNEL 3 GAIN UPPER BYTE REGISTER Address: 0x031, Reset: 0x00, Name: CH3_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 3 Table 92. Bit Descriptions for CH3_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH3_GAIN_ALL[23:16] Settings Rev. 0 | Page 78 of 97 Data Sheet AD7779 CHANNEL 3 GAIN MIDDLE BYTE REGISTER Address: 0x032, Reset: 0x00, Name: CH3_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 3 Table 93. Bit Descriptions for CH3_GAIN_MID_BYTE Bits Bit Name [7:0] CH3_GAIN_ALL[15:8] Settings Description Reset Access Combined Gain Register Channel 3 0x0 R/W Description Reset Access Combined Gain Register Channel 3 0x0 R/W CHANNEL 3 GAIN LOWER BYTE REGISTER Address: 0x033, Reset: 0x00, Name: CH3_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 3 Table 94. Bit Descriptions for CH3_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH3_GAIN_ALL[7:0] Settings CHANNEL 4 OFFSET UPPER BYTE REGISTER Address: 0x034, Reset: 0x00, Name: CH4_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 4 Table 95. Bit Descriptions for CH4_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH4_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 4 0x0 R/W Description Reset Access Combined Offset Register Channel 4 0x0 R/W CHANNEL 4 OFFSET MIDDLE BYTE REGISTER Address: 0x035, Reset: 0x00, Name: CH4_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 4 Table 96. Bit Descriptions for CH4_OFFSET_MID_BYTE Bits Bit Name [7:0] CH4_OFFSET_ALL[15:8] Settings Rev. 0 | Page 79 of 97 AD7779 Data Sheet CHANNEL 4 OFFSET LOWER BYTE REGISTER Address: 0x036, Reset: 0x00, Name: CH4_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 4 Table 97. Bit Descriptions for CH4_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH4_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 4 0x0 R/W Description Reset Access Combined Gain Register Channel 4 0x0 R/W Description Reset Access Combined Gain Register Channel 4 0x0 R/W Description Reset Access Combined Gain Register Channel 4 0x0 R/W CHANNEL 4 GAIN UPPER BYTE REGISTER Address: 0x037, Reset: 0x00, Name: CH4_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 4 Table 98. Bit Descriptions for CH4_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH4_GAIN_ALL[23:16] Settings CHANNEL 4 GAIN MIDDLE BYTE REGISTER Address: 0x038, Reset: 0x00, Name: CH4_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 4 Table 99. Bit Descriptions for CH4_GAIN_MID_BYTE Bits Bit Name [7:0] CH4_GAIN_ALL[15:8] Settings CHANNEL 4 GAIN LOWER BYTE REGISTER Address: 0x039, Reset: 0x00, Name: CH4_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 4 Table 100. Bit Descriptions for CH4_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH4_GAIN_ALL[7:0] Settings Rev. 0 | Page 80 of 97 Data Sheet AD7779 CHANNEL 5 OFFSET UPPER BYTE REGISTER Address: 0x03A, Reset: 0x00, Name: CH5_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 5 Table 101. Bit Descriptions for CH5_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH5_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 5 0x0 R/W Description Reset Access Combined Offset Register Channel 5 0x0 R/W CHANNEL 5 OFFSET MIDDLE BYTE REGISTER Address: 0x03B, Reset: 0x00, Name: CH5_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 5 Table 102. Bit Descriptions for CH5_OFFSET_MID_BYTE Bits Bit Name [7:0] CH5_OFFSET_ALL[15:8] Settings CHANNEL 5 OFFSET LOWER BYTE REGISTER Address: 0x03C, Reset: 0x00, Name: CH5_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 5 Table 103. Bit Descriptions for CH5_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH5_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 5 0x0 R/W Description Reset Access Combined Gain Register Channel 5 0x0 R/W CHANNEL 5 GAIN UPPER BYTE REGISTER Address: 0x03D, Reset: 0x00, Name: CH5_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 5 Table 104. Bit Descriptions for CH5_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH5_GAIN_ALL[23:16] Settings Rev. 0 | Page 81 of 97 AD7779 Data Sheet CHANNEL 5 GAIN MIDDLE BYTE REGISTER Address: 0x03E, Reset: 0x00, Name: CH5_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 5 Table 105. Bit Descriptions for CH5_GAIN_MID_BYTE Bits Bit Name [7:0] CH5_GAIN_ALL[15:8] Settings Description Reset Access Combined Gain Register Channel 5 0x0 R/W Description Reset Access Combined Gain Register Channel 5 0x0 R/W CHANNEL 5 GAIN LOWER BYTE REGISTER Address: 0x03F, Reset: 0x00, Name: CH5_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 5 Table 106. Bit Descriptions for CH5_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH5_GAIN_ALL[7:0] Settings CHANNEL 6 OFFSET UPPER BYTE REGISTER Address: 0x040, Reset: 0x00, Name: CH6_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 6 Table 107. Bit Descriptions for CH6_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH6_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 6 0x0 R/W Description Reset Access Combined Offset Register Channel 6 0x0 R/W CHANNEL 6 OFFSET MIDDLE BYTE REGISTER Address: 0x041, Reset: 0x00, Name: CH6_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 6 Table 108. Bit Descriptions for CH6_OFFSET_MID_BYTE Bits Bit Name [7:0] CH6_OFFSET_ALL[15:8] Settings Rev. 0 | Page 82 of 97 Data Sheet AD7779 CHANNEL 6 OFFSET LOWER BYTE REGISTER Address: 0x042, Reset: 0x00, Name: CH6_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 6 Table 109. Bit Descriptions for CH6_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH6_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 6 0x0 R/W Description Reset Access Combined Gain Register Channel 6 0x0 R/W Description Reset Access Combined Gain Register Channel 6 0x0 R/W Description Reset Access Combined Gain Register Channel 6 0x0 R/W CHANNEL 6 GAIN UPPER BYTE REGISTER Address: 0x043, Reset: 0x00, Name: CH6_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_GAIN_ALL[23:16] (R/W) Com bined gain register Channel 6 Table 110. Bit Descriptions for CH6_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH6_GAIN_ALL[23:16] Settings CHANNEL 6 GAIN MIDDLE BYTE REGISTER Address: 0x044, Reset: 0x00, Name: CH6_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 6 Table 111. Bit Descriptions for CH6_GAIN_MID_BYTE Bits Bit Name [7:0] CH6_GAIN_ALL[15:8] Settings CHANNEL 6 GAIN LOWER BYTE REGISTER Address: 0x045, Reset: 0x00, Name: CH6_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_GAIN_ALL[7:0] (R/W) Com bined gain register Channel 6 Table 112. Bit Descriptions for CH6_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH6_GAIN_ALL[7:0] Settings Rev. 0 | Page 83 of 97 AD7779 Data Sheet CHANNEL 7 OFFSET UPPER BYTE REGISTER Address: 0x046, Reset: 0x00, Name: CH7_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_OFFSET_ALL[23:16] (R/W) Com bined offset register Channel 7 Table 113. Bit Descriptions for CH7_OFFSET_UPPER_BYTE Bits Bit Name [7:0] CH7_OFFSET_ALL[23:16] Settings Description Reset Access Combined Offset Register Channel 7 0x0 R/W Description Reset Access Combined Offset Register Channel 7 0x0 R/W CHANNEL 7 OFFSET MIDDLE BYTE REGISTER Address: 0x047, Reset: 0x00, Name: CH7_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_OFFSET_ALL[15:8] (R/W) Com bined offs et regis ter Channel 7 Table 114. Bit Descriptions for CH7_OFFSET_MID_BYTE Bits Bit Name [7:0] CH7_OFFSET_ALL[15:8] Settings CHANNEL 7 OFFSET LOWER BYTE REGISTER Address: 0x048, Reset: 0x00, Name: CH7_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_OFFSET_ALL[7:0] (R/W) Com bined offset register Channel 7 Table 115. Bit Descriptions for CH7_OFFSET_LOWER_BYTE Bits Bit Name [7:0] CH7_OFFSET_ALL[7:0] Settings Description Reset Access Combined Offset Register Channel 7 0x0 R/W Description Reset Access Combined Gain Register Channel 7 0x0 R/W CHANNEL 7 GAIN UPPER BYTE REGISTER Address: 0x049, Reset: 0x00, Name: CH7_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_GAIN ALL[23:16] (R/W) Com bined gain regis ter Channel 7 Table 116. Bit Descriptions for CH7_GAIN_UPPER_BYTE Bits Bit Name [7:0] CH7_GAIN ALL[23:16] Settings Rev. 0 | Page 84 of 97 Data Sheet AD7779 CHANNEL 7 GAIN MIDDLE BYTE REGISTER Address: 0x04A, Reset: 0x00, Name: CH7_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_GAIN ALL[15:8] (R/W) Com bined gain regis ter Channel 7 Table 117. Bit Descriptions for CH7_GAIN_MID_BYTE Bits Bit Name [7:0] CH7_GAIN ALL[15:8] Settings Description Reset Access Combined Gain Register Channel 7 0x0 R/W Description Reset Access Combined Gain Register Channel 7 0x0 R/W Description Reset Access CHANNEL 7 GAIN LOWER BYTE REGISTER Address: 0x04B, Reset: 0x00, Name: CH7_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_GAIN ALL[7:0] (R/W) Com bined gain regis ter Channel 7 Table 118. Bit Descriptions for CH7_GAIN_LOWER_BYTE Bits Bit Name [7:0] CH7_GAIN ALL[7:0] Settings CHANNEL 0 STATUS REGISTER Address: 0x04C, Reset: 0x00, Name: CH0_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH0_ERR_AINM_UV (R) AIN0- undervoltage error [3] CH0_ERR_AINM_OV (R) AIN0- overvoltage error [0] CH0_ERR_REF_DET (R) Channel 0 - Reference detect error [1] CH0_ERR_AINP_OV (R) AIN0+ overvoltage error [2] CH0_ERR_AINP_UV (R) AIN0+ undervoltage error Table 119. Bit Descriptions for CH0_ERR_REG Bits Bit Name Settings [7:5] RESERVED Reserved 0x0 R/W 4 CH0_ERR_AINM_UV Channel 0—AIN0− Undervoltage Error 0x0 R 3 CH0_ERR_AINM_OV Channel 0—AIN0− Overvoltage Error 0x0 R 2 CH0_ERR_AINP_UV Channel 0—AIN0+ Undervoltage Error 0x0 R 1 CH0_ERR_AINP_OV Channel 0—AIN0+ Overvoltage Error 0x0 R 0 CH0_ERR_REF_DET Channel 0—Reference Detect Error 0x0 R Rev. 0 | Page 85 of 97 AD7779 Data Sheet CHANNEL 1 STATUS REGISTER Address: 0x04D, Reset: 0x00, Name: CH1_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH1_ERR_REF_DET (R) Channel 1 - Reference detect error [4] CH1_ERR_AINM_UV (R) AIN1- undervoltage error [1] CH1_ERR_AINP_OV (R) AIN1+ overvoltage error [3] CH1_ERR_AINM_OV (R) AIN1- overvoltage error [2] CH1_ERR_AINP_UV (R) AIN1+ undervoltage error Table 120. Bit Descriptions for CH1_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH1_ERR_AINM_UV Channel 1—AIN1− Undervoltage Error 0x0 R 3 CH1_ERR_AINM_OV Channel 1—AIN1− Overvoltage Error 0x0 R 2 CH1_ERR_AINP_UV Channel 1—AIN1+ Undervoltage Error 0x0 R 1 CH1_ERR_AINP_OV Channel 1—AIN1+ Overvoltage Error 0x0 R 0 CH1_ERR_REF_DET Channel 1—Reference Detect Error 0x0 R Description Reset Access CHANNEL 2 STATUS REGISTER Address: 0x04E, Reset: 0x00, Name: CH2_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH2_ERR_AINM_UV (R) AIN2- undervoltage error [3] CH2_ERR_AINM_OV (R) AIN2- overvoltage error [0] CH2_ERR_REF_DET (R) Channel 2 - Reference detect error [1] CH2_ERR_AINP_OV (R) AIN2+ overvoltage error [2] CH2_ERR_AINP_UV (R) AIN2+ undervoltage error Table 121. Bit Descriptions for CH2_ERR_REG Bits Bit Name Settings [7:5] RESERVED Reserved 0x0 R/W 4 CH2_ERR_AINM_UV Channel 2—AIN2− Undervoltage Error 0x0 R 3 CH2_ERR_AINM_OV Channel 2—AIN2− Overvoltage Error 0x0 R 2 CH2_ERR_AINP_UV Channel 2—AIN2+ Undervoltage Error 0x0 R 1 CH2_ERR_AINP_OV Channel 2—AIN2+ Overvoltage Error 0x0 R 0 CH2_ERR_REF_DET Channel 2—Reference Detect Error 0x0 R Rev. 0 | Page 86 of 97 Data Sheet AD7779 CHANNEL 3 STATUS REGISTER Address: 0x04F, Reset: 0x00, Name: CH3_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH3_ERR_REF_DET (R) Channel 3 - Reference detect error [4] CH3_ERR_AINM_UV (R) AIN3- undervoltage error [1] CH3_ERR_AINP_OV (R) AIN3+ overvoltage error [3] CH3_ERR_AINM_OV (R) AIN3- overvoltage error [2] CH3_ERR_AINP_UV (R) AIN3+ undervoltage error Table 122. Bit Descriptions for CH3_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH3_ERR_AINM_UV Channel 3—AIN3− Undervoltage Error 0x0 R 3 CH3_ERR_AINM_OV Channel 3—AIN3− Overvoltage Error 0x0 R 2 CH3_ERR_AINP_UV Channel 3—AIN3+ Undervoltage Error 0x0 R 1 CH3_ERR_AINP_OV Channel 3—AIN3+ Overvoltage Error 0x0 R 0 CH3_ERR_REF_DET Channel 3—Reference Detect Error 0x0 R Description Reset Access CHANNEL 4 STATUS REGISTER Address: 0x050, Reset: 0x00, Name: CH4_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH4_ERR_AINM_UV (R) AIN4- undervoltage error [3] CH4_ERR_AINM_OV (R) AIN4- overvoltage error [0] CH4_ERR_REF_DET (R) Channel 4 - Reference detect error [1] CH4_ERR_AINP_OV (R) AIN4+ overvoltage error [2] CH4_ERR_AINP_UV (R) AIN4+ undervoltage error Table 123. Bit Descriptions for CH4_ERR_REG Bits Bit Name Settings [7:5] RESERVED Reserved 0x0 R/W 4 CH4_ERR_AINM_UV Channel 4—AIN4− Undervoltage Error 0x0 R 3 CH4_ERR_AINM_OV Channel 4—AIN4− Overvoltage Error 0x0 R 2 CH4_ERR_AINP_UV Channel 4—AIN4+ Undervoltage Error 0x0 R 1 CH4_ERR_AINP_OV Channel 4—AIN4+ Overvoltage Error 0x0 R 0 CH4_ERR_REF_DET Channel 4—Reference Detect Error 0x0 R Rev. 0 | Page 87 of 97 AD7779 Data Sheet CHANNEL 5 STATUS REGISTER Address: 0x051, Reset: 0x00, Name: CH5_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH5_ERR_REF_DET (R) Channel 5 - Reference detect error [4] CH5_ERR_AINM_UV (R) AIN5- undervoltage error [1] CH5_ERR_AINP_OV (R) AIN5+ overvoltage error [3] CH5_ERR_AINM_OV (R) AIN5- overvoltage error [2] CH5_ERR_AINP_UV (R) AIN5+ undervoltage error Table 124. Bit Descriptions for CH5_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH5_ERR_AINM_UV Channel 5—AIN5− Undervoltage Error 0x0 R 3 CH5_ERR_AINM_OV Channel 5—AIN5− Overvoltage Error 0x0 R 2 CH5_ERR_AINP_UV Channel 5—AIN5+ Undervoltage Error 0x0 R 1 CH5_ERR_AINP_OV Channel 5—AIN5+ Overvoltage Error 0x0 R 0 CH5_ERR_REF_DET Channel 5—Reference Detect Error 0x0 R Description Reset Access CHANNEL 6 STATUS REGISTER Address: 0x052, Reset: 0x00, Name: CH6_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH6_ERR_AINM_UV (R) AIN6- undervoltage error [3] CH6_ERR_AINM_OV (R) AIN6- overvoltage error [0] CH6_ERR_REF_DET (R) Channel 6 - Reference detect error [1] CH6_ERR_AINP_OV (R) AIN6+ overvoltage error [2] CH6_ERR_AINP_UV (R) AIN6+ undervoltage error Table 125. Bit Descriptions for CH6_ERR_REG Bits Bit Name Settings [7:5] RESERVED Reserved 0x0 R/W 4 CH6_ERR_AINM_UV Channel 6—AIN6− Undervoltage Error 0x0 R 3 CH6_ERR_AINM_OV Channel 6—AIN6− Overvoltage Error 0x0 R 2 CH6_ERR_AINP_UV Channel 6—AIN6+ Undervoltage Error 0x0 R 1 CH6_ERR_AINP_OV Channel 6—AIN6+ Overvoltage Error 0x0 R 0 CH6_ERR_REF_DET Channel 6—Reference Detect Error 0x0 R Rev. 0 | Page 88 of 97 Data Sheet AD7779 CHANNEL 7 STATUS REGISTER Address: 0x053, Reset: 0x00, Name: CH7_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH7_ERR_REF_DET (R) Channel 7 - Reference detect error [4] CH7_ERR_AINM_UV (R) AIN7- undervoltage error [1] CH7_ERR_AINP_OV (R) AIN7+ overvoltage error [3] CH7_ERR_AINM_OV (R) AIN7- overvoltage error [2] CH7_ERR_AINP_UV (R) AIN7+ undervoltage error Table 126. Bit Descriptions for CH7_ERR_REG Bits Bit Name Settings Description Reset Access 4 CH7_ERR_AINM_UV Channel 7—AIN7− Undervoltage Error 0x0 R 3 CH7_ERR_AINM_OV Channel 7—AIN7− Overvoltage Error 0x0 R 2 CH7_ERR_AINP_UV Channel 7—AIN7+ Undervoltage Error 0x0 R 1 CH7_ERR_AINP_OV Channel 7—AIN7+ Overvoltage Error 0x0 R 0 CH7_ERR_REF_DET Channel 7—Reference Detect Error 0x0 R CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER Address: 0x054, Reset: 0x00, Name: CH0_1_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] CH1_ERR_MOD_SAT (R) Channel 1 - Modulator output saturation error [4] CH1_ERR_FILTER_SAT (R) Channel 1 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [3] CH1_ERR_OUTPUT_SAT (R) Channel 1 - ADC conversion has exceeded limits and has been clamped [0] CH0_ERR_OUTPUT_SAT (R) Channel 0 - ADC conversion has exceeded lim its and has been clam ped [1] CH0_ERR_FILTER_SAT (R) Channel 0 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH0_ERR_MOD_SAT (R) Channel 0 - Modulator output saturation error Table 127. Bit Descriptions for CH0_1_SAT_ERR Bits Bit Name 5 Settings Description Reset Access CH1_ERR_MOD_SAT Channel 1—Modulator Output Saturation Error 0x0 R 4 CH1_ERR_FILTER_SAT Channel 1—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 3 CH1_ERR_OUTPUT_SAT Channel 1—ADC conversion has exceeded limits and has been clamped 0x0 R 2 CH0_ERR_MOD_SAT Channel 0—Modulator Output Saturation Error 0x0 R 1 CH0_ERR_FILTER_SAT Channel 0—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 0 CH0_ERR_OUTPUT_SAT Channel 0—ADC conversion has exceeded limits and has been clamped 0x0 R Rev. 0 | Page 89 of 97 AD7779 Data Sheet CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER Address: 0x055, Reset: 0x00, Name: CH2_3_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] CH2_ERR_OUTPUT_SAT (R) Channel 2 - ADC conversion has exceeded lim its and has been clam ped [5] CH3_ERR_MOD_SAT (R) Channel 3 - Modulator output saturation error [1] CH2_ERR_FILTER_SAT (R) Channel 2 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [4] CH3_ERR_FILTER_SAT (R) Channel 3 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH2_ERR_MOD_SAT (R) Channel 2 - Modulator output saturation error [3] CH3_ERR_OUTPUT_SAT (R) Channel 3 - ADC conversion has exceeded limits and has been clamped Table 128. Bit Descriptions for CH2_3_SAT_ERR Bits Bit Name 5 4 Settings Description Reset Access CH3_ERR_MOD_SAT Channel 3—Modulator Output Saturation Error 0x0 R CH3_ERR_FILTER_SAT Channel 3—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 3 CH3_ERR_OUTPUT_SAT Channel 3—ADC conversion has exceeded limits and has been clamped 0x0 R 2 CH2_ERR_MOD_SAT Channel 2—Modulator Output Saturation Error 0x0 R 1 CH2_ERR_FILTER_SAT Channel 2—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 0 CH2_ERR_OUTPUT_SAT Channel 2—ADC conversion has exceeded limits and has been clamped 0x0 R CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER Address: 0x056, Reset: 0x00, Name: CH4_5_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] CH5_ERR_MOD_SAT (R) Channel 5 - Modulator output saturation error [4] CH5_ERR_FILTER_SAT (R) Channel 5 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [3] CH5_ERR_OUTPUT_SAT (R) Channel 5 - ADC conversion has exceeded limits and has been clamped [0] CH4_ERR_OUTPUT_SAT (R) Channel 4 - ADC conversion has exceeded lim its and has been clam ped [1] CH4_ERR_FILTER_SAT (R) Channel 4 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH4_ERR_MOD_SAT (R) Channel 4 - Modulator output saturation error Table 129. Bit Descriptions for CH4_5_SAT_ERR Bits Bit Name Description Reset Access 5 CH5_ERR_MOD_SAT Settings Channel 5—Modulator Output Saturation Error 0x0 R 4 CH5_ERR_FILTER_SAT Channel 5—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 3 CH5_ERR_OUTPUT_SAT Channel 5—ADC conversion has exceeded limits and has been clamped 0x0 R 2 CH4_ERR_MOD_SAT Channel 4—Modulator Output Saturation Error 0x0 R 1 CH4_ERR_FILTER_SAT Channel 4—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 0 CH4_ERR_OUTPUT_SAT Channel 4—ADC conversion has exceeded limits and has been clamped 0x0 R Rev. 0 | Page 90 of 97 Data Sheet AD7779 CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER Address: 0x057, Reset: 0x00, Name: CH6_7_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] CH6_ERR_OUTPUT_SAT (R) Channel 6 - ADC conversion has exceeded lim its and has been clam ped [5] CH7_ERR_MOD_SAT (R) Channel 7 - Modulator output saturation error [1] CH6_ERR_FILTER_SAT (R) Channel 6 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [4] CH7_ERR_FILTER_SAT (R) Channel 7 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH6_ERR_MOD_SAT (R) Channel 6 - Modulator output saturation error [3] CH7_ERR_OUTPUT_SAT (R) Channel 7 - ADC conversion has exceeded limits and has been clamped Table 130. Bit descriptions for CH6_7_SAT_ERR Bits Bit Name 5 4 Settings Description Reset Access CH7_ERR_MOD_SAT Channel 7—Modulator Output Saturation Error 0x0 R CH7_ERR_FILTER_SAT Channel 7—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 3 CH7_ERR_OUTPUT_SAT Channel 7—ADC conversion has exceeded limits and has been clamped 0x0 R 2 CH6_ERR_MOD_SAT Channel 6—Modulator Output Saturation Error 0x0 R 1 CH6_ERR_FILTER_SAT Channel 6—Filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 R 0 CH6_ERR_OUTPUT_SAT Channel 6—ADC conversion has exceeded limits and has been clamped 0x0 R CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER Address: 0x058, Reset: 0xFE, Name: CHX_ERR_REG_EN 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 [7] OUTPUT_SAT_TEST_EN (R/W) ADC conversion error test enable [0] REF_DET_TEST_EN (R/W) Reference detect test enable [6] FILTER_SAT_TEST_EN (R/W) Filter saturation error test enable [1] AINP_OV_TEST_EN (R/W) AINx+ overvoltage test enable [5] MOD_SAT_TEST_EN (R/W) Enable error flag for Modulator saturation [2] AINP_UV_TEST_EN (R/W) AINx+ undervoltage test enable [4] AINM_UV_TEST_EN (R/W) AINx- undervoltage test enable [3] AINM_OV_TEST_EN (R/W) AINx- overvoltage test enable Table 131. Bit Descriptions for CHX_ERR_REG_EN Bits Bit Name 7 Settings Description Reset Access OUTPUT_SAT_TEST_EN ADC Conversion Error Test Enable 0x1 R/W 6 FILTER_SAT_TEST_EN Filter Saturation Test Enable 0x1 R/W 5 MOD_SAT_TEST_EN Enable Error Flag for Modulator Saturation 0x1 R/W 4 AINM_UV_TEST_EN AINx− Undervoltage Test Enable 0x1 R/W 3 AINM_OV_TEST_EN AINx− Overvoltage Test Enable 0x1 R/W 2 AINP_UV_TEST_EN AINx+ Undervoltage Test Enable 0x1 R/W 1 AINP_OV_TEST_EN AINx+ Overvoltage Test Enable 0x1 R/W 0 REF_DET_TEST_EN Reference Detect Test Enable 0x0 R/W Rev. 0 | Page 91 of 97 AD7779 Data Sheet GENERAL ERRORS REGISTER 1 Address: 0x059, Reset: 0x00, Name: GEN_ERR_REG_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] MEMMAP_CRC_ERR (R) A CRC of the m em ory map contents is run periodically to check for errors [4] ROM_CRC_ERR (R) A CRC of the fuse contents is run periodically to check for errors in the fuses [0] SPI_CRC_ERR (R) SPI CRC error [1] SPI_INVALID_WRITE_ERR (R) SPI invalid write address [2] SPI_INVALID_READ_ERR (R) SPI invalid read address [3] SPI_CLK_COUNT_ERR (R) SPI clock counter error Table 132. Bit Descriptions for GEN_ERR_REG_1 Bits Bit Name 5 Settings Description Reset Access MEMMAP_CRC_ERR A CRC of the memory map contents is run periodically to check for errors 0x0 R 4 ROM_CRC_ERR A CRC of the fuse contents is run periodically to check for errors in the fuses 0x0 R 3 SPI_CLK_COUNT_ERR SPI clock counter error 0x0 R 2 SPI_INVALID_READ_ERR SPI invalid read address 0x0 R 1 SPI_INVALID_WRITE_ERR SPI invalid write address 0x0 R 0 SPI_CRC_ERR SPI CRC error 0x0 R GENERAL ERRORS REGISTER 1 ENABLE Address: 0x05A, Reset: 0x3E, Name: GEN_ERR_REG_1_EN Table 133. Bit Descriptions for GEN_ERR_REG_1_EN Bits Bit Name Settings Description Reset Access 5 MEMMAP_CRC_TEST_EN Memory Map CRC Test Enable 0x1 R/W 4 ROM_CRC_TEST_EN Fuse CRC Test Enable 0x1 R/W 3 SPI_CLK_COUNT_TEST_EN SPI Clock Counter Test Enable 0x1 R/W 2 SPI_INVALID_READ_TEST_EN SPI Invalid Read Address Test Enable 0x1 R/W 1 SPI_INVALID_WRITE_TEST_EN SPI Invalid Write Address Test Enable 0x1 R/W 0 SPI_CRC_TEST_EN SPI CRC Error Test Enable 0x0 R/W Rev. 0 | Page 92 of 97 Data Sheet AD7779 GENERAL ERRORS REGISTER 2 Address: 0x05B, Reset: 0x00, Name: GEN_ERR_REG_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] DLDO_PSM_ERR (R) DRegCap power s upply error [5] RESET_DETECTED (R) Reset detected [1] ALDO2_PSM_ERR (R) AReg2Cap power supply error [4] EXT_MCLK_SWITCH_ERR (R) Clock not switched over [2] ALDO1_PSM_ERR (R) AReg1Cap power supply error [3] RESERVED Table 134. Bit Descriptions for GEN_ERR_REG_2 Bits Bit Name 5 Settings Description Reset Access RESET_DETECTED Reset Detected 0x0 R 4 EXT_MCLK_SWITCH_ERR Clock Not Switched Over 0x0 R 2 ALDO1_PSM_ERR AREG1CAP Power Supply Error 0x0 R 1 ALDO2_PSM_ERR AREG2CAP Power Supply Error 0x0 R 0 DLDO_PSM_ERR DREGCAP Power Supply Error 0x0 R Reset Access GENERAL ERRORS REGISTER 2 ENABLE Address: 0x05C, Reset: 0x3C, Name: GEN_ERR_REG_2_EN 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 0 [7:6] RESERVED [1:0] LDO_PSM_TRIP_TEST_EN (R/W) LDO PSM trip test enable 0: 00 - No trip detect test enabled. 1: 01 - Run trip detect test on AReg1Cap. 10: 10 - Run trip detect test on AReg2Cap. 11: 11 - Run trip detect test on DRegCap. [5] RESET_DETECT_EN (R/W) Reset detect enable [4] RESERVED [3:2] LDO_PSM_test_EN (R/W) LDO PSM test EN 0: 00 - No power supply m onitor test enabled. 1: 01 - Run power supply m onitor test on ARegxCap. 10: 10 - Run power supply m onitor test on DRegCap. 11: 11 - Run power supply m onitor test on all LDOs. Table 135. Bit Descriptions for GEN_ERR_REG_2_EN Bits Bit Name 5 RESET_DETECT_EN Reset Detect Enable 0x1 R/W 4 RESERVED Reserved 0x1 R/W [3:2] LDO_PSM_TEST_EN LDO PSM Test EN 0x3 R/W 0x0 R/W [1:0] Settings Description 0 00—no power supply monitor test enabled. 1 01—run power supply monitor test on AREGxCAP 10 10—run power supply monitor test on DREGCAP 11 11—run power supply monitor test on all LDOs LDO_PSM_TRIP_TEST_EN LDO PSM Trip Test Enable 0 00—no trip detect test enabled 1 01—run trip detect test on AREG1CAP 10 10—run trip detect test on AREG2CAP 11 11—run trip detect test on DREGCAP Rev. 0 | Page 93 of 97 AD7779 Data Sheet ERROR STATUS REGISTER 1 Address: 0x05D, Reset: 0x00, Name: STATUS_REG_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ERR_LOC_CH0 (R) An error specific to CH0_ERR_REG is active [5] CHIP_ERROR (R) Set high if any error bit is high [1] ERR_LOC_CH1 (R) An error specific to CH1_ERR_REG is active [4] ERR_LOC_CH4 (R) An error specific to CH4_ERR_REG is active [2] ERR_LOC_CH2 (R) An error specific to CH2_ERR_REG is active [3] ERR_LOC_CH3 (R) An error specific to CH3_ERR_REG is active Table 136. Bit Descriptions for STATUS_REG_1 Bits Bit Name 5 Settings Description Reset Access CHIP_ERROR Set this bit high if any error bit is high 0x0 R 4 ERR_LOC_CH4 An error specific to CH4_ERR_REG is active 0x0 R 3 ERR_LOC_CH3 An error specific to CH3_ERR_REG is active 0x0 R 2 ERR_LOC_CH2 An error specific to CH2_ERR_REG is active 0x0 R 1 ERR_LOC_CH1 An error specific to CH1_ERR_REG is active 0x0 R 0 ERR_LOC_CH0 An error specific to CH0_ERR_REG is active 0x0 R ERROR STATUS REGISTER 2 Address: 0x05E, Reset: 0x00, Name: STATUS_REG_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ERR_LOC_CH5 (R) An error specific to CH5_ERR_REG is active [5] CHIP_ERROR (R) Set high if any error bit is high [4] ERR_LOC_GEN2 (R) An error specific to GEN_ERR_REG_2 is active [3] ERR_LOC_GEN1 (R) An error specific to GEN_ERR_REG_1 is active [1] ERR_LOC_CH6 (R) An error specific to CH6_ERR_REG is active [2] ERR_LOC_CH7 (R) An error specific to CH7_ERR_REG is active Table 137. Bit Descriptions for STATUS_REG_2 Bits Bit Name 5 Settings Description Reset Access CHIP_ERROR Set high if any error bit is high 0x0 R 4 ERR_LOC_GEN2 An error specific to GEN_ERR_REG_2 is active 0x0 R 3 ERR_LOC_GEN1 An error specific to GEN_ERR_REG_1 is active 0x0 R 2 ERR_LOC_CH7 An error specific to CH7_ERR_REG is active 0x0 R 1 ERR_LOC_CH6 An error specific to CH6_ERR_REG is active 0x0 R 0 ERR_LOC_CH5 An error specific to CH5_ERR_REG is active 0x0 R Rev. 0 | Page 94 of 97 Data Sheet AD7779 ERROR STATUS REGISTER 3 Address: 0x05F, Reset: 0x00, Name: STATUS_REG_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ERR_LOC_SAT_CH0_1 (R) An error specific to CH0_1_SAT_ERR reg is active [5] CHIP_ERROR (R) Set high if any error bit is high [1] ERR_LOC_SAT_CH2_3 (R) An error specific to CH2_3_SAT_ERR reg is active [4] INIT_COMPLETE (R) Fuse initialization is complete. Device is ready to receive commands [2] ERR_LOC_SAT_CH4_5 (R) An error specific to CH4_5_SAT_ERR reg is active [3] ERR_LOC_SAT_CH6_7 (R) An error specific to CH6_7_SAT_ERR reg is active Table 138. Bit Descriptions for STATUS_REG_3 Bits Bit Name 5 Settings Description Reset Access CHIP_ERROR Set high if any error bit is high. 0x0 R 4 INIT_COMPLETE Fuse initialization is complete. Device is ready to receive commands. 0x0 R 3 ERR_LOC_SAT_CH6_7 An error specific to CH6_7_SAT_ERR register is active. 0x0 R 2 ERR_LOC_SAT_CH4_5 An error specific to CH4_5_SAT_ERR register is active. 0x0 R 1 ERR_LOC_SAT_CH2_3 An error specific to CH2_3_SAT_ERR register is active. 0x0 R 0 ERR_LOC_SAT_CH0_1 An error specific to CH0_1_SAT_ERR register is active. 0x0 R DECIMATION RATE (N) MSB REGISTER Address: 0x060, Reset: 0x00, Name: SRC_N_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [3:0] SRC_N_ALL[11:8] (R/W) SRC N Com bined [7:4] RESERVED Table 139. Bit Descriptions for SRC_N_MSB Bits Bit Name [3:0] SRC_N_ALL[11:8] Settings Description Reset Access SRC N Combined 0x0 R/W Description Reset Access SRC N Combined 0x0 R/W DECIMATION RATE (N) LSB REGISTER Address: 0x061, Reset: 0x80, Name: SRC_N_LSB 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] SRC_N_ALL[7:0] (R/W) SRC N Com bined Table 140. Bit Descriptions for SRC_N_LSB Bits Bit Name [7:0] SRC_N_ALL[7:0] Settings Rev. 0 | Page 95 of 97 AD7779 Data Sheet DECIMATION RATE (IF) MSB REGISTER Address: 0x062, Reset: 0x00, Name: SRC_IF_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SRC_IF_ALL[15:8] (R/W) SRC IF ALL Table 141. Bit Descriptions for SRC_IF_MSB Bits Bit Name [7:0] SRC_IF_ALL[15:8] Settings Description Reset Access SRC IF All 0x0 R/W Description Reset Access SRC IF All 0x0 R/W Description Reset Access DECIMATION RATE (IF) LSB REGISTER Address: 0x063, Reset: 0x00, Name: SRC_IF_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SRC_IF_ALL[7:0] (R/W) SRC IF ALL Table 142. Bit Descriptions for SRC_IF_LSB Bits Bit Name [7:0] SRC_IF_ALL[7:0] Settings SRC LOAD SOURCE AND LOAD UPDATE REGISTER Address: 0x064, Reset: 0x00, Name: SRC_UPDATE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SRC_LOAD_SOURCE (R/W) Select which option to load an SRC update [0] SRC_LOAD_UPDATE (R/W) Ass ert bit to load SRC registers into SRC [6:1] RESERVED Table 143. Bit Descriptions for SRC_UPDATE Bits Bit Name Settings 7 SRC_LOAD_SOURCE Selects which option to load an SRC update 0x0 R/W 0 SRC_LOAD_UPDATE Asserts bit to load SRC registers into SRC 0x0 R/W Rev. 0 | Page 96 of 97 Data Sheet AD7779 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 49 1 0.50 BSC EXPOSED PAD 7.70 7.60 SQ 7.50 33 TOP VIEW 0.80 0.75 0.70 16 32 17 BOTTOM VIEW 7.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE PKG-004396 0.45 0.40 0.35 PIN 1 INDICATOR 64 48 COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 0.20 MIN 02-12-2014-A PIN 1 INDICATOR Figure 120. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm × 9 mm Body and 0.75 mm Package Height (CP-64-15) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7779ACPZ AD7779ACPZ-RL 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] Z = RoHs Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13295-0-2/16(0) Rev. 0 | Page 97 of 97 Package Option CP-64-15 CP-64-15