IPD03N03LB G OptiMOS®2 Power-Transistor Product Summary Features • Ideal for high-frequency dc/dc converters 1) • Qualified according to JEDEC for target applications V DS 30 V R DS(on),max 3.3 mΩ ID 90 A • N-channel, logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance PG-TO252-3-11 • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Type Package Ordering Code Marking IPD03N03LB G P-TO252-3-11 Q67042-S4260 03N03LB Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C2) 90 T C=100 °C 90 Pulsed drain current I D,pulse T C=25 °C3) 360 Avalanche energy, single pulse E AS I D=90 A, R GS=25 Ω 240 Reverse diode dv /dt dv /dt I D=90 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C 6 Gate source voltage4) V GS Power dissipation P tot Operating and storage temperature T j, T stg T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.11 Unit A mJ kV/µs ±20 V 115 W -55 ... 175 °C 55/175/56 page 1 2004-12-16 IPD03N03LB G Parameter Values Symbol Conditions Unit min. typ. max. - - 1.3 minimal footprint - - 75 6 cm2 cooling area5) - - 50 Thermal characteristics Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=70 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=30 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=30 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=60 A - 3.9 4.9 mΩ V GS=10 V, I D=60 A - 2.8 3.3 - 1.3 - Ω 60 120 - S Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=60 A 1) J-STD20 and JESD22 1) Current is limited by bondwire; with an R thJC=1.3 K/W the chip is able to carry 142 A. 3) See figure 3 4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V 5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.11 page 2 2004-12-16 IPD03N03LB G Parameter Values Symbol Conditions Unit min. typ. max. - 3900 5200 - 1400 1900 Dynamic characteristics Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 180 270 Turn-on delay time t d(on) - 13 19 Rise time tr - 9 14 Turn-off delay time t d(off) - 41 61 Fall time tf - 6.2 9 Gate to source charge Q gs - 12 16 Gate charge at threshold Q g(th) - 6.3 8.3 Gate to drain charge Q gd - 7.9 12 Switching charge Q sw - 14 20 Gate charge total Qg - 30 40 Gate plateau voltage V plateau - 3.1 - Gate charge total, sync. FET Q g(sync) V DS=0.1 V, V GS=0 to 5 V - 27 35 Output charge Q oss V DD=15 V, V GS=0 V - 31 42 - - 90 - - 420 V GS=0 V, V DS=15 V, f =1 MHz V DD=15 V, V GS=10 V, I D=45 A, R G=2.7 Ω pF ns Gate Charge Characteristics6) V DD=15 V, I D=45 A, V GS=0 to 5 V nC V nC Reverse Diode Diode continous forward current IS Diode pulse current I S,pulse Diode forward voltage V SD V GS=0 V, I F=90 A, T j=25 °C - 0.92 1.2 V Reverse recovery charge Q rr V R=15 V, I F=I S, di F/dt =400 A/µs - - 10 nC 6) T C=25 °C A See figure 16 for gate charge parameter definition Rev. 1.11 page 3 2004-12-16 IPD03N03LB G 1 Power dissipation 2 Drain current P tot=f(T C) I D=f(T C); V GS≥10 V 120 100 100 80 80 I D [A] P tot [W] 60 60 40 40 20 20 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 1000 10 1 µs limited by on-state resistance 10 µs 1 100 µs 0.5 100 0.2 Z thJC [K/W] DC I D [A] 1 ms 10 0.1 0.1 0.05 0.02 0.01 10 ms single pulse 0.01 1 0.1 1 10 100 V DS [V] Rev. 1.11 0.001 0 0 -6 10 0 -5 10 0 -4 10 0 -3 10 0 -2 10 1 -1 10 100 t p [s] page 4 2004-12-16 IPD03N03LB G 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 12 200 4.5 V 10 V 180 4.1 V 3V 140 R DS(on) [mΩ] 120 100 3.5 V 80 3.5 V 8 3.8 V I D [A] 3.2 V 10 160 6 3.8 V 4.1 V 4.5 V 4 60 3.2 V 10 V 40 2 3V 20 2.8 V 0 0 0 1 2 0 3 20 V DS [V] 40 60 80 100 I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 200 180 180 160 160 140 140 120 g fs [S] I D [A] 120 100 80 80 60 60 40 40 175 °C 20 20 25 °C 0 0 0 1 2 3 4 5 0 20 40 60 80 100 I D [A] V GS [V] Rev. 1.11 100 page 5 2004-12-16 IPD03N03LB G 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=60 A; V GS=10 V V GS(th)=f(T j); V GS=V DS parameter: I D 7 2.5 6 2 5 4 V GS(th) [V] R DS(on) [mΩ] 700 µA 98 % typ 3 1.5 70 µA 1 2 0.5 1 0 0 -60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 1000 10000 25 °C, 98% Ciss 175 °C, 98% 100 25 °C 175 °C I F [A] C [pF] Coss 1000 10 Crss 100 1 0 5 10 15 20 25 30 V DS [V] Rev. 1.11 0.0 0.5 1.0 1.5 2.0 V SD [V] page 6 2004-12-16 IPD03N03LB G 13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 Ω V GS=f(Q gate); I D=45 A pulsed parameter: T j(start) parameter: V DD 100 12 100 °C 25 °C 15 V 10 5V 20 V 150 °C V GS [V] I AV [A] 8 10 6 4 2 1 0 1 10 100 1000 0 20 40 60 80 Q gate [nC] t AV [µs] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=1 mA 38 V GS 36 Qg 34 V BR(DSS) [V] 32 30 28 V g s(th) 26 24 Q g (th) 22 Q sw Q gs 20 -60 -20 20 60 100 140 Q gate Q gd 180 T j [°C] Rev. 1.11 page 7 2004-12-16 IPD03N03LB G Package Outline P-TO252-3-11: Outline Footprint: Packaging: Dimensions in mm Rev. 1.11 page 8 2004-12-16 IPD03N03LB G Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Straße 53 D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. 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Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.11 page 9 2004-12-16