INFINEON SAB83C517A-5N18-T3

Microcomputer Components
SAB 80C517A/83C517A-5
8-Bit CMOS Single-Chip Microcontroller
Addendum to User's Manual SAB 80C517/80C537 05.94
Edition 05.94
This edition was realized using the software
system FrameMaker.
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
© Siemens AG 1994.
All Rights Reserved.
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characteristics.
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reserved.
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Critical components1 of the Semiconductor
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SAB 80C517A/83C517A-5
Revision History:
05.94
Previous Version:
11.92
Page
Subjects (major changes since last revision 11.92)
3-8
4-1
5-3
5-10/5-11
S0RELL adresses corrected
HWPD pin number corrected
TS/TC in table 5-1 corrected
CC4EN bit names and table 5-3 corrected
Device Specifications SAB 80C517A/83C517A-5
Revision History:
05.94
Previous Releases:
01.94/08.93/11.92/10.91/04.91
Page
Subjects (changes since last revision 04.91)
5
4
6-14
several
2
25,26,30
33
39
57
60
62
65
several
66
68
Pin configuration P-MQFP-100-2 added
Pin differences updated
Pin numbers for P-MQFP-100-2 package added
Correction of P-MRFP-100 into P-MQFP-100-2
Ordering information for – 40 to + 110 °C versions
Correction of register names S0RELL, SCON, ADCON, ICRON and SBUF
Figure 4 corrected
Figure 8 corrected
PE/SWD function description completed
Correct ordering numbers
Test condition for VOH, VOH1 corrected
tPXIZ name corrected
tAVIV, tAZPL values corrected
Minimum clock frequence is now 3.5 MHz
tQVWH (data setup before WR) corrected and added
tLLAX2 corrected
Page
Subjects (changes since last version 08.93)
25
51
65
67
74
Corrected SFR name S0RELL
Below “Termination of HWPD Mode”: 4th paragraph with ident corrected
Description of tLLIV corrected
Program Memory Read Cycle: fPXAV added
Oscillator circuit drawings: MQFP-100-2 pin numbers added.
Page
Subjects (changes since last revision 01.94)
47
Minor changes on several pages
Table 6 corrected
80C517A/83C517A-5
Contents
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Program Memory, ROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Architecture for the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Accesses to XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Control of XRAM in the SAB 80C517A . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
4
4.1
4.2
4.3
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Additional Hardware Power Down Mode in the SAB 80C517A . . . . . . . . . . 4-1
Hardware Power Down Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Fast internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
5
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.5
On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Digital I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
10-bit A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Additional Compare Mode for the Concurrent Compare Unit . . . . . . . . . . . 5-8
New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 . . 5-14
Serial Channel 0 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Serial Channel 1 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Modified Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
6
6.1
6.2
6.3
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Additional Interrupt for Compare Registers CM0 to CM7 . . . . . . . . . . . . . . . 6-1
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
7
Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Semiconductor Group
Introduction
1
Introduction
The SAB 80C517A is a superset of the high end microcontroller SAB 80C517.
While maintaining all architectural and operational characteristics of the SAB 80C517 the
SAB 80C517A incorporates more on-chip RAM as well as some enhancements in the compare /
capture unit. The oscillator watchdog got an improved functionality. Also the operating frequency is
higher than that of the SAB 80C517.
SAB 80C517A / 83C517A-5
In this manual, any reference made to the SAB 80C517A applies to both versions, the
SAB 80C517A and the SAB 83C517A-5, unless otherwise noted. Furthermore only new features of
the SAB 80C517A in addition to the features of the SAB 80C517A/83C517A-5 are described. For
additional reference, the user’s manual of the SAB 80C517/80C537 (Ord. No. B258-H6075-G1-X7600) should be used.
Semiconductor Group
1-1
Introduction
Listed below is a summary of the main features of the SAB 80C517A:
● SAB 80C517A/83C517A-5, up to
●
●
●
●
●
●
●
● Fast 32-bit division, 16-bit multiplication, 32-
18 MHz operation frequency
32 K×8 ROM (SAB 83C517A-5 only, ROMProtection available)
256×8 on-chip RAM
2K×8 on-chip RAM (XRAM)
Superset of SAB 80C51 architecture:
– 1 µs instruction cycle time at 12 MHz
– 666 ns instruction cycle time at 18 MHz
– 256 directly addressable bits
– Boolean processor
– 64 Kbyte external data and program
memory addressing
Four 16-bit timer/counters
Powerful 16-bit compare/capture unit (CCU)
with up to 21 high-speed or PWM output
channels and 5 capture inputs
Versatile "fail-safe" provisions
●
●
●
●
●
●
●
●
●
●
bit normalize and shift by peripheral MUL/
DIV unit (MDU)
Eight data pointers for external memory
addressing
Seventeen interrupt vectors, four priority
levels selectable
genuine 10-bit A/D converter with 12
multiplexed inputs
Two full duplex serial interfa ce s with
programmable Baudrate-Generators
Fully upward compatible with SAB 80C515,
SAB 80C517, SAB 80C515A
Extended power saving modes
Fast Power-On Reset
Nine ports: 56 I/O lines, 12 input lines
Three temperature ranges available:
0 to 70 °C
(T1)
– 40 to + 85 °C
(T3)
– 40 to + 110 °C
(T4)
Plastic packages: P-LCC-84
P-MQFP-100-2
The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with one
exception:
Package
SAB 80C517A
SAB 80C517 / 80C537
HWPD
VSS
PLCC-84/60
PMRFP-100/72
Semiconductor Group
1-2
Fundamental Structure
2
Fundamental Structure
The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of
microcontrollers. It is designed in Siemens ACMOS technology and based on the SAB 8051
architecture. ACMOS is a technology which combines high-speed and density characteristics with
low-power consumption or dissipation.
While maintaining all the SAB 80C517 features and operating characteristics the SAB 80C517A is
expanded in its "fail-safe" characteristics and timer capabilities.
Furthermore, the SAB 80C517A additionally contains 2 kByte of on-chip RAM (called XRAM), a
10bit A/D converter with 12 multiplexed inputs, enhanced Baud Rate Generators and the
capabilities of the Compare Capture Unit are improved.
The SAB 80C517A is identical with the SAB 83C517A-5 except that it lacks the on-chip program
memory. The SAB 80C517A / 83C517A-5 is supplied in a 84-pin plastic leaded chip carrier package
(P-LCC-84) and in a 100-pin plastic metric rectangular flat package (P-MRFP-100).
The essential enhancements to the SAB 80C517 are:
–
–
–
–
–
–
–
–
–
–
Additional 2KByte RAM on chip.
32 kByte on-chip program memory (SAB 83C517A-5 only)
12-channel 10-bit A/D Converter
Additional Compare Mode for Concurrent Compare function at Port 5; up to eight pins on P5
can be either set or reset on a compare match in two additional compare registers.
Dedicated interrupt vector for the 16-bit compare registers CM0-CM7: Interrupt requested on
a compare match in one of the eight compare channels (eight request flags are available)
New baud rate generator for Serial Channel 0
Expanded baud rate range for Serial Channel 1
Hardware controlled Power Down Mode
Improved functionality of the Oscillator Watchdog
High speed operation of the device (up to 18 MHz crystal frequency)
Figure 2-1 shows a block diagram of the SAB 80C517A
Semiconductor Group
2-1
Fundamental Structure
Figure 2-1, Block Diagram of the SAB 80C517A
Semiconductor Group
2-2
Memory Organization
3
Memory Organization
According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces for
program and data memory. Figure 3-1 illustrates the mapping of address spaces.
Figure 3-1
Memory Map
Semiconductor Group
3-1
Memory Organization
3.1
Program Memory, ROM Protection
The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal
ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whether
program fetches below address 8000H are done from internal or external memory.
As a new feature the SAB 83C517A-5 offers the possibillity of protecting the internal ROM against
unauthorized access. This protection is implemented in the ROM-Mask. Therefore, the decision
ROM-Protection ’yes’ or ’no’ has to be made when delivering the ROM-Code. Once enabled, there
is no way of disabling the ROM-Protection.
Effect : The access to internal ROM done by an externally fetched MOVC instruction is disabled.
Nevertheless, an access from internal ROM to external ROM is possible.
To verify the read protected ROM-Code a special ROM-Verify-Mode is implemented. This mode
also can be used to verify unprotected internal ROM.
ROM-Protection
ROM-Verification Mode
(see ’AC Characteristics’)
no
ROM-Verification Mode 1
–
(standard 8051 Verification Mode)
ROM-Verification Mode 2
yes
ROM-Verification Mode 2
Semiconductor Group
3-2
Restrictions
– standard 8051 Verification
Mode is disabled
– externally applied MOVC
accessing to internal ROM
is disabled
Memory Organization
3.2
Data Memory
The data memory space consists of an internal and an external memory space. The SAB 80C517A
contains another 2 kByte of On-Chip RAM above the 256 Bytes internal RAM of the base type
SAB 80C517. This RAM is called XRAM in this document.
– External Data Memory
Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16bit indirect addressing. For 8-bit addressing MOVX instructions in combination with registers
R0 and R1 can be used. A 16-bit external memory addressing is supported by eight 16-bit
datapointers. Registers XPAGE and SYSCON are controlling whether data fetches at
addresses F800H to FFFFH are done from internal XRAM or from external data memory.
– Internal Data Memory
The internal data memory is divided into four physically distinct blocks:
– the lower 128 bytes of RAM including four banks containing eight registers each
– the upper 128 byte of RAM
– the 128 byte special function register area
– a 2Kx8 area which is accessed like external RAM (MOVX-instructions), called XRAM
implemented on chip at the address range fromF800H to FFFFH. Special Function
Register SYSCON controls whether data is read or written (to) XRAM or external RAM
Semiconductor Group
3-3
Memory Organization
3.3
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the
special function register area. The 81 special function registers include arithmetic registers,
pointers, and registers that provide an interface between the CPU and the on-chip peripherals.
There are also 128 directly addressable bits within the SFR area. All special function registers are
listed in table 3-1 and table 3-2.
In table 3-1 they are organized in numeric order of their addresses. In table 3-2 they are organized
in groups which refer to the functional blocks of the SAB 80C517A.
Table 3-1, Special Function Register
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
80H
81H
82H
83H
84H
85H
86H
87H
P0 1)
SP
DPL
DPH
(WDTL)
(WDTH)
WDTREL
PCON
FFH
07H
00H
00H
–
–
00H
00H
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
P2 1)
COMSETL
COMSETH
COMCLRL
COMCLRH
SETMSK
CJRMSK
–
FFH
00H
00H
00H
00H
00H
00H
–
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
TCON 1)
TMOD
TL0
TL1
TH0
TH1
–
–
00H
00H
00H
00H
00H
00H
–
–
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
IEN0 1)
IP0
SORELL
–
–
–
–
–
00H
00H
D9H
–
–
–
–
–
90H
91H
92H
93H
94H
95H
96H
97H
P1 1)
XPAGE
DPSEL
–
–
–
–
–
FFH
00H
XXXXX000B
–
–
–
–
–
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
P3 1)
SYSCON
–
–
–
–
–
–
FFH
XXXX XX01B
–
–
–
–
–
–
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
S0CON 1)
S0BUF
IEN2
S1CON
S1BUF
S1RELL
–
–
00H
XXH
XX00 00X0B
0X00 0000B
XXH
00H
–
–
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
IEN1 1)
IP1
S0RELH
S1RELH
–
–
–
–
00H
XX00 0000B
XXXX XX11B
XXXX XX11B
–
–
–
–
1) : Bit-addressable Special Function Register
Semiconductor Group
3-4
Memory Organization
Table 3-1, Special Function Register (cont´d)
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
IRCON0 1)
CCEN
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
00H
00H
00H
00H
00H
00H
00H
00H
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
ACC 1)
CTCON
CML3
CMH3
CML4
CMH4
CML5
CMH5
00H
0X00 0000B
00H
00H
00H
00H
00H
00H
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
T2CON 1)
CC4EN
CRCL
CRCH
TL2
TH2
CCL4
CCH4
00H
00H
00H
00H
00H
00H
00H
00H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
P4 1)
MD0
MD1
MD2
MD3
MD4
MD5
ARCON
FFH
XXH
XXH
XXH
XXH
XXH
XXH
0XXX XXXXB
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
PSW 1)
IRCON1
CML0
CMH0
CML1
CMH1
CML2
CMH2
00H
00H
00H
00H
00H
00H
00H
00H
F0
F1H
F2H
F3H
F4H
F5H
F6H
F7H
B 1)
–
CML6
CMH6
CML7
CMH7
CMEN
CMSEL
00H
–
00H
00H
00H
00H
00H
00H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
ADCON0 1)
ADDATH
ADDATL
P7
ADCON1
P8
CTRELL
CTRELH
00H
00H
00H
XXH
XXXX 0000B
XXH
00H
00H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
P5 1)
–
P6
–
–
–
–
–
FFH
–
FFH
–
–
–
–
–
1) : Bit-addressable Special Function Register
Semiconductor Group
3-5
Memory Organization
Table 3-1, Special Function Register (cont´d)
Block
Symbol
Name
XRAM
XPAGE
Address
Contents after
Reset
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
Page Address. Reg. for extended onchip 91H
RAM
XRAM Control Reg.
B1H
E0H 1)
Accumulator
B-Register
F0H 1)
Data Pointer, High Byte
83H
Data Pointer, Low Byte
82H
Data Pointer Select Register
92H
Program Status Word Register
D0H 1)
Stack Pointer
81H
A/DConverter
ADCON0
ADCON1
ADDATH
ADDATL
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register High Byte
A/D Converter Data Register Low Byte
D8H 1)
DH
D9H
DAH
00H
00H
00H
00H
Interrupt
System
IEN0
CTCON 2)
IEN1
IEN2
IP0
IP1
IRCON0
IRCON1
TCON 2)
T2CON 2)
Interrupt Enable Register 0
Com. Timer Control Register
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register
Interrupt Request Control Register
Timer Control Register
Timer 2 Control Register
A8H 1)
E1H
B8H 1)
9AH
A9H
B9H
C0H 1)
D1H
88H 1)
0C8H 1)
00H
0X00 0000B3)
00H
XX00 00X0B 3)
00H
XX00 0000B
00H
00H
00H
00H
MUL/DIV
Unit
ARCON
MD0
MD1
MD2
MD3
MD4
MD5
Arithmetic Control Register
Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5
EFH
E9H
EAH
EBH
ECH
EDH
EEH
0XXX XXXXB
XXH
XXH
XXH
XXH
XXH
XXH
Compare/
CaptureUnit
(CCU),
Timer2
CCEN
CC4EN
CCH1
CCH2
CCH3
CCH4
CCL1
Comp./Capture Enable Reg.
Comp./Capture 4 Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 4, High Byte
Comp./Capture Reg. 1, Low Byte
C1H
C9H
C3H
C5H
C7H
CFH
C2H
00H
00H
00H
00H
00H
00H
00H
SYSCON
00H
XXXX XX01B3)
00H
00H
00H
00H
XXXXX000B 3)
00H
07H
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate
Semiconductor Group
3-6
Memory Organization
Table 3-1, Special Function Register
Block
Symbol
Name
Address
Contents after
Reset
Compare/
CaptureUnit (CCU)
(cont´d)
CCL2
CCL3
CCL4
CMEM
CMH0
CMH1
CMH2
CMH3
CMH4
CMH5
CMH6
CMH7
CML0
CML1
CML2
CML3
CML4
CML5
CML6
CML7
CMSEL
CRCH
CRCL
COMSETL
COMSETH
COMCLRL
COMCLRH
SETMSK
CLRMSK
CTCON
CTRELH
CTRELL
TH2
TL2
T2CON
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Comp./Capture Reg. 4, Low Byte
Compare Enable Register
Compare Reg. 0, High Byte
Compare Reg. 1, High Byte
Compare Reg. 2, High Byte
Compare Reg. 3, High Byte
Compare Reg. 4, High Byte
Compare Reg. 5, High Byte
Compare Reg. 6, High Byte
Compare Reg. 7, High Byte
Compare Register 0, Low Byte
Compare Register 1, Low Byte
Compare Register 2, Low Byte
Compare Register 3, Low Byte
Compare Register 4, Low Byte
Compare Register 5, Low Byte
Compare Register 6, Low Byte
Compare Register 7, Low Byte
Compare Input Select
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Compare register, Low Byte
Compare register, High Byte
Compare register, Low Byte
Compare register, High Byte
mask register, concerning COMSET
mask register, concerning COMCLR
Com. Timer Control Reg.
Com. Timer Rel. Reg., High Byte
Com. Timer Rel. Reg., Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
C4H
C6H
CEH
F6H
D3H
D5H
D7H
E3H
E5H
E7H
F3H
F5H
D2H
D4H
D6H
E2H
E4H
E6H
F2H
F4H
F7H
CBH
CAH
A1H
A2H
A3H
A4H
A5H
A6H
E1H
DFH
DEH
CDH
CCH
C8H 1)
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0X00 0000B 3)
00H
00H
00H
00H
00H
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate
Semiconductor Group
3-7
Memory Organization
Table 3-1, Special Function Register
Block
Symbol
Name
Address
Contents after
Reset
Ports
P0
P1
P2
P3
P4
P5
P6
P7
P8
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7, Analog/Digital Input
Port 8, Analog/Digital Input, 4-bit
80H 1)
90H 1)
A0H 1)
B0H 1)
E8H 1)
F8H 1)
FAH
DBH
DDH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
–
–
Pow. Save
Modes
PCON
Power Control Register
87H
00H
Serial
Channels
ADCON0 2)
PCON 2)
S0BUF
S0CON
S0RELL
S0RELH
S1BUF
S1CON
S1RELL
S1RELH
A/D Converter Control Reg.
Power Control Register
Serial Channel 0 Buffer Reg.
Serial Channel 0 Control Reg.
Serial Channel 0 Reload Reg., low byte
Serial Channel 0 Reload Reg., high byte
Serial Channel 1 Buffer Reg.
Serial Channel 1 Control Reg.
Serial Channel 1 Reload Reg., low byte
Serial Channel 1 Reload Reg., high byte
D8H 1)
87H
99H
98H 1)
0AAH
BAH
9CH
9BH
9DH
BBH
00H
00H
XXH
00H
D9H
XXXX XX11B3)
XXH 3)
0X00 0000B 3)
00H
XXXX XX11B 3)
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Watchdog
IEN0 2)
IEN1 2)
IP0 2)
IP1 2)
WDTREL
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Watchdog Timer Reload Reg.
A8H 1)
B8H 1)
A9H
B9H
86H
00H
00H
00H
XX00 0000B 3)
00H
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate
Semiconductor Group
3-8
Memory Organization
3.4
Architecture for the XRAM
The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the
contents is undefined, while it remains unchanged during and after a reset or HW Power Down if
the power supply is not turned off.
The additional On-Chip RAM is logically located in the "external data memory" range at the upper
end of the 64 KByte address range (F800H-FFFFH). It is possible to enable and disable (only by
reset) the XRAM. If it is disabled the device shows the same behaviour as the parts without XRAM,
i.e. all MOVX accesses use the external bus to physically external data memory.
3.4.1 Accesses to XRAM
Because the XRAM is used in the same way as external data memory the same instruction types
must be used for accessing the XRAM.
Note:
If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the cycle which
the reset is detected at (MOVX is a 2-cycle instruction):
Reset detection at cycle 1: The new value will not be written to XRAM. The old value is not
affected.
Reset detection at cycle 2: The old value in XRAM is overwritten by the new value.
Accesses to XRAM using the DPTR
There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR for
indirect addressing. The instructions are:
MOVX
A, @DPTR
(Read)
MOVX
@DPTR, A
(Write)
Normally the use of these instructions would use a physically external memory. However, in the
SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address
space (DPTR ≥ F800H).
Semiconductor Group
3-9
Memory Organization
Accesses to XRAM using the Registers R0/R1
The 8051 architecture provides also instructions for access to external data memory range which
use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are:
MOVX
A, @ Ri
(Read)
MOVX
@Ri, A
(Write)
In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as page
register which selects pages of 256-Byte. However, the distinction, whether Port 2 is used as
general purpose I/0 or as "page address" is made by the external system design. From the device’s
point of view it cannot be decided whether the Port 2 data is used externally as address or as I/0
data!
Hence, a special page register is implemented into the SAB 80C517A to provide the possibility of
accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same function
for the XRAM as Port 2 for external data memory.
Special Function Register XPAGE
Bit No.
MSB
7
6
5
4
Addr. 91H
3
2
1
LSB
0
XPAGE
The reset value of XPAGE is 00H.
XPAGE can be set and read by software.
Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain
the differencies in accessing XRAM, ext. RAM or what is to do when Port 2 is used as an I/O-port.
Semiconductor Group
3 - 10
Memory Organization
Figure 3-2
Write Page Address to Port 2
MOV P2, pageaddress will write the page address to Port 2 and XPAGE-Register.
When external RAM is to be accessed in the XRAM address range (F800H - FFFFH) XRAM has to
be disabled. When additional external RAM is to be addressed in an address range ≤ XRAM
(F800H) XRAM may remain being enabled and there is no need to overwrite XPAGE by a second
move.
Semiconductor Group
3 - 11
Memory Organization
Figure 3-3
Write Page Address to XPAGE
The page address is only written to XPAGE-register. Port 2 is available for addresses or I/O-Data.
See figure 3-4 to see what happens when Port 2 is used as I/O-Port.
Semiconductor Group
3 - 12
Memory Organization
Figure 3-4
Use of Port 2 as I/O-Port
At a write to Port 2, XRAM address in XPAGE-register will be overwritten because of the concurrent
write to Port 2 and XPAGE-register. So whenever XRAM is used and the XRAM address differs
from the byte written to Port 2 latch it is absolutely nessesary to rewrite XPAGE with page address.
Example:
I/O-Data at Port 2 shall be 0AAH. A Byte shall be fetched from XRAM at address 0F830H
MOV R0, #30H
MOV P2, #0AAH
MOV XPAGE, #0F8H
MOVX A, @R0
Semiconductor Group
; P2 shows 0AAH
; P2 still shows 0AAH but XRAM is addressed
; the contents of XRAM at 0F830H is moved to accu
3 - 13
Memory Organization
The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri
instructions. If the address formed from XPAGE and Ri is less than the XRAM address range, then
an external access is performed. For the SAB 80C517A the contents of XPAGE must be greater or
equal than F8H in order to use the XRAM. Of course, the XRAM must be enabled if it shall be used
with MOVX @Ri instructions.
Thus, the register XPAGE is used for addressing of the XRAM; additionally its contents are used
for generating the internal XRAM select. If the contents of XPAGE is less than the XRAM address
range then an external bus access is performed where the upper address byte is provided by P2
and not by XPAGE!
Therefore, the software has to distinguish two cases, if the MOVX @Ri instructions with paging shall
be used:
a) Access to XRAM:
The upper address byte must be written to XPAGE or P2;
both writes selects the XRAM address range.
b) Access to external memory:
The upper address byte must be written to P2; XPAGE
will be loaded with the same address in order to deselect
the XRAM.
The behaviour of Port0, Port2 and the RD/WR signals depends on the state of pin EA and on the
control bits XMAP0 and XMAP1 in register SYSCON.
Semiconductor Group
3 - 14
Memory Organization
3.4.2 Control of XRAM in the SAB 80C517A
There are two control bits in register SYSCON which control the use and the bus operation during
^ XRAM).
accesses to the additional On-Chip RAM in XDATA range ( =
Special Function Register SYSCON
Bit No.
Addr. 0B1H
MSB
7
6
5
4
3
2
–
–
–
–
–
–
1
LSB
0
XMAP1 XMAP0 SYSCON
Bit
Function
XMAP0
Global enable/disable bit for XRAM memory.
XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.
XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are performed by
the external bus.
XMAP1
Control bit for RD/WR signals during accesses to XRAM; this bit has no effect if
XRAM is disabled (XMAP0 = 1) or if addresses outside the XRAM address range are
used for MOVX accesses.
XMAP1 = 0: The signals RD and WR are not activated during accesses to XRAM.
XMAP1 = 1: The signals RD and WR are activated during accesses to XRAM.
Reset value of SYSCON is XXXX XX01B.
The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM). If this
bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external bus. In
this case the SAB80C517A can’t use the additional On-Chip RAM and is compatible with the types
without XRAM.
Semiconductor Group
3 - 15
Memory Organization
A hardware protection is done by an unsymetric latch at XMAP0-bit. A unintentional disabling of
XRAM could be dangerous since indeterminate values could be read from external bus. To avoid
this the XMAP-bit is forced to ’1’ only by reset. Additional during reset an internal capacitor is loaded.
So the reset state is a disabled XRAM. Because of the load time of the capacitor XMAP0-bit once
written to ’0’ (that is, discharging capacitor) cannot be set to ’1’ again by software. On the other hand
any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the stable
status is XRAM enabled. The only way to disable XRAM after it was enabled is a reset.
The clear instruction for the XMAP0-bit should be integrated in the program initialization routine
before XRAM is used. In extremely noisy systems the user may have redundant clear instructions.
The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the external RD and
WR signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For debug
purposes it might be useful to have these signals available. This is performed if XMAP1 is set.
3.4.3 Behaviour of Port0 and Port2
The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA. The table 3-3 lists the various operating conditions. It shows
the following characteristics:
a) Use of P0 and P2 pins during the MOVX access.
Bus: The pins work as external address/data bus. If (internal) XRAM is accessed,
the data read from the XRAM can not be seen on the bus.
I/0:
The pins work as Input/Output lines under control of their latch.
b) Activation of the RD and WR pin during the access.
c) Use of internal or external XDATA memory.
The shaded areas describe the standard operation as each 80C51 device without on-chip XRAM
behaves.
Semiconductor Group
3 - 16
Semiconductor Group
3 - 17
a)P0/P2→Bus a)P0/P2→Bus a)P0/P2→I/O
(WR-Data only)
b)RD/WR active b)RD/WR active b)RD/WR
c)XRAM is used c) ext.memory
inactive
is used
c)XRAM is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
a)P0/P2→I/O
a)P0→Bus
(WR-Data only) P2→I/O
P2→I/O
b)RD/WR active b)RD/WR active b)RD/WR
inactive
c)XRAM is used c)ext.memory
c)XRAM is used
is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
(WR-Data only)
P2→I/O
b)RD/WR
inactive
c)XRAM is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
(WR-Data only)
b)RD/WR
inactive
c)XRAM is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
modes compatible to 8051-family
XPAGE
≥
XRAM
addr.page
range
XPAGE
<
XRAM
addr.page
range
00
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
Table 3-3: Behaviour of P0/P2 and RD/WR During MOVX Accesses
MOVX
@ Ri
DPTR
≥
XRAM
address
range
MOVX
DPTR
@DPTR <
XRAM
address
range
X1
10
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
X1
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
c)XRAM is used c)ext.memory
is used
a)P0→Bus
a)P0→Bus
(WR-Data only) P2→I/O
P2→I/O
b)RD/WR active b)RD/WR active
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus a)P0/P2→Bus
(WR-Data only)
b)RD/WR active b)RD/WR active
c)XRAM is used c) ext.memory
is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
10
XMAP1, XMAP0
XMAP1, XMAP0
00
EA = 1
EA = 0
Memory Organization
System Reset
4
System Reset
4.1
Additional Hardware Power Down Mode in the SAB 80C517A
The SAB 80C517A has an additional Power Down Mode which can be initiated by an external signal
at a dedicated pin. This pin is labeled HWPD and is a floating input line (active low). This pin
substitutes one of the VSS pins of the base types SAB 80C517 (PLCC84: Pin60; P-MQFP-100-2:
Pin36). Because this new power down mode is activated by an external hardware signal this mode
is referred to as Hardware Power Down Mode in opposite to the program controlled Software Power
Down Mode.
For a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its
internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE = High), if
the Hardware Power Down Mode shall be used. However, the control pin PE/SWD has no control
function for the Hardware Power Down Mode; it enables and disables only the use of all software
controlled power saving modes (Slow Down Mode, Idle Mode, Software Power Down Mode).
The function of the new Hardware Power Down Mode is as follows:
The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware Power
Down Mode; as mentioned above this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete internal
reset sequence. This takes two machine cycles; all pins have their default reset states during this
time. This reset has exactly the same effects as a hardware reset; i.e.especially the watchdog timer
is stopped and its status flag WDTS is cleared. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled, the on-chip
oscillator as well as the oscillator watchdog’s RC oscillator. At the same time the port pins and
several control lines enter a floating state as shown in table 4-1. In this state the power consumption
is reduced to the power down current IPD. Also the supply voltage can be reduced.
Table 4-1 also lists the voltages which may be applied at the pins during Hardware Power Down
Mode without affecting the low power consumption.
Semiconductor Group
4-1
System Reset
Table 4-1, Status of all Pins During Hardware Power Down Mode
Pins
Status
Voltage Range at Pin During
HW-Power Down
P0, P1, P2, P3, P4, Floating outputs /
P5, P6, P7, P8
Disabled input function
VSS ≤ VIN ≤ VCC
EA
active input
VIN = VCC or VIN = VSS
PE/SWD
active input, Pull-up resistor disabled VIN = VCC or VIN = VSS
during HW power down
XTAL1
active output
pin may not be driven
XTAL2
disabled input function
VSS ≤ VIN ≤VCC
PSEN, ALE
Floating outputs /
Disabled input function
(for test modes only)
VSS ≤ VIN ≤ VCC
VAREF, VAGND
active supply pins
VAGnd ≤ VIN ≤ VCC
OWE
active input; must be at high level for VIN = VCC
start-up after HW PD; pull up resistor or
disabled during HW-power down
(VIN = VSS)
Reset
active input; must be on high level if
HW PD is used
VIN = VCC
R0
Floating output
VSS ≤ VIN ≤ VCC
Semiconductor Group
4-2
System Reset
The power down state is maintained while pin HWPD is held active. If HWPD goes to high level
(inactive state) an automatic start up procedure is performed:
– First the pins leave their floating condition and enter their default reset state as they
had immediately before going to float state.
– Both oscillators are enabled (only if OWE = high). While the on-chip oscillator (with
pins XTAL1 and XTAL2) usually needs a longer time for start-up, if not externally driven (with
crystal approx. 1 ms), the oscillator watchdog's RC oscillator has a very short start-up time
(typ. less than 2 microseconds).
– Because the oscillator watchdog is active it detects a failure condition if the on-chip
oscillator hasn't yet started. Hence, the watchdog keeps the part in reset and supplies the
internal clock from the RC oscillator.
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases the
part from reset after it performed a final internal reset sequence and switches the clock supply
to the on-chip oscillator. This is exactly the same procedure as when the oscillator watchdog
detects first a failure and then a recovering of the oscillator during normal operation.
Therefore, also the oscillator watchdog status flag is set after restart from Hardware Power
Down Mode.
When automatic start of the watchdog was enabled (PE/SWD connected to V CC ), the
Watchdog Timer will start, too (with its default reload value for time-out period).
The SWD-Function of the PE/SWD Pin is sampled only by a hardware reset. Therefore at least one
Power On Reset has to be performed.
Semiconductor Group
4-3
System Reset
4.2
Hardware Power Down Reset Timing
Following figures are showing the timing diagrams for entering (figure 4-1) and leaving (figure 4-2)
the Hardware Power Down Mode. If there is only a short signal at pin HWPD (i.e. HWPD is sampled
active only once), then a complete internal reset is executed. Afterwards the normal program
execution starts again (figure 4-3).
Note:
Delay time caused by internal logic is not included.
The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active during
Hardware Power Down it is terminated and the device performs the normal reset function. Thus, pin
Reset has to be inactive during Hardware Power Down Mode.
Semiconductor Group
4-4
System Reset
Figure 4-1
Timing Diagram of Entering Hardware Power Down Mode
Semiconductor Group
4-5
System Reset
Figure 4-2
Timing Diagram of Leaving Hardware Power Down Mode
Semiconductor Group
4-6
System Reset
Figure 4-3
Timing Diagram of Hardware Power Down Mode, HWPD-Pin is Active for only one cycle
Semiconductor Group
4-7
System Reset
4.3
Fast internal Reset after Power-On
The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after
power-on.
Figure 4-4 shows the power-on sequence under control of the oscillator watchdog.
Normally the devices of the 8051 family (like the SAB 80C517) enter their default reset state not
before the on-chip oscillator starts. The reason is that the external reset signal must be internally
synchronized and processed in order to bring the device into the correct reset state. Especially if a
crystal is used the start up time of the oscillator is relatively long (typ. 1ms). During this time period
the pins have an undefined state which could have severe effects especially to actuators connected
to port pins.
In the SAB 80C517A the oscillator watchdog unit can avoid this situation. For doing this, the
oscillator watchdog must be enabled. In this case, after power-on the oscillator watchdog’s RC
oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the
following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has
not yet started (a failure is always recognized if the watchdog’s RC oscillator runs faster than the
on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output
as clock source for the chip rather than the on-chip oscillator’s output. This allows correct resetting
of the part and brings also all ports to the defined state (see figure 4-4, I). The time period from
power-on till reaching the reset state at the ports adds from the following terms:
– RC oscillator start-up
– synchronization of the RC oscillators divider-by-5
– synchronization of the state and cycle counters
– reset procedure till correct port states are reached
Delay between power-on and correct reset state:
Typ.: 18 µs
Max.: 34 µs
Semiconductor Group
4-8
< 2 µs
<6T
<6T
< 12T
System Reset
After the on-chip oscillator finally has started, the oscillator watchdog detects the correct function;
then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in
order to allow the oscillation of the on-chip oscillator to stabilize (figure 4-4, II). Subsequently the
clock is supplied by the on-chip oscillator and the oscillator watchdog’s reset request is released
(figure 4-4, III). However, an externally applied reset still remains (figure 4-4, IV) active and the
device does not start program execution (figure 4-4, V) before the external reset is also released.
Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply
the external reset signal when powering up. The reasons are as follows:
– Termination of Hardware Power Down Mode (a HWPD signal is overridden
by reset)
– Termination of Software Power Down Mode
– Reset of the status flag OWDS that is set by the oscillator watchdog during the
power up sequence.
The external reset signal must be hold active at least until the on-chip oscillator has started and the
internal watchdog reset phase is completed. An external reset time of more than 5 ms should be
sufficient in typical applications. If only a capacitor at pin Reset is used a value of 100 nF provides
the desired reset time.
Semiconductor Group
4-9
System Reset
Figure 4-4
Power-On of the SAB 80C517A
Semiconductor Group
4 - 10
On-Chip Peripheral Components
5
On-Chip Peripheral Components
5.1
Digital I/O Port Circuitry
To realize the Hardware Power Down Mode with floating Port pins in the SAB 80C517A/83C517A 5
the standard port structure used in the 8051 Family is modified (figure 5-1).
The FETs p4, p5 and n2 are added. During Hardware Power Down this FETs disconnect the port
pins from internal logic.
Figure 5-1
Port Structure
Semiconductor Group
5-1
On-Chip Peripheral Components
P1 and p3 are not active during Hardware Power Down.
P1 is activated only for two oscillator periods if a 0-to-1 transition is programmed to the port pin (not
possible during HWPD).
P3 is turned off during reset state (also HWPD).
For detailled description of the port structure please refer to the SAB 80C517/80C537 User’s
Manual.
Semiconductor Group
5-2
On-Chip Peripheral Components
5.2
10-bit A/D-Converter
In the SAB 80C517A is a new high performance / high speed 12-channel 10-bit A/D-Converter is
implemented. Its successive approximation techniqe provides 7 µs conversion time (fOSC=16 MHz).
The conversion principle is upward compatible to the one used in the SAB 80C517. The major
components are shown in figure 5-1.
The comparator is a fully differential comparator for a high power supply rejection ratio and very low
offset voltages. The capacitor network is binary weighted providing 10-bit resolution.
The table 5-1 below shows the sample time TS and the conversion time TC (including TS), which
depend on fOSC and the selected prescaler (see also Bit ADCL in SFR ADCON 1).
Table 5-1, ADC-Convertion Time
fOSC[MHz]
Prescaler
fADC[MHz]
TS [µs]
TC [µs]
(incl. TS)
12
÷8
1.5
1.33
8
÷ 16
0.75
2.8
16
÷8
2.0
2.0
7.0
÷ 16
1.0
4.0
14.0
÷8
–
–
–
÷ 16
1.125
3.555
12.4
16
18
Semiconductor Group
5-3
On-Chip Peripheral Components
Figure 5-1
10-Bit A/D-Converter
Semiconductor Group
5-4
On-Chip Peripheral Components
Special Function Registers ADCON0, ADCON1
Bit No.
MSB
7
6
5
4
3
2
1
LSB
0
Addr. 0D8H
BD
CLK
ADEX
BSY
ADM
MX2
MX1
MX0
Bit No.
MSB
7
6
5
4
3
2
1
LSB
0
MX3
MX2
MX1
MX0
Addr. 0DCH ADCL
ADCON0
ADCON1
These bits are not used in controlling A/D converter functions in the 80C517A
Bit
Function
ADEX
Internal / external start of conversion.
When set, the external start of conversion by P6.0 / ADST is enabled.
BSY
Busy flag.
This flag indicates whether a conversion is in progress (BSY = 1). The flag is
cleared by hardware when the conversion is finished.
ADM
A/D Conversion mode.
When set, a continous conversion is selected.
If cleared, the converter stops after one conversion.
MX3 - MX0
Select 12 input channels of the ADC.
Bits MX0 to MX2 con be written or read either in ADCON0 or in ADCON1.
ADCL
ADC Clock.
When set fADC = fOSC / 16. Has to be set when fOSC > 16 MHz
The reset value of ADCON0 and ADCON1 is 00H
Semiconductor Group
5-5
On-Chip Peripheral Components
Special Function Register ADDATH, ADDATL
Bit No.
MSB
7
Addr. 0D9H
msb
Bit No.
MSB
7
Addr. 0DAH
6
5
4
3
2
1
LSB
0
ADDATH
6
5
4
3
lsb
2
1
LSB
0
ADDATL
These bits are not used for conversion result
The reset value of ADDATH and ADDATL is 00H.
The registers ADDATH (0D9H) and ADDATL (0DAH) contain the 10-bit conversion result. The data
is read as two 8-bit bytes. Data is presented in left justified format (i.e. the msb is the most left-hand
bit in a 16-bit word). To get a 10-bit conversion result two READ operations are required. Otherwise
ADDATH contains the 8-bit conversion result.
Semiconductor Group
5-6
On-Chip Peripheral Components
A/D Converter Timing
After a conversion has been started (by a write to ADDATL, external start by P6.0/ADST or in
continous mode) the analog input voltage is sampled for 4 clock cycles. The analog source must be
capable of charging the capacitor network of appr. 50 pF to full accuracy in this time. During this
period the converter is susceptable to spikes and noise at the analog input, which may cause wrong
codes at the digital outputs. Therefore RC-filtering at the analog inputs is recommended (see figure
5-2 below).
Conversion of the sampled analog voltage takes place between the 4th an 14th clock cycle.
Figure 5-2
Recommended RC-filtering at the Analog Inputs
Semiconductor Group
5-7
On-Chip Peripheral Components
5.3
Additional Compare Mode for the Concurrent Compare Unit
The SAB 80C517A has an additional compare mode (compare mode 2) in the Compare/Capture
Unit which can be used for the Concurrent Compare Output at P5. In this compare mode 2 the P5
pins are no longer general purpose I/O pins or under control of compare/capture register CC4, but
under control of the new compare registers COMSET and COMCLR. These both 16-bit registers
are always associated with Timer 2 (same as CRC, CC1 to CC4). Each of these registers consists
of two 8-bit portions, i.e COMSET consists of COMSETL (address 0A1 H) and COMSETH (address
0A2H), COMCLR consists of COMCLRL (address 0A3H) and COMCLRH (address 0A4H)
In compare mode 2 the concurrent compare output pins on Port 5 are used as follows (see
figure 5-3):
– When a compare match occurs with register COMSET, a high level appears at the pins of port
5 whose corresponding bits in the mask register SETMSK (address 0A5H) are set.
– When a compare match occurs in register COMCLR, a low level appears at the pins of port 5
whose corresponding bits in the mask register CLRMSK (address 0A6H) are set.
– Additionally the Port 5 pins used for compare mode 2 may also be directly written to by write
instructions to SFR P5. Of course, the pins can also be read under program control.
If compare mode 2 shall be selected register CC4 must operate in compare mode 1 (with the
corresponding output pin P1.4); thus, compare mode 2 is selected by enabling compare function for
register CC4 (COCAH4=1; COCAL4=0 SFR CC4EN) and by programming bits COCOEN0 and
COCOEN1 in SFR CC4EN. Like in concurrent compare mode associated with CC4, the number of
port pins at P5 which serve the compare output function can be selected by bits COCON0COCON2 (in SFR CC4EN). If a set and reset request occurs at the same time (identical values in
COMSET and COMCLR), the set operation takes precedence. It is also possible to use only the
interrupts which are generated by matches in COMSET and COMCLR without affecting P5
("software compare"). For this "interrupt-only" mode it is not necessary that the compare function at
CC4 is selected.
Semiconductor Group
5-8
On-Chip Peripheral Components
Figure 5-3
Compare Mode 2 (Port 5 only)
Semiconductor Group
5-9
On-Chip Peripheral Components
Special Function Register CC4EN
Bit No.
0C9H
MSB
7
6
5
4
3
2
COCOEN1 COCON2 COCON1 COCON0 COCOEN0 COCAH4
1
LSB
0
COCAL4
COM0
CC4EN
Bit
Function
COCON2
COCON1
COCON0
Selects number of compare outputs at P5 (for compare modes 1 and 2);
see table 2-2
COCAH4
COCAL4
Compare/capture mode for register CC4 and compare modes 1 and 2 at P5
Compare/capture at CC4 disabled
Capture on falling/rising edge at pin P1.4/INT2/CC4
Compare enabled at CC4
Capture on write operation into register CCL4
0
0
1
1
0
1
0
1
COCOEN1
COCOEN0
Selection of compare modes 1 and 2 at P5; valid only in combination with
certain configurations in COCAH4, COCAL4; see table 2-3
Setting of bit COCOEN0 automatically sets COM0
COM0
Compare Mode for register CC4
COM0 = 0 selects compare mode 0
COM0 = 1 selects compare mode 1
Setting of bit COCOEN0 automatically sets COM0
The reset value of SFR CC4EN is 00H.
COCON2
COCON1
COCON0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
One additional output of CC4 at P5.0
Additional outputs of CC4 at P5.0 to P5.1
Additional outputs of CC4 at P5.0 to P5.2
Additional outputs of CC4 at P5.0 to P5.3
Additional outputs of CC4 at P5.0 to P5.4
Additional outputs of CC4 at P5.0 to P5.5
Additional outputs of CC4 at P5.0 to P5.6
Additional outputs of CC4 at P5.0 to P5.7
Semiconductor Group
5 - 10
On-Chip Peripheral Components
Table 5-3, Configurations for Concurrent Compare Mode and Compare Mode 2 at P5
COCAH4
COCAL4
COCOEN1 COCOEN0
Function of CC4
Function of Compare
Modes at P5
0
0
0
0
Compare / Capture
disabled
Compare / Capture
disabled
Disabled
0
0
1
0
0
0
1
1
Compare / Capture
disabled
Compare Mode 2
selected at P5
0
1
0
0
Disabled
1
1
0
Capture on falling/
rising edge at pin
P1.4/INT2/CC4
–
0
1
0
0
0
Disabled
1
0
0
1
1
0
1
0
Compare enable at
CC4; Mode 0/1 is
selected by COM0
Compare mode 1
enabled at CC4;
COM0 is
automatically set
Compare enable at
CC4; mode 0/1 is
selected by COM0
1
0
1
1
1
1
0
0
Disabled
1
1
1
0
Capture on write
operation into register
CCL4
Capture on write
operation into register
CCL4
Compare modes 2
selected, but olny
interrupt generation
(ICR, ICS); no output
signals at P5
Concurrent compare
(mode 1) selected at
P5
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS); no output
signals at P5
Compare mode 1 en- Compare Mode 2
abled at CC4; COM0 selected at P5
is automatically set
The other combinations are reserved and must not be used.
Semiconductor Group
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS); no output
signals
5 - 11
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS); no output
signals at P5
On-Chip Peripheral Components
The following table 5-4 lists the SFR’s with their addresses and default values after reset which are
used in compare mode 2:
Table 5-4, Compare Mode 2, used SFR’s and their default Reset Value
SFR
Address
Default Value after Reset
COMSETL
0A1H
0A2H
00H
COMSETH
COMCLRL
00H
0A3H
0A4H
COMCLRH
SETMSK
00H
00H
0A5H
0A6H
CLRMSK
CTCON
00H
00H
0E1H
0C9H
CC4EN
0X00 0000B
00H
The compare registers COMSET and COMCLR have their dedicated interrupt vectors. The
corresponding request flags are ICS for register COMSET and ICR for register COMCLR. The flags
are set by a match in registers COMSET and COMCLR, when enabled. As long as the match
condition is valid the request flags can’t be reset (neither by hardware nor software). The request
flags are located in SFR CTCON.
Special Function Register CTCON
Bit No.
0BAH
MSB
7
6
5
4
3
2
1
LSB
0
T2PS1
–
ICR
ISC
CTF
CLK2
CLK1
CLK0
CTCON
Bit
Function
CLK0
CLK1
CLK2
CTF
Same function as SAB 80C517
ICS
Interrupt request flag for Compare register COMSET. ICS is set when a compare
match occured. Cleared when interrupt is processed.
ICR
Interrupt request flag for Compare register COMRES. ICR is set when a compare
match occured. Cleared when interrupt is processed.
T2PS1
Prescaler select bit for Timer 2. See table 5-5
The default value of CTCON after reset is 0X00 0000B
Semiconductor Group
5 - 12
On-Chip Peripheral Components
Extended Prescaler for Timer 2
The prescaler for Timer 2 has an extended range. This prescaler divides the input clock for Timer 2
when it is operated in timer mode. In addition to the ÷ 2 option there are now scale ratings of ÷ 4
and ÷ 8 available. The rate is selected by the control bits T2PS (T2CON.7) and T2PS1 (CTCON.7).
Table 5-5 lists all available options. This prescaler must not be used when Timer 2 is operated in
counter mode.
Table 5-5, Timer 2 Prescaler
T2PS1 (CTCON.7)
T2PS (T2CON.7)
Prescaler Ratio
0
0
÷1
0
1
÷2
1
0
÷4
1
1
÷8
Semiconductor Group
5 - 13
On-Chip Peripheral Components
5.4
New Baud Rate Generators for Serial Channel 0 and Serial Channel 1
5.4.1 Serial Channel 0 Baud Rate Generator
The Serial Channel 0 has a new baud rate generator which provides greater flexibility and better
resolution. It substitutes the 80C517’s baud rate generator at Serial Channel 0 which provides only
4.8 kBaud or 9.6 kBaud at 12 MHz crystal frequency. Since the new generator offers greater
flexibility it is often possible to use it instead of Timer1 which is then free for other tasks.
Figure 5-4 shows a block diagram of the new baud rate generator for Serial Channel 0. It consists
of a free running 10-bit timer with fOSC /2 input frequency. On overflow of this timer there is an
automatic reload from the registers S0RELL (address AAH) and S0RELH (address BAH). The
lower 8 bits of the timer are reloaded from S0RELL, while the upper two bits are reloaded from bit
0 and 1 of register S0RELH. The baud rate timer is reloaded by writing to S0RELL.
Figure 5-4
Baud Rate Generator for Serial Interface 0
The default value after reset of S0RELL is 0D9H, S0 RELH contains XXXX XX11B.
Semiconductor Group
5 - 14
On-Chip Peripheral Components
Special Function Register S0RELH, S0RELL
MSB
7
Bit No.
6
5
4
3
2
Addr. 0BAH
msb
MSB
7
Bit No.
1
LSB
0
6
5
4
3
2
1
Addr. 0AAH
S0RELH
LSB
0
lsb
shaded areas are not used for programming the baudrate timer
Bit
Function
S0RELH.0-1
Reload value. Upper two bits of the timer reload value.
S0RELL.0-7
Reload value. Lower 8 bit of timer reload value.
Reset value of S0RELL is 0D9H, S0RELH contains XXXX XXX11B.
Semiconductor Group
5 - 15
S0RELL
On-Chip Peripheral Components
Figure 5-5 shows a block diagram of the options available for baud rate generation of Serial
Channel 0. It is a fully compatible superset of the functionality of the SAB 80C517. The new baud
rate generator can be used in modes 1 and 3 of the Serial Channel 0. It is activated by setting bit
BD (ADCON0.7). This also starts the baud rate timer. When Timer1 shall be used for baud rate
generation, bit BD must be cleared. In any case, bit SMOD (PCON.7) selects an additional divider
by two.
The default values after reset in registers S0RELL and S0RELH provide a baud rate of 4.8 kBaud
(with SMOD = 0) or 9.6 kBaud (with SMOD = 1) at 12 MHz oscillator frequency. This guarantees
full compatibility to the SAB 80C517.
Figure 5-5
Block Diagram of Baud Rate Generation for Serial Interface 0
If the new baud rate generator is used the baud rate of Serial Channel 0 in Mode 1 and 3 can be
determined as follows:
Mode 1, 3 baud rate =
2SMOD x oscillator frequency
64 x (210 – S0REL)
with S0REL = S0RELH.1 – 0, S0RELL.7 – 0
Semiconductor Group
5 - 16
On-Chip Peripheral Components
5.4.2 Serial Channel 1 Baud Rate Generator
A new baud rate generator for Serial Channel 1 now offers a wider range of selectable baud rates.
Especially a baud rate of 1200 baud can be achieved now.
The baud rate generator itself is identical with the one used for Serial Channel 0. It consists of a free
running 10-bit timer with FOSC /2 input frequency. On overflow of this timer there is an automatic
reload from the registers S1RELL (address 9DH) and S1RELH (address BBH). The lower 8 bits of
the timer are reloaded from S1RELL, while the upper two bits are reloaded from bit 0 and 1 of
register S1RELH. The baud rate timer is reloaded by writing to S1RELL.
The baud rate in mode A and B can be determined by the following formula:
Mode A, B baud rate =
oscillator frequency
32 x (210 – S1REL)
with S1REL = S1RELH.1 – 0, S1RELL.7 – 0
Figure 5-6 shows a block diagram of the baud rate generator for Serial Interface 1.
Figure 5-6
Baud Rate Generator for Serial Interface 1
Semiconductor Group
5 - 17
On-Chip Peripheral Components
Special Function Register SRELH, SRELL
MSB
7
Bit No.
6
5
4
3
2
Addr. 0BBH
msb
MSB
7
Bit No.
1
LSB
0
6
5
4
3
2
1
Addr. 09DH
S1RELH
LSB
0
lsb
shaded areas are not used for programming the baudrate timer
Bit
Function
S1RELH.0-1
Reload value. Upper two bits of the timer reload value.
S1RELL.0-7
Reload value. Lower 8 bit of timer reload value.
Reset value of S1RELL is 00H, S1RELH contains XXXX XXX11B.
Semiconductor Group
5 - 18
S1RELL
On-Chip Peripheral Components
5.5
Modified Oscillator Watchdog Unit
The SAB 80C517A has a new oscillator watchdog unit that has an improved functionality with
respect to the SAB 80C517’s oscillator watchdog.
Use of the Oscillator Watchdog Unit
The unit serves three functions:
– Monitoring of the on-chip oscillator's function.
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of appr. 0.5 ms in order to allow the oscillatior to stabilize; then the oscillator watchdog
reset is released and the part starts program execution again.
– Restart from the Hardware Power Down Mode.
If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete Hardware Power Down sequence; however, the
watchdog works identically to the monitoring function.
– Fast internal reset after power-on.
In this function the oscillator watchdog unit provides a clock supply for the reset before the onchip oscillator has started. In this case the oscillator watchdog unit also works identically to
the monitoring function.
If the oscillator watchdog unit shall be used it must be enabled (this is done by applying high level
to the control pin OWE).
Semiconductor Group
5 - 19
On-Chip Peripheral Components
Detailled Description of the Oscillator Watchdog Unit
Figure 5-7 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC
oscillator which provides the reference frequency for the comparison with the frequency of the onchip oscillator. The RC oscillator can be enabled/disabled by the control pin OWE . If it is disabled
the complete unit has no function.
Figure 5-7
Oscillator Watchdog Unit
Special Function Register IP0 (Address 0A9H)
Bit No.
0A9H
MSB
7
6
5
4
3
2
1
LSB
0
OWDS
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
IP0
These bits are not used in controlling the fail safe mechanisms.
Bit
Function
OWDS
Oscillator watchdog timer status flag.
Set by hardware when an oscillator watchdog reset occurred. Can be cleared or
set by software.
Reset value of IP0 is 00H.
Semiconductor Group
5 - 20
On-Chip Peripheral Components
The frequency coming from the RC oscillator is divided by 5 and compared to the on-chip oscillator’s
frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency
derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip
oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal
clock system to the output of the RC oscillator. This means that the part is being clocked even if the
on-chip oscillator has stopped or has not yet started. At the same time the watchdog activates the
internal reset in order to bring the part in its defined reset state. The reset is performed because
clock is available from the RC oscillator. This internal watchdog reset has the same effects as an
externally applied reset signal with the following exception: The Watchdog Timer Status flag WDTS
(IP0.6) is not reset (the Watchdog Timer however is stopped) and bit OWDS is set. This allows the
software to examine error conditions detected by the Watchdog Timer even if meanwhile an
oscillator failure occured.
The oscillator watchdog is able to detect a recovery of the on-chip oscillator after a failure. If the
frequency derived from the on-chip oscillator is again higher than the reference the watchdog starts
a final reset sequence which takes typ. 1 ms. Within that time the clock is still supplied by the RC
oscillator and the part is held in reset. This allows a reliable stabilization of the on chip oscillator.
After that, the watchdog toggles the clock supply back to the on-chip oscillator and releases the
reset request. If no external reset is applied in this moment the part will start program execution. If
an external reset is active, however, the device will keep the reset state until also the external reset
request disappears.
Furthermore, the status flag OWDS (IP0.7) is set if the oscillator watchdog was active. The status
flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog. The
flag OWDS can be set or cleared by software. An external reset request, however, also resets
OWDS (and WDTS).
Semiconductor Group
5 - 21
Interrupt System
6
Interrupt System
6.1
Additional Interrupt for Compare Registers CM0 to CM7
There is an additional interrupt which is vectored to on a compare match in one of the eight
comparators of the compare registers CM0 to CM7, when compare mode 1 is selected for the
corresponding channel (assigned to Timer 2 by control bit CMSEL.x). For that purpose the
SAB 80C517A provides eight interrupt request flags (in SFR IRCON1, address 0D1H) which are
ORed to form the interrupt request for that vector, i.e. each of the eight comparators has its own
request flag. Thus the service routine may decide which compare match requested the interrupt.
The corresponding request flag is set by every match in the compare channel when the Compare
Mode 1 is selected for this channel (assigned to Timer 2). If Compare Mode 0 is selected for a
channel (assigned to the Compare Timer), the corresponding interrupt request flag will not be set
on a compare match.
This interrupt is enabled by setting the enable bit ECMP in SFR IEN2. If this bit is set the program
vectors to location 0A3H if one of the eight request flags in IRCON 1 is set.
Figure 6-1 shows a functional block diagram of the new structure concerning the interrupts. The
further functions of this compare unit keep full compatibility to the SAB 80C517.
Semiconductor Group
6-1
Interrupt System
Figure 6-1
Interrupts of Compare Registers CM0-CM7 Assigned to Timer II
Semiconductor Group
6-2
Interrupt System
Special Function Register IRCON1
Bit No.
MSB
7
0D1H
ICMP7
6
5
4
3
2
ICMP6 ICMP5 ICMP4 ICMP3 ICMP2
1
LSB
0
ICMP1 ICMP0 IRCON1
Bit
Function
ICMPx
Compare x interrupt request flag. Set by hardware when a compare match in
compare mode 1 with compare register CMx occured (only, if compare function
enabled for CMx). ICMPx must be cleared by software (CMSEL.x = 0 and
CMEN.x = 1).
The reset value of IRCON1 is 00H.
Semiconductor Group
6-3
Interrupt System
6.2
Interrupt Structure
This section summarizes the expanded interrupt structure of the SAB 80C517A which has 3 new
interrupt vectors in addition to the 14 vectors of the SAB 80C517. Thus, 17 vectors are available
now.
The new interrupt sources are:
1. Request Flags
ICMP0 to ICMP7: These eight request flags are set by compare matches in the compare
registers CM0-7, if the compare function is enabled and compare mode 1 is
selected for the corresponding register SCM0-7.
Interrupt vector:
0093H
Enable Bit:
ECMP (IEN2.2)
Priority:
Same priority as IE1/IEX3, programmed by IP1.2/IP0.2
2. Request Flag:
ICS
This request flag is set by a compare match in compare register COMSET.
Interrupt Vector:
00A3H
Enable Bit:
ECS (IEN2.4)
Priority:
Same priority as RI0+TI0/IEX5, programmed by IP1.4/IP0.4
3. Request Flag:
ICR
This request flag is set by a compare match in compare register COMCLR
Interrupt Vector:
00ABH
Enable Bit:
ECR (IEN2.5)
Priority:
Same priority as TF2+EXF2/IEX6, programmed by IP1.5/IP0.5
Semiconductor Group
6-4
Interrupt System
3.1
Priority Level Structure
The following tables show the SFR IEN2, the priority level grouping (table 6-1) and the priority within
level (table 6-2). The principle of the priority level selection is identical to the SAB 80C517, i.e. a
pair or triple can be programmed to one of four priority levels.
Special Function Register IEN2
Bit No.
09AH
MSB
7
–
6
5
4
3
2
1
LSB
0
–
ECR
ECS
ECT
ECMP
–
ES1
IEN2
Bit
Function
ES1
Enable serial interrupt of interface 1. Enables or disables the interrupt of serial
interface 1. If ES1 = 0, the interrupt is disabled.
ECMP
Enables interrupt on compare match in compare registers CM0 - CM7. If
ECMP = 0, the interrupt is disabled.
ECT
Enable compare timer interrupt. Enables or disables the interrupt at compare
timer overflow. If ECT = 0, the interrupt is disabled.
ECS
Enables interrupt on compare match in compare register COMSET. If ECS = 0,
the interrupt is disabled.
ECR
Enabled interrupt on compare match in compare register COMCLR. If ECR = 0,
the interrupt is disabled.
The reset value of IEN2 is XX00 00X0B.
Semiconductor Group
6-5
Interrupt System
Table 6-1, Pairs and triplets of interrupt sources
External Interrupt 0
Serial Channel 1 Interrupt
A/D Converter Interrupt
Timer 0 Interrupt
–
External Interrupt 2
External Interrupt 1
Match in CM0 - CM7
External Interrupt 3
Timer 1 Interrupt
Compare Timer Overflow
External Interrupt 4
Serial Channel 0 Interrupt
Match in COMSET
External Interrupt 5
Timer 2 Interrupt
Match in COMCLR
External Interrupt 6
Table 6-2, Priority within Level
Interrupt Source
High
IE0
TF0
IE1
TF1
RI0 + TI0
TF2 + EXF2
Semiconductor Group
Priority
→
Low
RI1 + TI1
–
ICMP0-7
CTF
ICS
ICR
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
6-6
High
↓
Low
Device Specification
4
Device Specification
High-Performance
8-Bit CMOS Single-Chip Microcontroller
SAB 80C517A/83C517A-5
Preliminary
SAB 83C517A-5
SAB 80C517A
●
●
●
●
●
●
●
●
●
Microcontroller with factory mask-programmable ROM
Microcontroller for external ROM
SAB 80C517A/83C517A-5,
up to 18 MHz operation
32 K × 8 ROM (SAB 83C517A-5 only,
ROM-Protection available)
256 × 8 on-chip RAM
2 K × 8 on-chip RAM (XRAM)
Superset of SAB 80C51 architecture:
– 1 µs instruction cycle time at 12 MHz
– 666 ns instruction cycle time at 18 MHz
– 256 directly addressable bits
– Boolean processor
– 64 Kbyte external data and
program memory addressing
Four 16-bit timer/counters
Powerful 16-bit compare/capture unit
(CCU) with up to 21 high-speed or PWM
output channels and 5 capture inputs
Versatile "fail-safe" provisions
Fast 32-bit division, 16-bit multiplication,
32-bit normalize and shift by peripheral
MUL/DIV unit (MDU)
●
●
●
●
●
●
●
●
●
●
Eight data pointers for external memory
addressing
Seventeen interrupt vectors, four priority
levels selectable
Genuine 10-bit A/D converter with
12 multiplexed inputs
Two full duplex serial interfaces with
programmable Baudrate-Generators
Fully upward compatible with SAB 80C515,
SAB 80C517, SAB 80C515A
Extended power saving mode
Fast Power-On Reset
Nine ports: 56 I/O lines, 12 input lines
Three temperature ranges available:
0 to 70 oC (T1)
– 40 to 85oC (T3)
– 40 to 110oC (T4)
Plastic packages: P-LCC-84,
P-MQFP-100-2
The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of
microcontrollers. It is designed in Siemens ACMOS technology and based on SAB 8051
architecture. ACMOS is a technology which combines high-speed and density characteristics
with low-power consumption or dissipation.
While maintaining all the SAB 80C517 features and operating characteristics the
SAB 80C517A is expanded in its "fail-safe" characteristics and timer capabilities.The
SAB 80C517A is identical with the SAB 83C517A-5 except that it lacks the on-chip program
memory. The SAB 80C517A/83C517A-5 is supplied in a 84-pin plastic leaded chip carrier
package (P-LCC-84) and in a 100-pin plastic quad flat package (P-MQFP-100-2).
7-1
05.94
Device Specification
Ordering Information
Type
Ordering
code
Package
SAB 80C517A-N18
Q67120-C583
P-LCC-84
SAB 80C517A-M18
TBD
P-MRFP-100
SAB 83C517A-5N18
Q67120-C582
P-LCC-84
with mask-programmable ROM,
18 MHz
SAB 80C517A-N18-T3
Q67120-C769
P-LCC-84
for external memory,18 MHz
ext. temperature – 40 to 85 oC
SAB 83C517A-5N18-T3
Q67120-C771
P-LCC-84
with mask-programmable ROM,
18 MHz
ext. temperature – 40 to 85 oC
SAB 83C517A-N18-T4
TBD
P-LCC-84
for external memory, 18 MHz
ext. temperature -40 to +110oC
SAB 83C517A-5N18-T4
TBD
P-LCC-84
with mask-programmable ROM,
18 MHz
ext. temperature -40 to +110oC
Semiconductor Group
7-2
Description
8-bit CMOS microcontroller
for external memory,18 MHz
Device Specification
Logic Symbol
Semiconductor Group
7-3
Device Specification
The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with
one exception:
Typ
P-LCC-84, Pin 60
P-MQFP-100-2,Pin 36
SAB 80C517A
SAB 80C517/80C537
HWPD
N.C.
Pin Configuration
(P-LCC-84)
Semiconductor Group
7-4
Device Specification
Pin Configuration
(P-MQFP-100-2)
Semiconductor Group
7-5
Device Specification
Pin Definitions and Functions
Symbol
Pin Number
P-LCC-84
I/O *)
Function
P-MQFP-100-2
P4.0 – P4.7 1– 3, 5 – 9
64 - 66,
68 - 72
I/O
Port 4
is a bidirectional I/O port with internal
pull-up resistors. Port 4 pins that have 1
s written to them are pulled high by the
internal pull-up resistors, and in that
state can be used as inputs. As inputs,
port 4 pins being externally pulled low
will source current (IIL, in the DC characteristics) because of the internal pullup resistors.
This port also serves alternate compare
functions. The secondary functions are
assigned to the pins of port 4 as follows:
– CM0 (P4.0): Compare Channel 0
– CM1 (P4.1): Compare Channel 1
– CM2 (P4.2): Compare Channel 2
– CM3 (P4.3): Compare Channel 3
– CM4 (P4.4): Compare Channel 4
– CM5 (P4.5): Compare Channel 5
– CM6 (P4.6): Compare Channel 6
– CM7 (P4.7): Compare Channel 7
PE/SWD
67
I
Power saving modes enable Start
Watchdog Timer
A low level on this pin allows the software to enter the power down, idle and
slow down mode. In case the low level
is also seen during reset, the watchdog
timer function is off on default.
Use of the software controlled power
saving modes is blocked, when this pin
is held on high level. A high level during
reset performs an automatic start of the
watchdog timer immediately after reset.
When left unconnected this pin is pulled
high by a weak internal pull-up resistor.
*
4
I = Input
O = Output
Semiconductor Group
7-6
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O *)
Function
I
RESET
A low level on this pin for the duration of
one machine cycle while the oscillator is
running resets the SAB 80C517A. A
small internal pull-up resistor permits
power-on reset using only a capacitor
connected to VSS.
P-LCC-84
P-MQFP-100-2
RESET
10
73
V AREF
11
78
Reference voltage for the A/D converter.
V AGND
12
79
Reference ground for the A/D
converter.
P7.7 -P7.0
13 - 20
80 - 87
*
I
I = Input
O = Output
Semiconductor Group
7-7
Port 7
is an 8-bit unidirectional input port. Port
pins can be used for digital input, if
voltage levels meet the specified input
high/low voltages, and for the lower 8bit of the multiplexed analog inputs of
the A/D converter, simultaneously.
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
P-LCC-84
P3.0 - P3.7 21 - 28
I/O *) Function
P-MQFP-100-2
90 - 97
I/O
Port 3
is a bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 3
pins being externally pulled low will source
current (IIL, in the DC characteristics)
because of the internal pull-up resistors.
Port 3 also contains the interrupt, timer,
serial port 0 and external memory strobe
pins that are used by various options. The
output latch corresponding to a secondary
function must be programmed to a one (1)
for that function to operate.
The secondary functions are assigned to
the pins of port 3, as follows:
– R × D0 (P3.0): receiver data input
(asynchronous) or data input/output
(synchronous) of serial interface
– T × D0 (P3.1): transmitter data output
(asynchronous) or clock output
(synchronous) of serial interface 0
– INT0 (P3.2):
gate control
interrupt 0 input/timer 0
– INT1 (P3.3):
gate control
interrupt 1 input/timer 1
– T0 (P3.4):
counter 0 input
– T1 (P3.5):
counter 1 input
– WR (P3.6):
the write control signal
latches the data byte from port 0 into the
external data memory
– RD (P3.7):
the read control signal
enables the external data memory to
port 0
*
I = Input
O = Output
Semiconductor Group
7-8
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
P-LCC-84
P1.7 - P1.0 29 - 36
I/O *) Function
P-MQFP-100-2
98 - 100,
1, 6 - 9
I/O
Port 1
is a bidirectional I/O port with internal
pull-up resistors. Port 1 pins that have
1 s written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 1
pins being externally pulled low will source
current (IIL, in the DC characteristics)
because of the internal pull-up resistors. It
is used for the low order address byte
during program verification. It also contains
the interrupt, timer, clock, capture and
compare pins that are used by various
options. The output latch must be
programmed to a one (1) for that function to
operate (except when used for the
compare functions).
The secondary functions are assigned to
the port 1 pins as follows:
– INT3/CC0 (P1.0): interrupt 3 input/
compare 0 output /capture 0 input
– INT4/CC1 (P1.1): interrupt 4 input /
compare 1 output /capture 1 input
– INT5/CC2 (P1.2): interrupt 5 input /
compare 2 output /capture 2 input
– INT6/CC3 (P1.3): interrupt 6 input /
compare 3 output /capture 3 input
– INT2/CC4 (P1.4): interrupt 2 input /
compare 4 output /capture 4 input
– T2EX (P1.5):
timer 2 external
reload trigger input
*
I = Input
O = Output
Semiconductor Group
7-9
– CLKOUT (P1.6):
system clock output
– T2 (P1.7):
counter 2 input
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O *) Function
P-LCC-84
P-MQFP-100-2
XTAL2
39
12
–
XTAL2
Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
XTAL1
40
13
–
XTAL1
Output of the inverting oscillator amplifier.
To drive the device from an external clock
source, XTAL2 should be driven, while
XTAL1 is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, since the input to the
internal clocking circuitry is devided down
by a divide-by-two flip-flop. Minimum and
maximum high and low times as well as
rise/fall times specified in the AC
characteristics must be observed.
14 - 21
I/O
Port 2
is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as in-puts. As inputs, port 2
pins being externally pulled low will source
current (IIL, in the DC characteristics)
because of the internal pull-up resistors.
Port 2 emits the high-order address byte
during fetches from external program
memory and during accesses to external
data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses
strong internal pull-up resistors when
issuing1 s. During accesses to external
data memory that use 8-bit addresses
(MOVX @Ri), port 2 issues the contents of
the P2 special function register.
P2.0 - P2.7 41 - 48
*
I = Input
O = Output
Semiconductor Group
7-10
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O *) Function
P-LCC-84
P-MQFP-100-2
PSEN
49
22
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus during
external fetch operations. It is activated
every six oscillator periodes except during
external data memory accesses. Remains
high during internal program execution.
ALE
50
23
O
The Address Latch Enable
output is used for latching the address into
external memory during normal operation.
It is activated every six oscillator periodes
except during an external data memory
access
EA
51
24
I
External Access Enable
When held at high level, instructions are
fetched from the internal ROM (SAB
83C517A-5 only) when the PC is less than
8000H. When held at low level, the SAB
80C517A fetches all instructions from external program memory. For the SAB
80C517A this pin must be tied low
26 - 27,
30 - 35
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1 s written to them
float, and in that state can be used as highimpe-dance inputs. Port 0 is also the
multiplexed low-order address and data
bus during accesses to external program or
data memory. In this application it uses
strong internal pull-up resistors when
issuing 1 s. Port 0 also out-puts the code
bytes during program verification in the
SAB 83C517A if ROM-Protection was not
enabled. External pull-up resistors are
required during program verification.
P0.0 - P0.7 52 - 59
*
I = Input
O = Output
Semiconductor Group
7-11
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
HWPD
Pin Number
I/O *) Function
P-LCC-84
P-MQFP-100-2
60
36
I
Hardware Power Down
A low level on this pin for the duration of
one machine cycle while the oscillator is
running resets the SAB 80C517A. A low
level for a longer period will force the part to
Power Down Mode with the pins floating.
(see table 7)
37 - 44
I/O
Port 5
is a bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 5
pins being externally pulled low will source
current (IIL, in the DC characteristics)
because of the internal pull-up resistors.
This port also serves the alternate function
"Concurrent Compare" and "Set/Reset
Compare". The secondary functions are
assigned to the port 5 pins as follows:
P5.7 - P5.0 61 - 68
I
OWE
*
69
45
I/O
I = Input
O = Output
Semiconductor Group
7-12
– CCM0 to CCM7 (P5.0 to P5.7):
concurrent compare or Set/Reset
Oscillator Watchdog Enable
A high level on this pin enables the
oscillator watchdog. When left
unconnected this pin is pulled high by a
weak internal pull-up resistor. When held at
low level the oscillator watchdog function is
off.
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
P-LCC-84
P6.0 - P6.7 70 - 77
I/O *) Function
P-MQFP-100-2
46 - 50,
54 - 56
I/O
Port 6
is a bidirectional I/O port with internal pullup resistors. Port 6 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 6
pins being externally pulled low will source
current (I IL, in the DC characteristics)
because of the internal pull-up resistors.
Port 6 also contains the external A/D
converter control pin and the transmit and
receive pins for serial channel 1. The
output latch corresponding to a secondary
function must be programmed to a one (1)
for that function to operate.
The secondary functions are assigned to
the pins of port 6, as follows:
– ADST (P6.0): external A/D converter
start pin
– R × D1 (P6.1): receiver data input
of serial interface 1
– T × D1 (P6.2): transmitter data output
of serial interface 1
P8.0 - P8.3 78 - 81
*
57 - 60
I
I = Input
O = Output
Semiconductor Group
7-13
Port 8
is a 4-bit unidirectional input port. Port pins
can be used for digital input, if voltage
levels meet the specified input high/low
voltages, and for the higher 4-bit of the
multiplexed analog inputs of the A/D
converter, simultaneously
Device Specification
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O *)
Function
P-LCC-84
P-MQFP-100-2
RO
82
61
O
Reset Output
This pin outputs the internally
synchronized reset request signal. This
signal may be generated by an external
hardware reset, a watchdog timer reset
or an oscillator watch-dog reset. The
reset output is active low.
VS S
37, 83
10, 62
–
Circuit ground potential
VCC
38, 84
11, 63
–
Supply Terminal for all operating
modes
N.C.
–
2 - 5, 25,
28 - 29,
51 - 53,
74 - 77,
88 - 89
–
Not connected
*
I = Input
O = Output
Semiconductor Group
7-14
Device Specification
Figure 1
Block Diagram
Semiconductor Group
7-15
Device Specification
Functional Description
The SAB 80C517A is based on 8051 architecture. It is a fully compatible member of the
Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced
SAB 80C517. The SAB 80C517A is therefore compatible with code written for the
SAB 80C517.
Having an 8-bit CPU with extensive facilities for bit-handling and binary BCD arithmetics the
SAB 80C517A is optimized for control applications. With a 18 MHz crystal, 58 % of the
instructions are executed in 666.67 ns.
Being designed to close the performance gap to the 16-bit microcontroller world, the
SAB 80C517A’s CPU is supported by a powerful 32-/16-bit arithmetic unit and a more flexible
addressing of external memory by eight 16-bit datapointers.
Memory Organisation
According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces for
program and data memory. Figure 2 illustrates the mapping of address spaces.
Figure 2
Memory Map
Semiconductor Group
7-16
Device Specification
Program Memory (’Code Space’)
The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal
ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls
whether program fetches below address 8000H are done from internal or external memory.
As a new feature the SAB 83C517A-5 offers the possibility of protecting the internal ROM
against unauthorized access. This protection is implemented in the ROM-Mask.Therefore, the
decision ROM-Protection ’yes’ or ’no’ has to be made when delivering the ROM-Code. Once
enabled, there is no way of disabling the ROM-Protection.
Effect:
The access to internal ROM done by an externally fetched MOVC instruction
is disabled. Nevertheless, an access from internal ROM to external ROM is possible.
To verify the read protected ROM-Code a special ROM-Verify-Mode is implemented. This
mode also can be used to verify unprotected internal ROM.
ROM -Protection
ROM-Verification Mode
(see ’AC Characteristics’)
Restrictions
no
ROM-Verification Mode 1
(standard 8051 Verification Mode)
ROM-Verification Mode 2
–
yes
ROM-Verification Mode 2
– standard 8051
Verification Mode is
disabled
– externally applied MOVC
accessing internal ROM
is disabled
Semiconductor Group
7-17
Device Specification
Data Memory (’Code Space’)
The data memory space consists of an internal and an external memory space. The
SAB 80C517A contains another 2 Kbyte on On-Chip RAM above the 256-bytes internal RAM
of the base type SAB 80C517. This RAM is called XRAM in this document.
External Data Memory
Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit
indirect addressing. For 8-bit addressing MOVX instructions in combination with registers R0
and R1 can be used. A 16-bit external memory addressing is supported by eight 16-bit
datapointers. Registers XPAGE and SYSCON are controlling whether data fetches at
addresses F800H to FFFFH are done from internal XRAM or from external data memory.
Internal Data Memory
The internal data memory is divided into four physically distinct blocks:
– the lower 128 bytes of RAM including four banks containing eight registers each
– the upper 128 byte of RAM
– the 128 byte special function register area.
– a 2 K × 8 area which is accessed like external RAM (MOVX-instructions), implemented on
chip at the address range from F800H to FFFFH. Special Function Register SYSCON
controls whether data is read or written to XRAM or external RAM.
A mapping of the internal data memory is also shown in figure 2. The overlapping address
spaces are accessed by different addressing modes (see User's Manual SAB 80C517). The
stack can be located anywhere in the internal data memory.
Architecture for the XRAM
The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the
contents is undefined, while it remains unchanged during and after a reset or HW Power Down
if the power supply is not turned off.
The additional On-Chip RAM is logically located in the "external data memory" range at the
upper end of the 64 Kbyte address range (F800 H-FFFFH). It is possible to enable and disable
(only by reset) the XRAM. If it is disabled the device shows the same behaviour as the parts
without XRAM, i.e. all MOVX accesses use the external bus to physically external data
memory.
Semiconductor Group
7-18
Device Specification
Accesses to XRAM
Because the XRAM is used in the same way as external data memory the same instruction
types must be used for accessing the XRAM.
Note: If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the
cycle which the reset is detected at (MOVX is a 2-cycle instruction):
Reset detection at cycle 1:
The new value will not be written to XRAM. The old value
is not affected.
Reset detection at cycle 2:
The old value in XRAM is overwritten by the new value.
Accesses to XRAM using the DPTR
There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR
for indirect addressing. The instructions are:
MOVX A,
@DPTR (Read)
MOVX
@DPTR, A (Write)
Normally the use of these instructions would use a physically external memory. However, in the
SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM
address space (DPTR F800H).
Accesses to XRAM using the Registers R0/R1
The 8051 architecture provides also instructions for accesses to external data memory range
which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions
are:
MOVX A,
@Ri (Read)
MOVX
@Ri, A (Write)
In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as
page register which selects pages of 256-byte. However, the distinction, whether Port 2 is
used as general purpose I/O or as "page address" is made by the external system design. From
the device’s point of view it cannot be decided whether the Port 2 data is used externally as
address or as I/O data!
Hence, a special page register is implemented into the SAB 80C517A to provide the possibility
of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same
function for the XRAM as Port 2 for external data memory.
Semiconductor Group
7-19
Device Specification
Special Function Register XPAGE
Addr. 91H
XPAGE
The reset value of XPAGE is 00H.
XPAGE can be set and read by software.
The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri
instructions. If the address formed from XPAGE and Ri is less than the XRAM address range,
then an external access is performed. For the SAB 80C517A the contents of XPAGE must be
greater or equal than F8H in order to use the XRAM. Of course, the XRAM must be enabled if
it shall be used with MOVX @Ri instructions.
Thus, the register XPAGE is used for addressing of the XRAM; additionally its contents are
used for generating the internal XRAM select. If the contents of XPAGE is less than the XRAM
address range then an external bus access is performed where the upper address byte is
provided by P2 and not by XPAGE!
Therefore, the software has to distinguish two cases, if the MOVX @Ri instructions with paging
shall be used:
a) Access to XRAM:
The upper address byte must be written to XPAGE
or P2; both writes selects the XRAM address range.
b) Access to external memory: The upper address byte must be written to P2; XPAGE
will be loaded with the same address in order to deselect
the XRAM.
Semiconductor Group
7-20
Device Specification
Control of XRAM in the SAB 80C517A
There are two control bits in register SYSCON which control the use and the bus operation
during accesses to the additional On-Chip RAM (XRAM).
Special Function Register SYSCON
Addr. 0B1H
—
—
—
—
—
—
XMAP1 XMAP0 SYSCON
Bit
Function
XMAP0
Global enable/disable bit for XRAM memory.
XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.
XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are performed by the external bus (reset state).
XMAP1
Control bit for RD/WR signals during accesses to XRAM; this bit has no
effect if XRAM is disabled (XMAP0 = 1) or if addresses exceeding the
XRAM address range are used for MOVX accesses.
XMAP1 = 0: The signals RD and WR are not activated during accesses
to XRAM.
XMAP1 = 1: The signals RD and WR are activated during accesses to
XRAM.
Reset value of SYSCON is xxxx xx01B.
The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM).
If this bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external
bus. In this case the SAB 80C517A does not use the additional On-Chip RAM and is compatible
with the types without XRAM.
Semiconductor Group
7-21
Device Specification
XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM
could be dangerous since indeterminate values would be read from external bus. To avoid this
the XMAP-bit is forced to ’1’ only by reset. Additionally, during reset an internal capacitor is
loaded. So after reset state XRAM is disabled. Because of the load time of the capacitor
XMAP0-bit once written to ’0’ (that is, discharging capacitor) cannot be set to ’1’ again by
software. On the other hand any distortion (software hang up, noise, ...) is not able to load this
capacitor, too. That is, the stable status is XRAM enabled. The only way to disable XRAM after
it was enabled is a reset.
The clear instruction for XMAP0 should be integrated in the program initialization routine before
XRAM is used. In extremely noisy systems the user may have redundant clear instructions.
The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the externa RD
and WR signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For
debug purposes it might be useful to have these signals and the addresses at Ports 0.2
available. This is performed if XMAP1 is set.
The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA. The table 1 lists the various operating conditions. It shows
the following characteristics:
a) Use of P0 and P2 pins during the MOVX access.
Bus: The pins work as external address/data bus. If (internal) XRAM is accessed, the
data written to the XRAM can be seen on the bus in debug mode.
I/0:
The pins work as Input/Output lines under control of their latch.
b) Activation of the RD and WR pin during the access.
c) Use of internal or external XDATA memory.
The shaded areas describe the standard operation as each 80C51 device without on-chip
XRAM behaves.
Semiconductor Group
7-22
Semiconductor Group
MOVX
@Ri
MOVX
@DPTR
7-23
a) P0/P2➝BUS
(WR -Data only)
P2➝I/0
b) RD/WR active
c) XRAM is used
(WR -Data only)
P2➝I/0
b) RD/WR inactive
c) XRAM is used
b) RD/WR active
c) ext. memory is
used
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝BUS
a) P0➝Bus
P2➝I/0
b) RD/WR active
c) XRAM is used
b) RD/WR inactive
c) XRAM is used
P2➝I/0
(WR -Data only)
a) P0➝Bus
a) P0/P2➝BUS
(WR -Data only)
b) RD/WR active
c) ext. memory is
used
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝BUS
a) P0/P2➝Bus
10
a) P0/P2➝Bus
modes compatible to 8051 - family
XPAGE ≥ XRAM
addr.
page
range
XPAGE < XRAM
addr.
page
range
DPTR ≥ XRAM
address
range
DPTR < XRAM
address
range
00
=0
XMAP1, XMAP0
EA
Table 1:
Behaviour of P0/P2 and RD/WR during MOVX accesses
b) RD/WR inactive
c) XRAM is used
b) RD/WR active
c) ext. memory is
used
P2➝I/0
b) RD/WR active
c) ext. memory is
used
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝I/0
P2➝I/0
a) P0➝Bus
a) P0➝Bus
P2➝I/0
b) RD/WR inactive
c) XRAM is used
b) RD/WR active
c) ext. memory is
used
a) P0➝Bus
a) P0/P2➝I/0
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝Bus
00
a) P0/P2➝Bus
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝Bus
X1
=1
b) RD/WR active
c) XRAM is used
P2➝I/0
(WR -Data only)
a) P0➝BUS
b) RD/WR active
c) ext. memory is
used
P2➝I/0
a) P0➝Bus
b) RD/WR active
c) XRAM is used
(WR -Data only)
a) P0/P2➝BUS
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝Bus
10
XMAP1, XMAP0
EA
b) RD/WR active
c) ext. memory is
used
P2➝I/0
a) P0➝Bus
b) RD/WR active
c) ext. memory is
used
P2➝I/0
a) P0➝Bus
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝Bus
b) RD/WR active
c) ext. memory is
used
a) P0/P2➝Bus
X1
Device Specification
s
Device Specification
Multiple Datapointers
As a functional enhancement to standard 8051 controllers, the SAB 80C517A contains eight
16-bit datapointers. The instruction set uses just one of these datapointers at a time. The
selection of the actual datapointer is done in special function register DPSEL (data pointer
select, addr. 92H). Figure 3 illustrates the addressing mechanism.
Figure 3
Addressing of External Data Memory
Semiconductor Group
7-24
Device Specification
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside
in the special function register area. The 81 special function registers include arithmetic
registers, pointers, and registers that provide an interface between the CPU and the on-chip
peripherals. There are also 128 directly addressable bits within the SFR area. All special
function registers are listed in table 1 and table 2.
In table 1 they are organized in numeric order of their addresses. In table 2 they are organized
in groups which refer to the functional blocks of the SAB 80C517A.
Table 2
Special Function Register
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
80H
81H
82H
83H
84H
85H
86H
87H
P0 1)
SP
DPL
DPH
(WDTL) 3)
(WDTH) 3)
WDTREL
PCON
0FFH
07H
00H
00H
(00H)
(00H)
00H
00H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
S0CON 1)
S0BUF
IEN2
S1CON
S1BUF
S1RELL
reserved
reserved
00H
XXH
XX00 00X0B
0X00 0000B
XXH
00H
XXH
XXH
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
TCON 1)
TMOD
TL0
TL1
TH0
TH1
reserved
reserved
00H
00H
00H
00H
00H
00H
XXH 2)
XXH 2)
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
P2 1)
COMSETL
COMSETH
COMCLRL
COMCLRH
SETMSK
CLRMSK
reserved
0FFH
00H
00H
00H
00H
00H
00H
XXH 2)
90H
91H
92H
93H
94H
95H
96H
97H
P1 1)
XPAGE
DPSEL
reserved
reserved
reserved
reserved
reserved
0FFH
00H
XXXXX000B
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
IEN0 1)
IP0
S0RELL
reserved
reserved
reserved
reserved
reserved
00H
00H
0D9H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
1)
Bit-addressable special function registers
X means that the value is indeterminate and the location is reserved
3) ( )... SFRs not user accessable
2)
Semiconductor Group
7-25
Device Specification
Table 2
Special Function Register (cont’d)
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
P3 1)
SYSCON
reserved
reserved
reserved
reserved
reserved
reserved
0FFH
XXXX XX01B
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
PSW 1)
IRCON1
CML0
CMH0
CML1
CMH1
CML2
CMH2
00H
00H
00H
00H
00H
00H
00H
00H
B8H
B9H
BAH
BBH
BCH
BDH
BSH
BFH
IEN1 1)
IP1
S0RELH
S1RELH
reserved
reserved
reserved
reserved
00H
XX00 0000B
XXXX XX11B
XXXX XX11B
XXH
XXH
XXH
XXH
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
ADCON0 1)
ADDATH
ADDATL
P7
ADCON1
P8
CTRELL
CTRELH
00H
00H
00H
XXH
XXXX 0000B
XXH
00H
00H
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
IRCON0 1)
CCEN
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
00H
00H
00H
00H
00H
00H
00H
00H
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
ACC 1)
CTCON
CML3
CMH3
CML4
CMH4
CML5
CMH5
00H
0X00 000B
00H
00H
00H
00H
00H
00H
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
T2CON 1)
CC4EN
CRCL
CRCH
TL2
TH2
CCL4
CCH4
00H
00H
00H
00H
00H
00H
00H
00H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
P4 1)
MD0
MD1
MD2
MD3
MD4
MD5
ARCON
0FFH
XXH
XXH
XXH
XXH
XXH
XXH
0XXX XXXXB
1)
Bit-addressable special function registers
X means that the value is indeterminate and the location is reserved
3) ( )... SFRs not user accessable
2)
Semiconductor Group
7-26
Device Specification
Table 2
Special Function Register (cont’d)
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
B 1)
reserved
CML6
CMH6
CML7
CMH7
CMEN
CMSEL
00H
XXH
00H
00H
00H
00H
00H
00H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
P5 1)
reserved
P6
reserved
reserved
(IS0)
(IS1)
reserved
0FFH
XXH
0FFH
XXH
XXH
XXH
XXH
XXH
1)
Bit-addressable special function registers
X means that the value is indeterminate and the location is reserved
3) ( )... SFRs not user accessable
2)
Semiconductor Group
7-27
Device Specification
Table 3
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
Contents
after Reset
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
0E0H 1)
0F0H 1)
83H
82H
92H
0D0H 1)
81H
00H
00H
00H
00H
XXXX X000B3)
00H
07H
A/DConverter
ADCON0
ADCON1
ADDATH
ADDATL
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Reg. High Byte
A/D Converter Data Reg. Low Byte
0D8H 1)
0DCH
0D9H
0DAH
00H
00H
00H
00H
Interrupt
System
IEN0
CTCON 2)
IEN1
IEN2
IP0
IP1
IRCON0
IRCON1
TCON 2)
TCON 2)
Interrupt Enable Register 0
Com. Timer Control Register
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register
Interrupt Request Control Register
Timer Control Register
Timer 2 Control Register
0A8H 1)
0E1H
0B8H 1)
9AH
0A9H
0B9H
0C0H 1)
0D1H
88H 1)
0C8H
00H
0X00 0000B
00H
XX00 00X0B 3)
00H
XX00 0000B
00H
00H
00H
00H
MUL/DIV
Unit
ARCON
MD0
MD1
MD2
MD3
MD4
MD5
Arithmetic Control Register
Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5
0EFH
0E9H
0EAH
0EBH
0ECH
0EDH
0EEH
0XXXX XXXXB
XXH
XXH
XXH
XXH
XXH
XXH
1)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate and the location is reserved
2)
Semiconductor Group
7-28
Device Specification
Table 3
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address
Contents
after Reset
Compare/
CaptureUnit
(CCU)
Timer 2
CCEN
CC4EN
CCH1
CCH2
CCH3
CCH4
CCL1
CCL2
CCL3
CCL4
CMEN
CMH0
CMH1
CMH2
CMH3
CMH4
CMH5
CMH6
CMH7
CML0
CML1
CML2
CML3
CML4
CML5
CML6
CML7
CMSEL
CRCH
CRCL
COMSETL
COMSETH
COMCLRL
COMCLRH
SETMSK
Comp./Capture Enable Reg.
Comp./Capture Enable 4 Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 4, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Comp./Capture Reg. 4, Low Byte
Compare Enable Register
Compare Register 0, High Byte
Compare Register 1, High Byte
Compare Register 2, High Byte
Compare Register 3, High Byte
Compare Register 4, High Byte
Compare Register 5, High Byte
Compare Register 6, High Byte
Compare Register 7, High Byte
Compare Register 0, Low Byte
Compare Register 1, Low Byte
Compare Register 2, Low Byte
Compare Register 3, Low Byte
Compare Register 4, Low Byte
Compare Register 5, Low Byte
Compare Register 6, Low Byte
Compare Register 7, Low Byte
Compare Input Select
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Compare Register, Low Byte
Compare Register, High Byte
Compare Register, Low Byte
Compare Register, High Byte
Mask Register, concerning
COMSET
0C1H
0C9H
0C3H
0C5H
0C7H
0CFH
0C2H
0C4H
0C6H
0CEH
0F6H
0D3H
0D5H
0D7H
0E3H
0E5H
0E7H
0F3H
0F5H
0D2H
0D4H
0D6H
0E2H
0E4H
0E6H
0F2H
0F4H
0F7H
0CBH
0CAH
0A1H
0A2H
0A3H
0A4H
0A5H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
1)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate and the location is reserved
2)
Semiconductor Group
7-29
Device Specification
Table 3
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address
Contents
after Reset
Compare/
CaptureUnit
(CCU),
(cont’d)
CLRMSK
0A6H
00H
CTCON
CTRELH
CTRELL
TH2
TL2
T2CON
Mask Register, concerning
COMCLR
Com. Timer Control Reg.
Com. Timer Rel. Reg., High Byte
Com. Timer Rel. Reg., Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
0E1H
0DFH
0DEH
0CDH
0CCH
0C8H 1)
0X00 0000B 3)
00H
00H
00H
00H
00H
Ports
P0
P1
P2
P3
P4
P5
P6
P7
P8
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6,
Port 7, Analog/Digital Input
Port 8, Analog/Digital Input, 4-bit
80H 1)
90H 1)
0A0H 1)
0B0H 1)
0E8H 1)
0F8H 1)
0FAH
0DBH
0DDH
0FFH
0FFH
0FFH
0FFH
0FFH
0FFH
0FFH
Pow.Sav.
Modes
PCON
Power Control Register
87H
00H
Serial
Channels
ADCON 02)
PCON 2)
S0BUF
S0CON
S0RELL
A/D Converter Control Reg.
Power Control Register
Serial Channel 0 Buffer Reg.
Serial Channel 0 Control Reg.
Serial Channel 0 Reload Reg.,
low byte
Serial Channel 0 Reload Reg.,
high byte
Serial Channel 1 Buffer Reg.,
Serial Channel 1 Control Reg.
Serial Channel 1 Reload Reg.,
low byte
Serial Channel 1 Relaod Reg.,
high byte
0D8H 1)
87H
99H
98H 1)
B2H
00H
00H
0XXH 3)
00H
D9H
BAH
XXXX.XX11B 3)
9CH
9BH
9DH
0XXH 3)
0X00 000B 3)
00H
BBH
XXXX.XX11B 3)
S0RELH
S1BUF
S1CON
S1RELL
S1RELH
1)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate and the location is reserved
2)
Semiconductor Group
7-30
Device Specification
Table 3
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address
Contents
after Reset
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Watchdog
IEN0 2)
IEN1 2)
IP0 2)
IP1 2)
WDTREL
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Watchdog Timer Reload Reg.
0A8H 1)
0B8H 1)
0A9H
0B9H
86H
00H
00H
00H
XX00 0000B 3)
00H
1)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is indeterminate and the location is reserved
2)
Semiconductor Group
7-31
Device Specification
A/D Converter
In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is
implemented. Its successive approximation technique provides 7 µs con-version time (fOSC= 16
MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The
main functional blocks are shown in figure 4.
The comparator is a fully differential comparator for a high power supply rejection ratio and very
low offset voltages. The capacitor network is binary weighted providing genuine 10-bit
resolution.
The table below shows the sample time T S and the conversion time T C, which are dependend
on f OSC and a new prescaler (see also Bit ADCL in SFR ADCON 1).
f OSC [MHz]
12
16
18
Prescaler
f ADC [MHz]
Sample Time
TS [µs]
Conversion Time
(incl. sample time)
TC [µs]
÷8
1.5
2.67
9.33
÷ 16
0.75
5.33
18.66
÷8
2.0
2.0
7.0
÷ 16
1.0
4.0
14.0
÷8
–
–
–
÷ 16
1.125
3.55
12.4
Semiconductor Group
7-32
Device Specification
Figure 4
Block Diagram A/D Converter
Semiconductor Group
7-33
Device Specification
Compare/Capture Unit (CCU)
The compare/capture unit is a complex timer/register array for applications that require high
speed I/O pulse width modulation and more timer/counter capabilities.
The CCU contains
– one 16-bit timer/counter (timer2) with 2-bit prescaler, reload capability and a max. clock
frequency of fOSC/12 (1 MHz with a 12 MHz crystal).
– one 16-bit timer (compare timer) with 8-bit prescaler, reload capability and a max. clock
frequency of fOSC/2 (6 MHz with a 12 MHz crystal).
– fifteen 16-bit compare registers.
– five of which can be used as 16-bit capture registers.
– up to 21 output lines controlled by the CCU.
– nine interrupts which can be generated by CCU-events.
Figure 5 shows a block diagram of the CCU. Eight compare registers (CM0 to CM7) can
individually be assigned to either timer 2 or the compare timer. Diagrams of the two timers are
shown in figures 6 and 7. The four compare/capture registers, the compare/reload/capture
register and the comset/comclr register are always connected to timer 2. Depending on the
register type and the assigned timer three different compare modes can be selected.
Table 3 illustrates possible combinations and the corresponding output lines.
Semiconductor Group
7-34
Device Specification
Table 4
CCU Compare Configuration
Assigned Timer Compare Register
Compare Output
Possible Modes
Timer 2
CRCH/CRCL
CC1H/CC1L
CC2H/CC2L
CC3H/CC3L
CC4H/CC4L
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2/CC4
Comp. mode 0, 1 + Reload
Comp. mode 0, 1
Comp. mode 0, 1
Comp. mode 0, 1
Comp. mode 0, 1
CC4H/CC4L
:
CC4H/CC4L
P5.0/CCM0
:
P5.7/CCM7
Comp. mode 1
:
Comp. mode 1
COMSETL/COMSETH P5.0/CCM0
:
P5.7/CCM7
Comp. mode 2
:
Comp. mode 2
P5.0/CCM0
:
P5.7/CCM7
Comp. mode 2
:
Comp. mode 2
P4.0/CM0
:
P4.7/CM7
Comp. mode 1
:
Comp. mode 1
P4.0/CM0
Comp. mode 0
(with shadow latches)
:
Comp. mode 0
(with shadow latches)
COMCLRL/
COMCLRH
CM0H/CM0L
:
CM7H/CM7L
Compare
timer
CM0H/CM0L
:
CM7H/CM7L
Semiconductor Group
:
P4.7/CM7
7-35
Device Specification
Figure 5
Block Diagram of the Compare/Capture Unit
Semiconductor Group
7-36
Device Specification
Compare
In compare mode, the 16-bit values stored in the dedicated compare registers are compared
to the contents of the timer 2 register or the compare timer register. If the count value in the
timer registers matches one of the stored value, an appropriate output signal is generated at
the corresponding pin(s) and an interrupt is requested. Three compare modes are provided:
Mode 0:
Upon a match the output signal changes from low to high.
It returns to low level at timer overflow.
Mode 1:
The transition of the output signal can be determined by software.
A timer overflow signal does not affect the compare-output.
Mode 2:
In compare mode 2 the concurrent compare output pins on Port 5 are used
as follows (see figure 9)
– When a compare match occurs with register COMSET, a high level
appears at the pins of port 5 whose corresponding bits in the mask
register SETMSK (address 0A5H) are set.
– When a compare match occurs in register COMCLR, a low level
appears at the pins of port 5 whose corresponding bits in the mask
register CLRMSK (address 0A6H) are set.
Additionally the Port 5 pins used for compare mode 2 may also be
directly written to by write instructions to SFR P5. Of course, the pins
can also be read under program control.
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.
Figure 8 shows the function of these latches. The latches are implemented to prevent from loss
of compare matches which may occur when loading of the compare values is not correlated
with the timer count. The compare latches are automatically loaded from the compare registers
at every timer overflow.
Capture
This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to 'freeze' the current
16-bit value of timer 2 registers into a dedicated capture register.
Mode 0:
Capture is performed in response to a transition at the corresponding
port 1 pins CC0 to CC3.
Mode 1:
Write operation into the low-order byte of the dedicated capture register
causes the timer 2 contents to be latched into this register.
Semiconductor Group
7-37
Device Specification
Reload of Timer 2
A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the
8-bit registers CRCL and CRCH. There are two modes from which to select:
Mode 0:
Reload is caused by a timer overflow (auto-reload).
Mode 1:
Reload is caused in response to a negative transition at pin T2EX (P1.5),
which can also request an interrupt.
Timer/Counters 0 and 1
These timer/counters are fully compatible with timer/counter 0 or 1 of the SAB 8051 and can
operate in four modes:
Mode 0:
8-bit timer/counter with 32:1 prescaler
Mode 1:
16-bit timer/counter
Mode 2:
8-bit timer/counter with 8-bit auto reload
Mode 3:
Timer/counter 0 is configured as one 8-bit timer;
timer/counter 1 in this mode holds its count.
External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters
0 and 1 to facilitate pulse width measurements.
Semiconductor Group
7-38
Device Specification
Figure 6
Block Diagram of Timer 2
Semiconductor Group
7-39
Device Specification
Figure 7
Block Diagram of the Compare Timer
Figure 8
Compare-Mode 0 with Registers CM0 to CM7
Semiconductor Group
7-40
Device Specification
Figure 9
Compare-Mode 2 (Port 5 only)
Semiconductor Group
7-41
Device Specification
Interrupt Structure
The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request
flags.
Table 5
Interrupt Sources and Vectors
Interrupt Request Flags
Interrupt Vector Address
Interrupt Source
IE0
TF0
IE1
TF1
RI0 + TI0
TF2 + EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
RI1/TI1
ICMP0 to ICMP7
0003H
000BH
0013H
001BH
CTF
ICS
009BH
ICR
00ABH
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
Serial channel 0
Timer 2 overflow/ext. reload
A/D converter
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Serial channel 1
Compare match interrupt of
Compare Registers CM0CM7 assigned to Timer 2
Compare timer overflow
Compare match interrupt of
Compare Register COMSET
Compare match interrupt of
Compare Register COMCLR
0023H
002BH
0043H
004BH
0053H
005BH
0063H
006BH
0083H
0093H
00A3H
Each interrupt vector can be individually enabled/disabled. The response time to an interrupt
request is more than 3 machine cycles and less than 9 machine cycles.
External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)
at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering
on a negative or a positive transition. The external interrupts 2 to 6 are combined with the
corresponding alternate functions compare (output) and capture (input) on port 1.
For programming of the priority levels the interrupt vectors are combined to pairs or triples.
Each pair or triple can be programmed individually to one of four priority levels by setting or
clearing one bit in special function register IP0 and one in IP1. Figure 9 shows the interrupt
request sources, the enabling and the priority level structure.
Semiconductor Group
7-42
Device Specification
Figure 10
Interrupt Structure of the SAB 80C517A
Semiconductor Group
7-43
Device Specification
Figure 10
Interrupt Structure of the SAB 80C517A (cont’d)
Semiconductor Group
7-44
Device Specification
Figure 10
Interrupt Structure of the SAB 80C517A (cont’d)
Semiconductor Group
7-45
Device Specification
Multiplication/Division Unit
This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift
and normalize features. All operations are integer operation.
Operation
Result
Remainder
Execution Time
32-bit/16-bit
32-bit
16-bit
6 t cy 1)
16-bit/16-bit
16-bit
16-bit
4 t cy
16-bit *16-bit
32-bit
–
4 t cy
32-bit normalize
–
–
6 t cy 2)
32-bit shift left/right
–
–
6 t cy 2)
1)
2)
1 tcy = 1 µs @ 12 MHz oscillator frequency.
The maximal shift speed is 6 shifts/cycle.
The MDU consists of six registers used for operands and results and one control register.
Operation of the MDU can be divided in three phases:
Operation of the MDU
To start an operation, register MD0 to MD5 (or ARCON) must be written to in a certain sequence according to table 5 or 6. The order the registers are accessed determines the type of
the operation. A shift operation is started by a final write operation to register ARCON (see also
the register description).
Semiconductor Group
7-46
Device Specification
Table 6
Performing a MDU-Calculation
Operation
32 Bit/16 Bit
16 Bit/16 Bit
16 Bit * 16 Bit
First Write
MD0
MD1
MD2
MD3
MD4
MD5
D’endL
D’end
D’end
D’endH
D’orL
D’orH
MD0
MD1
D’endL
D’endH
MD0
MD4
M’andL
M’orL
MD4
D’orL
MD1
M’andH
MD5
D’orH
MD5
M’orH
MD0
MD1
MD2
MD3
MD4
MD5
QuoL
Quo
Quo
QuoH
RemL
RemH
MD0
MD1
QuoL
QuoH
MD0
MD1
PrL
MD4
RemL
MD2
MD5
RemH
MD3
Last Write
First Read
Last Read
PrH
Table 7
Shift Operation with the MDU
Operation
Normalize, Shift Left, Shift Right
First Write
MD0
MD1
MD2
MD3
ARCON
Last Write
First Read
Last Read
MD0
MD1
MD2
MD3
least significant byte
most significant byte
start of conversion
least significant byte
most significant byte
Abbreviations
D’end
D’or
M’and
M’or
Pr
Rem
Quo
...L
...H
:
:
:
:
:
:
:
:
:
Dividend, 1st operand of division
Divisor, 2nd operand of division
Multiplicand, 1st operand of multiplication
Multiplicator, 2nd operand of multiplication
Product, result of multiplication
Remainder
Quotient, result of division
means, that this byte is the least significant of the 16-bit or 32-bit operand
means, that this byte is the most significant of the 16-bit or 32-bit operand
I/O Ports
The SAB 80C517A has seven 8-bit I/O ports and two input ports (8-bit and 4-bit wide).
Port 0 is an open-drain bidirectional I/O port, while ports 1 to 6 are quasi-bidirectional I/O ports
Semiconductor Group
7-47
Device Specification
with internal pull-up resistors. That means, when configured as inputs, ports 1 to 6 will be
pulled high and will source current when externally pulled low. Port 0 will float when configured
as input.
Port 0 and port 2 can be used to expand the program and data memory externally. During an
access to external memory, port 0 emits the low-order address byte and reads/writes the data
byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain
port, but uses a strong internal pull-up FET. Port 1, 3, 4, 5 and port 6 provide several alternate
functions. Please see the "Pin Description" for details.
Port pins show the information written to the port latches, when used as general purpose port.
When an alternate function is used, the port pin is controlled by the respective peripheral unit.
Therefore the port latch must contain a "one" for that function to operate. The same applies
when the port pins are used as inputs. Ports 1, 3, 4 and 5 are bit- addressable.
The SAB 80C517A has two dual-purpose input ports. The twelve port lines at port 7 and port
8 can be used as analog inputs for the A/D converter. If input voltages at P7 and P8 meet the
specified digital input levels (VIL and VIH) the port can also be used as digital input port.
In Hardware Power Down Mode the port pins and several control lines enter a floating state.
For more details see the section about Hardware Power Down Mode.
Semiconductor Group
7-48
Device Specification
Power Saving Modes
The SAB 80C517A provides – due to Siemens ACMOS technology – four modes in which power consumption can be significantly reduced.
– The Slow Down Mode
The controller keeps up the full operating functionality, but is driven with one eighth
of its normal operating frequency. Slowing down the frequency remarkable reduces
power consumption.
– The Idle Mode
The CPU is gated off from the oscillator, but all peripherals are still supplied with the
clock and continue working.
– The Power Down Mode
Operation of the SAB 80C517A is stopped, the on-chip oscillator and the RC-oscillator
are turned off. This mode is used to save the contents of the internal RAM with a very
low standby current.
– The Hardware Power Down Mode
Operation of the SAB 80C517A is stopped, the on-chip oscillator and the RC-Oscillator
are turned off. The pin HWPD controls this mode. Port pins and several control lines
enter a floating state. The Hardware Power Down Mode is independent of the state of
pin PE/SWD.
Hardware Enable for Software controlled Power Saving Modes
A dedicated Pin PE/SWD) of the SAB 80C517A allows to block the Software controlled power
saving modes. Since this pin is mostly used in noise-critical application it is combined with an
automatic start of the Watchdog Timer.
PE/SWD = V IH (logic high level):
Using of the power saving modes is not possible.
The watchdog timer starts immediately after reset.
The instruction sequences used for entering of
power saving modes will not affect the normal operation
of the device.
PE/SWD = V IL (logic low level):
All power saving modes can be activated by software.
When left unconnected, Pin /PE/SWD is pulled high by a weak internal pullup. This is done to
provide system protection on default.
The logic-level applied to pin PE/SWD can be changed during program execution to allow or to
block the use of the power saving modes without any effect on the on-chip watchdog circuitry.
Semiconductor Group
7-49
Device Specification
Requirements for Hardware Power Down Mode
There is no dedicated pin to enable the Hardware Power Down Mode. Nevertheless for a
correct function of the Hardware Power Down Mode the oscillator watchdog unit including its
internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE =
high). However, the control pin PE/SWD has no control function in this mode. It enables and
disables only the use of software controlled power saving modes.
Software controlled power saving modes
All of these modes are entered by software. Special function register PCON (power control
register, address is 87H) is used to select one of these modes.
Slow Down Mode
During slow down operation all signal frequencies that are derived from the oscillator clock, are
divided by eight, also the clockout signal and the watchdog timer count.
The slow down mode is enabled by setting bit SD. The controller actually enters the slow down
mode after a short synchronisation period (max. 2 machine cycles).
The slow down mode is disabled by clearing bit SD.
Idle Mode
During idle mode all peripherals of the SAB 80C517A (except for the watchdog timer) are still
supplied by the oscillator clock. Thus the user has to take care which peripheral should
continue to run and which has to be stopped during Idle.
The procedure to enter the idle mode is similar to the one entering the power down mode. The
two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of
unintentional activating of the idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will
be serviced and the instruction to be executed following the RETI instruction will be the
one following the instruction that set the bit IDLS.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is
still running, the hardware reset must be held active only for two machine cycles for
a complete reset.
Normally the port pins hold the logical state they had at the time idle mode was activated. If
some pins are programmed to serve their alternate functions they still continue to output during
idle mode if the assigned function is on. The control signals ALE and hold at logic high levels
PSEN (see table 8).
Semiconductor Group
7-50
Device Specification
Power Down Mode
The power down mode is entered by two consecutive instructions directly following each other.
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
automatically be cleared after having been set.
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset.
The status of all output lines of the controller can be looked up in table 8.
Hardware Controlled Power Down Mode
The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware
Power Down Mode; this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
same time the port pins and several control lines enter a floating state as shown in table 8. In
this state the power consumption is reduced to the power down current IPD. Also the supply
voltage can be reduced. Table 8 also lists the voltages which may be applied at the pins during
Hardware Power Down Mode without affecting the low power consumption.
Termination of HWPD Mode:
This power down state is maintained while pin HWPD is held active. If HWPD goes to high
level (inactive state) an automatic start up procedure is performed:
– First the pins leave their floating condition and enter their default reset state
(as they had immediately before going to float state).
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
oscillator starts up very fast (typ. less than 2 micro
microseconds).
seconds)
– Because the oscillator watchdog is active it detects a failure condition if the
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
and supplies the internal clock from the RC oscillator.
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
the part from reset with oscillator watchdog status flag not set
set.
When automatic start of the watchdog was enabled (PE/SWD connected to VCC),
the Watchdog Timer will start, too (with its default reload value for time-out period).
– The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active
during Hardware Power Down it is terminated and the device performs the normal
reset function. (Thus, pin Reset has to be inactive during Hardware Power Down Mode).
Semiconductor Group
7-51
Device Specification
Table 8
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode
Pins
Idle Mode
Last instruction
executed from
internal
ROM
external
ROM
Power Down Mode
Last instruction
executed from
internal
ROM
external
ROM
Hardware Power Down
Status
P0
Data
float
Data
float
P1
Data alt
outputs
Data alt
outputs
Data last
outputs
Data last
outputs
floating
P2
Data
Address
Data
Data
output
P3
Data alt
outputs
Data alt
outputs
Data
Data
outputs
last output last output
P4
Data alt
outputs
Data alt
outputs
Data last
outputs
P5
Data
alt output
Data
alt output
Data
Data
input
last output last output
P6
Data
alt output
Data
alt output
Data
Data
function
last output last output
Data
disabled
last output
Voltage range
at pin
VSS ≤ VIN ≤ VCC
P7
P8
EA
active input
VIN = VCC or
VIN = VSS
PE/SWD
active input
pull-up
disabled
VIN = VCC or
VIN = VSS
XTAL1
active output pin may not be
driven
XTAL2
disabled
input
functions
Semiconductor Group
7-52
VSS ≤VIN ≤ VCC
Device Specification
Table 8
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode (cont’d)
Pins
Idle Mode
Last instruction
executed from
internal
ROM
external
ROM
Power Down Mode
Last instruction
executed from
internal
ROM
Status
Voltage range
at pin
VSS ≤ VIN≤ VCC
ALE
floating
outp. disabled input
functions
VAREF
VAGND
active supply pins
VAGND ≤ VIN
≤ VCC
OWE
active input,
must be
high pull-up
disabl.
VIN = VCC
RESET
active input
VIN = VCC
must be high
RO
floating
output
PSEN
Semiconductor Group
7-53
external
ROM
Hardware Power Down
VSS ≤ VIN≤ VCC
Device Specification
Serial Interfaces
The SAB 80C517A has two serial interfaces. Both interfaces are full duplex and receive
buffered. They are functionally identical with the serial interface of the SAB 8051 when working
as asynchronous channels. Serial interface 0 additionally has a synchronous mode. Table 9
shows possible configurations and the according baud rates.
Table 9
Baud Rate Generation
Mode
8-Bit
synchronous
channel
Baudrate
Mode 0
f O SC =1
2 MHz
1MHz
–
fOSC =
16 MHz
1.33 MHz
–
f OSC =
18 MHz
1.5 MHz
–
f OSC
–
derived from
Mode
8-Bit
UART
Baudrate
derived
from
Mode B
1 Baud –
62.5 kBaud
183 Baud –
375 kBaud
366 Baud –
375 kBaud
fOSC =
16 MHz
1 Baud –
83 kBaud
244 Baud –
500 kBaud
244 Baud –
500 kBaud
fOSC =
18 MHz
1 Baud –
93.7 kBaud
2375 Baud –
562.5 kBaud
549 Baud –
562.5 kBaud
Timer 1
10-Bit
Baudrate
Generator
10-Bit
Baudrate
Generator
Mode
Baudrate
Mode 1
f OSC =
12 MHz
derived from
9-Bit
UART
–
Mode 2
Mode 3
Mode A
fOSC =
12 MHz
187.5 kBaud/ 1 Baud –
375 kBaud
62.5 kBaud
183 Baud –
75 kBaud
183 Baud –
75 kBaud
fOSC=
16 MHz
250 Baud/
500 kBaud
244 Baud –
500 kBaud
244 Baud –
500 kBaud
fOSC =
18 MHz
281.2 kBaud/ 1 Baud –
562.5 kBaud 93.7 kBaud
275 Baud
562.5 kBaud
549 Baud –
562.5 kBaud
fOSC/2
Timer 1
Semiconductor Group
1 Baud –
83.3 kBaud
10-Bit
Baudrate
Generator
7-54
10-Bit
Baudrate
Generator
Device Specification
Serial Interface 0
Serial Interface 0 can operate in 4 modes:
Mode 0:
Shift register mode:
Serial data enters and exits through R × D0. T × D0 outputs the shift
clock 8 data bits are transmitted/received (LSB first). The baud rate is fixed at
1/12 of the oscillator frequency.
Mode 1:
8-bit UART, variable baud rate:
10-bit are transmitted (through T × D0) or received (through R × D0): a start
bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit
goes into RB80 in special function register S0CON. The baud rate is
variable.
Mode 2:
9-bit UART, fixed baud rate:
11-bit are transmitted (through T × D0) or received (through R × D0): a start
bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1).
On transmission, the 9th data bit (TB80 in S0CON) can be assigned to the
value of 0 or 1. For example, the parity bit (P in the PSW) could be moved
into TB80 or a second stop bit by setting TB80 to 1. On reception the 9th
data bit goes into RB80 in special function register S0CON, while the stop
bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the
oscillator frequency.
Mode 3:
9-bit UART, variable baud rate:
11-bit are transmitted (through T × D0) or received (through R × D0): a start
bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1). In
fact, mode 3 is the same as mode 2 in all respects except the baud rate.
The baud rate in mode 3 is variable.
Variable Baud Rates for Serial Interface 0
Variable baud rates for modes 1 and 3 of serial interface 0 can be derived from either timer 1
or a dedicated Baudrate Generator.
The baud rate is generated by a free running 10-bit timer with programmable reload register.
Mode 1.3 baud rate =
Mode 1.3 baud rate =
2 SMOD * f OSC
64*(210-S0REL)
The default value after reset in the reload registers S0RELL and S0RELH provide a baud rate
of 4.8 kBaud (SMOD = 0) or 9.6 kBaud (SMOD = 1) at 12 MHz oscillator frequency. This guarantees full compatibility to the SAB 80C517.
Semiconductor Group
7-55
Device Specification
Serial Interface 1
Serial interface 1 can operate in two asynchronous modes:
Mode A:
9-bit UART, variable baud rate.
11 bits are transmitted (through T × D1) or received (through R × D1):
a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1).
On transmission, the 9th data bit (TB81 in S1CON) can be assigned to the
value of 0 or 1. For example, the parity bit (P in the PSW) could be moved
into TB81 or a second stop bit by setting TB81 to 1. On reception the 9th
data bit goes into RB81 in special function register S1CON, while the stop
bit is ignored.
Mode B:
8-bit UART, variable baud rate.
10 bits are transmitted (through T × D1) or received (through R × D1):
a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the
stop bit goes into RB81 in special function register S1CON.
Variable Baud Rates for Serial Interface 1.
Variable baud rates for modes A and B of serial interface 1 are derived from a dedicated baud
rate generator.
baud rate clock
The baud rate clock (baud rate =
) is generated by an 10-bit free running timer
16
with programmable reload register.
f O SC
Mode A, B baudrate =
32 * (2 10 - SREL)
Semiconductor Group
7-56
Device Specification
Watchdog Units
The SAB 80C517A offers two enhanced fail safe mechanisms, which allow an automatic
recovery from hardware failure or software upset:
– programmable watchdog timer (WDT), variable from 512 µs up to appr. 1.1 s time-out
period @12 MHz. Upward compatible to SAB 80515 watchdog.
– oscillator watchdog (OWD), monitors the on-chip oscillator and forces the microcontroller into reset state, in case the on-chip oscillator fails, controls the restart from
the Hardware Power Down Mode and provides clock for a fast internal reset after power-on.
Programmable Watchdog Timer
The WDT can be activated by hardware or software.
Hardware initialization is done when pin PE/SWD (Pin 4) is held high during RESET. The
SAB 80C517A then starts program execution with the WDT running. Since Pin PE/SWD is
only sampled during Reset (and hardware power down at parts with stepping code AD and
later) dynamical switching of the WDT is not possible.
Software initialization is done by setting bit SWDT.
A refresh of the watchdog timer is done by setting bits WDT and SWDT consecutively.
A block diagram of the watchdog timer is shown in figure 11.
When a watchdog timer resest occurs, the watchdog timer keeps on running, but a status flag
WDTS is set. This flag can also be cleared by software.
Figure 11
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group
7-57
Device Specification
Oscillator Watchdog
The unit serves three functions:
– Monitoring of the on-chip oscillator’s function.
The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is
supplied by the RC oscillator and the device is forced into reset; if the failure condition
disappears (i.e. the on-chip oscillator has again a higher frequency than the RC oscillator),
the part executes a final reset phase of appr. 0.25 ms in order to allow the oscillator
to stabilize; then the oscillator watchdog reset is released and the part starts
program execution again.
– Restart from the Hardware Power Down Mode.
If the Hardware Power Down Mode is terminated the oscillator watchdog has to control
the correct start-up of the on-chip oscillator and to restart the program. The oscillator
watchdog function is only part of the complete Hardware Power Down sequence; however,
the watchdog works identically to the monitoring function.
– Fast internal reset after power-on.
In this function the oscillator watchdog unit provides a clock supply for the reset before
the on-chip oscillator has started. In this case the oscillator watchdog unit also
works identically to the monitoring function.
If the oscillator watchdog unit is to be used it must be enabled (this is done by applying high
level to the control pin OWE).
Figure 12 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC
oscillator which provides the reference frequency of the on-chip oscillator. The RC oscillator
can be enabled/disabled by the control pin OWE. If it is disabled the complete unit has no
function.
Semiconductor Group
7-58
Device Specification
Figure 12
Functional Block Diagram of the Oscillator Watchdog
Semiconductor Group
7-59
Device Specification
Fast internal reset after power-on
The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after
power-on.
Normally members of the 8051 family (like the SAB 80C517) enter their default reset state not
before the on-chip oscillator starts. The reason is that the external reset signal must be
internally synchronized and processed in order to bring the device into the correct reset state.
Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms).
During this time period the pins have an undefined state which could have severe effects e.g.
to actuators connected to port pins.
In the SAB 80C517A the oscillator watchdog unit avoids this situation. However, the oscillator
watchdog must be enabled. In this case, after power-on the oscillator watch-dog’s RC
oscillator starts working within a very short start-up time (typ. less than 2 micro-seconds). In
the following the watchdog circuitry detects a failure condition for the on-chip oscillator
because this has not yet started (a failure is always recognized if the watchdog’s RC oscillator
runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the
RC oscillator output as clock source for the chip rather than the on-chip oscillator’s output.This
allows correct resetting of the part and brings also all ports to the defined state.
Delay time between power-on and correct reset state:
Typ.: 18 µs
Max.: 34 µs
Instruction Set
The SAB 80C517A / 83C517A-5 has the same instruction set as the industry standard 8051
microcontroller.
A pocket guide is available which contains the complete instruction set in functional and
hexadecimal order. Furtheron it provides helpful information about Special Function Registers,
Interrupt Vectors and Assembler Directives.
Literature Information
Title
Ordering No.
Microcontroller Family SAB 8051 Pocket Guide
B158-H6497-X-X-7600
Semiconductor Group
7-60
Device Specification
Absolute Maximum Ratings
Ambient temperature under bias................................................................. – 40 to 110° C
Storage temperature ................................................................................... – 65 to 150 oC
Voltage on VCC pins with respect to ground (VSS) ...................................... – 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS) ........................................ – 0.5 to VCC +0.5 V
Input current on any pin during overload condition ..................................... – 10mA to +10mA
Absolute sum of all input currents during overload condition...................... |100mA|
Power dissipation ........................................................................................ 1 W
Note Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or V IN <
VSS) theVoltage on VCC pins with respect to ground (VSS) must not exeed the values
definded by the absolute maximum ratings.
DC Characteristics
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
TA=
0 to 70 oC for the SAB 80C517A/83C517A-5
T A = – 40 to 85 oC for the SAB 80C517A-T3/83C517A-5-T3
T A = – 40 to 110 oC for the SAB 80C517A-T4/83C517A-5-T4
Parameter
Symbol
Limit Values
min.
Unit
Test condition
max.
Input low voltage
(except EA, RESET, HWPD)
VIL
– 0.5
0.2 VCC –
0.1
V
–
Input low voltage (EA)
VIL1
– 0.5
0.2 VCC –
0.3
V
–
Input low voltage (HWPD,
RESET)
VIL2
– 0.5
0.2 V C C
+ 0.1
V
–
Input high voltage (except
RESET, XTAL2 and HWPD
VIH
0.2 VCC
+ 0.9
VCC + 0.5 V
–
Input high voltage to XTAL2
VIH1
0.7 VCC
VCC + 0.5 V
–
Input high voltage to RESET
and HWPD
VIH2
0.6 VCC
VCC + 0.5 V
–
Semiconductor Group
7-61
Device Specification
DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
min.
Unit
Test condition
max.
Output low voltage
(ports 1, 2, 3, 4, 5, 6)
VOL
–
0.45
V
IOL=1.6 mA1)
Output low voltage
(ports ALE, PSEN, RO)
VOL1
–
0.45
V
IOL=3.2 mA 1)
Output high voltage
(ports 1, 2, 3, 4, 5, 6)
VOH
2.4
0.9 VCC
–
–
V
V
IOH =–80 µA
IOH =–10 µA
Output high voltage
(port 0 in external bus mode,
ALE, PSEN, RO)
VOH1
2.4
0.9 VCC
–
–
V
V
IOH =–800 µA2)
IOH =–80 µA2)
Logic input low current
(ports 1, 2, 3, 4, 5, 6)
IIL
– 10
– 70
µA
VIN = 0.45 V
Logical 1-to-0 transition current ITL
(ports 1, 2, 3, 4, 5, 6)
– 65
– 650
µA
VIN = 2 V
Input leakage current
(port 0, EA, ports 7, 8, HWPD)
ILI
–
±
100
nA
0.45 < VIN < VCC
±
150
nA
0.45 < VIN < VCC
TA > 100 oC
Input low current to RESET
for reset
IIL2
– 10
–100
µA
VIN = 0.45 V
Input low current (XTAL2)
IIL3
–
– 15
µA
VIN = 0.45 V
Input low current
(PE/SWD, OWE)
IIL4
–
– 20
µA
VIN = 0.45 V
Pin capacitance
CIO
–
10
pF
fC= 1 MHz
TA= 25 oC
Power supply current:
Active mode, 12 MHz7)
Active mode, 18 MHz7)
Idle mode, 12 MHz7)
Idle mode, 18 MHz7)
Slow down mode, 12 MHz
Slow down mode, 18 MHz
Power Down Mode
ICC
ICC
ICC
ICC
ICC
ICC
I PD
–
–
–
–
–
–
–
28
37
24
31
12
16
50
mA
mA
mA
mA
mA
mA
µA
VCC = 5 V,4)
VCC = 5 V,4)
VCC = 5 V,5)
VCC = 5 V,5)
VCC = 5 V,6)
VCC = 5 V,6)
VCC = 2...5.5 V, 3)
Notes see page 63.
Semiconductor Group
7-62
Device Specification
Notes for page 62:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed
on the VOL of ALE and ports 1, 3, 4, 5 and 6. The noise is due to external bus capacitance
discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during
bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line
may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily
fall below the 0.9 V C C specification when the address lines are stabilizing.
3) IPD (Power down mode) is measured with:
EA = RESET = VCC; Port0 = Port7 = Port8 = VCC; XTAL1 = N.C.; XTAL2 = VSS;
PE/SWD = OWE = V SS;HWDP = VCC (Software Power Down mode); V ARef = VCC;
V AGND = V SS; all other pins are disconnected. Hardware Powerdown IPD : OWE =VCC
or VSS. No certain pin connection for the other pins.
4) ICC (active mode) is measured with:
XTAL2 driven with tCLCH, tCHCL = 5 ns, V IL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL1 = N.C.;
EA = PE/SWD = VCC; Port0 = Port7 = Port8 = VCC; HWPD = VCC; RESET = V SS
all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is
used (appr. 1 mA).
5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with tCLCH, t CHCL = 5 ns, V IL = VSS + 0.5 V, VIH = VCC – 0.5 V;
XTAL1 = N.C.; RESET = VCC; HWPD = VCC; Port0 = Port7 = Port8 =VCC ;
EA = PE/SWD = VSS; all other pins are disconnected;
6) ICC (slow down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH, t CHCL = 5 ns, VIL = VSS + 0.5 V, VIH =VCC – 0.5 V;
XTAL1 = N.C.;RESET= VCC; HWPD = VCC; Port7 = Port8 = VCC; EA = PE/SWD = VSS ;
all other pins are disconnected;
7) ICC Max at other frequencies is given by:
active mode: ICC (max) = 1.50* f OSC + 10
idle mode: ICC (max) = 1.17* f OSC + 10
where fOSC is the oscillator frequency in MHz. ICC values are given in mA and
measured at VCC = 5 V.
Semiconductor Group
7-63
Device Specification
A/D Converter Characteristics
V CC = 5 V + 10 %, – 15 %; V SS = 0 V
VAREF = VCC ± 5%; VAGND = VSS ± 0.2 V;
0 to 70 oC for the SAB 80C517A/83C517A-5
TA=
T A = – 40 to 85 o C for the SAB 80C517A-T3/83C517A-5-T3
T A = – 40 to 110 oC for the SAB 80C517A-T4/83C517A-5-T4
Parameter
Symbol
Limit values
min.
Analog input capacitance CI
Unit
typ.
max.
25
70
pF
Test condition
Sample time
(inc. load time)
TS
4 t CY1)
µs
2)
Conversion time
(inc. sample time)
TC
14 t CY1) µs
3)
Total unadjusted error
TUE
±
LSB
VAREF = V CC
VAGND = V SS
VAREF supply current
IREF
µA
4)
1)
2)
3)
4)
±
ADCL
ADCL
20
2
) /f
t CY = (8*2
))
OSC; (tCY = 1/fADC; fADC = fOSC/(8*2
This parameter specifies the time during the input capacitance CI, can be charged/discharged by the
external source. It must be guaranteed, that the input capacitance CI,, is fully loaded within this time.
4TCY is 2 µs at the fOSC= 16 MHz. After the end of the sample time T S, changes of the analog input
voltage have no effect on the conversion result.
This parameter includes the sample time T S. 14TCY is 7 µs at fOSC = 16 MHz.
The differencial impedance rD of the analog reference source must be less than 1 KΩ at reference supply
voltage.
Semiconductor Group
7-64
Device Specification
AC Characteristics
V CC = 5 V + 10 %, – 15 %; V SS = 0 V
TA=
0 to 70 oC for the SAB 80C517A/83C517A-5
T A = – 40 to 85 oC for the SAB 80C517A-T3/83C517A-5-T3
T A = – 40 to110 o C for the SAB 80C517A-T4/83C517A-5-T4
(C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF)
Parameter
Symbol
Limit values
18 MHz clock
min.
Unit
Variable clock
1/t CLCL = 3.5 MHz to 18 MHz
max.
min.
max.
Program Memory Characteristics
ALE pulse width
tLHLL
71
–
2 tCLCL – 40
–
ns
Address setup to ALE
tAVLL
26
–
tCLCL – 30
–
ns
Address hold after ALE
tLLAX
26
–
tCLCL – 30
–
ns
ALE to valid instruction
tLLIV
–
122
–
4tCLCL – 100
ns
ALE to PSEN
tLLPL
31
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
132
–
3 tCLCL – 35
–
ns
PSEN to valid instruction tPLIV
–
92
–
3tCLCL – 75
ns
Input instruction hold
after PSEN
tPXIX
0
–
0
Input instruction float
after PSEN
tPXIZ
–
46
–
tCLCL – 10
ns
Address valid after
PSEN
tPXAV*)
48
–
tCLCL – 8
–
ns
Address to valid instr in
tAVIV
–
218
–
5tCLCL – 60
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*)
ns
Interfacing the SAB 80C51 7A to devices with float times up to 45 ns is permissible.
This limited bus contention will not cause any damage to port 0 drivers.
Semiconductor Group
7-65
Device Specification
AC Characteristics (cont’d)
Parameter
Symbol
Limit values
18 MHz clock
min.
Unit
Variable clock
1/t CLCL = 3.5 MHz to 18 MHz
max.
min.
max.
External Data Memory Characteristics
RD pulse width
tRLRH
233
–
6 tCLCL – 100
–
ns
WR pulse width
tWLWH
233
–
6 tCLCL – 100
–
ns
Address hold after ALE
tLLAX2
81
–
2 tCLCL – 30
–
ns
RD to valid data in
tRLDV
–
128
–
5 tCLCL – 150
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
51
–
2 tCLCL – 60
ns
ALE to valid data in
tLLDV
–
294
–
8 tCLCL – 150
ns
Address to valid data in
tAVDV
–
335
–
9 tCLCL – 165
ns
ALE to WR or RD
tLLWL
117
217
3 tCLCL – 50
3 tCLCL +50
ns
WR or RD high to ALE
high
tWHLH
16
96
tCLCL – 40
tCLCL +40
ns
Address valid to WR
tAVWL
92
–
4 tCLCL – 130
–
ns
Data valid to WR
transition
tQVWX
11
–
tCLCL – 45
–
ns
Data setup before WR
tQVWH
239
–
7 tCLCL – 150
–
ns
Data hold after WR
tWHQX
16
–
tCLCL – 40
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
Semiconductor Group
7-66
Device Specification
t LHLL
ALE
t AVLL
t PLPH
t LLPL
t
LLIV
t PLIV
PSEN
t AZPL
t PXAV
t LLAX
t PXIZ
t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Program Memory Read Cycle
Data Memory Read Cycle
Semiconductor Group
7-67
Device Specification
t WHLH
ALE
PSEN
t LLWL
t WLWH
WR
t QVWX
t AVLL
t WHQX
t LLAX2
Port 0
A0 - A7 from
Ri or DPL
t QVWH
Data OUT
A0 - A7
from PCL
Instr.IN
t AVWL
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00098
Data Memory Write Cycle
Semiconductor Group
7-68
Device Specification
AC Characteristics (cont’d)
Parameter
Symbol
Limit values
Unit
Variable clock
Frequ. = 3.5 MHz to 18 MHz
min.
max.
External Clock Drive
Oscillator period
tCLCL
55.6
285
ns
High time
tCHCX
20
tCLCL-tCHCX
ns
Low time
tCLCX
20
tCLCL-tCHCX
ns
Rise time
tCLCH
–
20
ns
Fall time
tCHCL
–
20
ns
Oscillator frequency
1/tCLC
3.5
18
MHz
External Clock Cycle
Semiconductor Group
7-69
Device Specification
AC Characteristics (cont’d)
Parameter
Symbol
Limit values
18 MHz clock
min.
max.
Unit
Variable clock
1/t CLCL = 3.5 MHz to 18 MHz
min.
max.
System Clock Timing
ALE to CLKOUT
tLLSH
349
–
7 tCLCL – 40
–
ns
CLKOUT high time
tSHSL
71
–
2 tCLCL – 40
–
ns
CLKOUT low time
tSLSH
516
–
10 tCLCL – 40
–
ns
CLKOUT low to ALE
high
tSLLH
16
96
tCLCL – 40
tCLCL +40
ns
System Clock Timing
Semiconductor Group
7-70
Device Specification
ROM Verification Characteristics
T A = 25°C ± 5°C; V CC = 5 V ± 10%; V SS = 0 V
Parameter
Symbol
Limit values
min.
Unit
max.
ROM Verification Mode 1 (Standard Verify Mode for not Read Protected ROM)
Address to valid data
tAVQV
–
48 tCLCL
ns
ENABLE to valid data
tELQV
–
48 tCLCL
ns
Data float after ENABLE tEHOZ
0
48 tCLCL
ns
Oscillator frequency
4
6
MHz
1/tCLCL
ROM Verification Mode 1
Semiconductor Group
7-71
Device Specification
ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM)
ROM Verification Mode 2
Semiconductor Group
7-72
Device Specification
Application Circuitry for Verifying the Internal ROM
Semiconductor Group
7-73
Device Specification
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and
begins to float when a 100 mV change from the loaded V OH/V OL level occurs. IOL/IOH ≥ ± 20 mA.
AC Testing: Float Waveforms
Recommended Oscillator Circuits
Semiconductor Group
7-74
Device Specification
Package Outlines
Plastic Package, P-LCC-84 – SMD
(Plastic Leaded Chip-Carrier)
Dimensions in mm
Plastic Package, P-MQFP-100-2 – SMD
(Plastic Metric Rectangular Flat Package)
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
7-75