INFINEON SAF

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Microcomputer Components
8-bit CMOS Microcontroller
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Data Sheet 02.00
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C513AO Data Sheet
Revision History :
Current Version: 02.00
Previous Releases:
(Original Version)
For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com
Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to
Infineon Technologies.
Edition 02.00
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 2000.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
c513ao_ds_0200.frm Page 1 Wednesday, August 30, 2000 12:45 PM
8-Bit CMOS Microcontroller
C513AO
Advance Information
• Full upward compatibility with standard 8051 microcontroller
• Up to 16 MHz external operating frequency
– 750 ns instruction cycle at 16 MHz operation
• On-chip program memory
– C513AO-2R: 16 Kbytes ROM (with optional ROM protection)
– C513AO-2E: 16 Kbytes OTP
– C513AO-L: version without on-chip program memory (ROMless)
• Up to 64K byte external data memory
• 256 × 8 RAM
• 256 × 8 XRAM
• Four 8-bit digital I/O ports
• Three 16-bit timers/counters (Timer 2 with Up/Down and 16-bit auto-reload features)
• Full duplex serial interface (USART)
• Synchronous Serial Channel (SSC)
• Seven interrupt sources with two priority levels
• On-chip emulation support logic (Enhanced Hooks Emulation Technology™)
On-Chip Emulation Support Module
(further features are on next page)
Oscillator
Watchdog
Timer 2
XRAM
256 x 8
XRAM
256 x 8
T0
C500
Core
SSC
Interface
Watchdog Timer
T1
ROM/OTP
16 K x 8
Port 0
I/O
Port 1
I/O
Port 2
I/O
Port 3
I/O
8-Bit
USART
MCB04006
Figure 1
C513AO Functional Units
Data Sheet
1
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C513AO
Features (continued):
•
•
•
•
Programmable 15-bit Watchdog Timer
Oscillator Watchdog
Fast Power On Reset
Power Saving Modes
– Slow-down mode
– Idle mode
– Software power-down mode with optional wake up capability through pin P3.2/INT0
• Available in P-DIP40-2, P-LCC-44-1 and P-MQFP-44-2 packages
• Fully pin-compatible with C501, C504, C505C, C505CA and C511/C513-devices.
TA: 0 to 70 °C
• Temperature ranges: SAB-C513AO
TA: – 40 to 85 °C
SAF-C513AO
Ordering Information
The ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:
• the derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery
For the available ordering codes for the C513AO please refer to the “Product Information
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after the
verification of the respective ROM code.
Data Sheet
2
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C513AO
VDD
VSS
Port 0
8-Bit Digital I/O
XTAL1
XTAL2
RESET
Port 1
8-Bit Digital I/O
C513AO
EA
Port 2
8-Bit Digital I/O
ALE
PSEN
Port 3
8-Bit Digital I/O
MCL04007
Figure 2
Logic Symbol
Data Sheet
3
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C513AO
P1.0/T2
1
40
VDD
P1.1/T2EX
2
39
P0.0/AD0
P1.2/SCLK
3
38
P0.1/AD1
P1.3/SRI
4
37
P0.2/AD2
P1.4/STO
5
36
P0.3/AD3
P1.5/SLS
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
RESET
9
32
P0.7/AD7
31
EA
P3.0/RxD
10
C513AO
P3.1/TxD
11
30
ALE
P3.2/INT0
12
29
PSEN
P3.3/INT1
13
28
P2.7/A15
P3.4/T0
14
27
P2.6/A14
P3.5/T1
15
26
P2.5/A13
P3.6/WR
16
25
P2.4/A12
P3.7/RD
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
MCP04008
Figure 3
P-DIP-40-2 Package Pin Configuration (top view)
Data Sheet
4
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P3.7/RD
P3.6/WR
XTAL1
XTAL2
VDD
VSS
P2.1/A9
P2.0/A8
P2.3/A11
P2.2/A10
P2.4/A12
C513AO
28 27 26 25 24 23 22 21 20 19 18
P2.5/A13
29
17
P3.5/T1
P2.6/A14
30
16
P3.4/T0
P2.7/A15
31
15
P3.3/INT1
PSEN
32
14
P3.2/INT0
ALE
33
13
P3.1/TxD
N.C.
34
12
N.C.
EA
35
11
P3.0/RxD
P0.7/AD7
36
10
RESET
P0.6/AD6
P0.5/AD5
37
38
9
8
P1.7
P1.6
P0.4/AD4
39
7
P1.5/SLS
C513AO
P1.3/SRI
P1.4/STO
P1.1/T2EX
P1.2/SCLK
P1.0/T2
VDD
VSS
P0.0/AD0
P0.1/AD1
P0.3/AD3
P0.2/AD2
40 41 42 43 44 1 2 3 4 5 6
MCP04009
Figure 4
P-LCC-44-1 Package Pin Configuration (top view)
Data Sheet
5
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P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
N.C.
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
C513AO
33 32 31 30 29 28 27 26 25 24 23
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
34
22
35
21
36
20
37
19
VDD
VSS
38
P1.0/T2
P1.1/T2EX
P1.2/SCLK
P1.3/SRI
P1.4/STO
40
16
41
15
42
14
43
13
18
C513AO
39
17
12
44
2
3
4
5
6
7
8
VDD
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
9 10 11
P1.5/SLS
P1.6
P1.7
RESET
P3.0/RxD
N.C.
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
MCP04010
Figure 5
P-MQFP-44-2 Package Pin Configuration (top view)
Data Sheet
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C513AO
Table 1
Pin Definitions and Functions
Symbol Pin Number
P- DIP P-LCC- P-MQFP-40
44
44
P1.7P1.0
8-1
9-2
3-1,
44-40
I/O Function
*)
I/O Port 1
Port 1 is an 8-bit quasi-bidirectional port with internal
pull-up arrangement. Port 1 pins that have “1s”
written to them are pulled high by the internal pull-up
transistors and in that state can be used as inputs.
As inputs, Port 1 pins being externally pulled low will
source current (IIL, in the DC characteristics)
because of the internal pull-up transistors.
The output latch corresponding to a secondary
function must be programmed to 1 for that function
to operate.
For the outputs of the Synchronous Serial Channel
(SSC), SCLK and STO, special circuitry is
implemented providing true push-pull capability.
The STO output, in addition, will have true tristate
capability. When used for SSC inputs, the pull-up
transistors will be switched off and the inputs float
(high ohm inputs).
The secondary functions are assigned to the pins of
Port 1 as follows:
*)
1
2
2
3
40
41
3
4
42
4
5
6
5
6
7
43
44
1
P1.0 / T2
P1.1 / T2EX
P1.2 / SCLK
P1.3 / SRI
P1.4 / STO
P1.5 / SLS
Input to Counter 2
Capture/reload trigger of Timer 2
Up-Down count
SSC Master Clock Output
SSC Slave Clock Input
SSC Receive Input
SSC Transmit Output
Slave Select Input
I = Input
O = Output
Data Sheet
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C513AO
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number
P- DIP P-LCC- P-MQFP-40
44
44
P3.0P.3.7
10-17
11,
13-19
5,
7-13
I/O Function
*)
I/O Port 3
Port 3 is an 8-bit quasi-bidirectional port with internal
pull-up arrangement. Port 3 pins that have “1”s
written to them are pulled high by the internal pull-up
transistors and in that state can be used as inputs.
As inputs, Port 3 pins being externally pulled low will
source current (IIL, in the DC characteristics)
because of the internal pull-up transistors.
The output latch corresponding to a secondary
function must be programmed to a “1” for that
function to operate (except for TxD and WR).
The secondary functions are assigned to the pins of
Port 3 as follows:
RESET
*)
10
11
5
P3.0 / RxD
11
13
7
P3.1 / TxD
12
14
8
P3.2 / INT0
13
15
9
P3.3 / INT1
14
15
16
16
17
18
10
11
12
P3.4 / T0
P3.5 / T1
P3.6 / WR
17
19
13
P3.7 / RD
9
10
4
I
Receiver data input (asynch.)
or data input/output (synch.) of
serial interface
Transmitter data output
(asynch.) or clock output
(synch.) of serial interface
External Interrupt 0 input /
Timer 0 gate control input
External Interrupt 1 input /
Timer 1 gate control input
Timer 0 counter input
Timer 1 counter input
WR control output; latches the
data byte from Port 0 into the
external data memory
RD control output; enables the
external data memory to Port 0
RESET
A high level on this pin for the duration of two
machine cycles while the oscillator is running resets
the device. An internal diffused resistor to VSS
permits power-on reset using only an external
capacitor to VDD.
I = Input
O = Output
Data Sheet
8
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C513AO
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number
P- DIP P-LCC- P-MQFP-40
44
44
I/O Function
*)
XTAL2
18
20
14
O
XTAL2
Output of the inverting oscillator amplifier.
XTAL1
19
21
15
I
XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left
unconnected. There are no requirements on the
duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down
by a divide-by-two flip-flop. Minimum and maximum
high and low times as well as rise/fall times specified
in the AC characteristics must be observed.
P2.0P2.7
21-28
24-31
18-25
I/O Port 2
Port 2 is a an 8-bit quasi-bidirectional I/O port with
internal pull-up arrangement. Port 2 pins that have
“1s” written to them are pulled high by the internal
pull-up transistors, and in that state can be used as
inputs. As inputs, Port 2 pins being externally pulled
low will source current (IIL, in the DC characteristics)
because of the internal pullup transistors. Port 2
emits the high-order address byte during fetches
from external program memory and during
accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullup transistors when issuing
“1”s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), Port 2 issues the
contents of the P2 Special Function Register and
uses only the internal pull-up transistors.
PSEN
29
32
26
O
*)
Program Store Enable
This is a control signal that enables output of the
external program memory to the bus during external
fetch operations. It is activated every three oscillator
periods except during external data memory
accesses. It remains high during internal program
execution.
This pin should not be driven during reset operation.
I = Input
O = Output
Data Sheet
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C513AO
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number
P- DIP P-LCC- P-MQFP-40
44
44
I/O Function
*)
ALE
30
33
27
O
Address Latch Enable
This output is used for latching the low-byte of the
address into external memory during normal
operation. It is activated every six oscillator periods
except during an external data memory access.
When instructions are executed from internal
program memory (EA = 1) the ALE generation can
be disabled by bit EALE in SFR SYSCON.
This pin should not be driven during reset operation.
EA
31
35
29
I
External Access Enable
When held at high level, instructions are fetched
from the internal program memory when the PC is
less than 4000H. When held at low level, the
C513AO fetches all instructions from external
program memory.
This pin should not be driven during reset operation.
Note: For the C513AO-L this pin must be tied low.
P0.0P0.7
32-39
43-36
37-30
I/O Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have “1s” written to them float, and
in that state can be used as high-impendance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program or
data memory. In this application, it uses strong
internal pull-up transistors when issuing 1s. External
pull-up resistors are required during program
verification.
VSS
20
22, 1
16, 39
–
Ground (0 V)
VDD
40
44, 23
38, 17
–
Power Supply (+ 5 V)
N.C.
–
12, 34
6, 28
–
No Connection. These pins should not be
connected.
*)
I = Input
O = Output
Data Sheet
10
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C513AO
VDD
C513AO
VSS
XRAM
256 byte
XTAL1
XTAL2
RAM
256 byte
ROM/OTP
16 K x 8
Oscillator
Watchdog
OSC & Timing
RESET
CPU
ALE
PSEN
Timer 0
Port 0
Port 0
8-Bit
Digital I/O
Timer 1
Port 1
Port 1
8-Bit
Digital I/O
Timer 2
Port 2
Port 2
8-Bit
Digital I/O
Interrupt Unit
Port 3
Port 3
8-Bit
Digital I/O
EA
USART
Emulation
Support
Logic
SSC
MCB04011
Figure 6
Block Diagram of the C513AO
Data Sheet
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C513AO
CPU
The C513AO is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and
15% three-byte instructions. With a 16-MHz crystal, 58% of the instructions execute in 750 ns.
Special Function Register PSW (Address D0H)
Reset Value: 00H
Bit No. MSB
D0H
LSB
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag 0
RS1
RS0
Register bank Select control bits
These bits are used to select one of the four register banks.
RS1
RS0
PSW
Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag 1
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of “one” bits in the accumulator, i.e. even parity.
Data Sheet
12
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C513AO
Memory Organization
The C513AO CPU manipulates operands in the following five address spaces:
• Up to 64 Kbytes of program memory (up to 16 KB on-chip program memory for the C513AO-2R/
2E)
• Up to 64 Kbytes of external data memory
• 256 bytes of internal data memory
• 256 bytes of internal XRAM data memory
• One 128-byte special function register area
Figure 7 illustrates the memory address spaces of the C513AO.
FFFFH
Ext.
Data
Memory
Internal FFFFH
XRAM
(256 byte) FF00
H
FEFFH
Ext.
Indirect
Addr.
Ext.
Data
Memory
Internal
RAM
4000H
Int.
(EA = 1)
Ext.
(EA = 0)
"Code Space"
3FFFH
0000H
0000H
"Data Space"
Direct
Addr.
FFH
80H
Internal
RAM
Special
Function
Regs.
FFH
80H
7FH
00H
"Internal Data Space"
MCA04012
Figure 7
C513AO Memory Map
Data Sheet
13
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C513AO
Reset and System Clock
The reset input is an active high input. An internal Schmitt-trigger is used at the input for noise
rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least
two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running,
the internal reset is executed during the second machine cycle and is repeated every cycle until
RESET goes low again. Figure 8 shows the possible reset circuitries.
VDD
+
VDD
C513AO
RESET
&
C513AO
C513AO
RESET
RESET
+
a)
b)
c)
MCS03291
Figure 8
Reset Circuitries
Data Sheet
14
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C513AO
Figure 9 shows the recommended oscillator circiutries for crystal and external clock operation.
C
XTAL2
C513AO
3.5-16 MHz
C
XTAL1
C = 20 pF ±10 pF for crystal operation
MCS04014
Figure 9
Recommended Oscillator Circuitry
In this application, the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator
(a more detailed schematic is given in Figure 10). lt is operated in its fundamental response mode
as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal
specifications and capacitances are non-critical. In this circuit, 20 pF can be used as single
capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used
in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors
normally will have different values, dependent on the oscillator frequency. We recommend
consulting the manufacturer of the ceramic resonator for value specifications of these capacitors.
Data Sheet
15
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C513AO
To internal
timing circuitry
**)
C513AO
XTAL2
XTAL1
*)
C1
C2
*) Crystal or ceramic resonator
**) Resistor is only in the C513AO-2E
MCS04015
Figure 10
On-Chip Oscillator Circuitry
To drive the C513AO with an external clock source, the external clock signal must be applied to
XTAL1, as shown in Figure 11. XTAL2 must be left unconnected. A pull-up resistor is suggested to
increase the noise margin, but is optional if VOH of the driving gate corresponds to the VIH2
specification of XTAL1.
C513AO
N.C.
XTAL2
VDD
External
Clock
Signal
XTAL1
MCS04016
Figure 11
External Clock Source
Data Sheet
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C513AO
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.
The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.
ICE-System interface
to emulation hardware
RESET
EA
ALE
PSEN
SYSCON
PCON
TCON
C500
MCU
opt.
I/O Ports
RSYSCON
RPCON
Enhanced Hooks
Interface Circuit
Port 0
Port 2
Port 3
EH-IC
RTCON
RPORT RPORT
2
0
TEA TALE TPSEN
Port 1
Target System Interface
MCS03254
Figure 12
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.
1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Infineon
Technologies.
Data Sheet
17
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C513AO
Special Function Registers
The registers reside in the special function register area, with the exception of the Program Counter
and the four General Purpose Register banks. The special function register area consists of two
portions: the standard special function register area and the mapped special function register area.
Four special function registers of the C513AO (PCON1, VR0, VR1 & VR2) are located in the
mapped special function register area. For accessing the mapped special function register area, bit
RMAP in special function register SYSCON must be set. All other special function registers of the
C513AO are located in the standard special function register area.
Special Function Register SYSCON (Address B1 H)
Bit No. MSB
7
B1H
–
Reset Value: XX10XXX0B
6
5
4
3
2
1
LSB
0
–
EALE
RMAP
–
–
–
XMAP
SYSCON
The functions of the shaded bits are not described in this section.
Bit
Function
RMAP
Special function Register MAP bit
RMAP = 0: The access to the non-mapped (standard) special function
register area is enabled.
RMAP = 1: The access to the mapped special function register area is
enabled.
–
Reserved bits for future use. Read by CPU returns undefined values.
If bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by
hardware automatically.
The forty Special Function Registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C513AO are listed in Table 2 and Table 3. In Table 2, they are organized in groups
which refer to the functional blocks of the C513AO. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
Data Sheet
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C513AO
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address Contents after
Reset
CPU
ACC
B
DPH
DPL
PSW
SP
VR04) 5)
VR14) 5)
VR24) 5)
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
System Control Register
Version Register 0
Version Register 16)
Version Register 27)
E0H1)
F0H1)
83H
82H
D0H1)
81H
B1H
FCH
FDH
FEH
00H
00H
00H
00H
00H
07H
XX10XXX0B3)
C5H
–
–
Interrupt
System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8H1)
B8H1)
00H
X0000000B3)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80H1)
90H1)
A0H1)
B0H1)
FFH
FFH
FFH
FFH
Serial
Channel
(USART)
PCON2)
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
87H
99H
98H1)
000X0000B
XXH3)
00H
SSC
Interface
SSCCON
STB
SRB
SCF
SCIEN
SSCMOD8)
SSC Control Register
SSC Transmit Register
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register
E8H1)
E9H
EAH
F8H1)
F9H
EBH
07H
XXH3)
XXH3)
XXXXXX00B3)
XXXXXX00B3)
00H
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
SYSCON2)
1)
2)
3)
4)
5)
6)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
“X” means that the value is undefined and the location is reserved
This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
This SFR is read-only.
C513AO-L/2R: 13H
C513AO-2E: 83H
7) This SFR varies with the step of the microcontroller: for example, 01H for the first step
8) This register is only used for test purposes and must not be written during normal operation. Unpredictable
results may occur upon a write operation.
Data Sheet
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C513AO
Table 2
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address Contents after
Reset
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture Register, High Byte
Timer 2 Reload/Capture Register, Low Byte
Timer 2 High Byte
Timer 2 Low Byte
C8H1)
C9H
CBH
CAH
CDH
CCH
00H
XXXXXXX0B3)
00H
00H
00H
00H
WDTREL
Watchdog Timer Control Register
Watchdog Timer Reload Register
C0H1)
86H
XXXX0000B3)
00H
PCON2)
PCON14)
Power Control Register
Power Control Register 1
87H
88H
000X0000B3)
0XXXXXXXB3)
Watchdog WDCON
Power
Save
Mode
1)
2)
3)
4)
5)
6)
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
“X” means that the value is undefined and the location is reserved
This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
This SFR is read-only.
C513AO-L/2R: 13H
C513AO-2E: 83H
7) This SFR varies with the step of the microcontroller: for example, 01H for the first step
8) This register is only used for test purposes and must not be written during normal operation. Unpredictable
results may occur upon a write operation.
Data Sheet
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C513AO
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses
Addr.
Register
Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H2)
P0
FFH
.7
.6
.5
.4
.3
.2
.1
.0
81H
SP
07H
.7
.6
.5
.4
.3
.2
.1
.0
82H
DPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H
DPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
86H
WDTREL 00H
WDT
PSEL
.6
.5
.4
.3
.2
.1
.0
87H
PCON
0XX00000B
SMOD
–
–
SD
GF1
GF0
PDE
IDLE
88H2) 3) TCON
00H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
88H3)
PCON1
0XX0XXXXB
EWPD
–
–
–
–
–
–
–
89H
TMOD
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
TL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH
TL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
8CH
TH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8DH
TH1
00H
.7
.6
.5
.4
.3
.2
.1
90H2)
P1
FFH
–
–
.SLS
STO
SRI
SCLK T2EX
T2
98H2)
SCON
00H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99H
SBUF
XXH
.7
.6
.5
.4
.3
.2
.1
.0
A0H2)
P2
FFH
.7
.6
.5
.4
.3
.2
.1
.0
A8H2)
IE
00H
EA
ESSC ET2
ES
ET1
EX1
ET0
EX0
B0H2)
P3
FFH
RD
WR
T1
T0
INT1
INT0
TxD
RxD
B1H
SYSCON XX10XXX0B
–
–
EALE RMAP
–
–
–
XMAP
B8H2)
IP
X0000000B
–
PSSC PT2
PS
PT1
PX1
PT0
PX0
C0H2)
WDCON
XXXX0000B
–
–
–
OWDS WDTS WDT
1)
2)
3)
4)
5)
6)
–
.0
SWDT
“X” means that the value is undefined and the location is reserved.
Bit-addressable special function registers.
SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
These are read-only registers.
The content of this SFR varies with the actual step of the C513A0: for example, 01H for the first step).
This register is only used for test purposes and must not be written during normal operation. Unpredictable
results may occur upon a write operation.
Data Sheet
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C513AO
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
Addr.
Register
Content Bit 7
after
Reset1)
Bit 6
C8H2)
T2CON
00H
TF2
C9H
T2MOD
XXXXXXX0B
CAH
RC2L
CBH
RC2H
CCH
TL2
CDH
D0H2)
Bit 2
Bit 1
Bit 0
EXF2 RCLK TCLK
EXEN2 TR2
C/T2
CP/
RL2
–
–
–
–
–
–
–
DCEN
00H
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
00H
.7
.6
.5
.4
.3
.2
.1
.0
TH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
PSW
00H
CY
AC
F0
RS1
RS0
OV
F1
P
E0H2)
ACC
00H
.7
.6
.5
.4
.3
.2
.1
.0
E8H2)
SSCCON 07H
SCEN
TEN
MSTR CPOL
CPHA
BRS2 BRS1
BRS0
E9H
STB
XXH
.7
.6
.5
.3
.2
.0
EAH
SRB
XXH
.7
.6
.5
.4
.3
.2
.1
.0
EBH
SSCMOD 00H6)
LOOPB TRIO 0
0
0
0
0
LSBSM
F0H2)
B
00H
.7
.6
.5
.4
.3
.2
.1
.0
SCF
XXXXXX00B
–
–
–
–
–
–
WCOL
TC
SCIEN
XXXXXX00B
–
–
–
–
–
–
WCEN TCEN
C5H
.7
.6
.5
.4
.3
.2
.1
.0
7)
.7
.6
.5
.4
.3
.2
.1
.0
–5)
.7
.6
.5
.4
.3
.2
.1
.0
F8H
2)
F9H
FCH3) 4) VR0
FDH
3) 4)
VR1
FEH3) 4) VR2
–
Bit 5
Bit 4
.4
Bit 3
.1
1)
2)
3)
4)
5)
6)
“X” means that the value is undefined and the location is reserved
Bit-addressable special function registers
SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
These SFRs are read-only registers.
The content of this SFR varies with the actual step of the C513A0: for example, 01H for the first step)
This register is only used for test purposes and must not be written during normal operation. Unpredictable
results may occur upon a write operation.
7) C513AO-L/2R: 13H
C513AO-2E: 83H
Data Sheet
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C513AO
Parallel I/O Port
The C513AO has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while Ports 1, 2,
and 3 are quasi-bidirectional I/O ports with internal pull-up resistors. Thus, when configured as
inputs, Ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will
float when configured as input.
The output drivers of Port 0 and Port 2 and the input buffers of Port 0 are also used for accessing
external memory. In this application, Port 0 outputs the low byte of the external memory address,
time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external
memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the
P2 SFR contents. In this case, Port 0 is not an open-drain port, but uses a strong internal pull-up
Field Effect Transistors (FETs).
Port 1 pins used for Synchronous Serial Channel (SSC) outputs are true push-pull outputs. When
used as SSC inputs, they float (no pull-up).
Data Sheet
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C513AO
Timer/Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
0
8-bit timer/counter with a
divide-by-32 prescaler
M1
M0
0
0
1
16-bit timer/counter
1
1
2
8-bit timer/counter with
8-bit autoreload
1
0
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
1
1
Input Clock
Internal
External (max.)
fOSC/(12 × 32)
fOSC/(24 × 32)
fOSC/12
fOSC/24
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Since a machine
cycle consists of twelve oscillator periods, the count rate is 1/12th of the oscillator frequency.
In “counter” function, the register is incremented in response to a 1-to-0 transition (falling edge) at
its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, respectively).
Since it takes two machine cycles to detect a falling edge; therefore, the maximum count rate is 1/
24th of the oscillator frequency. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to
function as a gate to facilitate pulse width measurements. Figure 13 illustrates the input clock logic.
f OSC
f OSC/12
÷ 12
C/T
÷12
TMOD
0
P3.4/T0
P3.5/T1
max f OSC/24
Timer 0/1
Input Clock
1
TR 0/1
Control
TCON
Gate
&
=1
TMOD
<_ 1
P3.2/INT0
P3.3/INT1
MCS01768
Figure 13
Timer/Counter 0 and 1 Input Clock Logic
Data Sheet
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C513AO
Timer/Counter 2 with Compare/Capture/Reload
Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating modes:
• 16-bit auto-reload mode (up or down counting)
• 16-bit capture mode
• Baudrate generator
Table 5
Timer / Counter 2 Operating Modes
T2CON
T2MOD T2CON P1.1/ Remarks
T2EX
Input Clock
Internal
Mode
RCLK CP/ TR2
RL2
or
TCLK
DCEN
EXEN2
16-bit
Autoreload
0
0
1
0
0
X
0
0
1
0
1
↓
0
0
0
0
1
1
1
1
X
X
0
1
0
1
1
X
0
X
0
1
1
X
1
↓
Baudrate 1
Generator
X
1
X
0
X
1
X
1
X
1
↓
X
X
0
X
X
X
16-bit
Capture
off
reload upon
overflow
fOSC/12
reload trigger
(falling edge)
down counting
up counting
16-bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
no overflow
interrupt
request (TF2)
extra external
interrupt
(“Timer 2”)
Timer 2 stops
fOSC/12
External
(P1.0/
T2)
max
fOSC/24
max
fOSC/24
fOSC/12
max
fOSC/24
–
–
Note: ↓ denotes a falling edge
Data Sheet
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C513AO
Serial Interface (USART)
The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also
receive-buffered; it can commence reception of a second byte before a previously-received byte
has been read from the receive register. The serial port can operate in 4 modes (one synchronous
and three asynchronous) as illustrated in Table 6.
Table 6
USART Operating Modes
Mode
SCON
Description
SM0
SM1
0
0
0
Shift register mode
Serial data enters and exits through R×D. T×D outputs the
shift clock. 8-bit data are transmitted/received (LSB first) at a
fixed baudrate of 1/12th of the oscillator frequency.
1
0
1
8-bit USART, variable baudrate
10 bits are transmitted (through T×D) or received (at R×D).
2
1
0
9-bit USART, fixed baudrate
11 bits are transmitted (through T×D) or received (at R×D).
3
1
1
9-bit USART, variable baudrate
Similar to mode 2, except for the variable baudrate.
For clarification, some terms regarding the difference between “baudrate clock” and “baudrate”
should be mentioned.
The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization.
Therefore, the baudrate generators must provide a “baudrate clock” to the serial interface which
divides it by 16, thereby resulting in the actual “baudrate”.
The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be
determined by Timer 1 or by Timer 2 or both (one for transmit, the other for receive).
Data Sheet
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C513AO
Mode 1
Mode 3
Mode 2
Timer 1 Overflow
fOSC /2
÷6
SCON.7/
SCON.6
(SM0/
SM1)
PCON.7
(SMOD)
÷2
0
1
Baudrate
Clock
Mode 0
Only one mode
can be selected
Note: The switch configuration shows the reset state
MCS04017
Figure 14
Block Diagram of Baudrate Generation for the Serial Interface
Table 7 lists the values/formulas for the baudrate calculation of the serial interface with its
dependencies on the control bits SMOD (in SFR PCON), TCLK and RCLK (both in SFR T2CON).
Table 7
Serial Interface - Baudrate Dependencies
Serial Interface
Operating Modes
SMOD
Mode 0 (Shift Register)
–
–
fOSC/12
Mode 1 (8-bit UART)
Mode 3 (9-bit UART)
X
0
Determined by timer 1 overflow rate:
(2SMOD × timer 1 overflow rate)/32
–
1
Determined by timer 2 overflow rate:
Timer 2 overflow rate/16
0
1
–
–
fOSC/64
fOSC/32
Mode 2 (9-bit UART)
Data Sheet
Control Bits
Baudrate Calculation
TCLK/RCLK
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C513AO
SSC Interface
The Synchronous Serial Channel (SSC) interface is compatible to the popular SPI serial bus
interface. It can be used for simple I/O expansion via shift registers, for connection with a variety of
peripheral components (such as A/D converters, EEPROMs etc.), or interconnection of several
microcontrollers in a master/slave structure. The SSC unit supports full-duplex or half-duplex
operation and can run in Master Mode or Slave Mode.
Figure 15 shows the block diagram of the SSC.
P1.2/SCLK
f OSC
P1.3/SRI
Clock Divider
STB
Pin
Control
Logic
Shift Register
Clock Selection
P1.4/STO
SRB
P1.5/SLS
Receive Buffer Register
Interrupt
SCIEN
Int. Enable Reg.
SSCCON
Control Register
Control Logic
SCF
Status Register
Internal Bus
MCB02735
Figure 15
SSC Block Diagram
Interrupt System
The C513AO provides seven interrupt sources with two priority levels. Five of the interrupts can be
generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, USART, and SSC) and three of the
interrupts may be triggered externally (P1.1/T2EX, P3.2/INT0, P3.3/INT1). A non-maskable eighth
interrupt is reserved for external wake-up from power-down mode.
Figure 16 gives a general overview of the interrupt sources and illustrates the request and the
control flags. Table 8 lists the vector addresses of each interrupt source.
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C513AO
Figure 16
Interrupt Request Sources
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C513AO
Table 8
Interrupt Vector Addresses
Interrupt Source
Request Flags
Vector Address
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
USART serial port interrupt
Timer 2 interrupt
Synchronous Serial Channel interrupt (SSC)
Wake-up from power-down mode
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
WCOL+TC
–
0003H
000BH
0013H
001BH
0023H
002BH
0043H
007BH
If two interrupt requests of different priority levels are received simultaneously, the request of higher
priority is serviced. If requests of the same priority are received simultaneously, an internal polling
sequence determines which request is serviced. Thus, within each priority level there is a second
priority structure determined by the polling sequence as shown in Table 9.
Table 9
Interrupt Source Structure
Interrupt Source
External Interrupt 0
Synchronous Serial Channel
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Universal Serial Channel
Timer 2 Interrupt
Priority
IE0
WCOL OR TC
TFO
IE1
TF1
RI OR TI
TF2 OR EXF2
High
Low
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority
interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
Data Sheet
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C513AO
Fail Save Mechanisms
The C513AO offers enhanced fail-safe mechanisms which allow automatic recovery from a
software upset or a hardware failure:
• A programmable Watchdog Timer (WDT) has variable time-out period from 512 µs up to approx.
1.1 sec. at 12 MHz
• An Oscillator Watchdog (OWD) monitors the on-chip oscillator and forces the microcontroller into
reset state if the on-chip oscillator fails. It also provides the clock for a fast internal reset after
power-on.
The Watchdog Timer in the C513AO is a 15-bit timer which is incremented by a count rate of either
fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). That is, the machine clock is divided by a fixed divide-by-two
prescaler and an optional divide-by-16 prescaler arranged in series. For programming of the
watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 17 shows
the block diagram of the watchdog timer unit.
Figure 17
Block Diagram of the Watchdog Timer
The Watchdog Timer can be started by software (bit SWDT in SFR WDCON); but, it cannot be
stopped during active mode of the device. If the software fails to clear the Watchdog Timer, an
internal reset will be initiated. The reset cause can be examined by software (status flag WDTS in
WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR WDCON) and
SWDT consecutively. This double instruction sequence has been implemented to increase system
security. During a refresh, the content of the SFR WDTREL is transferred to SFR WDTH, i.e. the
upper 7-bit of the watchdog timer. It must be noted, however, that the watchdog timer is stopped
during the idle mode and power down mode of the processor.
Data Sheet
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C513AO
Oscillator Watchdog
The Oscillator Watchdog (OWD) unit is used for three functions:
• Monitoring the on-chip oscillator’s function
The watchdog supervises the on-chip oscillator’s frequency. If the frequency is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the
RC oscillator and the device is brought into reset. If the failure condition disappears (that is, if the
on-chip oscillator has a higher frequency than the RC oscillator), the device executes a final reset
phase of typically 1 ms to allow the oscillator to stabilize. Then, the oscillator watchdog reset is
released and the device resumes program execution.
• Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for reset before the on-chip oscillator has
started. The oscillator watchdog unit reset works identically to the monitoring function.
• Control of external wake-up from software power-down mode
When power-down mode is terminated by a low level at the INT0 pin, the oscillator watchdog unit
ensures that the microcontroller resumes operation (execution of the power-down wake-up
interrupt) with the nominal clock rate. In power-down mode, the RC oscillator and the on-chip
oscillator are stopped. Both oscillators are started again when power-down mode is terminated.
When the on-chip oscillator has a frequency higher than the RC oscillator, the microcontroller
starts operation after a final delay of typ. 1 ms to allow the on-chip oscillator to stabilize.
Note: The Oscillator Watchdog unit is always enabled.
Figure 18 shows the block diagram of the Oscillator Watchdog unit.
Data Sheet
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C513AO
Figure 18
Block Diagram of the Oscillator Watchdog
Data Sheet
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C513AO
Power Saving Modes
The C513AO provides three basic power-saving modes: Idle Mode, Slow-down Mode, and Powerdown Mode.
• Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are
able to function. Idle mode is entered by software and can be left by an interrupt or reset.
• Slow down mode
The controller keeps up the full operating functionality, but its normal clock frequency is internally
divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32nd
of their normal operating frequency and also reduces power consumption.
• Power down mode
The operation of the C513AO is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. This power down
mode is entered by software and can be left by reset or a short low pulse at pin P3.2/INT0.
In the power down mode of operation, VDD can be reduced to minimize power consumption. It must
be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD
is restored to its normal operating level, before the power down mode is terminated. Table 10 gives
a general overview of the entry and exit procedures of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering
Example
Leaving by
Idle mode
ORL PCON, #01H
Occurrence of an any CPU clock is stopped;
enabled interrupt
CPU maintains their data;
peripheral units are active (if
Hardware reset
enabled) and provided with clock
Slow Down Mode
In normal mode:
ORL PCON,#10H
ANL PCON,#0EFH
or Hardware reset
Internal clock rate is reduced to
1/32 of its nominal frequency
With idle mode:
ORL PCON,#11H
Occurrence of any
enabled interrupt and
the instruction
ANL PCON,#0EFH
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/32
of its nominal frequency
Hardware reset
Power Down
Mode
Data Sheet
ORL PCON, #02 H
Remarks
Hardware reset
Oscillator is stopped;
Short low pulse at pin contents of on-chip RAM and
SFRs are maintained;
P3.2/INT0
34
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C513AO
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit Notes
Storage temperature
TST
– 65
150
°C
–
Voltage on VDD pins with respect
to ground (VSS)
VDD
– 0.5
6.5
V
–
Voltage on any pin with respect
to ground (VSS)
VIN
– 0.5
VDD + 0.5
V
–
Input current on any pin during
overload condition
–
– 10
10
mA
–
–
|100 mA|
mA
–
–
t.b.d.
W
–
Absolute sum of all input currents –
during overload condition
Power dissipation
PDISS
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During absolute maximum rating overload conditions
(VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed
the values defined by the absolute maximum ratings.
Operating Conditions
Parameter
Symbol
Limit Values
Supply voltage
VDD
Ground voltage
VSS
Ambient temperature
SAB-C513AO
SAF-C513AO
TA
TA
0
– 40
70
85
CPU clock
fCPU
3.5
16
min.
Data Sheet
max.
4.25
5.5
0
35
Unit Notes
V
–
V
–
°C
–
MHz –
02.00
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C513AO
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C513AO and partly
its demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C513AO will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the C513AO.
DC Characteristics
(Operating Conditions apply)
Parameter
Symbol
Input low voltage
Pins except EA, RESET
EA pin
RESET pin
VIL
VIL1
VIL2
Input high voltage
Pins except XTAL1, RESET
XTAL1 pin
RESET pin
VIH
VIH1
VIH2
Output low voltage
Ports 1, 2, 3 (except P1.2, P1.4)
Port 0, ALE, PSEN
P1.2, P1.4 pull-up transistor
resistance
SR
SR
SR
SR
SR
SR
Limit Values
Unit Test Condition
min.
max.
– 0.5
– 0.5
– 0.5
0.2 VDD – 0.1 V
0.2 VDD – 0.3 V
0.2 VDD + 0.1 V
–
–
–
0.6 VDD
0.7 VDD
0.6 VDD
VDD + 0.5
VDD + 0.5
VDD + 0.5
V
V
V
–
–
–
–
–
–
0.45
0.45
120
V
V
Ω
I OL = 1.6 mA1)
I OL = 3.2 mA1)
VOL = 0.45 V
–
–
–
–
120
V
V
V
V
Ω
IOH = – 80 µA,
IOH = – 10 µA
IOH = – 800 µA,
IOH = – 80 µA2)
VOH = 0.9 VDD
VOL
VOL1
RDSON
CC
VOH
CC
VOH1
CC
RDSON
CC
2.4
0.9 VDD
2.4
0.9 VDD
–
Logic 0 input current
Ports 1, 2, 3
IIL
SR
– 10
– 70
µA
VIN = 0.45 V
Logical 0-to-1 transition current,
Ports 1, 2, 3
ITL
SR
– 65
– 650
µA
V IN = 2 V
ILI
CC
–
±1
µA
0.45 < VIN < VDD
IIH
CC
5
100
µA
0.6 < VIN < VDD
Output High Voltage
Ports 1, 2, 3
Port 0 in external bus mode,
ALE, PSEN
P1.2, P1.4 pull-up transistor
resistance
Input Leakage Current
Port 0, EA
P1.2, P1.3, P1.5 as SSC inputs
Input high current to RESET for
reset
Data Sheet
CC
CC
36
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C513AO
DC Characteristics (cont’d)
(Operating Conditions apply)
Parameter
Symbol
Input low current to XTAL1
IIL2
Pin capacitance
C IO
Limit Values
Unit Test Condition
min.
max.
CC
–
– 20
µA
CC
–
10
pF
VI N = 0.45 V
f C = 1 MHz,
T A = 25 °C
Overload current
IOV
SR
±5
–
8) 9)
mA
Notes see next page.
Power Supply Current
Parameter
Symbol Limit Values Unit Test Condition
typ.10) max.
Active mode
Idle mode
Active mode with
slow-down enabled
Idle mode with
slow-down enabled
Power-down mode
Data Sheet
C513AO-2E 12 MHz IDD
16 MHz IDD
10.3
13.1
13.0
16.6
mA
mA
4)
C513AO-2R 12 MHz IDD
16 MHz IDD
6.9
8.5
9.0
10.9
mA
mA
4)
C513AO-2E 12 MHz IDD
16 MHz IDD
5.7
6.8
7.2
8.7
mA
mA
5)
C513AO-2R 12 MHz IDD
16 MHz IDD
4.1
4.8
5.5
6.0
mA
mA
5)
C513AO-2E 12 MHz IDD
16 MHz IDD
4.5
5.1
5.7
6.5
mA
mA
6)
C513AO-2R 12 MHz IDD
16 MHz IDD
3.3
3.6
4.1
4.5
mA
mA
6)
C513AO-2E 12 MHz IDD
16 MHz IDD
3.7
4.0
4.7
5.1
mA
mA
7)
C513AO-2R 12 MHz IDD
16 MHz IDD
2.6
2.8
3.3
3.5
mA
mA
7)
C513AO-2E
IPD
8.8
50
µA
VDD = 2 … 5.5 V 3)
C513AO-2R
IPD
1.28
20
µA
VDD = 2 … 5.5 V 3)
37
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C513AO
Notes:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger,
or use an address latch with a Schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the
0.9 VDD specification when the address lines are stabilizing.
3) IPD (power-down mode) is measured under following conditions:
EA = Port0 = VDD; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected. IDD would be
slightly higher if a crystal oscillator is used (appr. 1 mA).
4) IDD (active mode) is measured with:
XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.;
EA = PE/SWD = Port 0 = Port 6 = VDD; HWPD = VDD; RESET = VDD;
all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA).
5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS; Port0 = VDD; all other pins are disconnected.
6) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS; Port0 = VDD; all other pins are disconnected.
7) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS; Port0 = VDD; all other pins are disconnected.
8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VDD and VSS
must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed
50 mA.
9) Not 100% tested, guaranteed by design characterization.
10)The typical IDD values are periodically measured at TA = + 25 °C and VDD = 5 V but not 100% tested.
Data Sheet
38
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C513AO
C513AO-2E
MCD04314
17.5
mA
Ι DD max
Ι DD typ
Ι DD 15
ode
ve M
Acti
12.5
de
e Mo
Activ
10
e
Idle Mod
e
od
Idle M
7.5
5
2.5
Idle + Slow Down Mode
Active + Slow Down Mode
0
2
4
6
8
10
12
14 MHz
f OSC
16
C513AO-2R
MCD04315
14
mA
Ι DD max
Ι DD typ
Ι DD 12
de
e Mo
10
Activ
8
Active
6
Idle Mode
Idle Mode
Mode
4
2
Idle + Slow Down Mode
Active + Slow Down Mode
0
2
4
6
8
10
12
14 MHz
f OSC
16
Figure 19
IDD Diagram
Data Sheet
39
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C513AO
Power Supply Current Calculation Formula
Parameter
Active mode
Idle mode
Active mode with
slow-down enabled
Idle mode with
slow-down enabled
Symbol
Formula
C513-2E
IDD typ
IDD max
0.70 × fOSC + 1.8
0.91 × fOSC + 2.0
C513-2R
IDD typ
IDD max
0.40 × fOSC + 2.1
0.48 × fOSC + 3.2
C513-2E
IDD typ
IDD max
0.29 × fOSC + 2.2
0.36 × fOSC + 2.9
C513-2R
IDD typ
IDD max
0.18 × fOSC + 1.9
0.13 × fOSC + 3.9
C513-2E
IDD typ
IDD max
0.15 × fOSC + 2.6
0.20 × fOSC + 2.9
C513-2R
IDD typ
IDD max
0.08 × fOSC + 2.4
0.10 × fOSC + 2.9
C513-2E
IDD typ
IDD max
0.09 × fOSC + 2.5
0.12 × fOSC + 3.2
C513-2R
IDD typ
IDD max
0.05 × fOSC + 2.0
0.05 × fOSC + 2.7
Note: fosc is the oscillator frequency in MHz. IDD values are given in mA.
Data Sheet
40
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C513AO
AC Characteristics (16 MHz)
(Operating Conditions apply)
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Parameter
Symbol
Limit Values
16 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 16 MHz
min.
max.
min.
max.
Program Memory Characteristics
ALE pulse width
tLHLL
CC
85
–
2 tCLCL – 40
–
ns
Address setup to ALE
tAVLL
CC
33
–
tCLCL – 30
–
ns
Address hold after ALE
tLLAX
CC
28
–
tCLCL – 35
–
ns
ALE low to valid instruction in
tLLIV
SR
–
150
–
4 tCLCL – 100
ns
ALE to PSEN
tLLPL
CC
38
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
CC
153
–
3 tCLCL – 35
–
ns
PSEN to valid instruction in
tPLIV
SR
–
88
–
3 tCLCL – 100
ns
Input instruction hold after PSEN
tPXIX
SR
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ*)
SR
–
43
–
tCLCL – 20
ns
*)
PXAV CC
Address valid after PSEN
t
48
–
tCLCL – 8
–
ns
Address to valid instr in
tAVIV
SR
–
198
–
5 tCLCL – 115
ns
Address float to PSEN
tAZPL
CC
0
–
0
–
ns
*)
Interfacing the C513AO to devices with float times up to 55 ns is permissible. This limited bus contention will
not cause any damage to port 0 drivers.
Data Sheet
41
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C513AO
AC Characteristics (16 MHz, cont’d)
(Operating Conditions apply)
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Parameter
Symbol
Limit Values
16 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 16 MHz
min.
max.
min.
max.
–
External Data Memory Characteristics
RD pulse width
tRLRH
CC
275
–
6 tCLCL – 100
WR pulse width
tWLWH
CC
275
–
6 tCLCL – 100
–
ns
Address hold after ALE
tLLAX2
CC
90
–
2 tCLCL – 35
–
ns
RD to valid data in
tRLDV
SR
–
148
–
5 tCLCL – 165
ns
Data hold after RD
tRHDX
SR
0
–
0
–
ns
Data float after RD
tRHDZ
SR
–
55
–
2 tCLCL – 70
ns
ALE to valid data in
tLLDV
SR
–
350
–
8 tCLCL – 150
ns
Address to valid data in
tAVDV
SR
–
398
–
9 tCLCL – 165
ns
ALE to WR or RD
tLLWL
CC
138
238
3 tCLCL – 50
3 tCLCL + 50
ns
Address valid to WR or RD
tAVWL
CC
120
–
4 tCLCL – 130
–
ns
WR or RD high to ALE high
tWHLH
CC
23
103
tCLCL – 40
tCLCL + 40
ns
Data valid to WR transition
tQVWX
CC
13
–
tCLCL – 50
–
ns
Data setup before WR
tQVWH
CC
288
–
7 tCLCL – 150
–
ns
Data hold after WR
tWHQX
CC
13
–
tCLCL – 50
–
ns
Address float after RD
tRLAZ
CC
–
0
–
0
ns
Data Sheet
42
ns
02.00
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C513AO
Synchronous Serial Channel (SSC) Interface Characteristics
Parameter
Symbol
Limit Values
Unit
16 MHz Clock
Clock Cycle Time: Master Mode
Slave Mode
tSCLK
tSCLK
Clock High Time
tSCH
Clock Low Time
tSCL
Data Output Delay
tD
Data Output Hold
tHO
Data Input Setup
tS
Data Input Hold
tHI
TC Bit Set Delay
tDTC
min.
max.
500
450
–
–
ns
ns
1)
200
–
ns
1)
CC/SR
200
–
ns
CC
–
100
ns
CC
0
–
ns
SR
80
–
ns
SR
80
–
ns
CC
–
16 tCLCL
ns
CC
SR
CC/SR
1) This parameter is ‘CC’ in Master Mode, and ‘SR’ in Slave Mode.
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 16 MHz
min.
max.
Oscillator period
tCLCL
SR
62.5
285
ns
High time
tCHCX
SR
15
tCLCL – tCLCX
ns
Low time
tCLCX
SR
15
tCLCL – tCHCX
ns
Rise time
tCLCH
SR
–
15
ns
Fall time
tCHCL
SR
–
15
ns
Data Sheet
43
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C513AO
t LHLL
ALE
t AVLL
t PLPH
t LLPL
t LLIV
t PLIV
PSEN
t AZPL
t PXAV
t LLAX
t PXIZ
t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 20
Program Memory Read Cycle
Data Sheet
44
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C513AO
t WHLH
ALE
PSEN
t LLDV
t LLWL
t RLRH
RD
t RLDV
t AVLL
t RHDZ
t LLAX2
t RLAZ
Port 0
t RHDX
A0 - A7 from
Ri or DPL
Data IN
A0 - A7
from PCL
Instr.
IN
t AVWL
t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 21
Data Memory Read Cycle
Data Sheet
45
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C513AO
t WHLH
ALE
PSEN
t LLWL
t WLWH
WR
t QVWX
t AVLL
t WHQX
t LLAX2
Port 0
A0 - A7 from
Ri or DPL
t QVWH
Data OUT
A0 - A7
from PCL
Instr.IN
t AVWL
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00098
Figure 22
Data Memory Write Cycle
Data Sheet
46
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C513AO
t SCLK
t SCL
t SCH
~
~
SCLK
t HD
~
~
tD
MSB
LSB
~
~
STO
t HI
~
~
tS
MSB
LSB
~
~
SRI
t DTC
~
~
TC
MCT02417
Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is
valid for the other cases accordingly.
In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA = 0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
Figure 23
SSC Timing
t CLCL
VDD- 0.5V
0.45V
0.7 VDD
0.2 VDD - 0.1
t CHCL
t CLCX
t CHCX
MCT00033
t CLCH
Figure 24
External Clock Drive on XTAL1
Data Sheet
47
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C513AO
OTP Memory Characteristics (C513AO-2E only)
Programming Mode Timing Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
Unit
PALE Pulse Width
tPAW
35
–
ns
PMSEL Set-up to PALE Rising Edge
tPMS
10
–
–
Address Set-up to PALE, PROG, or PRD
Falling Edge
tPAS
10
–
ns
Address Hold after PALE, PROG, or PRD
Falling Edge
tPAH
10
–
ns
Address, Data Set-up to PROG or PRD
tPCS
100
–
ns
Address, Data Hold after PROG or PRD
tPCH
0
–
ns
PMSEL Set-up to PROG or PRD
tPMS
10
–
ns
PMSEL Hold after PROG or PRD
tPMH
10
–
ns
PROG Pulse Width
tPWW
100
–
µs
PRD Pulse Width
tPRW
100
–
ns
Address to Valid Data out
tPAD
–
75
ns
PRD to Valid Data out
tPRD
–
20
ns
Data Hold after PRD
tPDH
0
–
ns
Data float after PRD
tPDF
–
20
ns
PROG High between two Consecutive
PROG Low Pulses
tPWH1
1
–
µs
PRD High between two Consecutive PRD
Low Pulses
tPWH2
100
–
ns
XTAL Clock Period
tCLKP
62.5
286
ns
Data Sheet
48
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C513AO
tPAW
PALE
tPMS
PMSEL1, 0
H, H
tPAS
Port 2
tPAH
A8-13
A0-7
Port 0
D0-7
tPCH
PROG
tPCS
tPWW
tPWH
Notes: PRD must be high during a programming write cycle
MCT04318
Figure 25
Programming Code Byte - Write Cycle Timing
Data Sheet
49
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C513AO
tPAW
PALE
tPMS
PMSEL1, 0
H, H
tPAS
Port 2
tPAH
A8-13
A0-7
tPAD
tPDH
Port 0
D0-7
tPRD
tPDF
tPCH
PRD
tPCS
tPRW
tPWH
Notes: PROG must be high during a programming read cycle
MCT04319
Figure 26
Verify Code Byte - Read Cycle Timing
Data Sheet
50
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C513AO
PMSEL1, 0
H, L
Port 0
H, L
D0, D1
D0, D1
tPCH
tPCS
tPMS
tPMH
tPDH
PROG
tPWW
tPRD
tPMS
tPDR
tPMH
PRD
tPRW
Notes: PALE should be low during a lock bit read/write cycle
MCT04320
Figure 27
Lock Bit Access Timing
PMSEL1, 0
L, H
Port 2
e.g. FDH
tPCH
Port 0
D0-7
tPDH
tPCS
tPRD
tPDF
tPMH
tPMS
PRD
tPRW
Notes: PROG must be high during a programming read cycle
MCT04321
Figure 28
Version Registers - Read Timing
Data Sheet
51
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C513AO
OTP Verification Mode Characteristics
Note: ALE pin described below is not the OTP Programming Mode pin PALE
Parameter
Symbol
Limit Values
Unit
min.
typ
max.
ALE Pulse Width
tAWD
–
2 tCLCL
–
ALE Period
tACY
–
12 tCLCL
–
ns
Data Valid after ALE
tDVA
–
–
4 tCLCL
ns
Data Stable after ALE
tDSA
8 tCLCL
–
–
ns
P3.5 Set-up to ALE Low
tAS
–
tCLCL
–
ns
Oscillator Frequency
1/tCLCL
4
–
6
MHz
ns
tACY
tAWD
ALE
tDSA
tDVA
Port 0
Data Valid
tAS
P3.5
MCT04322
Figure 29
OTP Verification Mode
Data Sheet
52
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C513AO
V DD -0.5 V
0.2 VDD +0.9
Test Points
0.2 VDD -0.1
0.45 V
MCT00039
AC Inputs during testing are driven at VDD – 0.5 V for a logic “1” and 0.45 V for a logic “0”.
Timing measurements are made at VIHmin for a logic “1” and VILmax for a logic “0”.
Figure 30
AC Testing: Input, Output Waveforms
VOH -0.1 V
VLoad +0.1 V
Timing Reference
Points
VLoad
VLoad -0.1 V
VOL +0.1 V
MCT00038
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA.
Figure 31
AC Testing: Float Waveforms
Data Sheet
53
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C513AO
Driving from External Source
Crystal Oscillator Mode
C
N.C.
XTAL2
XTAL2
3.5-16 MHz
External Oscillator
Signal
C
XTAL1
XTAL1
Crystal Mode: C = 20 pF ± 10 pF (incl. stray capacitance)
MCS04317
Figure 32
Recommended Oscillator Circuits for Crystal Oscillator
Data Sheet
54
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C513AO
Package Outlines
2.54
1.5 max
0.45
+0.1
0.25 40x
40
~~ 1.3
3.7 ±0.3
0.5 min
5.1 max
Plastic Package, P-DIP-40-2
(Plastic Dual In-Line Package)
15.24 ±0.2
0.25 +0.1
14 -0.3
15.24 +1.2
21
1
20
50.9 -0.5
0.25 max
GPD05055
Index Marking
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
55
Dimensions in mm
02.00
c513ao_ds_0200.frm Page 56 Wednesday, August 30, 2000 12:45 PM
C513AO
GPL05102
Plastic Package, P-LCC-44-1
(Plastic Lead Chip Carrier)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
56
Dimensions in mm
02.00
c513ao_ds_0200.frm Page 57 Wednesday, August 30, 2000 12:45 PM
C513AO
GPM05622
Plastic Package, P-MQFP-44-2
(Plastic Metric Quad Flat Pack)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
57
Dimensions in mm
02.00