INFINEON TLE7234E

Data Sheet, Rev. 1.0, October 2008
SPIDER - TLE7234E
8 Channel High-Side and Low-Side Relay Switch
Automotive Power
TLE7234E
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
4.1
4.2
4.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
6.1
6.2
6.3
6.4
6.5
6.6
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channels 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
17
18
19
7
7.1
7.2
7.3
7.4
7.5
7.6
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
20
20
21
8
8.1
8.2
Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
9.1
9.2
9.3
9.4
9.5
9.6
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Sheet
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26
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Rev. 1.0, 2008-10-30
SPI Driver for Enhanced Relay Control
1
TLE7234E
Overview
Features
•
•
•
•
•
•
8 bit SPI for diagnostics and control, providing daisy chain capability
Very wide range for digital supply voltage
Three configurable input pins offer complete flexibility for
PWM operation
Stable behavior at under voltage
Green Product (RoHS compliant)
AEC Qualified
PG-SSOP-24-4
Description
The TLE7234E is an eight channel high-side and low-side power switch in PG-SSOP-24-4 package providing
embedded protective functions. It is especially designed for standard relays and LEDs in automotive applications.
The output stages incorporate two low-side, four high-side and two auto configuring high-side or low-side
switches.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load. For direct control,
there are three input pins available.
The power transistors are built by N-channel power MOSFETs. The device is monolithically integrated in
Smart Power Technology.
Type
Package
Marking
TLE7234E
PG-SSOP-24-4
TLE7234E
Data Sheet
3
Rev. 1.0, 2008-10-30
TLE7234E
Overview
Table 1
Product Summary
Vbb
VDD
RDS(ON)
Operating range power supply voltage
Digital supply voltage
Typical On-State resistance at 25 °C
5.5 … 28 V
3.0 … 5.5 V
high-side: 2 channels (Relay)
0.9 Ω
high-side: 2 channels (Generic, LED)
1.6 Ω
auto configuring: 2 channels (Relay, Supplies)
0.9 Ω
low-side: 2 channels (Relay)
0.9 Ω
IL(nom, min)
Nominal load current (all channels active)
Relay
350 mA
LED, Generic
175 mA
IDS(OVL, min)
IDS(OFF, max)
VDS(CL, min)
Vbb(CL, max)
fSCLK(max)
Over load switch off threshold
Output leakage current per channel at 25 °C
Drain to source clamping voltage
Source to ground clamping voltage
SPI clock frequency
500 mA
1 µA
41 V
-16 V
5 MHz
Protective Functions
•
•
•
Over load and short circuit protection
Thermal shutdown
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
•
Latched diagnostic information via SPI
Open load detection in OFF-state
Over load detection in ON-state
Over temperature
Applications
•
•
•
Especially designed for driving relays and LEDs in automotive applications
All types of resistive and inductive loads
Suitable to switch 5 V power supply lines by auto configuring channels
Data Sheet
4
Rev. 1.0, 2008-10-30
TLE7234E
Overview
Detailed Description
The TLE7234E is an eight channel high-side and low-side relay switch providing embedded protective functions.
The output stages incorporate two low-side switches (0.9 Ω per channel), four high-side switches (two channels
with 0.9 Ω and two channels with 1.6 Ω) and two auto-configuring high-side or low-side switches (0.9 Ω per
channel). The auto-configuring switches can be utilized in high-side or low-side configuration just by connecting
the load accordingly. They are also suitable to switch a 5 V supply line in high-side configuration. Protective and
diagnostic functions adjust automatically to the chosen configuration.
The 8 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads. The SPI
interface provides daisy chain capability in order to assemble multiple devices in one SPI chain by using the same
number of micro-controller pins.
Furthermore, the TLE7234E is equipped with three input pins that can be individually routed to the output control
of each channel thus offering complete flexibility in design and PCB-layout. The input multiplexer is controlled via
SPI.
The device provides full diagnosis of the load via open load, over load and short circuit detection. SPI diagnosis
flags indicate latched fault conditions that may have occurred.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off. There
are temperature sensors available for each channel to protect the device against over temperature.
The device protects itself with a build in reverse polarity protection which prohibits intrinsic current flow through
the logic during reverse polarity. However the output stages still incorporate a reverse diode where current can
flow through during reverse polarity.
The power transistors are built by N-channel power MOSFETs. The inputs are ground referenced CMOS
compatible. The device is monolithically integrated in Smart Power Technology.
Data Sheet
5
Rev. 1.0, 2008-10-30
TLE7234E
Block Diagram
2
Block Diagram
VBB
temperature
sensor
power supply
high -side
gate control
IN1
IN2
input mux
short circuit
detection
IN3
input register
open load
detection
control,
diagnostic
and
protective
functions
SPI
D4
D5
auto
configuring
gate control
VDD
CS
SCLK
SI
SO
OUT0
OUT1
OUT2
OUT3
S5
S4
stand-by
control
OUT6
OUT7
low-side
gate control
diagnosis register
reverse polarity protection
GND
Overview_4.emf
Figure 1
Data Sheet
Block Diagram
6
Rev. 1.0, 2008-10-30
TLE7234E
Block Diagram
2.1
Terms
Figure 2 shows all terms used in this data sheet.
Vbat
IS
IOUT_S0
VBB
OUT0
OUT1
IIN1
IIN2
VIN 1
IIN3
VIN2
IDD
VIN 3
I CS
VDD
V CS
ISCLK
VSCLK
ISI
VSI
ISO
VSO
IN1
OUT2
IN2
OUT3
IN3
TLE7234E
D4
VDD
S4
CS
D5
SCLK
S5
SI
SO
OUT6
OUT7
GND
VDS0
IOUT_S1
IOUT_S2
IOUT_S3
VDS1
VS 0
V DS2
VS1
VDS3
VS 2
IOUT_D4 V S3
IOUT_S4
VDS4
V D4
IOUT_D5
IOUT_S5
VS 4
VDS5 VD5
IOUT_D6
IOUT_D7
VS 5
VDS6
VDS 7
IGND
Terms_4.emf
Figure 2
Terms
In all tables of the electrical characteristics is valid:
Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is
valid for VDS0 … VDS7). In order to make the description of output currents easier, the load current IOut is equivalent
to the drain current IOUT_D in low-side configuration and the source current IOUT_S in high-side configuration.
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. ICR01.INX1). In SPI register description,
the values in bold letters (e.g. 0) are default values.
Data Sheet
7
Rev. 1.0, 2008-10-30
TLE7234E
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
l
(top view )
1
24
2
23
3
22
4
5
6
7
25
SUB
8
exposed pad (bottom)
n.c.
n.c.
OUT1
OUT3
IN3
IN1
IN2
D5
OUT7
S5
n.c.
n.c.
VBB
OUT0
OUT2
VDD
CS
SCLK
SI
SO
D4
OUT6
S4
GND
21
20
19
18
17
9
16
10
15
11
14
12
13
PG-SSOP -24-4.emf
Figure 3
Pin Configuration PG-SSOP24-4
3.2
Pin Definitions and Functions
Pin
Symbol
I/O
Function
Power Supply
21
VDD
-
Digital power supply
24
VBB
-
Power supply
13
GND
-
Digital, analog and power ground
25
SUB
-
Substrate pins for thermal connection.
To enable reverse polarity protection these pins must be floating
Power Stages
23
OUT0
O
Source of high side power transistor channel 0
3
OUT1
O
Source of high side power transistor channel 1
22
OUT2
O
Source of high side power transistor channel 2
4
OUT3
O
Source of high side power transistor channel 3
16
D4
O
Drain of auto configuring power transistor 4
14
S4
O
Source of auto configuring power transistor 4
8
D5
O
Drain of auto configuring power transistor 5
10
S5
O
Source of auto configuring power transistor 5
15
OUT6
O
Drain of low side power transistor channel 6
9
OUT7
O
Drain of low side power transistor channel 7
6
IN1
I
Input multiplexer input 1 pin (pull down)
7
IN2
I
Input multiplexer input 2 pin (pull down)
Inputs
Data Sheet
8
Rev. 1.0, 2008-10-30
TLE7234E
Pin Configuration
Pin
Symbol
I/O
Function
5
IN3
I
Input multiplexer input 3 pin (pull down)
20
CS
I
SPI Chip select (pull up)
19
SCLK
I
Serial clock
18
SI
I
Serial data in
17
SO
O
Serial data out
n.c.
I
not connected
SPI
Others
1,2,11,12
Data Sheet
9
Rev. 1.0, 2008-10-30
TLE7234E
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings 1)
Stresses above the ones listed here may affect device reliability or may cause permanent damage to the device.
The values below are not considering combinations of different maximum conditions at one time
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Absolute Maximum Ratings1)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
min.
max.
-16
40
V
-16V max. 2 minutes
-0.3
5.5
V
–
0
28
V
–
A
–
Power Supply
4.1.1
Power supply voltage
4.1.2
Digital supply voltage
4.1.3
Power supply voltage for full short circuit
protection (single pulse)
(Tj = -40 °C … 150 °C)
Vbb
VDD
Vbat(SC)
Power Stages
4.1.4
Load current
IL
channel 0, 1, 4, 5, 6, 7
-0.5
0.5
channel 2, 3
-0.25
0.25
VDS
VOut_S
Power transistor’s drain voltage
VOut_D
Max. energy dissipation one channel single EAS
4.1.5
Voltage at power transistor
–
41
V
–
4.1.6
Power transistor’s source voltage
-16
–
V
–
–
41
V
–
mJ
2)
4.1.7
4.1.8
pulse for ch. 0, 1, 4, 5, 6, 7
4.1.9
Maximum energy dissipation one channel
repetitive pulses for ch. 0, 1, 4, 5, 6, 7
–
65
–
50
EAR
Tj(0) = 105 °C
ID(0) = 0.35 A
Tj(0) = 150 °C
ID(0)= 0.250 A
mJ
1 · 104 cycles
–
18
1 · 106 cycles
–
13
4.1.10 Max. energy dissipation one channel single EAS
pulse for ch. 2,3
Tj(0) = 105 °C
ID(0) = 0.250 A
Tj(0) = 105 °C
ID(0) = 0.220 A
mJ
–
50
–
30
2)
2)
Tj(0) = 105 °C
ID(0) = 0.250 A
Tj(0) = 150 °C
ID(0)= 0.250 A
1) not subject to production test
Data Sheet
10
Rev. 1.0, 2008-10-30
TLE7234E
Electrical Characteristics
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Absolute Maximum Ratings1)
Pos.
Parameter
Symbol
Limit Values
min.
4.1.11 Maximum energy dissipation one channel
repetitive pulses for ch. 2,3
Unit
Test Conditions
mJ
2)
max.
EAR
1 · 104 cycles
–
12
1 · 106 cycles
–
11
VIN
VCS
VSCLK
VSI
VSO
-0.3
V
3)
V
3)
V
3)
V
3)
-0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
V
3)
Tj
Tstg
-40
150
°C
–
-55
150
°C
–
VESD
-2
2
kV
HBM4)
Tj(0) = 105 °C
ID(0) = 0.180 A
Tj(0) = 105 °C
ID(0) = 0.180 A
Logic Pins
4.1.12 Voltage at input pins
4.1.13 Voltage at chip select pin
4.1.14 Voltage at serial clock pin
4.1.15 Voltage at serial input pin
4.1.16 Voltage at serial output pin
-0.3
-0.3
-0.3
Temperatures
4.1.17 Junction Temperature
4.1.18 Storage Temperature
ESD Susceptibility
4.1.19 ESD susceptibility on all pins
1) not subject to production test
2) Pulse shape represents inductive switch off: IL(t) = IL(0) * (1 - t / tpulse); 0 < t < tpulse
3) VDD + 0.3 V < 5.5 V
4) ESD susceptibility, HBM according to EIA/JESD 22-A114
4.2
Pos.
Functional Range
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
9
16
V
–
4.2.1
Supply Voltage Range for
Nominal Operation
Vbb(nom)
4.2.2
upper Supply Voltage Range for
Extended Operation
Vbb(ext),up 16
28
V
Parameter
Deviations possible
4.2.3
lower Supply Voltage Range for
Extended Operation
Vbb(ext),low 5.5
9
V
Parameter
Deviations possible
4.2.4
Junction Temperature
Tj
150
°C
–
-40
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Data Sheet
11
Rev. 1.0, 2008-10-30
TLE7234E
Electrical Characteristics
Thermal Resistance1)
Pos.
Parameter
4.3.1
Junction to Case, bottom
4.3.2
Junction to Case, top
4.3.3
Junction to Pin (6,7,18 or 19)
Symbol
Limit Values
Unit
Conditions
2)
Min.
Typ.
Max.
RthJC,back
RthJC,top
RthJPin
RthJA,min
–
–
4
K/W
–
–
35
K/W
–
–
12
K/W
–
95
–
K/W
3)
2)
2)
4.3.4
Junction to Ambient
(1s0p, min. footprint)
4.3.5
Junction to Ambient
(1s0p+300mm2Cu)
RthJA,300
–
50
–
K/W
4)
4.3.6
Junction to Ambient
(1s0p+600mm2Cu)
RthJA,600
–
40
–
K/W
5)
4.3.7
Junction to Ambient (2s2p)
RthJA,2s2p
–
31
–
K/W
6)
1) Not subject to production test
2) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
Ta = 85 °C. Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
3) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70 µm thickness.
Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
4) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300mm2
and 70 µm thickness. Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
5) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm2
and 70 µm thickness. Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
6) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
Data Sheet
12
Rev. 1.0, 2008-10-30
TLE7234E
Power Supply
5
Power Supply
The TLE7234E is supplied by two supply voltages Vbb and VDD. The Vbb supply line is connected to a battery feed
and used by the power switches and by an integrated power supply for the register banks. There is an under
voltage reset function implemented for the Vbb power supply. After start-up of the power supply, all SPI registers
are reset to their default values and the device is in sleep mode (standby). The SPI command CMD.WAKE = 1 is
switching the device to operation mode (ON), while a command CMD.STB = 1 send the device to sleep mode
(standby) again.
The VDD supply line is used by the SPI shift register related circuitry and for driving the SO line. As a result, the
daisy chain function is available as soon as VDD is provided in the specified range independent of Vbb. A capacitor
between pins VDD and GND is recommended (especially in case of EMI).
The device provides a sleep mode (stand by) to minimize current consumption, which also resets the register
banks. It is entered and left by dedicated SPI commands or by turning off the VDD supply.
5.1
Reset
There are several reset trigger implemented in the device. A reset switches off all channels and sets the registers
to default values. After any kind of reset, the transmission error flag (TER) is set.
Under Voltage Reset:
During this device condition a read on SPI always delivers the Standard Diagnostic Frame with a TER flag.
This under voltage reset is released when all the supply voltages levels are above under voltage threshold.
Reset Command: There is a reset command available to reset all register bits of the register bank and the
diagnosis registers. As soon as CMD.RST = 1, a reset is triggered.
Data Sheet
13
Rev. 1.0, 2008-10-30
TLE7234E
Power Supply
5.2
Electrical Characteristics
Unless otherwise specified:
VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ.
max.
Vbb
Vbb(UV)
9
–
28
V
–
–
5.5
V
IS
–
–
15
mA
–
–
12
mA
Power Supply Vbb
5.2.1 Supply voltage for full operation
5.2.2 Under voltage reset threshold
voltage
5.2.3 Operating current
Vbb = 16 V
1)
Vbb = 16 V
all diagnosis off
5.2.4 Sleep mode current with
disconnected loads (stand by)
IS(Sleep)
µA
Vbb = 16 V
AWK= 0
Tj = 25 °C1)
–
–
10
–
–
13
–
–
20
VDD
VDD(PO)
3.0
–
5.5
V
–
–
3.0
V
IDD
–
–
0.2
mA
Tj = 85 °C 1)
Tj = 150 °C
Digital Power Supply VDD
5.2.5 Logic supply voltage
5.2.6 Under voltage reset threshold
voltage
5.2.7 Logic supply current
fSCLK = 0 Hz
VCS = 0 V
AWK= 1
VCS = 0V
5.2.8 Logic supply sleep mode current
IDD(Sleep)
µA
VCS = VDD
AWK = 0
Tj = 25 °C1)
–
–
20
–
–
20
–
–
40
–
–
200
µs
1)
–
–
1
µs
1)
–
–
1
µs
1)
Tj = 85 °C 1)
Tj = 150 °C
Timings
twu(Sleep)
5.2.10 Vbb under voltage reset delay time tbb(UVR)
5.2.11 VDD under voltage reset delay time tDD(UVR)
5.2.9 Sleep mode wake-up time
1) Not subject to production test, specified by design.
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature.
Typical values show the typical parameters expected at Vbb = 13.5 V, VDD = 5.0 V, Tj = 25 °C.
Data Sheet
14
Rev. 1.0, 2008-10-30
TLE7234E
Power Stages
6
Power Stages
The TLE7234E is an eight channel high-side and low-side relay switch. The power stages are built by N-channel
vertical power MOSFET transistors. The gates of the high-side switches are controlled by charge pumps.
6.1
Input Circuit
There are three input pins available at TLE7234E, which can be configured to be used for control of the output
stages. The INXn parameter of the input configuration register provide following possibilities:
•
•
•
•
channel is switched off
channel is switched according to signal level at input pin IN1
channel is switched according to signal level at input pin IN2 or IN3
channel is switched on
Figure 4 shows the input circuit of TLE7234E.
IN1
IIN1
Channel 6
Channel 4
Channel 2
Channel 0
0
IN2
IIN2
1
INX0
Channel 7
Channel 5
Channel 3
Channel 1
0
IN3
IIN3
1
INX1
InputLogic3in .emf
Figure 4
Input Multiplexer
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses.
6.2
Channels 4 and 5
The TLE7234E provides two auto-configuring high-side or low-side switches (channels 4 and 5). They adjust the
diagnostic and protective functions according their potentials at drain and source automatically.
In high-side configuration, the load is connected between ground and source of the power transistors (S4 or S5).
The drain of the power transistors (D4 and D5) can be connected to any potential between GND-pin potential and
VBB-pin potential. When the drain is connected to VBB, the channel behave like the other high side channels. The
drain can also be connected to a 5 V power supply and the source pin will be utilized as switched 5 V supply line.
In low-side configuration, the source of the power transistors are to be connected to GND.
The configuration can be chosen for each of these channels individually, so it is feasible to connect one channel
in low-side and the other in high-side configuration.
Data Sheet
15
Rev. 1.0, 2008-10-30
TLE7234E
Power Stages
6.3
Inductive Output Clamp
When switching off inductive loads with low-side switches, the potential at pin OUT rises to VDS(CL) potential,
because the inductance intends to continue driving the current. For the high-side channels, the potential at pin
OUT drops below ground potential to VS(CL). The voltage clamping is necessary to prevent destruction of the
device, see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited by the max.
clamping energy EAR see electrical characteristics “EAR” on Page 10.
V bb
high side
channel
low side
channel
VBB
OUT
ID
IL
L,
RL
VD
V DS(CL)
OUT
V S(CL)
VDS(CL)
IS
VS
GND
IL
L,
RL
GND
OutputClamp.emf
Figure 5
Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE7234E. This energy can be
calculated with following equations:
V bb – V D(CL) 
RL ⋅ IL 
L
- ⋅ ln 1 – ------------------------------E = V D(CL) ⋅ -------------------------------  + I L ⋅ -----RL
R
V
–
V

L
bb
D(CL) 
Low-side
(1)
V S(CL) 
R L ⋅ I L
L
- ⋅ ln  1 – --------------E = ( V bb – V S(CL) ) ⋅ --------------- + I L ⋅ -----RL
RL
V S(CL)

High-side
(2)

V bb
2 
1
E = --- LI L ⋅  1 – -------------------------------
2
V bb – V D(CL) 

Low-side
(3)
V bb 
2 
1
E = --- LI L ⋅  1 – ---------------
2
V S(CL)

High-side
(4)
These equations simplify under the assumption of RL = 0:
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
Data Sheet
16
Rev. 1.0, 2008-10-30
TLE7234E
Power Stages
6.4
Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the INX bits of the serial peripheral
interface (SPI). The switching times tON and tOFF are designed equally.
IN
VDS
tON
tOFF
t
80%
20%
t
Figure 6
SwitchOn .emf
Switching a Resistive Load
In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF
command respectively. Please refer to Section 9.3 for details on SPI protocol.
Data Sheet
17
Rev. 1.0, 2008-10-30
TLE7234E
Power Stages
6.5
Electrical Characteristics
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
Output Characteristics
6.5.1 On-State resistance
RDS(ON)
channel 0, 1, 4, 5, 6, 7
Ω
–
–
channel 2, 3
–
1.4
1.9
1.6
–
2.6
3.9
–
–
6.5.2 Nominal load current
0.9
IOut(nom)
mA
IL = 220 mA
Tj = 25 °C
Tj = 150 °C
IL = 110 mA
Tj = 25 °C
Tj = 150 °C
all channels on
Ta = 100 °C
Tj,max = 150 °C
based on Rthja
channel 0, 1, 4, 5, 6, 7
350
500
–
1)
channel 2, 3
175
250
–
1)
–
–
1
–
–
2
–
–
5
–
–
VOUT_DS(CL) 41
VIN(L)
VIN(H)
∆VIN
IIN(L)
IIN(H)
6.5.3 Output leakage current in sleep mode
6.5.4 Output clamping voltage
IOut(Sleep)
VOUT_S(CL)
µA
VDS = 13.5 V
Tj = 25 °C1)
Tj = 85 °C 1)
Tj = 150 °C
-16
V
–
–
–
V
–
0
–
0.6
V
–
1.8
–
5.5
V
–
–
0.1
–
V
1)
1.5
–
–
µA
10
40
80
µA
VIN = 0.6 V 1)
VIN = 5 V
µs
Vbb = 13.5 V
µs
IDS= 250 mA
IDS= 120 mA
IDS = 250 mA
Vbb = 13.5 V
Input Characteristics
6.5.5 L level of pin IN
6.5.6 H level of pin IN
6.5.7 Input voltage hysteresis at pin IN
6.5.8 L-input pull-down current through pin IN
6.5.9 H-input pull-down current through pin IN
Timings
6.5.10 Turn-on time
VDS = 20% Vbat
tON
resistive load
channel 0, 1,4,5
–
–
100
channel 2, 3
–
–
100
channel 6,7
–
–
100
6.5.11 Turn-off time
VDS = 80% Vbb
tOFF
resistive load
channel 0, 1, 4, 5
–
–
100
channel 2, 3 (HS)
–
–
100
channel 6, 7 (LS)
–
–
100
IDS = 250 mA
IDS = 120 mA
IDS = 250 mA
1) Not subject to production test, specified by design.
Data Sheet
18
Rev. 1.0, 2008-10-30
TLE7234E
Power Stages
6.6
Command Description
Input Configuration Registers
ICR01
000B
3
2
1
0
INX1
INX0
rw
rw
ICR23
001B
3
2
1
0
INX3
INX2
rw
rw
ICR45
010B
3
2
1
0
INX5
INX4
rw
rw
ICR67
011B
3
2
1
0
INX7
INX6
rw
rw
Field
Bits
Type
Description
INXn
n = 7 to 0
[3:2], [1:0]
rw
Input Multiplexer Configuration Channel n
00 Channel n is switched off
01 Channel n is switched by input 1
10 Channel n is switched by input 2 or 3
11 Channel n is switched on
Data Sheet
19
Rev. 1.0, 2008-10-30
TLE7234E
Protection Functions
7
Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC
destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal
operating range. Protection functions are not designed for continuous repetitive operation.
7.1
Over Load Protection
The TLE7234E is protected in case of over load or short circuit of the load. After time tOFF(OVL), the over loaded
channel n switches off and the according diagnosis flag Dn is set. The channel can be switched on after clearing
the protection latch by command CMD.CPL = 1. The CPL command clears itself with the next valid SPI
communication frame. Please refer to Figure 7 for details.
IN
t
ID0
I D0(OV L)
tOFF(OV L)
D0 = 1b
CPL = 1b
D0 = 00b
t
OverLoad.emf
Figure 7
Shut Down at Over Load
7.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel to switch off to prevent destruction. The
according diagnosis flag is set. This flag is also set in OFF state, if the regarding channel temperature is too
high.The channel can be only switched on after clearing the protection latch by SPI command CMD.CPL = 1. The
CPL command clears itself with the next valid SPI communication frame. Please refer to “Diagnostic Features”
on Page 22 for information on diagnosis features.
7.3
ESD protection
There is a designed in protection against ESD disturbances up to the specified limit by using the defined model.
Please see electrical characteristics “ESD susceptibility on all pins” on Page 11
7.4
Reverse Polarity Protection
There is a reverse polarity protection implemented in the TLE7234E. This protection has to be divided into two
parts. First the protection of the control circuits and second in the protection of the power transistors.
The control circuits are reverse polarity protected by protective measures in the ground connection. In case of
reverse polarity, there is no current flow through the control circuits. The digital pins need serial resistors if the
connected input stages are not floating to ground.
The power transistors contain intrinsic body diodes that cause power dissipation. The reverse current through
these intrinsic body diodes has to be limited by the connected loads. The over temperature and over load
protection are not active during reverse polarity.
7.5
Loss of Vbb
In case of loss of Vbb connection in on-state, all inductances of the loads have to be demagnetized through the
ground connection or through an additional path from Vbb to ground. Then for example, a diode (see D2 in
Figure 14 “Application Diagram” on Page 34) can be placed.
Data Sheet
20
Rev. 1.0, 2008-10-30
TLE7234E
Protection Functions
7.6
Electrical Characteristics
Unless otherwise specified:
VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
Over Load Protection
7.6.1 Over load detection current at channel
0,1,4,5,6,7
IOut(OVL)
7.6.2 Over load detection current at channel 2,3 IOut(OVL)
7.6.3 Over load shut-down delay time
0.5
1.0
A
0.22
0.5
A
60
µs
tOFF(OVL)
Over Temperature Protection
7.6.4 Thermal shut down temperature
Tj(SC)
150
1701)
°C
1) Not subject to production test, specified by design
Data Sheet
21
Rev. 1.0, 2008-10-30
TLE7234E
Diagnostic Features
8
Diagnostic Features
The SPI of TLE7234E provides diagnosis information about the device and about the load. The diagnosis
information of the protective functions of channel n is latched in the diagnosis flags Dn. It is cleared by the SPI
command CMD.CPL = 1. The CPL command clears itself with the next valid SPI communication frame.
The open load diagnosis of channel n is latched in the diagnosis flag OLn. This flag is cleared by reading the
according diagnosis register.
Following table shows possible failure modes and the according protective and diagnostic action.
Failure Mode
Comment
Open Load
Diagnosis, when channel n is switched on: none
Diagnosis, when channel n is switched off: according to voltage level at the
output pin, flag OLn is set after time td(OL).
A diagnosis current can be enabled by SPI command DCCR.DCENn = 1.
Over Temperature
When over temperature occurs, the according diagnosis flag Dn is set. If the
affected channel n was active it is switched off.
The diagnosis flags are latched until they have been cleared by SPI
command CMD.CPL = 1.
Over Load
(Short Circuit)
When over load is detected at channel n, the affected channel is switched
off after time tOFF(OVL) and the dedicated diagnosis flag Dn is set.
The diagnosis flags are latched until they have been cleared by SPI
command CMD.CPL = 1.
Data Sheet
22
Rev. 1.0, 2008-10-30
TLE7234E
Diagnostic Features
8.1
Electrical Characteristics
Unless otherwise specified:
VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VBAT = 13.5 V, VDD = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Uni Test Conditions
t
max.
100
–
250
µs
–
8.1.2
Open load detection threshold voltage for VD(OL0..3) 2.3
Channel 0,1,2,3
–
3.9
V
1)
8.1.3
Output diagnosis current channel 0,1,2,3 IL(DC0..3)
–
300
µA
measured at VD(OL)
threshold
–
2.2
V
1)
OFF State Diagnosis
8.1.1
Open load diagnosis delay time
td(OL)
High Side Channels 0,1,2,3
50
Configurable Channels 4,5
8.1.4
Open load detection threshold voltage for VD(OL4,5) 1
Channel 4,5 in all configurations
8.1.5
Output diagnosis current channel 4,5 in
high side configuration
IL(DCHS)
80
–
300
µA
measured at VD(OL)
threshold
8.1.6
Output diagnosis current channel 4,5 in
low side configuration
IL(DCLS)
20
–
100
µA
measured at VD(OL)
threshold
–
2.2
V
1)
50
–
100
µA
measured at VOL
threshold
Low side Channels 6,7
8.1.7
Open load detection threshold voltage for VD(OL6,7)
Channel 6,7
8.1.8
Output diagnosis current channel 6,7
IL(DC6,7)
ON State Diagnosis (see also Protection in Chapter 7)
Over load detection current at channel
0,1,4,5,6,7
IL(OVL)
0.5
–
1.0
A
–
8.1.10 Over load detection current at channel
2,3
IL(OVL)
0.22
–
0.5
A
–
–
60
µs
–
8.1.9
8.1.11 Over load detection delay time at channel tOFF(OVL) –
0,1,4,5,6,7
1) Open load detection voltages are referenced to ground
Data Sheet
23
Rev. 1.0, 2008-10-30
TLE7234E
Diagnostic Features
8.2
Command Description
Diagnosis Registers (read only, register bank RB = 1)
DR01
00B
3
2
1
0
OL1
D1
OL0
D0
r
r
r
r
DR23
01B
3
2
1
0
OL3
D3
OL2
D2
r
r
r
r
DR45
10B
3
2
1
0
OL5
D5
OL4
D4
r
r
r
r
DR67
11B
3
2
1
0
OL7
D7
OL6
D6
r
r
r
r
Field
Bits
Type
Description
Dn
n = 7 to 0
2, 0
r
Diagnostic Feedback of Channel n
0
normal operation
1
over load or over temperature switch off occurred
OLn
n = 7 to 0
3, 1
r
Open Load Detection of Channel n
0
normal operation
1
Open load at OFF-state occurred
r/
CMD
Command Register
110B
3
2
1
0
Wake
STB
RST
CPL
r/w
r/w
r/w
r/w
Field
Bits
Type
Description
CPL
0
r/w
please refer to Section 7 for description
RST
1
r/w
please refer to Section 5.1 for description
STB
2
r/w
please refer to Section 5 for description
Wake
3
r/w
please refer to Section 5 for description
Data Sheet
24
Rev. 1.0, 2008-10-30
TLE7234E
Diagnostic Features
Diagnosis Current Configuration Register
DCCR0
100B
3
2
1
0
DCEN3
DCEN2
DCEN1
DCEN0
r/w
r/w
r/w
r/w
DCCR1
101B
3
2
1
0
DCEN7
DCEN6
DCEN5
DCEN5
r/w
r/w
r/w
r/w
Field
Bits
Type
Description
DCENn
n = 7 to 0
3 to 0
r/w
Diagnosis Current Enable Channel n
0
Diagnosis current disabled
1
Diagnosis current enabled
Data Sheet
25
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
9
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO
SI
CS
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
CS
SCLK
time
SPI.emf
Figure 8
Serial Peripheral Interface
The SPI protocol is described in Section 9.3. It is reset to the default values after reset.
9.1
SPI Signal Description
CS - Chip Select: The system micro controller selects the TLE7234E by means of the CS pin. Whenever the pin
is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
•
•
The diagnosis information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. For details, please refer to Figure 9. This information stays
available to the first rising edge of SCLK.
TER
SI
SO
1
OR
0
SI
SPI
SO
S
CS
SCLK
S
TER.emf
Figure 9
Data Sheet
Transmission Error Flag on SO Line
26
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
CS Low to High transition:
•
•
Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
Data from shift register is transferred into the input matrix register.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 9.3
for further information.
SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state
until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please
refer to Section 9.3 for further information.
9.2
Daisy Chain Capability
The SPI of TLE7234E provides daisy chain capability. In this configuration several devices are activated by the
same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 10),
which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each
device in the chain.
Figure 10
SO
SPI
SI
SO
SPI
SCLK
SI
device 3
CS
SCLK
MI
MCS
MCLK
SO
SPI
CS
SI
CS
MO
device 2
SCLK
device 1
SPI_DasyChain.emf
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device #1 has been shifted in to device #2. When using three devices in daisy
chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must go high (see
Figure 11).
Data Sheet
27
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
MI
SO device 3
SO device 2
SO device 1
MO
SI device 3
SI device 2
SI device 1
MCS
MCLK
time
SPI_DasyChain2.emf
Figure 11
Data Transfer in Daisy Chain Configuration
9.3
SPI Protocol
The control and diagnosis function of the TLE7234E is based on two register banks which are accessed via
following SPI protocol. The control register bank contains eight registers (with 4 bit each) addressed by a 3 bit
pointer. The diagnosis register bank contains four registers (with 4 bit each) addressed by a 2 bit pointer. An
additional indication bit is available to differentiate between standard diagnosis information and data read from a
register bank.
Control and Diagnosis Mode
CS1)
7
6
5
4
3
2
1
0
Write Register Command
SI
1
ADDR
DATA
Read Register Command
SI
0
ADDR
x
x
0
RB
Read Standard Diagnosis
SI
0
x
x
x
x
x
1
x
0
AWK
0
D67
D45
D23
D01
Standard Diagnosis
S
O
TER
0
Second Frame of Read Command
S
O
TER
0
S
O
TER
1
1
ADDR (Diagnosis)
ADDR (Control)
DATA
DATA
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame,
the output at SPI signal SO will contain the requested information. Any command can be executed in the
second frame.
Data Sheet
28
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
Field
Bits
Type
TER
Description
Transmission Error
0
Previous transmission was successful (modulo 8 clocks
received)
1
Previous transmission failed or first transmission after reset
RB
0
Register Bank
0
CONTR Control Register Bank
1
DIAG Diagnosis Register Bank (read only)
ADDR
6:4
Address
Pointer to register for read and write command
DATA
3:0
Data
Data written to or read from register selected by address ADDR
Standard Diagnosis:
Field
Bits
AWK
5
Awake, Device active
Dxy
3, 2, 1, 0
Failure mode alert of channel x and y
9.4
Type
Description
Register Overview
Control Register Bank
default1)
type
INX0
0H
r/w
INX3
INX2
0H
r/w
010B
INX5
INX4
0H
r/w
ICR67
011B
INX7
INX6
0H
r/w
DCCR0
100B
DCEN3
DCEN2
DCEN1
DCEN0
0H
r/w
DCCR1
101B
DCEN7
DCEN6
DCEN5
DCEN4
0H
r/w
Name
Addr
3
2
ICR01
000B
INX1
ICR23
001B
ICR45
1
0
2)
CMD
110B
WAKE
STB
RST
CPL
0H
w
unused
111B
–
–
–
–
0H
–
1) The default values are set after Vbb power-on, STB-command and RST-command
All command bits are cleared at the end of transmission, respectively after execution
2) CPL bit needs a valid next SPI communication frame to be cleared
Data Sheet
29
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
Diagnosis Register Bank (read only)
Name
Addr
3
2
1
0
DR01
000B
OL1
D1
OL0
D0
DR23
001B
OL3
D3
OL2
D2
DR45
010B
OL5
D5
OL4
D4
DR67
011B
OL7
D7
OL6
D6
9.5
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P)
CS
tSCLK(H)
0.7Vcc
0.2Vcc
tSCLK(L)
0.7Vcc
0.2Vcc
SCLK
tSI(su)
tSI(h)
0.7Vcc
SI
0.2Vcc
tSO(en)
tSO(v)
tSO(dis)
0.7Vcc
0.2Vcc
SO
SPI Timing.emf
Figure 12
Data Sheet
Timing Diagram
30
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
9.6
Electrical Characteristics
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
0
–
0.2*VDD V
–
0.5*VDD –
VDD
V
–
5
40
90
µA
VCS = 0 V
VDD = 5 V
2.5
–
–
µA
1)
µA
1)
µA
1)
V
ISO = +2 mA
ISO = -1.5 mA
VCS = VDD
Input Characteristics (CS, SCLK, SI)
9.6.1 L level of pin
CS
SCLK
SI
9.6.2 H level of pin
CS
SCLK
SI
VCS(L)
VSCLK(L)
VSI(L)
9.6.3 L-input pull-up current through CS
VCS(H)
VSCLK(H)
VSI(H)
ICS(L)
9.6.4 H-input pull-up current through CS
ICS(H)
9.6.5 L-input pull-down current through pin ISCLK(L)
SCLK
ISI(L)
SI
9.6.6 H-input pull-down current through pin ISCLK(H)
SCLK
ISI(H)
SI
1.5
–
–
VDD = 5 V
VCS = 0.5*VDD
VDD = 5 V
VSCLK = VSI = 0.2*VDD
VDD= 5 V
VSCLK = VSI = VDD
10
40
80
0
–
0.4
VDD -
–
VDD
-10
–
10
µA
9.6.10 Serial clock frequency
0
–
5
MHz –
9.6.11
200
–
–
ns
–
50
–
–
ns
1)
50
–
–
ns
1)
250
–
–
ns
1)
250
–
–
ns
1)
Output Characteristics (SO)
9.6.7 L level output voltage
9.6.8 H level output voltage
VSO(L)
VSO(H)
0.4 V
9.6.9 Output tristate leakage current
ISO(OFF)
Timings
9.6.12
9.6.13
9.6.14
fSCLK
Serial clock period
tSCLK(P)
Serial clock high time
tSCLK(H)
Serial clock low time
tSCLK(L)
Enable lead time (falling CS to rising tCS(lead)
SCLK)
9.6.15 Enable lag time (falling SCLK to rising tCS(lag)
CS )
9.6.16 Transfer delay time (rising CS to
falling CS )
tCS(td)
250
–
–
ns
1)
9.6.17 Data setup time (required time SI to
falling SCLK)
tSI(su)
20
–
–
ns
1)
9.6.18 Data hold time (falling SCLK to SI)
tSI(h)
20
–
–
ns
1)
Data Sheet
31
Rev. 1.0, 2008-10-30
TLE7234E
Serial Peripheral Interface (SPI)
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
9.6.19 Output enable time (falling CS to SO tSO(en)
valid)
–
–
200
ns
CL = 20 pF 1)
9.6.20 Output disable time (rising CS to SO tSO(dis)
tri-state)
–
–
200
ns
CL = 20 pF 1)
9.6.21 Output data valid time with capacitive tSO(v)
load
–
–
100
ns
CL = 20 pF 1)
1) Not subject to production test, specified by design.
Data Sheet
32
Rev. 1.0, 2008-10-30
TLE7234E
Package Outlines
0.2
M
0.08 C
Seating Plane
C A-B D 24x
6 ±0.2
0.2
M
D
Bottom View
13
1
0.64 ±0.25
D
A
24
0.19 +0.06
0.1 C D
3.9 ±0.11)
12
1
12
24
13
B
8.65 ±0.1
Index Marking
2.65 ±0.25
0.25 ±0.05 2)
2x
8˚ MAX.
C
0.65
0.35 x 45˚
1.7 MAX.
Stand Off
(1.47)
Package Outlines
0.1+0
-0.1
10
6.4 ±0.25
0.1 C A-B 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 13
PG-SSOP-24-4 (Plastic Green Slim Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
33
Dimensions in mm
Rev. 1.0, 2008-10-30
TLE7234E
Application Information
11
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 14 shows a simplified application circuit. Vdd need to be externally reverse polarity protected.
D1
Vbat
Lowside
Loads
C1
C2
VDD
VBB
VDD
OUT0
OUT1
OUT2
D2
PWM
IN1
PWM
IN2
PWM
IN3
OUT3
D3
D4
S4
D5
S5
CS
SCLK
SPI uC
SI
SO
OUT6
OUT7
GND
Highside
Loads
Application_4G.emf
Figure 14
Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
The circuit above shows a example of using this device in a automotive target application.
D1,C1 are used for blocking negative disturbances from Battery supply.
D2 is optional for loss of battery if no other circuit on this battery feed can limit the voltage to the negative max.
rating of the device (-16 V) .
D3 is limiting the battery voltage below the maximum rated positive voltage of the VBB pin (40 V).
C2 is for EMC and to stabilize the digital driver, recommended value is 47nF.
There are no resistors to the µC needed due to the internal reverse polarity protection.
For further information you may contact http://www.infineon.com/
Data Sheet
34
Rev. 1.0, 2008-10-30
TLE7234E
Revision History
12
Revision History
Revision
Date
Changes
Rev. 1.0
2008-10-30
released Datasheet
Data Sheet
35
Rev. 1.0, 2008-10-30
Edition 2008-10-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
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