INFINEON TLE7232G

D a ta S h e e t , V 1 . 0, S ep t e mb e r 20 0 5
SPIDER - TLE 7232G
SPI Driver for Enhanced Relay Control
Eight Channel Low-Side Switch
Automotive Power
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Table of Contents
Page
Product Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 Pin Assignment SPIDER - TLE 7232G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4 Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .11
4.1 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.3 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1.6 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.5 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.2 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.4.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4.6 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Package Outlines SPIDER - TLE 7232G
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Data Sheet
2
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
The SPIDER - TLE 7232G is an eight channel lowside power switch in P-DSO-24-3 package providing
embedded protective functions. It is especially
designed for standard relays in automotive
applications.
P-DSO-24-3
A serial peripheral interface (SPI) is utilized for
control and diagnosis of the device and the load. For
direct control, there is an input pin available.
The power transistors are built by N-channel vertical
power MOSFETs. The device is monolithically
integrated in Smart Power Technology.
Product Summary
Supply voltage
Supply voltage for SO buffer
On-State resistance at 25 °C
Nominal load current
Over load current limitation
Output leakage current per channel at 25 °C
Drain to source clamping voltage
SPI clock frequency
Vdd
VVSO
RDS(ON, max)
IL(nom, max)
IDS(LIM, min)
IDS(OFF, max)
VDS(CL, min)
fSCLK(max)
4.5 … 5.5 V
3.0 … 5.5 V
1.2 Ω
240 mA
1A
1 µA
48 V
5 MHz
Type
Ordering Code
Package
SPIDER - TLE 7232G
SP0000-89034
P-DSO-24-3
Data Sheet
3
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Basic Features
•
•
•
•
•
16 bit SPI for diagnostics and control
SPI providing daisy chain capability
3.3 V and 5 V compatible SPI
A configurable input pin offers complete flexibility for PWM operation
Stable behavior at under voltage
Protective Functions
•
•
•
•
Short circuit protection
Over load protection, configurable behavior (limitation or shutdown)
Thermal shutdown, configurable behavior (latch or restart)
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
•
•
Diagnostic information via SPI
Open load detection in OFF-state
Shorted to GND detection in OFF-state
Over temperature in ON-state
Over load in ON-state
Applications
• Especially designed for driving relays in automotive applications
• All types of capacitive, resistive and inductive loads
Data Sheet
4
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Overview
1
Overview
The SPIDER - TLE 7232G is an eight channel low-side relay switch (1.2 Ω per channel)
in P-DSO-24-3 package providing embedded protective functions. The 16 bit serial
peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads.
The SPI interface provides daisy-chain capability in order to assemble multiple devices
in one SPI chain by using the same number of micro-controller pins.
The SPIDER - TLE 7232G is equipped with one input pin that can be individually routed
to the output control of each channel thus offering complete flexibility in design and PCBlayout. The input mapping as well as the boolean operation between input signal an
output control signal is configured via SPI.
The device provides full diagnosis of the load, which is open load, short to GND as well
as short circuit to Vbat detection and over load / over temperature indication. The SPI
diagnosis flags indicate latched fault conditions that may have occurred.
Each output stage is protected against short circuit. In case of over load, the current of
the affected channel is limited. There is a temperature sensor available for each channel
to protect the device in case of over temperature. The shut down behavior in case of over
load or over temperature can be configured via SPI for each channel individually.
1.1
Block Diagram
VDD
OUT0
OUT1
IN
input map
OUT2
boolean operation
OUT3
OUT4
output control
RST
OUT5
reset / stand-by
temperature
sensor
CS
SCLK
SI
VSO
SPI
hardware
configuration
SO
control,
diagnostic
and
protective
functions
OUT6
OUT7
short circuit
detection
gate
control
output monitor
open load
detection
diagnosis register
GND
Overview .emf
Figure 1
Data Sheet
Block Diagram
5
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Overview
1.2
Terms
Following figure shows all terms used in this data sheet.
Vbat
Idd
IVSO
Vdd
IRST
V VSO
VRST
IIN
VIN
ICS
V CS
ISCLK
VSCLK ISI
VSI
VSO
ISO
VDD
OUT0
VSO
OUT1
RST
IN
SPIDER TLE 7232G
OUT2
OUT3
CS
OUT4
SCLK
OUT5
SI
OUT6
SO
OUT7
GND
I D0
I D1
V DS0
I D2
V DS1
I D3
V DS2
I D4
V DS3
I D5
V DS4
I D6
I D7
VDS5
VDS6
VDS7
IGND
Terms.emf
Figure 2
Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel
number are valid for each channel separately (e.g. VDS specification is valid for
VDS0 … VDS7).
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. CTL.OUT0). In SPI
register description, the values in bold letters (e.g. 0) are default values.
Data Sheet
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V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Pin Configuration
2
Pin Configuration
2.1
Pin Assignment SPIDER - TLE 7232G
(top view)
CS
1
24
RST
IN
2
23
VDD
OUT2
3
22
OUT1
OUT3
4
21
OUT0
GND
5
20
GND
GND
6
19
GND
GND
7
18
GND
GND
8
17
GND
OUT4
9
16
OUT7
OUT5
10
15
OUT6
VSO
11
14
SI
SO
12
13
SCLK
P-DSO-24.emf
Figure 3
Pin Configuration P-DSO-24-3
2.2
Pin Definitions and Functions
Pin
Symbol
I/O
Function
Power Supply
23
VDD
–
Power supply
11
VSO
–
Power supply for SO buffer
5, 6, 7, 8, GND
17, 18, 19,
20
–
Ground
Power Stages
21
OUT0
O
Drain of power transistor channel 0
22
OUT1
O
Drain of power transistor channel 1
3
OUT2
O
Drain of power transistor channel 2
Data Sheet
7
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Pin Configuration
Pin
Symbol
I/O
Function
4
OUT3
O
Drain of power transistor channel 3
9
OUT4
O
Drain of power transistor channel 4
10
OUT5
O
Drain of power transistor channel 5
15
OUT6
O
Drain of power transistor channel 6
16
OUT7
O
Drain of power transistor channel 7
24
RST
I
Reset input pin (active low)
2
IN
I
Input multiplexer input pin
1
CS
I
SPI Chip select (active low)
13
SCLK
I
Serial clock
14
SI
I
Serial data in
12
SO
O
Serial data out
Inputs
SPI
Data Sheet
8
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Electrical Characteristics
3
Electrical Characteristics
3.1
Maximum Ratings
Stresses above the ones listed here may affect device reliability or may cause permanent
damage to the device.
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
Pos.
Parameter
Symbol
Limit Values
min.
max.
-0.3
5.5
Unit Test
Conditions
Power Supply
3.1.1
3.1.2
3.1.3
Vdd
VSO supply voltage
VVSO
Power supply voltage for full Vbat(SC)
Power supply voltage
-0.3
V
Vdd + 0.3 V
0
20
28
V
-1
1
A
48
V
short circuit protection
(single pulse)
1)
OVL = 0 2)
OVL = 1
Power Stages
3.1.4
3.1.5
3.1.6
ID
Voltage at power transistor VDS
Maximum energy
EAS
Load current
mJ
3)
dissipation one channel
single pulse
Tj(0) = 85 °C
ID(0) = 0.35 A
Tj(0) = 150 °C
ID(0) = 0.25 A
65
30
Maximum energy
dissipation one channel
repetitive pulses
EAR
mJ
1 · 104 cycles
18
1 · 106 cycles
13
3)
Tj(0) = 150 °C
ID(0) = 0.20 A
ID(0) =0.17 A
Logic Pins
3.1.7
Voltage at input pin
3.1.8
Voltage at reset pin
3.1.9
Voltage at chip select pin
3.1.10
Voltage at serial clock pin
Data Sheet
VIN
VRST
VCS
VSCLK
9
-0.3
5.5
V
-0.3
5.5
V
-0.3
5.5
V
-0.3
5.5
V
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
Pos.
Parameter
Symbol
Unit Test
Conditions
min.
max.
-0.3
5.5
V
-0.3
5.5
V
Tj
∆Tj
-40
150
°C
60
°C
Tstg
-55
150
°C
VESD
-2
2
kV
VSI
3.1.12 Voltage at serial output pin VSO
3.1.11
Limit Values
Voltage at serial input pin
Temperatures
3.1.13
Junction Temperature
3.1.14
Dynamic temperature
increase while switching
3.1.15
Storage Temperature
ESD Susceptibility
3.1.16
ESD susceptibility HBM
according to
EIA/JESD
22-A 114B
1) Vdd + 0.3 V < 5.5 V
2) Details on configuration of protective function OLCR.OVL can be found in Section 4.2.5
3) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse
Data Sheet
10
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4
Block Description and Electrical Characteristics
4.1
Power Stages
The SPIDER - TLE 7232G is an eight channel low-side relay switch. The power stages
are built by N-channel vertical power MOSFET transistors.
4.1.1
Power Supply
The SPIDER - TLE 7232G is supplied by power supply line Vdd which is used for the
digital as well as the analog functions of the device including the gate control of the
power stages. There is a power-on reset function implemented for the supply line. After
start-up of the power supply, all SPI registers are reset to their default values. A capacitor
at pins VDD to GND is recommended.
The voltage at pin VSO is used by the driver of the SO line at the SPI. It is designed to
be functional at a wide voltage range.
There is a reset pin available. At low level at this pin, all registers are set to their default
values and the quiescent supply current is minimized.
4.1.2
Input Circuit
There is an input pin available at SPIDER - TLE 7232G to control the output stages.
channel 2
channel 1
channel 0
OR
IN
IIN
gate
control
&
MAP0
OUT0
BOL0
SLE0
channel 7
channel 6
channel 5
channel 4
channel 3
gate
control
OR
&
OUT3
BOL3
MAP3
SLE3
InputLogic.emf
Figure 4
Data Sheet
Input Mapping and Boolean Operator
11
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
The input signal can be configured to be used as control signal of the output stages for
each channel separately. The channels 0 to 3 differ from the channels 4 to 7 in the
mapping behavior. Please refer to Figure 4 for details.
The current sink to ground at the input pin ensures that the channels switch off in case
of open pin. The zener diode protects the input circuit against ESD pulses.
4.1.3
Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential,
because the inductance intends to continue driving the current. The voltage clamping is
necessary to prevent destruction of the device, see Figure 5 for details. Nevertheless,
the maximum allowed load inductance is limited.
V bat
OUT
ID
L,
RL
VDS
VDS(CL)
GND
OutputClamp .emf
Figure 5
Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the SPIDER TLE 7232G. This energy can be calculated with following equation:
V bat – V DS(CL) 

RL ⋅ ID
L
- ⋅ ln 1 – ----------------------------------E = V DS(CL) ⋅ -----------------------------------  + I D ⋅ -----RL
RL
V bat – V DS(CL) 

(1)
The equation simplifies under the assumption of RL = 0:

V bat
2 
1
E = --- LI D ⋅ 1 – -----------------------------------
2
V bat – V DS(CL) 

(2)
The energy, which is converted into heat, is limited by the thermal design of the
component.
Data Sheet
12
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4.1.4
Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the OUT bits of
the serial peripheral interface SPI. The switching times tON and tOFF are designed
equally.
CS
VDS
SPI: ON
SPI: OFF
tON
tOFF
t
80%
20%
t
Figure 6
SwitchOn.emf
Switching a Resistive Load
When the input mapping is configured accordingly, a high signal at the input pin is
equivalent to a SPI ON command.
Data Sheet
13
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4.1.5
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
typical values: Vdd = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Test
Conditions
Power Supply
4.1.1
Power supply voltage Vdd
4.1.2
Power supply current Idd(ON)
4.1.3
Power supply reset
current
4.1.4
Power-on reset
threshold voltage
4.5
5.5
3
V
5
mA
all channels ON
Idd(RST)
10
µA
VRST = 0 V
VIN = 0 V
VSCLK = 0 V
VSI = 0 V
VCS = Vdd
Vdd(PO)
4.5
V
Output Characteristics
4.1.5
On-State resistance
per channel
RDS(ON)
Ω
1.0
4.1.6
4.1.7
1.2
2.1
Output leakage
current in stand-by
mode
(per channel)
ID(RST)
Output clamping
voltage
VDS(CL)
48
60
V
VIN(L)
VIN(H)
∆VIN
0
1.0
V
2.0
Vdd
V
1
2
5
µA
IL = 300 mA
Vdd = 5 V
Tj = 25 °C 1)
Tj = 150 °C
VDS = 13.5 V
Tj = 25 °C 1)
Tj = 125 °C
Tj = 150 °C 1)
Input Characteristics
4.1.8
L level of pin IN
4.1.9
H level of pin IN
4.1.10 Input voltage
hysteresis at pin IN
0.1
4.1.11 L-input pull-down
IIN(L)
current through pin IN
10
4.1.12 H-input pull-down
IIN(H)
current through pin IN
20
Data Sheet
14
100
50
100
V
1)
µA
1)
µA
VIN = 1 V
VIN = 5 V
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
typical values: Vdd = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Test
Conditions
Reset
VRST(L)
4.1.14 H level of pin RST
VRST(H)
4.1.15 L-input pull-up current IRST(L)
4.1.13 L level of pin RST
0
1
V
2
Vdd
V
0
10
µA
VRST = 1 V
100
µA
VRST = 2 V
K/W
1) 2)
through pin RST
4.1.16 H-input pull-up
current through pin
RST
IRST(H)
20
50
Thermal Resistance
4.1.17 Junction to ambient
all channels active
Rthja
75
Timings
4.1.18 Power-on wake up
time
twu(PO)
4.1.19 Reset duration
tRST(L)
tON
4.1.20 Turn-on time
VDS = 20% Vbat
200
µs
µs
10
µs
resistive load
SLE = 0
SLE = 1
15
60
4.1.21 Turn-off time
VDS = 80% Vbat
tOFF
µs
15
60
Vbat = 14 V
IDS = 300 mA,
Vbat = 14 V
IDS = 300 mA,
resistive load
SLE = 0
SLE = 1
1) Not subject to production test, specified by design
2) Device mounted on PCB (100 mm × 100 mm × 1.5 mm). PCB without blown air. All channels with balanced
loads.
Note: Characteristics show the deviation of parameter at the given supply voltage and
junction temperature. Typical values show the typical parameters expected from
manufacturing.
Data Sheet
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V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
4.1.6
Command Description
IMCR
Input Mapping Configuration Register
Reset Value: 08H
7
6
5
4
3
2
1
0
MAP7
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
MAPn
(n = 7-0)
n
rw
Input Mapping Configuration Channel n
0
Channel n can not be controlled with input pin
(default value).
1
Channel n can be controlled with input pin,
depending on additional set-up.
BOCR
Boolean Operator Configuration Register
Reset Value: 00H
7
6
5
4
3
2
1
0
BOL7
BOL6
BOL5
BOL4
BOL3
BOL2
BOL1
BOL0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
BOLn
(n = 7-0)
n
rw
Data Sheet
Boolean Operator Configuration Channel n
0
Logic “OR” for channel n (default value).
1
Logic “AND” for channel n.
16
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Block Description and Electrical Characteristics
SRCR
Slew Rate Configuration Register
Reset Value: 00H
7
6
5
4
3
2
1
0
SLE7
SLE6
SLE5
SLE4
SLE3
SLE2
SLE1
SLE0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
SLEn
(n = 7-0)
n
rw
Slew Rate Configuration Channel n
0
Channel n is switched fast (default value).
1
Channel n is switched slowly.
CTL
Output Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
OUTn
(n = 7-0)
n
rw
Data Sheet
Output Control Channel n
0
Channel n is switched off (default value).
1
Channel n is switched on, depending on
additional set-up.
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Protection Functions
4.2
Protection Functions
The device provides embedded protective functions. Integrated protection functions are
designed to prevent IC destruction under fault conditions described in this data sheet.
Fault conditions are considered as “outside” normal operating range. Protection
functions are not designed for continuous repetitive operation.
There is an over load and over temperature protection implemented in the SPIDER TLE 7232G. The behavior of the protective functions can be set-up via SPI. Following
figure gives an overview about the protective functions.
IN
OUTn
Tn
temperature
monitor
OVTn
input mapping
OUTn
BOLn
&
&
MAPn
delay
OVLn
T
gate control
current
limitation
CLn
GND
Protection.emf
Figure 7
4.2.1
Protective Functions
Over Load Protection
The SPIDER - TLE 7232G is protected in case of over load or short circuit of the load.
The behavior in case of over load can be configured as follows:
a) The current is limited to IDS(LIM). After time td(fault), the according over load flag Ln is
set. The channel may shut down due to over temperature.
b) The current is limited to IDS(LIM). After time td(off), the over loaded channel n switches
off and the according over load flag Ln is set.
The over load flag (CLn) of the affected channel is cleared by a low-high transition of the
input signal. For timing information, please refer to Figure 8 for details.
Data Sheet
18
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Protection Functions
OLCR.OVL = 0
OLCR.OVL = 1
IN
IN
t
ID
ID(lim)
t
ID
ID(lim)
td(fault)
td(off)
t
L = 1b
L = 0b
t
L = 1b
L = 0b
OverLoadTiming .emf
Figure 8
4.2.2
Over Load Behavior
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel n to switch off
immediately to prevent destruction. The behavior in case of over temperature can be
configured as follows:
a) After cooling down, the channel is switched on again with thermal hysteresis ∆Tj.
b) The affected channel stays switched off until the over temperature flag is cleared.
The over temperature flag of the affected channel is cleared by a low-high transition of
the input signal.
4.2.3
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode of the power transistor causes power
dissipation. The reverse current through the intrinsic body diode has to be limited by the
connected load. The Vdd supply pin must be protected against reverse polarity externally.
The over-temperature protection as well as other protective functions are not active
during reverse polarity.
Data Sheet
19
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Protection Functions
4.2.4
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
typical values: Vdd = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test
Conditions
max.
Over Load Protection
4.2.1
Over load current
limitation
ID(lim)
1
2
A
OVL = 0
4.2.2
Over load shut-down
delay time
td(off)
10
50
µs
OVL = 1
170
200
°C
1)
K
1)
Over Temperature Protection
4.2.3
Over temperature
shut-down threshold
Tj(OT)
4.2.4
Thermal hysteresis
∆Tj(OT)
10
1) Not subject to production test, specified by design
Data Sheet
20
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Protection Functions
4.2.5
Command Description
OLCR
Over Load Configuration Register
Reset Value: 00H
7
6
5
4
3
2
1
0
OVL7
OVL6
OVL5
OVL4
OVL3
OVL2
OVL1
OVL0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
OVLn
(n = 7-0)
n
rw
Over Load Configuration Channel n
0
Channel n limits the current in case of over load
(default value).
1
Channel n shuts down in case of over load.
OTCR
Over Temperature Configuration Register
Reset Value: 00H
7
6
5
4
3
2
1
0
OVT7
OVT6
OVT5
OVT4
OVT3
OVT2
OVT1
OVT0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
OVTn
(n = 7-0)
n
rw
Data Sheet
Over Temperature Configuration Channel n
0
Autorestart (default value)
1
Latched shut down
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Diagnostic Features
4.3
Diagnostic Features
The SPI of SPIDER - TLE 7232G provides diagnosis information about the device and
about the load. There are following diagnosis flags implemented:
• The diagnosis information of the protective functions (flags CLn and Tn) of channel n
is latched in the diagnosis flag Pn.
• The open load diagnosis of channel n is latched in the diagnosis flag OLn.
• The short to gnd monitor information of channel n is latched in the diagnosis flag SGn.
All flags are cleared after a successful SPI transmission.
There is an output state monitor implemented in the device that indicates the switch state
of the device in register STA. Depending on the voltage level at input pin and protective
functions the bits are high or low.
Please see Figure 9 for details:
VDD
V DS(SG)
SPI
CHn
MUX
00
01
10
IDS(SG)
SGn
OUTn
VDS(OL)
IDS(PD)
OLn
STA.
OUTn
gate control
CLn
Pn
OR
protective functions
Tn
GND
diagnosis .emf
Figure 9
Data Sheet
Block Diagram Diagnosis
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Diagnostic Features
4.3.1
Electrical Characteristics
Unless otherwise specified: Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
typical values: Vdd = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
OFF State Diagnosis
4.3.1
Open load detection
threshold voltage
VDS(OL)
Vdd - Vdd - Vdd - V
2.5
2
1.3
50
90
150
4.3.2
ID(PD)
Output pull-down
diagnosis current per
channel
4.3.3
Short to gnd
detection threshold
voltage
VDS(SG)
Vdd - Vdd - Vdd - V
3.4
3.0
2.6
4.3.4
Output diagnosis
current for short to
gnd per channel
ID(SG)
-150
-100
-50
µA
4.3.5
Fault delay time
td(fault)
50
100
200
µs
Data Sheet
23
µA
VDS = 0 V
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Diagnostic Features
4.3.2
Command Description
STA
Output Status Monitor
Reset Value: 00H
7
6
5
4
3
2
1
0
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
r
r
r
r
r
r
r
r
Field
Bits
Type Description
OUTn
(n = 7-0)
n
r
Data Sheet
Output Status
0
Voltage level at channel n: VDS > VDS(OL).
1
Voltage level at channel n: VDS < VDS(OL).
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SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI,
SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK.
The falling edge of CS indicates the beginning of a data access. Data is sampled in on
line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK.
Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures
that data is taken only, when a multiple of 8 bit has been transferred. The interface
provides daisy chain capability.
SO
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SI
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
LSB
CS
SCLK
time
SPI.emf
Figure 10
Serial Peripheral Interface
The SPI protocol is described in Section 4.4.5. It is reset to the default values after
power-on reset or a low signal at pin RST.
4.4.1
SPI Signal Description
CS - Chip Select: The system micro controller selects the SPIDER - TLE 7232G by
means of the CS pin. Whenever the pin is in low state, data transfer can take place.
When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is
forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
CS Low to High transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple
(1, 2, 3, …) of eight SCLK signals have been detected.
• Data from shift register is transferred into the input matrix register.
• The diagnosis flags are cleared.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI)
transfers data into the shift register on the falling edge of SCLK while the serial output
Data Sheet
25
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
(SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential
that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit
first. SI information is read on the falling edge of SCLK. The 16 bit input data consist of
two parts (control and data). Please refer to Section 4.4.5 for further information.
SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO
is in high impedance state until the CS pin goes to low state. New data will appear at the
SO pin following the rising edge of SCLK. Please refer to Section 4.4.5 for further
information.
4.4.2
Daisy Chain Capability
The SPI of SPIDER - TLE 7232G provides daisy chain capability. In this configuration
several devices are activated by the same CS signal MCS. The SI line of one device is
connected with the SO line of another device (see Figure 11), which builds a chain. The
ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected
to the SCLK line of each device in the chain.
Figure 11
device 3
SO
SPI
SI
SO
SPI
SCLK
SI
SCLK
SCLK
MI
MCS
MCLK
SO
SPI
CS
SI
CS
MO
device 2
CS
device 1
SPI_DasyChain.emf
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is
shifted in each SCLK. The bit shifted out can be seen at SO. After 16 SCLK cycles, the
data transfer for one device has been finished. In single chip configuration, the CS line
must go high to make the device accept the transferred data. In daisy chain configuration
the data shifted out at device #1 has been shifted in to device #2. When using three
devices in daisy chain, three times 16 bits have to be shifted through the devices. After
that, the MCS line must go high (see Figure 12).
Data Sheet
26
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
MI
SO device 3
SO device 2
SO device 1
MO
SI device 3
SI device 2
SI device 1
MCS
MCLK
time
SPI_DasyChain2.emf
Figure 12
4.4.3
Data Transfer in Daisy Chain Configuration
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P)
CS
0.7Vdd
0.2Vdd
tSCLK(H)
tSCLK(L)
0.7Vdd
SCLK
0.2Vdd
tSI(su)
tSI(h)
0.7Vdd
SI
0.2Vdd
tSO(v)
tSO(dis)
0.7Vdd
SO
0.2Vdd
SPI Timing.emf
Figure 13
Data Sheet
Timing Diagram
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4.4
Electrical Characteristics
Unless otherwise specified:
VVSO = 3.0 V to 5.5 V, Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
typical values: VVSO = 5.0 V, Vdd = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min. typ.
Unit
max.
Test
Conditions
Power Supply
4.4.1
Power supply voltage VVSO
for SO buffer
3.0
5.5
V
0
1
V
2
Vdd
V
50
µA
VCS = 0 V
50
µA
1)
µA
1)
Input Characteristics (CS, SCLK, SI)
4.4.2
L level of pin
CS VCS(L)
SCLK VSCLK(L)
SI VSI(L)
4.4.3
H level of pin
CS VCS(H)
SCLK VSCLK(H)
SI VSI(H)
4.4.4
L-input pull-up current ICS(L)
through CS
10
4.4.5
H-input pull-up
current through CS
ICS(H)
5
4.4.6
4.4.7
L-input pull-down
current through pin
SCLK ISCLK(L)
SI ISI(L)
5
H-input pull-down
current through pin
SCLK ISCLK(H)
SI ISI(H)
10
20
50
VCS = 2 V
VSCLK = 1 V
VSI = 1 V
20
50
µA
VSCLK = 5 V
VSI = 5 V
Output Characteristics (SO)
4.4.8
L level output voltage VSO(L)
4.4.9
H level output voltage VSO(H)
4.4.10 Output tristate
leakage current
Data Sheet
ISO(OFF)
0
0.4
4.6
2.4
5
3
-10
10
28
V
µA
ISO = -2.5 mA
ISO = 2 mA
VVSO = 5 V
VVSO = 3 V
VCS = Vdd
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
Unless otherwise specified:
VVSO = 3.0 V to 5.5 V, Vdd = 4.5 V to 5.5 V, Tj = -40 °C to 150 °C
typical values: VVSO = 5.0 V, Vdd = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
min. typ.
Unit
max.
Test
Conditions
Timings
4.4.11 Serial clock frequency fSCLK
0
5
MHz
tSCLK(P)
4.4.13 Serial clock high time tSCLK(H)
4.4.14 Serial clock low time tSCLK(L)
4.4.15 Enable lead time
tSCLK(lead)
200
ns
50
ns
50
ns
250
ns
4.4.16 Enable lag time
tSCLK(lag)
(falling SCLK to rising
CS)
250
ns
4.4.12 Serial clock period
(falling CS to rising
SCLK)
4.4.17 Transfer delay time
(rising CS to falling
CS)
tCS(del)
250
ns
4.4.18 Data setup time
(required time SI to
falling SCLK)
tSI(su)
20
ns
20
ns
4.4.19 Data hold time (falling tSI(h)
SCLK to SI)
4.4.20 Output disable time
(rising CS to SO tristate)
tSO(dis)
4.4.21 Output data valid time tSO(v)
with capacitive load
150
ns
1)
100
ns
CL = 50 pF 1)
1) Not subject to production test, specified by design.
Data Sheet
29
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4.5
SPI Protocol
The SPI protocol of the SPIDER - TLE 7232G provides two types of registers. The
control registers and the diagnosis registers. After power-on reset, all register bits set to
default values.
SI
Reset Value: xxxxH
15
14
CMD
13
12
11
0
0
0
10
9
8
7
ADDR
6
5
4
3
2
1
0
DATA
Field
Bits
CMD
15:14
Command
00
Diagnosis only: The requested data is shifted out
at SO. This command does not change any
register setting.
01
Read register: The register content of the
addressed register will be sent in the next frame.
10
Reset registers: All registers are reset to their
default values.
11
Write register: The data of the SI word will be
written to the addressed register.
ADDR
10:8
Address
Pointer to register for read and write command
DATA
7:0
Data
Data written to or read from register selected by address
ADDR
Data Sheet
Type Description
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
SO
Standard Diagnosis
15
14
13
CH7
12
Reset Value: xxxxH
11
CH6
10
9
CH5
Field
Bits
CHn
(n = 7-0)
(2n+1):
2n
8
7
CH4
6
5
CH3
4
3
CH2
2
1
CH1
0
CH0
Type Description
Standard Diagnosis for Channel n
00
Short circuit to GND
01
Open load
10
Over load, over temperature
11
Normal operation
SO
Second Frame of Read Command
15
14
13
12
11
0
1
0
0
0
10
9
Reset Value: xxxxH
8
7
ADDR
6
5
4
3
2
1
0
DATA
Field
Bits
Type Description
ADDR
10:8
Address
Pointer to register for read and write command
DATA
7:0
Data
Data written to or read from register selected by address
ADDR
Note: Reading a register needs two SPI frames. In the first frame the RD command is
sent. In the second frame the output at SPI signal SO will contain the requested
information. A new command can be executed in the second frame.
Data Sheet
31
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SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Serial Peripheral Interface (SPI)
4.4.6
Name
Register Overview
W/R
Addr
7
6
5
4
3
2
1
0
default
1)
W/R
001B
MAP7 MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 08H
BOCR W/R
010B
BOL7
BOL6
BOL5
BOL4
BOL3
BOL2
BOL1
BOL0
00H
OLCR
W/R
011B
OVL7
OVL6
OVL5
OVL4
OVL3
OVL2
OVL1
OVL0
00H
OTCR W/R
100B
OVT7 OVT6 OVT5 OVT4
OVT3 OVT2 OVT1 OVT0 00H
SRCR W/R
101B
SLE7
SLE3
STA
R
110B
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 00H
CTL
W/R
111B
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 00H
IMCR
SLE6
SLE5
SLE4
SLE2
SLE1
SLE0
00H
1) The default values are set after reset.
Data Sheet
32
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Package Outlines SPIDER - TLE 7232G
1.27
+0.0
9
7.6 -0.2 1)
8˚ MAX.
0.35 x 45˚
0.23
2.65 MAX.
2.45 -0.2
Package Outlines SPIDER - TLE 7232G
0.2 -0.1
5
0.4 +0.8
0.1
0.35 +0.15 2)
0.2 24x
24
1
10.3 ±0.3
13
15.6 -0.4 1)
12
Index Marking
1)
2)
Does not include plastic or metal protrusion of 0.15 max. per side
Lead width can be 0.61 max. in dambar area
Dimensions in mm
Figure 14
P-DSO-24-3 (Plastic Dual Small Outline Package)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page
“Products”: http://www.infineon.com/products.
Data Sheet
33
V1.0, 2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Revision History
6
Revision History
Version
Date
Changes
V1.0
05-09-30
release of data sheet
Data Sheet
34
2005-09-30
SPI Driver for Enhanced Relay Control
SPIDER - TLE 7232G
Edition 2005-09-30
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices please contact your nearest
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Due to technical requirements components may contain dangerous substances. For information on the types in
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Infineon Technologies Components may only be used in life-support devices or systems with the express written
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of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet
35
2005-09-30
http://www.infineon.com
Published by Infineon Technologies AG