UT54ACS139

Standard Products
UT54ACS139/UT54ACTS139
Dual 2-Line to 4-Line Decoders/Demultiplexers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Incorporates two enable inputs to simplify cascading and/or
data reception
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS139 - SMD 5962-96546
‰ UT54ACTS139 - SMD 5962-96547
PINOUTS
16-Pin DIP
Top View
IG
1
16
VDD
1A
2
15
2G
1B
3
14
2A
1Y0
1Y1
4
5
13
12
2B
2Y0
1Y2
1Y3
6
7
11
10
2Y1
2Y2
VSS
8
9
2Y3
16-Lead Flatpack
Top View
DESCRIPTION
The UT54ACS139 and the UT54ACTS139 are designed to be
used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.
The devices consist of two individual two-line to four-line decoders in a single package. The active-low enable input can be
used as a data line in demultiplexing applications.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
VDD
1A
15
2G
1B
3
14
2A
1Y0
1Y1
4
5
13
12
2B
1Y2
6
11
2Y1
1Y3
VSS
7
8
10
9
2Y2
2Y3
A
Y0
Y1
Y2
Y3
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
H
L
(4)
1G
H
H
H
H
H
(1)
(5)
(6)
SELECT
H
1A
1B
L
2Y0
OUTPUT
B
H
16
2
LOGIC DIAGRAM
SELECT
INPUTS
G
L
1
1Y0
1Y1
1Y2
(2)
(3)
(7)
1Y3
L
(12)
2G
(15)
(11)
(10)
SELECT
2A
2B
1
2Y0
2Y1
2Y2
(14)
(13)
(9)
2Y3
DATA
ENABLE
INPUTS
1G
LOGIC SYMBOL
1A
1B
1G
(2)
(3)
(1)
X/Y
1
2
EN
0
1
2
3
2A
2B
2G
(14)
(13)
(15)
(4)
(5)
(6)
(7)
(12)
(11)
(10)
(9)
1A
1Y0
1Y1
1B
1Y2
1G
(2)
(3)
(1)
DMUX
0
1
0
G --3
0
1
2
3
1Y3
2Y0
2Y1
2A
2Y2
2B
2Y3
2G
Note:
1. Logic symbols in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
(14)
(13)
(4)
(5)
(6)
(7)
(12)
(11)
(10)
(9)
(15)
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-.3 to VDD +.3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
20
°C/W
II
DC input current
±10
mA
PD
Maximum power dissipation
1
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
°C
3
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
CONDITION
VIL
Low-level input voltage 1
ACTS
ACS
VIH
High-level input voltage 1
ACTS
ACS
IIN
Input leakage current
ACTS/ACS
VIN = VDD or VSS
VOL
Low-level output voltage 3
ACTS
ACS
IOL = 8.0mA
IOL = 100μA
VOH
High-level output voltage 3
ACTS
ACS
IOH = -8.0mA
IOH = -100μA
IOL
Output current10
VIN = VDD or VSS
(Sink)
VOL = 0.4V
Output current10
VIN = VDD or VSS
(Source)
VOH = VDD - 0.4V
Short-circuit output current 2 ,4
ACTS/ACS
VO = VDD and VSS
Ptotal
Power dissipation 2, 8, ,9
IDDQ
IOH
IOS
ΔIDDQ
MIN
MAX
UNIT
0.8
.3VDD
V
.5VDD
.7VDD
-1
V
1
μA
0.40
0.25
V
.7VDD
VDD - 0.25
V
8
mA
-8
mA
200
mA
CL = 50pF
1.8
mW/
MHz
Quiescent Supply Current
VDD = 5.5V
10
μA
Quiescent Supply Current Delta
For input under test
1.6
ACTS
-200
mA
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
COUT
Input capacitance 5
ƒ = 1MHz @ 0V
15
pF
Output capacitance 5
ƒ = 1MHz @ 0V
15
pF
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL
Select to output Yn
2
14
ns
tPLH
Select to output Yn
2
15
ns
tPHL
Enable to output Yn
2
14
ns
tPLH
Enable to output Yn
2
12
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
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PACKAGING
Side-Brazed Packages
7
FLATPACK PACKAGES
8
UT54ACS139/UT54ACTS139: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96546 = UT54ACS139
96547 = UT54ACTS139
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-883 Test Method 1019 Condition A.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex)
reserves the right to make changes to any products and
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or an authorized sales representative to verify that the
information in this data sheet is current before using this
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