UT54ACS240

Standard Products
UT54ACS240/UT54ACTS240
Octal Buffers & Line Drivers, Inverted Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Three-state outputs drive bus lines or buffer memory address
registers
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 20-pin DIP
- 20-lead flatpack
‰ UT54ACS240 - SMD 5962-96568
‰ UT54ACTS240 - SMD 5962-96569
PINOUTS
20-Pin DIP
Top View
DESCRIPTION
The UT54ACS240 and the UT54ACTS240 are inverting octal
buffer and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
FUNCTION TABLE
OUTPUT
1G, 2G
A
Y
L
L
H
L
H
L
H
X
Z
LOGIC SYMBOL
1G
(1)
EN
(2)
(18)
(4)
1A2
(6)
1A3
(8)
1A4
(16)
1A1
2G
(19)
(14)
(12)
1Y1
1Y2
1Y3
1Y4
EN
(11)
(9)
(13)
2A2
(15)
2A3
(17)
2A4
(7)
2A1
(5)
(3)
2Y1
2Y2
2Y3
2Y4
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
20
2
19
VDD
2G
2Y4
3
18
1Y1
1A2
4
17
2Y3
5
16
2A4
1Y2
1A3
2Y2
6
15
7
14
1A4
2Y1
8
13
9
12
2A2
1Y4
VSS
10
11
2A1
2A3
1Y3
20-Lead Flatpack
Top View
The devices are characterized over full military temperature
range of -55°C to +125°C.
INPUTS
1G
1A1
1
1G
1
20
VDD
1A1
2
19
2G
2Y4
3
18
1Y1
1A2
2Y3
4
17
5
16
2A4
1Y2
1A3
6
15
2A3
2Y2
7
14
1Y3
1A4
2Y1
VSS
8
13
9
12
10
11
2A2
1Y4
2A1
LOGIC DIAGRAM
2G (19)
1G (1)
1A1
1A2
1A3
1A4
(2)
(18)
(4)
(16)
(6)
(14)
(8)
(12)
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
2
(11)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
2Y1
2Y2
2Y3
2Y4
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-.3 to VDD +.3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
20
°C/W
II
DC input current
±10
mA
PD
Maximum power dissipation
1
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
°C
3
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
VIL
VIH
IIN
PARAMETER
CONDITION
MIN
Low-level input voltage 1
ACTS
ACS
High-level input voltage 1
ACTS
ACS
MAX
UNIT
0.8
.3VDD
V
.5VDD
.7VDD
V
Input leakage current
ACTS/ACS
VIN = VDD or VSS
Low-level output voltage 3
ACTS
ACS
IOL = 12.0mA
IOL = 100μA
High-level output voltage 3
ACTS
ACS
IOH = -12.0mA
IOH = -100μA
IOZ
Three-state output leakage current
VO = VDD and VSS
-30
30
μA
IOS
Short-circuit output current 2 ,4
ACTS/ACS
VO = VDD and VSS
-300
300
mA
Output current10
VIN = VDD or VSS
12
mA
(Sink)
VOL = 0.4V
Output current10
VIN = VDD or VSS
-12
mA
(Source)
VOH = VDD - 0.4V
Ptotal
Power dissipation 2, 8, 9
CL = 50pF
2.1
mW/
MHz
IDDQ
Quiescent Supply Current
VDD = 5.5V
10
μA
Quiescent Supply Current Delta
For input under test
1.6
mA
VOL
VOH
IOL
IOH
ΔIDDQ
ACTS
-1
1
μA
0.40
0.25
V
.7VDD
VDD - 0.25
V
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
COUT
Input capacitance 5
ƒ = 1MHz @ 0V
15
pF
Output capacitance 5
ƒ = 1MHz @ 0V
15
pF
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH
Input to Yn
1
10
ns
tPHL
Input to Yn
1
13
ns
tPZL
G low to Yn active
1
11
ns
tPZH
G low to Yn active
2
13
ns
tPLZ
G high to Yn three-state
2
11
ns
tPHZ
G high to Yn three-state
2
14
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
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PACKAGING
Side-Brazed Packages
7
FLATPACK PACKAGES
8
UT54ACS240/UT54ACTS240: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 20-lead ceramic bottom-brazed dual-in-line Flatpack
C = 20-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96568 = UT54ACS240
96569 = UT54ACTS240
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-883 Test Method 1019 Condition A.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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reserves the right to make changes to any products and
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or an authorized sales representative to verify that the
information in this data sheet is current before using this
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