Standard Products UT54ACS283/UT54ACTS283 4-Bit Binary Full Adders Datasheet November 2010 www.aeroflex.com/logic PINOUTS FEATURES 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack UT54ACS283- SMD 5962-96584 UT54ACTS283 - SMD 5962-96585 16-Pin DIP Top View Σ2 1 16 VDD B2 2 15 B3 A2 3 14 A3 Σ1 A1 4 13 5 12 Σ3 A4 B1 6 11 B4 C0 7 10 Σ4 VSS 8 9 C4 DESCRIPTION 16-Lead Flatpack Top View The UT54ACS283 and the UT54ACTS283 are 4-bit binary adders. The adders perform addition of two 4-bit binary words. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is obtained as the fifth bit. The adders feature full internal look-ahead across all four bits for fast carry generation. Σ2 B2 1 16 VDD 2 15 B3 The devices are characterized over full military temperature range of -55°C to +125°C. A2 3 14 A3 Σ1 A1 4 5 13 12 Σ3 A4 LOGIC SYMBOL B1 C0 6 11 B4 7 8 10 9 Σ4 C4 A1 A2 A3 A4 B1 B2 B3 B4 C0 (5) (3) Σ 0 (14) (12) (6) (2) P (4) 0 3 Q 3 3 C1 (1) (13) 0 (15) (11) (7) VSS C0 (10) Σ1 Σ2 Σ3 Σ4 (9) C4 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 FUNCTION TABLE INPUT A1 A3 B1 B3 OUTPUT A2 A4 B2 B4 When C0 = L When C2 = L When C0 = H When C2 = H Σ1 Σ4 Σ1 Σ4 Σ3 Σ2 C2 C4 Σ3 Σ2 C2 C4 L L L L L L L H L L H L L L H L L L H L L H L L H L L L H L H H L L L H L H H L L L H L L H L H H L H L H L H H L L L H L H H L H H L L L H H H H L L L H H L H L L L H L H L H H L H L L H H H L L L H L H L H H H L L L H H H L H L L H H L H L L H H L L H H L H H L H H H L H L H H L H H H H L H L H H H H H H L H H H H H H = high level, L = low level Note: Input conditions at A1, A2, B1, B2, and C0 are used to determine outputs Σ1 and Σ2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs Σ3, Σ4, and C4. 2 LOGIC DIAGRAM (9) C4 B4 (11) A4 (12) B3 (15) A3 (14) B2 (2) A2 (3) B1 (6) A1 (5) C0 (7) (10) Σ4 3 (13) Σ3 (1) Σ2 (4) Σ1 OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C 4 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ΔIDDQ ACTS -1 1 μA 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF 5 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 6 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay C0 to Σn 2 16 ns tPHL Propagation delay C0 to Σn 2 19 ns tPLH Propagation delay C0 to C4 2 16 ns tPHL Propagation delay C0 to C4 2 17 ns tPLH Propagation delay An, Bn to C4 2 16 ns tPHL Propagation delay An, Bn to C4 2 15 ns tPLH Propagation delay An, Bn to Σn 2 14 ns tPHL Propagation delay An, Bn to Σn 2 16 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 7 PACKAGING Side-Brazed Packages 8 FLATPACK PACKAGES 9 UT54ACS283/UT54ACTS283: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 16-lead ceramic bottom-brazed dual-in-line Flatpack C = 16-lead ceramic side-brazed dip Class Designator: Q = QML Class Q V = QML Class V Device Type: 01 Drawing Number: 96584 = UT54ACS283 96585 = UT54ACTS283 Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 10 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex UTMC Microelectronic Systems Inc. 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