EVBUM2264/D KAI-0340 Imager Board User's Manual Description The KAI-0340 Imager Evaluation Board, referred to in this document as the Imager Board, is designed to be used as part of a two−board set, used in conjunction with a Timing Generator Board. ON Semiconductor offers an Imager Board / Timing Generator Board package that has been designed and configured to operate with the KAI-0340 Image Sensor. The Timing Generator Board generates the timing signals necessary to operate the CCD, and provides the power required by the Imager Board. The timing signals, in LVDS format, and the power, are provided to the Imager Board via the interface connector (J1). In addition, the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board. The KAI−0340 Imager Board has been designed to operate the KAI−0340 with the specified performance at 40 MHz pixel clocking rate and nominal operating conditions. (See the KAI−0340 Performance Specifications for details). http://onsemi.com EVAL BOARD USER’S MANUAL For testing and characterization purposes, the KAI−0340 Imager board provides the ability to adjust many of the CCD bias voltages and CCD clock level voltages by adjusting potentiometers on the board. The Imager Board provides the means to modify other device operating parameters (e.g., CCD reset clock pulse width) by populating components differently on the board. Some circuitry on the Imager Board (e.g., remote DAC control of bias and clock level voltages) is intended for ON Semiconductor test purposes only, and may not be populated. IMAGER BOARD INPUT REQUIREMENTS Table 1. POWER REQUIREMENTS Power Supplies Minimum Typical Maximum Units +5 V_MTR Supply 4.9 5 5.1 V 800 −5 V_MTR Supply −5.1 VPLUS Supply 18 mA −5 −4.9 V 200 mA 20 21 V 250 VMINUS Supply −21 mA −20 −18 V 250 mA Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) Vmin Vthreshold Vmax Units Signal Comments IMAGER_IN0 0 ±0.1 2.4 V AMP ENABLE Output Amplifier Enable IMAGER_IN1 0 ±0.1 2.4 V H1A H1A clock IMAGER_IN2 0 ±0.1 2.4 V H1B H1B clock IMAGER_IN3 0 ±0.1 2.4 V H2A H2A clock IMAGER_IN4 0 ±0.1 2.4 V H2B H2B clock IMAGER_IN5 0 ±0.1 2.4 V RESET Reset clock IMAGER_IN6 0 ±0.1 2.4 V V1 V1 clock © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 2 1 Publication Order Number: EVBUM2264/D EVBUM2264/D Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) Vmin Vthreshold Vmax Units Signal Comments IMAGER_IN7 0 ±0.1 2.4 V V2 V2 clock IMAGER_IN8 0 ±0.1 2.4 V VCLK_ENABLE Outer V2 clock control IMAGER_IN9 0 ±0.1 2.4 V V3RD V2 Clock 3rd level IMAGER_IN10 0 ±0.1 2.4 V FDG Outer Fast Dump clock IMAGER_IN11 0 ±0.1 2.4 V VES Electronic Shutter clock IMAGER_IN12 0 ±0.1 2.4 V VIDEO MUX VOUT MUX (J2) control IMAGER_IN13 0 ±0.1 2.4 V FDG_CENTER Center Fast Dump clock IMAGER_IN14 0 ±0.1 2.4 V (not used) IMAGER_IN15 0 ±0.1 2.4 V (not used) KAI−0340 IMAGER BOARD ARCHITECTURE OVERVIEW The current sources for these voltage levels are high current (up to 600 mA) transistors. The V2_CCD high level clock voltage is switched from V_MID to V_HIGH once per frame to transfer the charge from the photodiodes to the vertical CCDs. The V1 clock driver is a 2−level driver circuit, switching between VMID and VLOW voltage levels. There are two 3−level clock driver circuits, V2 and V2C, which are identical except for the input logic, which is controlled by the VCLK_ENABLE signal. This signal is used to control the outer V2 clocks to implement certain imaging modes where only the center rows are read out. The following sections describe the functional blocks of the KAI−0340 Imager Board (Refer to Figure 1). Power Filtering and Regulation Power is supplied to the Imager Board via the J1 interface connector. The power supplies are de−coupled and filtered with ferrite beads and capacitors to suppress noise. Voltage regulators are used to create the +15 V and –15 V supplies from the VPLUS and VMINUS supplies. LVDS Receivers / TTL Buffers LVDS timing signals are input to the Imager Board via the J1 interface connector. These signals are shifted to TTL levels before being sent to the CCD clock drivers. CCD FDG Driver The Fast Dump clock drivers consist of a transistor that will switch the voltage on the FD and FDC pins of the CCD from FDG_LOW to FDG_HIGH during Fast Dump Gate operations. When not in operation, or when the Fast Dump Gate feature is not being utilized, the FDG pin of the CCD is held at FDG_LOW. The FDG_HIGH and FDG_LOW voltage levels of the FDG driver are set by potentiometers, buffered by operational amplifiers configured as voltage followers. The FD and FDC CCD inputs are clocked separately, to implement certain imaging modes where only the center columns are read out. Reset Clock One−Shot The pulse width of the RESET_CCD clock is set by a programmable One−Shot. The One−Shot can be configured to provide a RESET_CCD clock signal with a pulse width from 5 ns to 15 ns. If pulse width control functionality is provided by the Timing Board, the One−Shot may be removed and bypassed by installing R170. CCD Pixel−Rate Clock Drivers (H1, H2 & Reset Clocks) The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL−level input clock signals to the voltage levels required by the CCD. The high level and low level of the CCD clocks are set by potentiometers, and are buffered by operational amplifiers configured as voltage followers. VSUB/VES Circuit The quiescent CCD substrate voltage (VSUB) is set by a potentiometer and resistor divider network. The VSUB voltage is buffered by an operational amplifier configured with a gain of 1.40, to allow the voltage to be adjusted to nearly 14.0 V. For electronic shutter operation, the VES signal drives a transistor amplifier circuit which AC−couples the voltage difference between the VPLUS and VMINUS supplies onto the Substrate voltage. This creates the necessary potential to clear all charge from the photodiodes, thereby acting as an electronic shutter to control exposure. CCD VCLK Drivers The vertical clock (VCLK) drivers consist of MOSFET driver IC’s. These drivers are designed to translate the TTL−level clock signals to the voltage levels required by the CCD. The high, middle, and low voltage levels of the vertical clocks are set by potentiometers buffered by operational amplifiers. The VHIGH and VLOW op−amps have a gain of 1.25, to allow the magnitude of the voltages to be adjusted to 12.5 V when using DAC control. http://onsemi.com 2 EVBUM2264/D VDD Bias Voltages CCD Image Sensor The VDDL and VDDR video output amplifier supplies in the CCD are coupled directly to the +15 V regulated supply on the Imager Board. The Imager Board contains optional circuitry which allows this voltage to be adjusted through the Alternate VDD bias circuit. This circuitry is for ON Semiconductor use only, and is not enabled. The Imager Board contains optional circuitry to control a multiplexer which switches the VDD voltage from +15 V to ALT_VDD. This circuitry is for ON Semiconductor use only, and is not enabled. This evaluation board supports the KAI−0340 Interline Image Sensor. Emitter−Followers The VOUT_LEFT_CCD and VOUT_RIGHT_CCD video output signals are buffered using bipolar junction transistors in the emitter−follower configuration. These circuits also provide the necessary 5 mA current sink for the CCD output circuits. The voltage gain of this stage is approximately 0.96. Line Drivers ESD Bias Voltage The buffered VOUT_LEFT_CCD and VOUT_RIGHT_CCD signals are AC−coupled and driven from the Imager Board by operational amplifiers in a non−inverting configuration. The operational amplifiers are configured to have a gain of 1.25, which yields an overall gain of 0.6 when driving the properly terminated 75 W video coaxial cabling from the SMB connector. This is done to prevent overloading the AFE on the Timing Board. The video output of either channel may be multiplexed to the VOUT_MUX output. The multiplexer is controlled by the VIDEO_MUX signal. This circuitry is for Truesense Imaging use only, and is not enabled. The RESET and HCLK gates on the KAI−0340 CCD are protected from ESD damage by internal circuitry. The ESD bias voltage is set by a potentiometer, buffered by an operational amplifier configured as a voltage follower. The ESD bias voltage must be more negative than any of the protected gates during operation and powerup. In order to ensure these conditions are met, diodes are connected external to the CCD between the protected gates and VESD, and between VSUB and VESD. It is also recommended that during powerup of the Timing Board and Imager Board, the VMINUS supply is applied before, or simultaneously with, the other power supplies. For more information, refer to the KAI−0340 CCD Image Sensor Device Performance Specification. KAI−0340 OPERATIONAL SETTINGS The Imager board is configured to operate the KAI−0340 Image Sensor under the following operating conditions: were correct at the time of this document’s publication, but may be subject to change; refer to the KAI−0340 device specification. Bias Voltages The following voltages are fixed, or adjusted with a potentiometer as noted. The nominal values listed in Table 3 Table 3. BIAS VOLTAGES Description Symbol Min Nom Max Units Left Output Amplifier Supply VDDL 15.0 V Right Output Amplifier Supply VDDR 15.0 V ESD Protection Potentiometer Notes ESD −6.0 −9.0 −11.0 V R11 1 Substrate VSUB 8.5 TBD 14.0 V R17 1, 2 Ground GND 0 1. The Min and Max voltages in the table indicate the imager board potentiometer adjustable voltage range. These values may exceed the specified CCD operating conditions. See the KAI−0340 device specification for details. 2. The recommended VSUB voltage is specified for each CCD image sensor, and is labeled on the container as VAB. http://onsemi.com 3 EVBUM2264/D Clock Voltages Table 4 were correct at the time of this document s publication, but may be subject to change; refer to the KAI−0340 device specification. The following clock voltage levels are fixed, or adjusted with a potentiometer as noted. The nominal values listed in Table 4. CLOCK VOLTAGES Description Symbol Level Min Nom Max Units Potentiometer Notes Horizontal CCD Clock Hxx_CCD Low −8.0 −5.0 −1.0 V R126 3, 8 High −5.0 0.0 5.0 V R92 4, 8 Vertical CCD Clock Vx_CCD Low −12.0 −9.0 −6.0 V R52 5, 8 Mid −3.0 0.0 3.0 V R81 6, 8 V2x_CCD High 6.0 10.0 12.0 V R71 8 RESET_CCD Low −8.0 −3.0 −1.0 V R153 8 High 0.5 2.0 5.0 V R135 8 Fdx_CCD Low −11.5 −9.0 −5.0 V R62 7, 8 +15 V High 2.5 5.0 7.5 V R45 8 V Fixed Reset Clock Fast Dump Clock VDD High 3. 4. 5. 6. 7. 8. 15.0 The H1A_CCD, H1B_CCD, H2A_CCD, and H2B_CCD low levels are controlled by the same potentiometer (R126). The H1A_CCD, H1B_CCD, H2A_CCD, and H2B_CCD high levels are controlled by the same potentiometer (R92). V1_CCD and V2_CCD low levels are controlled by the same potentiometer (R52). V1_CCD and V2_CCD mid levels are controlled by the same potentiometer (R81). FD is used to flush the outer columns when only the center columns are read out. The Min and Max voltages in the table indicate the imager board potentiometer adjustable voltage range. These values may exceed the specified CCD operating conditions. See the KAI−0340 device specification for details. Reset Clock Pulse Width This feature is optional, as the pulsewidth may also be controlled from the Timing Board. In that case, U14 should be removed, and R170 should be installed to bypass this circuitry. The pulse width of RESET_CCD is set by configuring P[2..0], the inputs to the programmable one−shot U14. P[2..0] can be tied high or low to achieve the desired pulse width by populating the resistors R161−164 accordingly. Table 5. RESET CLOCK PULSE WIDTH Pulse Width P0 P1 P2 R161 R162 R163 R164 15 ns 0 0 0 IN IN OUT OUT 5 ns 1 0 0 IN OUT IN OUT 7.5 ns 0 1 0 OUT IN OUT IN 10 ns 1 1 0 OUT OUT IN IN http://onsemi.com 4 Notes Default Setting EVBUM2264/D BLOCK DIAGRAM AND PERFORMANCE DATA J2 SMB J3 SMB LINE DRIVER EMITTER FOLLOWER EMITTER FOLLOWER V3RD DRIVER V2 DRIVER LINE DRIVER (optional) VOUT LEFT V2C DRIVER VOUT RIGHT RCLK DRIVER RCLK 1 SHOT FDC CKT CCD SENSOR FD CKT V1 DRIVER VESD CKT VSUB/ VES CKT H1A DRIVER H2A DRIVER H1B DRIVER H2B DRIVER LVDS TO TTL BUFFERS +15V REGULATOR LVDS RECEIVERS −15V REGULATOR J1 BOARD INTERFACE CONNECTOR Figure 1. KAI−0340 Imager Board Block Diagram Photon Transfer Noise (A/D counts) 100 Slope = el/Adu = 8.97 electrons Noise floor = 3.72 counts (33.4 electrons) 10 LVSAT = 18568 electrons VSAT = 23869 electrons 1 1 10 100 1000 10000 100000 Signal Mean (Electrons) Figure 2. Measured Performance − Dynamic Range and Noise Floor http://onsemi.com 5 EVBUM2264/D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J3 and J4 The emitter−follower buffered VOUT_LEFT and VOUT_RIGHT signals are driven from the Imager Board via the SMB connectors J4 and J3, respectively. VOUT_LEFT is the primary output from KAI−0340; VOUT_RIGHT is only used when the CCD is clocked in dual−channel mode. Coaxial cable with a characteristic impedance of 75 W should be used to connect the imager board to the Timing Generator Board to match the series and terminating resistors used on these boards. Table 6. J1 INTERFACE CONNECTOR PIN ASSIGNMENTS Pin Signal Pin Signal 1 N.C. 2 N.C. 3 AGND 4 AGND 5 IMAGER_IN11+ 6 IMAGER_IN11− 7 AGND 8 AGND 9 IMAGER_IN10+ 10 IMAGER_IN10− 11 AGND 12 AGND 13 IMAGER_IN9+ 14 IMAGER_IN9− 15 AGND 16 AGND 17 IMAGER_IN8+ 18 IMAGER_IN8− 19 AGND 20 AGND 21 IMAGER_IN7+ 22 IMAGER_IN7− 23 AGND 24 AGND 25 IMAGER_IN6+ 26 IMAGER_IN6− 27 AGND 28 AGND 29 IMAGER_IN5+ 30 IMAGER_IN5− 31 AGND 32 AGND 33 IMAGER_IN4+ 34 IMAGER_IN4− 35 AGND 36 AGND 37 IMAGER_IN3+ 38 IMAGER_IN3− 39 AGND 40 AGND 41 IMAGER_IN2+ 42 IMAGER_IN2− 43 AGND 44 AGND 45 IMAGER_IN1+ 46 IMAGER_IN1− 47 N.C. 48 N.C. 49 AGND 50 AGND 51 N.C. 52 N.C. 53 VMINUS_MTR 54 VMINUS_MTR 55 N.C. 56 N.C. 57 AGND 58 AGND 59 IMAGER_IN0+ 60 IMAGER_IN0− 61 −5 V_MTR 62 −5 V_MTR 63 IMAGER_IN15+ 64 IMAGER_IN15− 65 AGND 66 AGND 67 IMAGER_IN14+ 68 IMAGER_IN14− 69 +5 V_MTR 70 +5 V_MTR 71 IMAGER_IN13+ 72 IMAGER_IN13− 73 AGND 74 AGND 75 IMAGER_IN12+ 76 IMAGER_IN12− 77 VPLUS_MTR 78 VPLUS_MTR 79 N.C. 80 N.C. http://onsemi.com 6 EVBUM2264/D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer damage to the Imager Board or Imager Board electronics. The customer assumes responsibility and care must be taken when probing, modifying, or integrating the ON Semiconductor Evaluation Board Kits. When programming the Timing Board, the Imager Board must be disconnected from the Timing Board before power is applied. If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD, damage to the Imager Board will occur. Purchasers of an Evaluation Board Kit may, at their discretion, make changes to the Timing Generator Board firmware. ON Semiconductor can only support firmware developed by, and supplied by, ON Semiconductor. Changes to the firmware are at the risk of the customer. Please address all inquiries and purchase orders to: Truesense Imaging, Inc. 1964 Lake Avenue Rochester, New York 14615 Phone: (585) 784−5500 E−mail: [email protected] ON Semiconductor reserves the right to change any information contained herein without notice. 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