EVBUM2269/D KAI-1003 Imager Board User's Manual KAI−1003 Imager Evaluation Board Description The KAI−1003 Imager Evaluation Board, referred to in this document as the Imager Board, is designed to be used as part of a two−board set, used in conjunction with a Timing Generator Board. ON Semiconductor offers an Imager Board / Timing Generator Board package that has been designed and configured to operate with the KAI−1003 Image Sensor. The Timing Generator Board generates the timing signals necessary to operate the CCD, and provides the power required by the Imager Board. The timing signals, in LVDS format, and the power, are provided to the Imager Board via the interface connector (J3). In addition, the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board. http://onsemi.com EVAL BOARD USER’S MANUAL The KAI−1003 Imager Board has been designed to operate the KAI−1003 with the specified performance at 20 MHz pixel clocking rate and nominal operating conditions. (See the KAI−1003 performance specification for details). For testing and calibration purposes, the KAI−1003 Imager board provides the ability to adjust the CCD substrate bias voltages and Reset Low CCD clock level voltage by adjusting potentiometers on the board. IMAGER BOARD INPUT REQUIREMENTS Table 1. POWER REQUIREMENTS Power Supplies Minimum Typical Maximum Units +5 V_MTR Supply 4.9 5.0 5.1 V −5 V_MTR Supply −5.1 −5.0 −4.9 V VPLUS Supply 18 20 21 V VMINUS Supply −21 −20 −18 V Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) Vmin Vthreshold Vmax Units Comments H1A (±) 0 ±0.1 2.4 V H1A clock H1B (±) 0 ±0.1 2.4 V H1B clock H2 (±) 0 ±0.1 2.4 V H2A clock R (±) 0 ±0.1 2.4 V Reset clock V1 (±) 0 ±0.1 2.4 V V1 clock V2 (±) 0 ±0.1 2.4 V V2 clock FDG 0 ±0.1 2.4 V Fast Dump clock V3RD (±) 0 ±0.1 2.4 V V1 Clock 3rd level VES (±) 0 ±0.1 2.4 V Electronic Shutter © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 2 1 Publication Order Number: EVBUM2269/D EVBUM2269/D KAI−1003 IMAGER BOARD ARCHITECTURE OVERVIEW CCD VCLK Drivers The following sections describe the functional blocks of the KAI−1003 Imager board (Refer to Figure 1). Power is supplied to the Imager Board via the J3 interface connector. The power supplies are de−coupled and filtered with ferrite beads and capacitors to suppress noise. Voltage regulators are used to create the +15 V and –15 V supplies from the VPLUS and VMINUS supplies. The vertical clock (VCLK) drivers consist of MOSFET driver IC’s. These drivers are designed to translate the TTL−level clock signals to the voltage levels required by the CCD. The current sources for these voltage levels are high current (up to 600 mA) transistors. The V2_CCD high level clock voltage is switched from V_MID to V_HIGH once per frame to transfer the charge from the photodiodes to the vertical CCDs. LVDS Receivers / TTL Buffers CCD FDG Driver Power Filtering and Regulation LVDS timing signals are input to the Imager Board via the J3 interface connector. These signals are shifted to TTL levels before being sent to the CCD clock drivers. The KAI−1003 does not use a Fast Dump Gate (FDG) circuit. The FDG signal is located on the interface connector but is not connected beyond the TTL buffer IC. CCD Pixel−Rate Clock Drivers (H1, H2 & Reset Clocks) VES Circuit The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL−level input clock signals to the voltage levels required by the CCD. The low and high levels of the reset CCD clock are set by potentiometers. Please note that the silkscreen text has been removed near H1A, H2A, and H2B, as it was incorrect. The silkscreen for the Test Points is correct and may be used to probe the pixel rate clocks as shown in Table 3. The quiescent CCD substrate voltage (VSUB) is set by a potentiometer. For electronic shutter operation, the VES signal drives a transistor amplifier circuit that AC−couples the voltage difference between the VPLUS and VMINUS supplies onto the Substrate voltage. This creates the necessary potential to clear all charge from the photodiodes, thereby acting as an electronic shutter to control exposure. CCD Bias Voltages All CCD bias voltages are fixed on the KAI−1003 Imager Board except VSUB, which can be set by a potentiometer. Table 3. PIXEL RATE CLOCK TEST POINT LOCATIONS Testpoint Pixel Rate Clock TP8 H2A_CCD TP10 H1B_CCD TP12 H2B_CCD TP13 H1A_CCD CCD Image Sensor This evaluation board supports the KAI−1003 Image Sensor. Emitter−Follower The VOUT_CCD signals are buffered using bipolar junction transistors in an emitter−follower configuration that also provides the necessary 5 mA current sink for the CCD output circuits. Reset Clock One−Shot (U9; not populated) The pulse width of the RESET_CCD clock used to be set by a programmable One−Shot. It was configured to provide a pulse width from 5 ns to 15 ns. Now, the pulse width control functionality is provided by the KSC−1000 based Timing Generator Board, and the one−shot has been bypassed by removing U9 and inserting a shorting resistor on pads 1 and 2 of U9. Line Drivers The buffered VOUT_CCD signals are AC−coupled and driven from the Imager Board by operational amplifiers in a non−inverting configuration. The operational amplifiers are configured to have a gain of 1.25, to correctly drive 75 W video coaxial cabling from the SMB connectors. http://onsemi.com 2 EVBUM2269/D KAI−1003 OPERATIONAL SETTINGS were correct at the time of this document s publication, but may be subject to change; refer to the KAI−1003 device specification. The Imager board is configured to operate the KAI−1003 CCD image sensor under the following operating conditions: Bias Voltages The following voltages are fixed, or adjusted with a potentiometer as noted. The nominal values listed in Table 4 Table 4. BIAS VOLTAGES Description Symbol Min Nom Max Units Output Amplifier Supply VDD 12.0 15.0 15.0 V Output Amplifier Return VSS Output Gate VOG 1.8 2.0 2.2 V Reset Drain VRD 10.0 10.5 11.0 V Ground, P−Well GND Substrate VSUB Disable ESD Protection VMIN Output Amplifier Load Gate VLG 0 V 0 8.0 Vsub V 18.0 V −8.5 1.4 1.5 Clock Voltages Potentiometer R56 V 1.6 V Table 5 were correct at the time of this document’s publication, but may be subject to change; refer to the KAI−1003 device specification. The following clock voltage levels are fixed, or adjusted with a potentiometer as noted. The nominal values listed in Table 5. CLOCK VOLTAGES Description Symbol Level Min Nom Max Units Horizontal CCD Clocks Hxx_CCD Low −6.5 −6.0 −5.5 V Vertical CCD Clock V1 V1_CCD Vertical CCD Clock V2 Reset Clock V2_CCD RESET_CCD High 4.5 5.0 5.5 V Low −9.0 −8.5 −8.0 V High −0.8 −0.5 0.0 V Low −9.0 −8.5 −8.0 V Mid −0.8 −0.5 0.0 V High 9.5 10.5 11.5 V Low 0 TBS 5.0 V R28 V R64 Amplitude Electronic Shutter Pulse VES_CCD 5.0 37 http://onsemi.com 3 Potentiometer 40 45 V EVBUM2269/D BLOCK DIAGRAM AND PERFORMANCE DATA J1 SMB LINE DRIVER EMITTER FOLLOWER EMITTER FOLLOWER VOUT B CHANNEL 2 V1 DRIVER VOUTA CHANNEL 1 LINE DRIVER (optional) RCLK DRIVER RCLK 1 SHOT CCD SENSOR V2 DRIVER VES CKT V3RD DRIVER H1A DRIVER H2B H2A H1B DRIVER DRIVER DRIVER LVDS TOBUFFERS TTL BUFFERS LVDS +15V REGULATOR LVDS RECEIVERS −15V REGULATOR J3 BOARD INTERFACE CONNECTOR Figure 1. KAI−1003 Imager Board Block Diagram LINEARITY 100000 10000 SIGNAL MEAN (ELECTRONS) J2 SMB 1000 MEASURED 100 FIT 10 %DEVIATION FROM FIT 1 0.1 0.01 0.01 0.1 1 10 INTEGRATION TIME (SECONDS) Figure 2. Measured Performance − Linearity http://onsemi.com 4 EVBUM2269/D Photon Transfer Slope = el/Adu = 39.18 electrons 100 Noise floor = 1.61 counts (63.1 electrons) LVSAT = 135680 electrons Noise (A/D counts) VSAT = 156015 electrons 10 1 1 10 100 1000 10000 100000 Signal Mean (Electrons) Figure 3. Measured Performance − Dynamic Range and Noise Floor http://onsemi.com 5 1000000 EVBUM2269/D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J1 and J2 75 W should be used to connect the imager board to the Timing Generator Board to match the series and terminating resistors used on these boards. The emitter−follower buffered CCD_VOUT signals are driven from the Imager Board via the SMB connectors J1 and J2. Coaxial cable with a characteristic impedance of Table 6. J4 INTERFACE CONNECTOR PIN ASSIGNMENTS Pin Signal Pin Signal 1 N.C. 2 N.C. 3 AGND 4 AGND 5 VES+ 6 VES− 7 AGND 8 AGND 9 FDG+ 10 FDG− 11 AGND 12 AGND 13 V3RD+ 14 V3RD− 15 AGND 16 AGND 17 V2B+ 18 V2B− 19 AGND 20 AGND 21 V2+ 22 V2− 23 AGND 24 AGND 25 V1+ 26 V1− 27 AGND 28 AGND 29 R+ 30 R− 31 AGND 32 AGND 33 H2B+ 34 H2B− 35 AGND 36 AGND 37 H2A+ 38 H2A− 39 AGND 40 AGND 41 H1B+ 42 H1B− 43 AGND 44 AGND 45 H1A+ 46 H1A− 47 N.C. 48 N.C. 49 AGND 50 AGND 51 N.C. 52 N.C. 53 VMINUS_MTR 54 VMINUS_MTR 55 N.C. 56 N.C. 57 AGND 58 AGND 59 N.C. 60 N.C. 61 −5 V_MTR 62 −5 V_MTR 63 N.C. 64 N.C. 65 AGND 66 AGND 67 N.C. 68 N.C. 69 +5 V_MTR 70 +5 V_MTR 71 N.C. 72 N.C. 73 AGND 74 AGND 75 N.C. 76 N.C. 77 VPLUS_MTR 78 VPLUS_MTR 79 N.C. 80 N.C. http://onsemi.com 6 EVBUM2269/D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer damage to the Imager Board or Imager Board electronics. The customer assumes responsibility and care must be taken when probing, modifying, or integrating the ON Semiconductor Evaluation Board Kits. When programming the Timing Board, the Imager Board must be disconnected from the Timing Board before power is applied. If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD, damage to the Imager Board will occur. Purchasers of an Evaluation Board Kit may, at their discretion, make changes to the Timing Generator Board firmware. ON Semiconductor can only support firmware developed by, and supplied by, ON Semiconductor. Changes to the firmware are at the risk of the customer. Please address all inquiries and purchase orders to: Truesense Imaging, Inc. 1964 Lake Avenue Rochester, New York 14615 Phone: (585) 784−5500 E−mail: [email protected] ON Semiconductor reserves the right to change any information contained herein without notice. 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