Evaluation Board User Guide UG-071 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Setting Up the Evaluation Board for the ADCLK846 PACKAGE LIST GENERAL DESCRIPTION Evaluation board with components installed Applicable documents (schematic and layout) This user guide describes how to set up and use the evaluation board for ADCLK846. The ADCLK846 data sheet contains full technical details about the specifications and operation of this device and should be consulted when using the evaluation board. 08670-001 The ADCLK846 is a high performance clock fanout buffer. The evaluation board is fabricated using a high quality Rogers® dielectric material. Transmission line paths are kept as close to 100 Ω differentially as possible. Figure 1. Evaluation Board Please see the last page for an important warning and disclaimers. Rev. 0 | Page 1 of 8 UG-071 Evaluation Board User Guide TABLE OF CONTENTS Package List ....................................................................................... 1 Clock Outputs ................................................................................4 General Description ......................................................................... 1 Evaluation Board Schematics and Artwork ...................................5 Revision History ............................................................................... 2 ESD Caution...................................................................................8 Recommended Board Setup............................................................ 3 REVISION HISTORY 12/09—Revision 0: Initial Version Rev. 0 | Page 2 of 8 Evaluation Board User Guide UG-071 RECOMMENDED BOARD SETUP The range of the peak-to-peak input voltage swing at CLK is 0.15 V to 1.8 V. Output jitter performance is degraded by input slew rate, as shown in the ADCLK846 data sheet. The recommended setup for the ADCLK846 evaluation board is shown in Figure 2. VS is set to 1.8 V. The CLK input is set up for single-ended-to-differential operation via the balun on the evaluation board. In addition, series capacitors (C3 and C4) in the path provide ac-coupled inputs to the ADCLK846. Table 1. Basic Equipment Required Quantity 1 1 1 1 2 Description Single power supply Signal source High bandwidth oscilloscope High bandwidth differential probe Matched high speed cables POWER SUPPLY 1.8V GND VS CLK ADCLK846 CLK EVALUATION BOARD OUTx PROBE OSCILLOSCOPE OUTx 08670-002 CLOCK SOURCE GND Figure 2. Recommended Setup for ADCLK846 Evaluation Rev. 0 | Page 3 of 8 UG-071 Evaluation Board User Guide Outputs that go to a SMA connector may not have a full output swing, and reflections may be observed. CLOCK OUTPUTS The ADCLK846 outputs are pin programmable up to 6 differential LVDS outputs or 12 single-ended 1.8 V CMOS outputs. Jumpers CTRL_A, CTRL_B, and SLEEP are used to configure the outputs. See Table 2 and Figure 3 for jumper assignments. Table 2. Output Pin Assignment For high precision measurements, it is recommended to evaluate the nonlaunched outputs on the evaluation board. The nonlaunched outputs do not go to the SMA connectors. In this case, the ADCLK846 is physically close to the output load and avoids the issues of driving a 50 Ω cable. CMOS is not designed to operate in a 50 Ω environment. Jumper Name CTRL_A CTRL_B SLEEP Jumper Setting Logic 0 = LVDS; Logic 1 = CMOS Logic 0 = LVDS; Logic 1 = CMOS Logic 1 = sleep The nonlaunched outputs have a full output swing with 100 Ω differential trace impedance into a 100 Ω resistor to minimize reflections. These outputs are set up to evaluate using a high bandwidth differential probe and oscilloscope. See the evaluation board schematic in Figure 4 for more details. ADCLK846 LVDS/CMOS OUT0 (OUT0A) OUT0 (OUT0B) VREF OUT1 (OUT1A) CLK OUT1 (OUT1B) CLK CTRL_A LVDS/CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) OUT4 (OUT4A) OUT4 (OUT4B) CTRL_B SLEEP OUT5 (OUT5B) Figure 3. 1:6 Clock/Data Buffer Block Diagram Rev. 0 | Page 4 of 8 08670-003 OUT5 (OUT5A) Affected Outputs Output 0 to Output 1 Output 2 to Output 5 Output 0 to Output 5 Figure 4. Evaluation Board Schematic 2 3 4 5 1 GND 0 GND GND PRI 0 R4 0 DNI 3 1 T1 C2 0.1UF C1 100OHM DIFF MATCH DNI 49.9 VREF R6 SLEEP 3 1 2 3 1 VS GND R9 1.1K C4 R5 DNI 100 R11 ADCLK846 GND 4 R12 2 100 1 5 3 1 3 4 GND VS OUT2 5 C9 2 OUT4 14 16 5 1 4 GND 2 3 100OHM DIFF MATCH 0.1UF C13 0.1UF C12 4 GND 5 GND 5 GND 1 1 OUT2B 3 2 OUT3 3 3 GND GND GND BYPASS CAPACITORS (DUT) C16 4 GND C5 VS 5 CTRL_A CTRL_B 2 3 2 C6 0.1UF C17 0.1UF 10UF OUT0 100OHM DIFF MATCH OUT0 24 7 SLEEP 8 CLKB 5 GND 22 C7 20 19 VS 100OHM DIFF MATCH 0.1UF PWR 0.1UF 1 0.1UF VS 10 OUT4B 12 OUT4 100OHM DIFF MATCH Rev. 0 | Page 5 of 8 C8 3 0.1UF 1 Evaluation Board User Guide UG-071 EVALUATION BOARD SCHEMATICS AND ARTWORK 08670-004 0.1UF 0.1UF C20 C15 Evaluation Board User Guide 08670-006 UG-071 08670-007 Figure 5. Top Trace Layer Figure 6. Ground Plane Layer Rev. 0 | Page 6 of 8 UG-071 08670-008 Evaluation Board User Guide 08670-010 Figure 7. VS Power Plane Layer Figure 8. Bottom Trace Layer Rev. 0 | Page 7 of 8 UG-071 Evaluation Board User Guide NOTES ESD CAUTION Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG08670-0-12/09(0) Rev. 0 | Page 8 of 8