DATA SHEET
MOS INTEGRATED CIRCUIT
µPD168102
MONOLITHIC 6-CHANNEL H BRIDGE DRIVER
DESCRIPTION
The µPD168102 is a monolithic 6-channel H bridge driver IC consisting of a CMOS controller and a MOS output
stage. Because it uses a MOS process, this driver IC consumes less current and loses less voltage at the output
stage than conventional driver ICs that use bipolar transistors.
In addition, the µPD168102 employs P-channel
MOSFETs in its output stage, eliminating the need for an on-chip the charge pump circuit. Therefore, the current
consumption during circuit operation can be significantly reduced.
Of the six output channels, four channels are voltage drive type and two channels are current drive type (voltage
drive is also possible). The current drive method of the µPD168102 is the output chopping method, which realizes
lower power consumption drive than the conventional high-power-dissipation linear drive method.
The µPD168102 is housed in a 48-pin WQFN to decrease the mounting area and height. The µPD168102 can
simultaneously drive two stepper motors and two DC motors and is ideal for the motor driver of digital still cameras.
FEATURES
{ Six H bridge circuits employing power MOSFETs
{ Voltage drive type: 4 channels, current drive type (constant current chopping type): 2 channels
{ Low current consumption due to elimination of charge pump circuit
{ Input logic frequency: 100 kHz supported
{ 3 V power supply supported
Minimum operating supply voltage: 2.5 V
{ Low voltage malfunction prevention circuit
Internal circuit shutdown at VDD < 2.5 V
{ On-chip overheat protection circuit
{ 48-pin WQFN (7 mm × 7 mm)
ORDERING INFORMATION
Part Number
µPD168102K9-5B4
Package
48-pin plastic WQFN (7 mm × 7 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15301EJ1V0DS00 (1st edition)
Date Published April 2002 N CP(K)
Printed in Japan
©
2002
µPD168102
PIN FUNCTIONS
Package: 48-pin WQFN (7 mm × 7 mm)
Pin No.
Pin Name
1
BRKsel
Pin Function
2
VDD
3
PGND
Output GND pin
4
OUT1B
Ch 1 output pin
5
VM1
6
OUT1A
Ch 1 output pin
7
PGND
Output block GND pin
8
OUT2B
Ch 2 output pin
9
VM2
10
OUT2A
11
PGND
Output block GND pin
12
DGND
Control block GND pin
13
ISEN5
Ch 5 current sense signal input pin
14
CL5
Ch 5 reference voltage input pin
15
VM5
Ch 5 output block power supply pin
16
OUT5B
17
RF5
18
OUT5A
19
VM5
Ch 5 output block power supply pin
20
VM6
Ch 6 output block power supply pin
21
OUT6B
22
RF6
23
OUT6A
24
VM6
Ch 6 output block power supply pin
25
CL6
Ch 6 reference voltage input pin
26
ISEN6
Ch 6 current sense signal input pin
27
PGND
Output block GND pin
28
OUT3A
Ch 3 output pin
29
VM3
30
OUT3B
31
PGND
Output block GND pin
32
OUT4A
Ch 4 output pin
Stop mode switching pin when output open
Control block power supply pin
Ch 1 output block power supply pin
Ch 2 output block power supply pin
Ch 2 output pin
Ch 5 output pin
Ch 5 sense resistor connection pin
Ch 5 output pin
Ch 6 output pin
Ch 6 sense resistor connection pin
Ch 6 output pin
Ch 3 output block power supply pin
Ch 3 output pin
33
VM4
34
OUT4B
Ch 4 output block power supply pin
35
PGND
36
VIsel
Voltage/current control switching pin (ch 5, ch 6)
37
IN12
Ch 6 input pin
38
IN11
Ch 6 input pin
39
IN10
Ch 5 input pin
40
IN9
Ch 5 input pin
41
IN8
Ch 4 input pin
42
IN7
Ch 4 input pin
43
IN6
Ch 3 input pin
44
IN5
Ch 3 input pin
45
IN4
Ch 2 input pin
46
IN3
Ch 2 input pin
47
IN2
Ch 1 input pin
48
IN1
Ch 1 input pin
Ch 4 output pin
Output block GND pin
Caution Multiple pins with the same function must all be connected.
2
Data Sheet S15301EJ1V0DS
µPD168102
BLOCK DIAGRAM
BRKsel
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
48
47
46
45
44
43
42
41
40
39
38
37
1
VDD
2
PGND
3
OUT1B
4
Ch 1
controller
Ch 2
controller
Ch 3
controller
Ch 4
controller
Ch 5
controller
Ch 6
controller
Ch 4
H bridge
circuit
Ch 1
H bridge
circuit
36
VIsel
35
PGND
34
OUT4B
33
VM4
32
OUT4A
VM1
5
OUT1A
6
31
PGND
PGND
7
30
OUT3B
OUT2B
8
29
VM3
VM2
9
28
OUT3A
OUT1A
10
27
PGND
26
ISEN6
25
CL6
Ch 3
H bridge
circuit
Ch 5
controller
Ch 2
H bridge
circuit
Ch 6
controller
TSD
CMP5
CMP6
UVLO
PGND
DGND
11
Ch 6
H bridge
circuit
Ch 5
H bridge
circuit
12
13
14
15
16
17
18
19
20
21
22
23
24
ISEN5
CL6
VM5
OUT5B
RF5
OUT5A
VM5
VM6
OUT6B
RF6
OUT6A
VM6
Caution Multiple pins with the same function must all be connected. The motor power supply pins VM1
and VM2, and VM3 and VM4 are internally connected, so be sure to apply the same potential to
them.
Data Sheet S15301EJ1V0DS
3
µPD168102
EXAMPLE OF STANDARD CONNECTION
CPU
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
48
47
46
45
44
43
42
41
40
39
38
37
10 µF
BRKsel
Reg
M
1
3V
VDD
2
PGND
3
OUT1B
4
VM1
5
OUT1A
6
PGND
7
OUT2B
VM2
Ch 1
controller
Ch 2
controller
Ch 3
controller
Ch 4
controller
8
Ch 3
H bridge
circuit
Ch 5
controller
Ch 2
H bridge
circuit
9
Ch 6
controller
Ch 4
H bridge
circuit
Ch 1
H bridge
circuit
Ch 6
controller
TSD
CMP5
OUT1A
Ch 5
controller
CMP6
10
36
VIsel
35
PGND
34
OUT4B
33
VM4
32
OUT4A
31
PGND
30
OUT3B
29
VM3
28
OUT3A
27
PGND
26
ISEN6
25
CL6
UVLO
PGND
DGND
22 µF
2.7 V
to
5.5 V
11
12
330 pF
Ch 6
H bridge
circuit
Ch 5
H bridge
circuit
13
14
15
16
17
18
19
20
21
22
23
24
ISEN5
CL6
VM5
OUT5B
RF5
OUT5A
VM5
VM6
OUT6B
RF6
OUT6A
VM6
1 kΩ
1.5 Ω
M
1.5 Ω
1 kΩ
330 pF
M
This circuit diagram is shown as an example of connection, and is not intended for mass production design.
4
Data Sheet S15301EJ1V0DS
M
µPD168102
FUNCTION OPERATION TABLE
The logic of each channel is shown in the table below.
I/O Truth Table for Channels 1 to 6
Input
Output Status
Output
VIsel
IN1, 3, 5,
7, 9, 11
IN2, 4, 6,
8, 10, 12
OUTA
OUTB
L
L
L
Z
Z
Stopped (output open, standby)
L
H
L
H
Reverse (OUTB → OUTA)
H
L
H
L
Forward (OUTA → OUTB)
H
H
L
L
Stopped (short brake)
L
L
Z
Z
Stopped (output open)
L
H
L
H
Reverse (OUTB → OUTA)
H
L
H
L
Forward (OUTA → OUTB)
H
H
L
L
Stopped (short brake)
H
Operating Mode of
Ch 5 and Ch 6
Voltage control
output
Constant current
chopping
H: High level, L: Low level, Z: High impedance
Constant current chopping is possible for channels 5 and 6.
When VIsel is set to high level, if the voltage becomes higher than the reference voltage (external input) and the
current becomes higher than the current set by the feedback resistor, the output can be forcibly chopped.
When VIsel is set to low level, channels 5 and 6 function in the same way as channels 1 to 4.
Standby function
The µPD168102 realizes a standby function by combining the input signals.
By setting all the control input signals of channels 1 to 6 to low level, a standby mode in which the current
consumption of the internal circuit is suppressed is entered. Note that the output status is high impedance
(output open).
BRKsel pin function
By using the logic of BRKsel, whether the function that prevents the motor power supply rising in the Hi-Z output
status (input L, L) is enabled or disabled can be selected. Refer to the truth table below.
BRKsel Truth Table
BRKsel
Function
L
Hi-Z status
H
Regenerates output current using an internal channel. An internal timer is incorporated, through which the
regeneration period is set for approx. 1 ms, and then the Hi-Z status is entered.
Data Sheet S15301EJ1V0DS
5
µPD168102
ABSOLUTE MAXIMUM RATINGS (TA = 25°°C: MOUNTED ON GLASS EPOXY BOARD 100 mm × 100
mm × 1 mm, COPPER FILM AREA: 15%)
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
V
VDD
Control block
−0.5 to +6.0
VM
Motor block
−0.5 to +6.0
Input voltage
VIN
Output pin voltage
VOUT
−0.5 to VDD+0.5
V
Ch 1 to ch 4
6.2
V
Ch 5, ch 6
5.7
DC output current 1 (ch 1 to ch 4)
ID(DC)1
DC
±0.3
A/ch
DC output current 2 (ch 5, ch 6)
ID(DC)2
DC
±0.5
A/ch
Instantaneous output current 1 (ch 1 to ch 4)
ID(pulse)1
PW < 10 ms, duty ≤ 20%
±0.6
A/ch
Instantaneous output current 2 (ch 5, ch 6)
ID(pulse)2
PW < 10 ms, duty ≤ 20%
±1.0
A/ch
Power consumption
PT
1.0
W
Peak junction temperature
TCH(MAX)
150
°C
Storage temperature
Tstg
−55 to +150
°C
RECOMMENDED OPERATING CONDITIONS (TA = 25°°C: MOUNTED ON GLASS EPOXY BOARD
100 mm × 100 mm × 1 mm, COPPER FILM AREA:
15%)
Parameter
Supply voltage
Input voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VDD
Control block
2.5
5.5
V
VM
Motor block
2.7
5.5
V
0
VDD
V
VIN1
VIN2
CL pin
0.1
0.5
V
DC output current 1 (ch 1 to ch 4)
ID(DC)1
DC
–0.2
+0.2
A/ch
DC output current 2 (ch 5, ch 6)
ID(DC)2
DC
–0.4
+0.4
A/ch
Instantaneous output current 1 (ch 1 to ch 4)
ID(pulse)1
PW < 10 ms, duty ≤ 20%
–0.4
+0.4
A/ch
Instantaneous output current 2 (ch 5, ch 6)
ID(pulse)2
PW < 10 ms, duty ≤ 20%
–0.8
+0.8
A/ch
Logic input frequency
fIN
100
kHz
Operating temperature range
TA
85
°C
Peak junction temperature
TCH(MAX)
125
°C
6
–10
Data Sheet S15301EJ1V0DS
µPD168102
ELECTRICAL SPECIFICATIONS (Unless otherwise specified, VDD = VM = 3 V, TA = 25°°C)
Parameter
Symbol
Conditions
VDD pin current in standby mode
IDD(STB)
VDD pin current when operating
IDD(ACT)
Input current, high
IIH
VIN = VDD
Input current, low
IIL
VIN = 0
Input pull-down resistor
RIND
Input voltage, high
VIH
2.5 V ≤ VDD ≤ 5.5 V
Input voltage, low
VIL
2.5 V ≤ VDD ≤ 5.5 V
H bridge on-resistance 1 (ch 1 to ch 4)
RON1
IM = 0.2 A, sum of the top
and bottom stages
H bridge on-resistance 2 (ch 5, ch 6)
RON2
IM = 0.4 A, RF5, RF6 = 0 V,
sum of the top and bottom
stages
Output leakage current
IM(OFF)
Per VM pin, VM = 5.5 V, all
control pins are low level
Current detection comparator offset voltage
VCO
VCL = 0.1 V
Detection voltage at low voltage
VDDS
Output turn-on time
tON
Output turn-off time
tOFF
All-off time at mode change
tHIZ
Rise time
tr
Fall time
tf
Current detection comparator operation
delay time
tCDL
MIN.
TYP.
MAX.
Unit
1.0
µA
1.0
mA
60
µA
µA
−1.0
50
200
0.7 × VDD
V
0.3 × VDD
V
1.5
2.0
Ω
1.0
1.5
Ω
10
µA
10
mV
2.5
V
0.7
2.0
µs
0.2
0.5
µs
−10
RM = 20 Ω, see Figure 1
50
RM = 20 Ω, see Figure 1
VCL = 0.1 V, VISEN = 0 V ←→
0.2 V, see Figure 2
kΩ
ns
0.3
µs
0.1
µs
0.4
1.0
µs
The overheat protection circuit operates at Tch > 150°C. In the overheat protected status, all outputs are high
impedance.
In the standby mode, the overheat protection circuit and the low-voltage malfunction prevention circuit do not
operate.
Data Sheet S15301EJ1V0DS
7
µPD168102
SWITCHING CHARACTERISTICS WAVEFORMS
Figure 1. H Bridge Switching Waveform
(1) IN2 = Low level
100 %
90 %
VIN1
10 %
tON
tOFF
tr
tf
OUT1A→OUT1B
90 %
90 %
IOUT
Hi-Z
10 %
10 %
Hi-Z
(2) IN2 = High level
100 %
90 %
VIN1
10 %
tOFF
OUT1B→OUT1A
tON
tr
tf
90 %
OUT1B→OUT1A
90 %
IOUT
brake
10 %
10 %
A high impedance period of approx. 50 ns is secured to prevent through current when switching the mode.
Figure 2. Current Detection Comparator Switching Waveform
0.2 V
50 %
VCL
0%
0.1 V
0%
50 %
0V
VISEN
tCDL
tCDL
100 %
50 %
ID
0%
8
Data Sheet S15301EJ1V0DS
50 %
µPD168102
TOTAL POWER DISSIPATION AND OPERATING AMBIENT TEMPERATURE CHARACTERISTICS
PT vs. TA characteristics
1.4
When mounted on
100 mm × 100 mm × 1.0 mm
glass epoxy board
1.2
25˚C
Total power dissipation PT (W)
1.0 W
1.0
125˚C/W
0.8
0.6
0.4
0.2
85˚C
0
–20
0
25
50
75
100
125
150
Operating ambient temperature TA (˚C)
Remark When the operating ambient temperature is 25°C or lower, power application up to 1 W is possible.
When the operating ambient temperature is higher than 25°C, perform derating in accordance with the
above figure. In addition, when at 85°C (operating ambient temperature recommended condition), power
application up to 0.52 W is possible.
Data Sheet S15301EJ1V0DS
9
µPD168102
CHARACTERISTICS CURVES
IDD vs. VDD characteristics (VM = 3.0 V, TA = 25˚C)
IDD vs. TA characteristics (VDD = 5.5 V, VM = 3.0 V)
1
4
VDD pin current IDD ( µ A)
VDD pin current IDD ( µ A)
0.8
0.6
0.4
When operating
0.2
3
2
1
When operating
During standby
0
2
4
0
–20
6
VIH, VIL vs. VDD characteristics (VM = 3.0 V, TA = 25˚C)
40
60
80
100
5
High/low-level input voltage VIH, VIL (V)
High/low-level input voltage VIH, VIL (V)
20
VIH, VIL vs. TA characteristics (VDD = 5.5 V, VM = 3.0 V)
5
4
3
VIH
VIL
2
1
0
0
2
4
4
VIH
3
VIL
2
1
0
–20
6
Supply voltage VDD (V)
1
0.5
0
2
4
20
40
60
80
100
RON1 (ch 1 to ch 4) vs. TA characteristics (VDD = 3.0 V, VM 5.5 V)
2
H bridge on-resistance RON1 (Ω)
1.5
0
0
Operating ambient temperature TA (˚C)
RON1 (ch 1 to ch 4) vs. VM characteristics (VDD = 3.0 V, TA = 25˚C)
2
H bridge on-resistance RON1 (Ω)
0
Operating ambient temperature TA (˚C)
Supply voltage VDD (V)
6
1.5
1
0.5
0
–40
Motor supply voltage VM (V)
10
During standby
0
20
40
60
80
Operating ambient temperature TA (˚C)
Data Sheet S15301EJ1V0DS
100
µPD168102
CHARACTERISTICS CURVES
RON2 (ch 5, ch 6) vs. TA characteristics (VDD = 3.0 V, VM = 5.5 V)
3
H bridge on resistance RON2 (Ω)
H bridge on resistance RON2 (Ω)
RON2 (ch 5, ch 6) vs. VM characteristics (VDD = 3.0 V, TA = 25˚C)
2
1.5
1
0.5
0
2
4
1.5
1
0.5
0
–20
6
0
Motor supply voltage VM (V)
RIND vs. TA characteristics (VDD = VM = 3.0 V)
60
80
100
VDDS vs. TA characteristics (VDD = VM = 3.0 V)
2
Detection voltage at low voltage VDDS (V)
Input pull-down resistance RIND (kΩ)
40
Operating ambient temperature TA (˚C)
150
100
50
0
–20
0
20
40
60
80
1.5
1
0.5
0
–20
100
Operating ambient temperature TA (˚C)
0
20
40
60
80
100
Operating ambient temperature TA (˚C)
tON, tOFF vs. VM characteristics (VM = 2.5 V, TA = 25˚C)
tON, tOFF vs. VDD characteristics (VM = 2.7 V, TA = 25˚C)
1
Output turn on/off time tON, tOFF (µs)
2
Output turn on/off time tON, tOFF (µs)
20
1.5
tON
1
0.5
tOFF
1.5
tON
1
0.5
tOFF
0
0
2
4
60
0
Motor supply voltage VM (V)
2
4
6
Supply voltage VDD (V)
Data Sheet S15301EJ1V0DS
11
µPD168102
CHARACTERISTICS CURVES
tr, tf vs. VDD characteristics (VM = 2.7 V, TA = 25˚C)
1
0.8
0.8
Rise/fall time tr, tf ( µ s)
Rise/fall time tr, tf ( µ s)
tr, tf vs. VM characteristics (VDD = 2.5V, TA = 25˚C)
1
0.6
0.4
tr
0.2
0.6
0.4
tr
0.2
tf
tf
0
0
2
4
6
0
Motor supply voltage VM (V)
12
2
4
Supply voltage VDD (V)
Data Sheet S15301EJ1V0DS
6
µPD168102
PACKAGE DRAWING
48-PIN PLASTIC WQFN (7x7)
HD
D
D
HD /2
/2
/2
36
37
4−C0.5
25
24
detail of P part
A
E
A2
E
S
HE /2
HE
c
48
1
13
12
x4
ZE
f
ZD
y
A1
S A B
terminal section
c2
P
y1
S
c1
S
S
x4
t
B
S A B
b1
b
ITEM
A
6.75
E
6.75
f
0.20
HD
7.00
HE
7.00
t
0.20
A
A1
A2
e
0.08MIN.
b
x
M
Lp
S A B
0.08MIN.
0.67 +0.08
−0.04
0.03 +0.02
−0.025
0.64
b
0.23±0.05
b1
0.20±0.03
c
c1
NOTE
"t" and "f" excludes mold flash
MILLIMETERS
D
0.17
0.14∼0.16
c2
0.14∼0.20
e
0.50
Lp
0.40±0.10
x
0.05
y
0.08
y1
0.10
ZD
0.625
ZE
0.625
P48K9-50-5B4
Data Sheet S15301EJ1V0DS
13
µPD168102
RECOMMENDED SOLDERING CONDITIONS
The µPD168102 should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E). For soldering methods and conditions other than those recommended below,
contact an NEC sales representative.
Surface Mounting Type Soldering Conditions
Soldering Method
Infrared reflow
Note
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C
for 10 hours), Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt%
or below) is recommended
IR60-103-3
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
14
Data Sheet S15301EJ1V0DS
µPD168102
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15301EJ1V0DS
15
µ3'
• The information in this document is current as of February, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4