PDF User Guides

v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
Table of Contents
Product & Operating Guide
A
A-1
1.0
2.0
3.0
4.0
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.2.1
4.2.2.2
4.2.3
4.2.4
4.2.4.1
4.3
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.2.3
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.11.1
4.11.2
4.11.3
4.11.4
4.11.5
4.11.6
4.11.7
4.11.8
4.12
4.12.1
Applicable Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VCO Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VCO Subsystem with Divide-by-2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VCO Subsystem with Fundamental Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCO Subsystem with Doubler Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCO Subsystem with Tri-band Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VCO Subsystem with Wideband Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VCO Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCO Auto-Calibration (AutoCal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AutoCal Use of Reg05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Auto-reLock on Lock Detect Failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Manual VCO Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Registers required for Frequency Changes in Fractional Mode . . . . . . . . . . . . . . . . . . . 11
Registers Required for Frequency Changes in Integer Mode . . . . . . . . . . . . . . . . . . . . . 11
VCO AutoCal on Frequency Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCO AutoCal Time & Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCO AutoCal Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VCO Built in Test with AutoCal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Spurious Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Integer Operation and Reference Spurious . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Fractional Operation and Spurious. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Charge Pump and Phase Detector Spurious Considerations. . . . . . . . . . . . . . . . . . . . . 15
Spurious Related to Channel Step Size (Channel Spurs). . . . . . . . . . . . . . . . . . . . . . . . . 16
Spurious Reduction with Tunable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Integrated Phase Noise & Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reference Input Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reference Path ’R’ Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RF Path ’N’ Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Charge Pump & Phase Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Phase Detector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Phase Detector Window Based Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog Window Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Digital Window Lock Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Declaration of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Phase Offset & Fractional Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Digital Lock Detect with Digital Window Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cycle Slip Prevention (CSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Charge Pump Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Charge Pump Phase Offset - Fractional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Frequency Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Integer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Order On-line at www.analog.com/hittitemw
For technical application questions: Phone: 978-250-3343 or [email protected]
v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
4.12.1.1
4.12.2
4.12.2.1
4.12.2.2
4.12.2.3.3
4.12.2.4.4
4.12.2.5.5
4.12.2.6
4.13
4.14
4.15
4.16
4.17
4.17.1
4.17.2
4.17.3
4.17.3.1
4.17.3.2
4.17.4
4.17.4.1
4.17.4.2
4.17.4.3
4.18
4.19
4.19.1
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.14
5.15
5.16
5.17
5.18
5.19
6.0
Integer Frequency Tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Fractional Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Fractional Frequency Tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Exact Frequency Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Using Hittite Exact Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Configuring Exact Frequency Mode For a Particular Frequency . . . . . . . . . . . . . . . . . 29
Hittite Exact Frequency Channel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Seed Register & AutoSeed Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Soft Reset & Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chip Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General Purpose Output (GPO) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SERIAL PORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Port Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HMCSPI Protocol Decision after Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial Port HMC Mode - Single PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HMC Mode - Serial Port WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HMC Mode - Serial Port READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Port Open Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Open Mode - Serial Port WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Open Mode - Serial Port READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
HMCSPI Open Mode READ Operation - 2 Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Configuration at Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
VCO Serial Port Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
VSPI Use of Reg05h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PLL Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reg 00h ID Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reg 00h Open Mode Read Address/RST Strobe Register (Write Only). . . . . . . . . . . . . 43
Reg 01h Enables Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reg 02h REFDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reg 03h Frequency Register - Integer Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reg 04h Frequency Register - Fractional Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reg 05h VCO SPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reg 06h SD CFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Reg 07h Lock Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reg 08h Analog EN Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reg 09h Charge Pump Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reg 0Ah VCO AutoCal Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reg 0Ch Fine Frequency Correction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Reg 0Fh GPO_SPI_RDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reg 10h VCO Tune Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reg 11h SAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Reg 12h GPO2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Reg 13h BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
VCO Subsystem Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Order On-line at www.analog.com/hittitemw
For technical application questions: Phone: 978-250-3343 or [email protected]
A
Product & Operating Guide
Table of Contents (Continued)
A-2
v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
Table of Contents (Continued)
Product & Operating Guide
A
A-3
6.1
6.2
6.3
6.3.1
6.4
6.4.1
6.5
VCO_Reg 00h Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VCO_Reg 01h Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VCO_Reg 02h Biases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PLL Reg05h Values for VCO_Reg 02h Required Config Narrowband ONLY. . . . . . . . . 56
VCO_Reg 03h Config. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PLL Reg05h Values for VCO_Reg 03h Required Config Narrowband ONLY. . . . . . . . . 57
VCO_Reg 04h, VCO_Reg 05h, VCO_Reg 06h Wideband Devices Only. . . . . . . . . . . . . 57
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v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
Applicable Products
This Operating Guide applies to Hittite’s family of PLLs with Integrated VCO products. This family of
products is broadly categorized by the type of integrated VCO (Voltage Controlled Oscillator) subsystem,
see section “4.0 Theory of Operation” for more details.
Narrowband parts contain a VCO subsystem that can be configured to operate in a limited number of
configurations (any combination of divide-by-2 and/or fundamental, and/or doubler outputs from one
device). Narrowband parts can be further segmented into tri-band parts that contain a VCO subsystem
capable of operating in all three modes; fundamental (Fo), doubler (2Fo); and divide-by-2 (Fo/2), and
Single band parts that contain a VCO subsystem that is only capable of operating in one of the three
modes; fundamental (Fo) or doubler (2Fo) or divide-by-2 (Fo/2).
Wideband parts on the other hand contain a VCO subsystem that can be configured to operate with divide
by N, where N = 1,2,4,6,8...58,60,62. Detailed product family segmentation matrix is shown in Table 1.
Table 1. Hittite PLL with Integrated VCO Product Family Matrix
Narrowband
Clock Generators
Wideband
Single-band
Tri-band
Fo/2
Fo
2Fo
Divide By 2
Fundamental
Doubler
HMC826LP6CE
HMC828LP6CE
HMC824LP6CE
HMC831LP6CE
HMC820LP6CE
HMC1032LP6GE
HMC829LP6GE
HMC1033LP6GE
HMC830LP6GE
HMC1034LP6GE
HMC1032LP6GE
HMC1035LP6GE
HMC1034LP6GE
HMC821LP6CE
HMC822LP6CE
HMC837LP6CE
HMC838LP6CE
HMC836LP6CE
HMC839LP6CE
HMC840LP6CE
2.0
General Description
Hittite’s family of PLLs with Integrated VCOs offers pin-compatible integrated frequency generation solutions
across a wide range of frequency bands. The product family includes a high level of integration requiring
only an external loop-filter and an external reference source to build a complete frequency synthesizer.
A
Product & Operating Guide
1.0
The entire family of products shares a common architecture which has been specifically designed to have
the best phase noise and spurious performance in the industry. The superior performance as a Local
Oscillator minimizes blocker effects, improves receiver sensitivity, and improves transmitter spectral purity.
Superior phase noise and low noise floors lead to ultra low jitter which makes this family of PLLs with
integrated VCOs ideal for clocking high performance data-converters.
The architecture includes integrated Phase Detector (PD) and a delta-sigma modulator capable of
operating at up to 100 MHz which offers excellent phase noise and spectral performance and permits wide
loop-bandwidths, while delivering high frequency resolution and ultra-low step sizes. This architecture
also includes an integrated VCO subsystem, precision controlled charge-pump, low noise reference path
divider, and a 19-bit fractional divider with minimum division ratio of 16.
In addition to high integration and excellent performance, Hittite’s family of PLLs with Integrated VCOs
offers a number of features including (for details and additional features please see individual product data
sheets):
•
•
•
•
Exact Frequency Mode which enables users to generate frequencies with 0 Hz frequency error, with
minimal spurious emissions at multiples of the channel spacing.
CSP (cycle slip protection) technology that allows faster frequency convergence which enables faster
frequency hopping times.
Auto-Calibration of the VCO subsystem which ensures single point calibration for optimal operation
over the full temperature range of the device.
Built-In Self Test (BIST) controlled via the serial port which ensures full test coverage of the digital
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A-4
v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
•
Product & Operating Guide
A
A-5
•
•
3.0
logic.
Robust digital lock detect that provides faster and more accurate lock detect information compared
to conventional analog lock detect, and offers serial port monitoring of lock detect for unprecedented
visibility into device status from the host controller.
Versatile SPI (Serial Port Interface) with an option of two modes of operation that enables full control of
PLL and VCO subsystem configuration, offering a choice of industry standard SPI protocols, including
the possible use of multiple devices on a single bus.
GPO (General Purpose Output) that enables users to control and read various states of the PLL and
VCO subsystems.
Functional Diagram
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v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
Theory of Operation
The PLL with Integrated VCO is targeted for ultra low phase noise applications and has been designed
with very low noise reference path, phase detector and charge pump.
The PLL with Integrated VCO consists of the following functional blocks:
1. Reference Path Input Buffers and ’R’ Divider
2. VCO Path Input Buffer and Multi-Modulus ’N’ Divider
3. Δ∑ Fractional Modulator
4. Phase Detector
5. Charge Pump
6. Serial Port with Read Write Capability
7. General Purpose Output (GPO) Port
8. Power On Reset Circuit
9. VCO Subsystem
10. Built-In Self Test Features
Depending upon the PLL with Integrated VCO type, the VCO subsystem may be configured in one of five
ways:
a. VCO with fundamental output only
b. VCO with divide by two output only
c. VCO with doubler output only
d. VCO with tri-band output, that is a choice of divide-by-2, fundamental or doubler outputs in one
device.
e. VCO subsystem with a wideband output that can be configured to operate with divide by N, where
N = 1,2,4,6,8...58,60,62.
In all cases the internal PLL runs at the fundamental frequency of the VCO. Each of these blocks is
described briefly in the following section.
4.1
VCO Subsystem
There are 5 possible types of VCO subsystem. See Table 1 for more details.
4.1.1
A
Product & Operating Guide
4.0
VCO Subsystem with Divide-by-2 Output
The PLL with Integrated VCOs with only a Divide-by-2 output operates with the internal VCO at double
the output frequency. The PLL itself operates at the VCO fundamental. Hence the loop filter design is
implemented for a nominal VCO at double the output frequency.
Figure 1. PLL with Integrated VCO and Divide-by-2 Output
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A-6
v12.1215
PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
4.1.2
Product & Operating Guide
A
VCO Subsystem with Fundamental Output
The PLL with Integrated VCOs with only a fundamental output only operate with the internal VCO
operating at the same frequency as at the output frequency. Hence the loop filter design is implemented
for a nominal VCO at the output frequency.
Figure 2. PLL with Integrated VCO with Fundamental Output
4.1.3
VCO Subsystem with Doubler Output
The PLL with Integrated VCOs with only a doubler output only operate with the internal VCO operating at
half the frequency as the output frequency. Hence the loop filter design is implemented for a nominal VCO
at half the output frequency.
Figure 3. PLL with Integrated VCO and Doubler Output
A-7
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VCO Subsystem with Tri-band Output
The PLL with Integrated VCOs with a tri-band output offer a selectable output frequency band at half,
fundamental or double the internal VCO frequency. The loop filter design is implemented for a nominal
VCO at the same fundamental output frequency for all bands. Fundamental mode or divide-by-2 mode with
the tri-band PLL with Integrated VCO can be selected from the serial port with no changes to the external
circuit. Doubler mode however requires that RF_P and RF_N outputs on the application circuit board be
shorted together. Normally for best power output band specific matching is recommended.
Note:
RF_P & RF_N must be shorted
together for doubler operation
with Tri-band devices.
Figure 4. PLL with Integrated VCO and Selectable Tri-band Output
4.1.5
VCO Subsystem with Wideband Output
The PLL with Integrated VCOs with a wideband output contains a VCO subsystem that can be configured
to operate with divide by N, where N = 1,2,4,6,8...58,60,62. One loop filter design can be used for the entire
frequency of operation of the wideband PLL, or the loop filter can be optimized for a specific frequency
band of interest.
A
Product & Operating Guide
4.1.4
Figure 5. Wideband PLL with Integrated VCO
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Product & Operating Guide
A
4.2
VCO Calibration
4.2.1
VCO Auto-Calibration (AutoCal)
All of the VCO subsystem types use a step tuned type VCO. A simplified step tuned VCO is shown in
Figure 6. A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center
frequency of the VCO to be adjusted or ‘stepped’ by switching in/out VCO tank capacitors. A more detailed
view of a typical VCO subsystem configuration is shown in Figure 7. A step tuned VCO allows the user to
center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near
the mid-voltage tuning point of the PLL with Integrated VCO charge pump. This enables the PLL charge
pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning
sensitivity (kvco).
The VCO switches are normally controlled automatically by the PLL with Integrated VCO using the
Auto-Calibration feature. The Auto-Calibration feature is implemented in the internal state machine. It
manages the selection of the VCO sub-band (capacitor selection) when a new frequency is programmed.
The VCO switches may also be controlled directly via register Reg 05h for testing or for other special
purpose operation. Other control bits specific to the VCO are also sent via Reg 05h.
Figure 6. Simplified Step Tuned VCO
Figure 7. Typical PLL with Integrated VCO Subsystem
To use a step tuned VCO in a closed loop, the VCO must be calibrated such that the PLL with Integrated
VCO knows which switch position on the VCO is optimum for the desired output frequency. The PLL with
Integrated VCO supports the Auto-Calibration (AutoCal) of the step tuned VCO. The AutoCal fixes the VCO
A-9
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5
4
50MHz PFD, 500kHz Tuning Steps, +25C
256 Count Calibration ,195kHz Resolution
31usec Total Cal Time
3
31
15
0
2
1
0
920
960
1000
1040
1080
1120
1160
CALIBRATION FREQUENCY (MHz)
Figure 8. A Typical 5-Bit 32 Switch VCO Tuning Voltage After Calibration
The calibration is normally run automatically once for every change of frequency. This ensures optimum
selection of VCO switch settings vs. time and temperature. The user does not normally have to be concerned
about which switch setting is used for a given frequency as this is handled by the AutoCal routine. The
accuracy required in the calibration affects the amount of time required to tune the VCO. The calibration
routine searches for the best step setting that locks the VCO at the current programmed frequency, and
ensures that the VCO will stay locked and perform well over it’s full temperature range without additional
calibration, regardless of the temperature that the VCO was calibrated at.
Auto-Calibration can also be disabled allowing manual VCO tuning. Refer to section 4.2.2 for a description
of manual tuning
A
Product & Operating Guide
TUNE VOLTAGE AFTER CALIBRATION (V)
tuning voltage at the optimum mid-point of the charge pump output, then measures the free running VCO
frequency while searching for the setting which results in the free running output frequency that is closest
to the desired phase locked frequency. This procedure results in a phase locked oscillator that locks over
a very narrow voltage range on the varactor. A typical tuning curve for a step tuned VCO is shown in
Figure 8. Note how the tuning voltage stays in a narrow range over a wide range of output frequencies.
4.2.1.1 AutoCal Use of Reg05h
AutoCal transfers switch control data to the VCO subsystem via Reg 05h. The address of the VCO
subsystem in Reg 05h is not altered by the AutoCal routine. The address and ID of the VCO subsystem
in Reg 05h must be set to the correct value before AutoCal is executed. For more information see section
4.19.
4.2.1.2 Auto-reLock on Lock Detect Failure
It is possible by setting “Reg 07h”[13] to have the VCO subsystem automatically re-run the calibration
routine and re-lock itself if Lock Detect indicates an unlocked condition for any reason. With this option the
system will attempt to re-Lock only once. Auto-reLock is recommended.
4.2.2
Manual VCO Calibration
If it is desirable to switch frequencies very quickly it is possible to eliminate the AutoCal time by calibrating
the VCO in advance and storing the switch number vs frequency information in the host. This can be done
by initially locking the PLL with Integrated VCO on each desired frequency using AutoCal, then reading,
and storing the VCO switch settings selected. The VCO switch settings are available in Reg 10h[7:0] after
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every AutoCal operation. The host must then program the VCO switch settings directly when changing
frequencies. Manual writes to the VCO switches are executed immediately as are writes to the integer and
fractional registers when AutoCal is disabled. Hence frequency changes with manual control and AutoCal
disabled, requires a minimum of two serial port transfers to the PLL, once to set the VCO switches, and
once to set the PLL frequency.
Product & Operating Guide
A
If AutoCal is disabled Reg 0Ah[11]=1, the VCO will update its registers with the value written via Reg 05h
immediately. The VCO internal transfer requires 16 VSCK clock cycles after writing Reg 05h. VSCK and
the AutoCal controller clock are both equal to the input reference divided by 0, 4,16 or 32 as controlled by
Reg 0Ah[14:13].
4.2.2.1 Registers required for Frequency Changes in Fractional Mode
A large change of frequency, in fractional mode (Reg 06h[11]=1), may require Main Serial Port writes to:
1. the integer register intg, Reg 03h (only required if the integer part changes)
2. the VCO SPI register, Reg 05h, (only required for manual control of VCO Reg 0Ah[11]=1) and
3. the fractional register frac, Reg 04h. The frac register write triggers AutoCal if Reg 0Ah[11]=0, and is
loaded into the modulator automatically after AutoCal runs. If AutoCal is disabled, Reg 0Ah[11]=1, the
fractional frequency change is loaded into the modulator immediately when the register is written with
no adjustment to the VCO.
Small steps in frequency in fractional mode, with AutoCal enabled (Reg 0Ah[11]=0), usually only require
a single write to the frac register. Worst case, 3 Main Serial Port transfers to the PLL with Integrated VCO
could be required to change frequencies in fractional mode. If the frequency step is small and the integer
part of the frequency does not change, then the integer register is not changed. In all cases, in fractional
mode, it is necessary to write to the frac register Reg 04h for frequency changes.
4.2.2.2 Registers Required for Frequency Changes in Integer Mode
A change of frequency, in integer mode (Reg 06h[11]=0), requires Main Serial Port writes to:
1. VCO SPI register, Reg 05h, (only required for manual control of VCO Reg 0Ah[11]=1) and
2. the integer register intg Reg 03h. In integer mode, an integer register write triggers AutoCal if
Reg 0Ah[11]=0, and is loaded into the prescaler automatically after AutoCal runs. If AutoCal is
disabled, Reg 0Ah[11]=1, the integer frequency change is loaded into the prescaler immediately when
written with no adjustment to the VCO. Normally changes to the integer register cause large steps
in the VCO frequency, hence the VCO switch settings must be adjusted. AutoCal enabled is the
recommended method for integer mode frequency changes. AutoCal disabled would require a priori
knowledge of the correct VCO switch setting, and the corresponding adjustment to the VCO, before
executing the integer frequency change.
4.2.3
VCO AutoCal on Frequency Change
Assuming Reg 0Ah[11]=0, the VCO calibration starts automatically whenever a frequency change is
requested. If it is desired to rerun the AutoCal routine for any reason, at the same frequency, simply rewrite
the frequency change with the same value and the AutoCal routine will execute again without changing
final frequency.
4.2.4
VCO AutoCal Time & Accuracy
The VCO frequency is counted for Tmmt, the period of a single AutoCal measurement cycle.
n
Tmmt = Txtal · R · 2
A - 11
(EQ 1)
n
is set by Reg 0Ah[2:0] and results in measurement periods which are multiples of the PD
period, TxtalR.
R
is the reference path division ratio currently in use, Reg 02h
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is the period of the external reference (crystal) oscillator.
The VCO AutoCal counter will, on average, expect to register N counts, rounded down (floor) to the nearest
integer, every PD cycle.
N
is the ratio of the target VCO frequency, fvco, to the frequency of the PD, fpd, where N can
be any rational number supported by the N divider.
N is set by the integer (Nint = Reg 03h) and fractional (Nfrac = Reg 04h) register contents
N = Nint + Nfrac / 2
24
(EQ 2)
The AutoCal state machine and the data transfers to the internal VCO subsystem SPI (VSPI) run at the rate
of the FSM clock, TFSM, where the FSM clock frequency cannot be greater than 50 MHz.
m
TFSM = Txtal · 2
m
(EQ 3)
is 0, 2, 4 or 5 as determined by Reg 0Ah[14:13]
The expected number of VCO counts, V, is given by
n
V = floor (N · 2 )
(EQ 4)
The nominal VCO frequency measured, fvcom, is given by
n
fvcom = V · fxtal / (2 · R)
(EQ 5)
where the worst case measurement error, ferr , is:
n+1
ferr ≈ ±fpd / 2
(EQ 6)
A
Product & Operating Guide
Txtal
Figure 9. VCO Calibration
A 5-bit step tuned VCO, for example, nominally requires 5 measurements for calibration, worst case
6 measurements, and hence 7 VSPI data transfers of 20 clock cycles each. The measurement has a
programmable number of wait states, k, of 120 FSM cycles defined by Reg 0Ah[7:6] = k. Hence total
calibration time, worst case, is given by:
n
Tcal = k120TFSM + 6TPD 2 + 7 · 20TFSM
(EQ 7)
or equivalently
n
m
Tcal = Txtal (6R · 2 + (140+120k) · 2 )
where k = Reg 0Ah[7:6] decimal
(EQ 8)
For guaranteed hold of lock, across temperature extremes, the resolution should be better than
1/8th the frequency step caused by a VCO sub-band switch change or ~ 800 kHz to 2.75 MHz depending
on the VCO subystem. Better resolution settings will show no improvement.
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4.2.4.1 VCO AutoCal Example
A
This is an example for a 2 GHz VCO subsystem. Other VCO subsystems at different frequencies will be
similar. Each VCO subsystem must satisfy the maximum fpd limited by the two following conditions:
a. N ≥ 16 (fint), N ≥ 20.0 (ffrac), where N = f VCO/ fpd
Product & Operating Guide
b. fpd ≤ 100 MHz
Check the PLL with Integrated VCO data sheet for the actual VCO subsystem being used.
Suppose our VCO subsystem output frequency is to operate at 1.01 GHz. Our example crystal frequency
is fxtal = 50 MHz, R=1, and m=0 (Figure 9), hence TFSM = 20 ns (50 MHz). Note, when using AutoCal, the
maximum AutoCal Finite State Machine (FSM) clock cannot exceed 60 MHz (see Reg 0Ah[14:13]). The
FSM clock does not affect the accuracy of the measurement, it only affects the time to produce the result.
This same clock is used to clock the 16 bit VCO serial port.
If time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy,
and therefore not be concerned with measurement resolution.
Using an input crystal of 50 MHz (R=1 and fpd=50 MHz) the times and accuracies for calibration using
(EQ 6) and (EQ 8) are shown in Table 2. Where minimal tuning time is 1/8th of the VCO band spacing.
Across all VCOs, a measurement resolution better than 800 kHz will produce correct results. Setting
m = 0, n = 5, provides 781 kHz of resolution and adds 9.04 µs of AutoCal time to a normal frequency hop.
Once the AutoCal sets the final switch value, 9.04 µs after the frequency change command, the fractional
register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics.
Hence we can see in this example that AutoCal typically adds about 9.04 µs to the normal time to achieve
frequency lock. Hence we should use AutoCal for all but the most extreme frequency hopping requirements.
Table 2. AutoCal Example with Fxtal = 50 MHz, R = 1, m = 0
4.3
Control Value
Reg0Ah[2:0]
n
2n
Tmmt
(µs)
Tcal
(µs)
Ferr Max
0
0
1
0.02
5.32
± 25 MHz
1
1
2
0.04
5.44
± 12.5 MHz
2
2
4
0.08
5.68
± 6.25 MHz
3
3
8
0.16
6.16
± 3.125 MHz
4
5
32
0.64
9.04
± 781 kHz
5
6
64
1.28
12.88
± 390 kHz
6
7
128
2.56
20.56
± 195 kHz
7
8
256
5.12
35.92
± 98 kHz
VCO Built in Test with AutoCal
The frequency limits of the VCO can be measured using the BIST features of the AutoCal machine.
This is done by setting Reg 0Ah[10]=1 which freezes the VCO switches in one position. VCO switches
may then be written manually, with the varactor biased at the nominal mid-rail voltage used for AutoCal.
For example to measure the VCO maximum frequency use switch 0, written to the VCO subsystem via
Reg 05h=[ 000000000 0000 VCOID]. Where VCOID = ‘000’ or ‘101’ depending on the particular product.
If AutoCal is enabled, (Reg 0Ah[11] = 0), and a new frequency is written, AutoCal will run, but with switches
frozen. The VCO frequency error relative to the command frequency will be measured and results written
to Reg 11h[19:0] where Reg 11h[19] is the sign bit. The result will be written in terms of VCO count error
(EQ 4). For example if the expected VCO is 1 GHz, reference is 50 MHz, and n is 6, we expect to measure
1280 counts. If we measure a difference of -5 counts in Reg 11h, then it means we actually measured 1275
counts. Hence the actual frequency of the VCO is 5/1280 low, or 996.09 MHz, ±1 Count = ±800 kHz.
A - 13
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Spurious Performance
4.4.1
Integer Operation and Reference Spurious
The VCO always operates at an integer multiple of the PD frequency in an integer synthesizer. In general
spurious signals originating from an integer synthesizer can only occur at multiples of the PD frequency.
These unwanted outputs closest to the carrier are often simply referred to as reference sidebands.
Unwanted reference harmonics can also exist far from the carrier due to circuit isolation.
Spurs unrelated to the reference frequency must originate from outside sources. External spurious sources
can modulate the VCO indirectly through power supplies, ground, or output ports, or bypass the loop filter
due to poor isolation of the filter. It can also simply add to the output of the synthesizer.
Reference spuri­ous levels are typically below -100 dBc with a well designed board layout. A regulator
with low noise and high power supply rejection, such as the HMC860LP3E, is recommended to minimize
external spurious sources.
Reference spurious levels of below -100 dBc require superb board isolation of power supplies, isolation of
the VCO from the digital switching of the synthesizer and isolation of the VCO load from the synthesizer.
Typical board layout, regulator design, eval boards and application information are available for very low
spurious operation. Operation with lower levels of isolation in the application circuit board, from those rec­
ommended by Hittite, can result in higher spurious levels.
Of course, if the application environment contains other interfering frequencies unrelated to the PD fre­
quency, and if the application isolation from the board layout and regulation are insufficient, then the
unwanted interfering frequencies will mix with the desired synthesizer output and cause additional spurious
emissions. The level of these emissions is dependant upon isolation and supply regulation or rejection
(PSRR).
4.4.2
Fractional Operation and Spurious
Unlike an integer synthesizer, spurious signals in a fractional synthesizer can occur due to the fact that
the VCO operates at frequencies unrelated to the PD frequency. Hence intermodulation of the VCO and
the PD harmonics can cause spurious sidebands. Spurious emissions are largest when the VCO operates
very close to an integer multiple of the PD. When the VCO operates exactly at a harmonic of the PD then,
no in-close mixing products are present.
A
Product & Operating Guide
4.4
As shown in Figure 10, interference is always present at multiples of the PD frequency, fpd, and the VCO
frequency, fvco. The difference, Δ, between the VCO frequency and the nearest har­monic of the reference,
will create what are referred to as integer boundary spurs. Depending upon the mode of operation of
the synthesizer, higher order, lower power spurs may also occur at multiples of integer fractions (subharmonics) of the PD frequency. That is, fractional VCO frequencies which are near nfpd + fpdd/m, where
n, d and m are all integers and d<m (mathematicians refer to d/m as a rational num­ber). We will refer to
fpdd/m as an integer fraction. The denominator, m, is the order of the spurious product. Higher values of
m produce smaller amplitude spurious at offsets of mΔ and usually when m>4 spurs are very small or
unmeasurable.
The worst case, in fractional mode, is when d=0, and the VCO frequency is offset from nfpd by less than
the loop bandwidth. This is the “in-band integer boundary” case.
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Product & Operating Guide
A
Figure 10. Fractional Spurious Example
Characterization of the levels and orders of these products is not unlike a mixer spur chart. Exact levels
of the products are dependent upon isolation of the various synthesizer parts. Hittite can offer guidance
about expected levels of spurious with our PLL and VCO application boards. Regulators with high power
supply rejection ratios (PSRR) are recommended, especially in noisy applications.
4.4.2.1 Charge Pump and Phase Detector Spurious Considerations
Charge pump and phase detector linearity are of paramount importance when operating in fractional
mode. Any non-linearity degrades phase noise and spurious performance.
We define zero phase error when the reference signal and the divider VCO signal arrive at the Phase
Detector at the same time. Phase detector linearity degrades when the phase error is very small and
when the random phase errors cause the phase detector to switch back an forth between reference lead
and VCO lead.
These switching non-linearities in fractional mode are eliminated by operating the phase detector with
an average phase offset such that either the reference or VCO always leads. A programmable charge
pump offset current source is used to add DC current to the loop filter and create the desired phase offset.
Positive current causes the VCO to lead, negative current causes the reference to lead.
The offset charge pump is controlled via Reg 09h. The phase offset is scaled from 0 degrees, that is the
reference and the VCO path arrive in phase, to 360 degrees, where they arrive a full cycle late. The offset
can also be thought of in absolute time difference between the arrivals.
The recommended operating point for the charge pump in fractional mode is one where the time offset at
the phase detector is ~2.5ns + 4TVCO, where TVCO is the RF period at the fractional prescaler input.
The specific level of charge pump offset current Reg 09h[20:14] is determined by this time offset, the
comparison frequency and the charge pump current:
Required CP Offset = (2.5 ∙ 10 -9+ 4TVCO)(sec) ∙ (Fcomparison) ∙ ICP
where:
TVCO: is the RF period at the fractional prescaler input
ICP: is the full scale current setting of the switching charge pump Reg 09h[6:0] Reg 09h[13:7]
(EQ 9)
Charge Pump Offset Leakage current should never be more than 25% of the programmed Charge Pump
A - 15
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Operation with charge pump offset influences the required configuration of the Lock Detect function. Refer
to the description of Lock Detect function in section 4.11. Note that this calculation can be performed for
the center frequency of the VCO, and does not need refinement for small differences < 25 % in center
frequencies.
Another factor in the spectral performance in Fractional Mode is the choice of the Delta-Sigma Modulator
mode. Mode A can offer better in-band spectral performance (inside the loop bandwidth) while Mode B
offers better out of band performance. See “Reg 06h”[3:2] for DSM mode selection. Finally, all fractional
synthesizers cre­ate fractional spurs at some level. Hittite offers the lowest level fractional spurious in the
indus­try in an integrated solution.
4.4.2.2 Spurious Related to Channel Step Size (Channel Spurs)
Many fractional PLLs also create spurious emissions at offsets which are multiples of the channel step
size. We refer to these as Channel Spurs. It is common in the industry to set the channel step size by use
of the so-called modulus. For example, channel step size of 100 kHz requires a small modulus related to
the step size, and often results in 100 kHz Channel Spurs.
All Hittite fractional PLLs use a large fixed modulus unrelated to the channel step size. As a result, Hittite
PLLs have extremely low or unmeasurable Channel Spurs. In addition Exact Frequency Mode (4.12.2.2)
allows exact channel step size with no Channel Spurs.
The lack of Channel Spurs means that Hittite PLL VCOs have large regions of operation between Integer
Boundaries with little or no spurs of any kind. Large spurious free zones enable HIttite PLLs to be used
with a tunable reference, to effectively move the spur free zones and hence achieve spur-free operation at
all frequencies. The resulting PLL is virtually spur-free at all frequencies.
For more information see 4.4.2.3.
4.4.2.3 Spurious Reduction with Tunable Reference
A
Product & Operating Guide
current. When using high comparison frequencies, >50MHz, during frequency changes, it may be
necessary to momentarily disable the Charge Pump Offset Leakage current, initiate the frequency change,
allow the PLL to lock, and then re-enable the Charge Pump Offset Leakage current.
Section 4.4.2 discussed fractional mode Integer Boundary spurious caused by VCO operation near
reference harmonics. It is possible, with Hittite fractional synthesizers, to virtually eliminate the integer
boundary spurious at a given VCO frequency by changing the frequency of the reference. The reference
frequency is normally generated by a crystal oscillator and is not tunable. However, Hittite wideband PLLs
with Integrated VCOs can be used as a high-quality tunable reference source, as shown in Figure 11.
Figure 11. Tunable reference source
With the setup shown in Figure 11, Hittite PLLs are capable of operating at all frequencies supported by
the output VCO without sacrificing phase noise, while virtually eliminating spurious emissions. Optimum
operation requires appropriate configuration of the two synthesizers to achieve this performance. Hittite
apps-support can assist with the required algorithms for ultra-low spurious tunable reference applications.
An PLLVCO Operating Guide tunable reference PLL typically uses a high frequency crystal reference for
best performance. Phase noise from the PLLVCO Operating Guide tunable reference output at 100 kHz
offset varies typically from -145 dBc at 100 MHz output to -157 dBc at 25 MHz output. This perfromance
of PLLVCO Operating Guide as a tunable reference is equivalent to the phase noise of high performance
crystal oscillators.
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-120
A
Carrier Frequency = 25 MHz
Carrier Frequency = 55.55 MHz
Carrier Frequency = 100 MHz
Product & Operating Guide
PHASE NOISE (dBc/Hz)
-130
-140
-150
-160
-170
0.1
1
10
100
1000
10000
100000
OFFSET (kHz)
Figure 12. Phase noise performance of the HMC830LP6GE when used
as a tunable reference source. (HMC830LP6GE operating at 3
GHz/30, 3 GHz/54, and 1.55 GHz/62 for the 100 MHz, 55.55 MHz,
and 25 MHz curves respectively.)
Worst case spurious levels (largest spurs at any offset) of conventional fixed reference vs. a tunable
reference can be compared by multiple individual phase noise measurements and summarized on a single
plot vs. carrier frequency.
For example, Figure 13 shows the spectrum of a carrier operating at 2000.1 MHz with a 50 MHz fixed
reference. This case is 100 kHz away from an Integer Boundary (50 MHz x 40). Worst case spurious can
be observed at 100 kHz offset and about -52 dBc in magnitude.
Figure 14 shows the same PLLVCO Operating Guide PLL VCO operating at the same 2000.1 MHz carrier
frequency, using a tunable reference at 47.5 MHz generated by a second PLLVCO Operating Guide. Worst
case spurious in this case can be observed at 5.1 MHz offset and about -100 dBc in magnitude.
The results of Figure 13 and Figure 14 show that the tunable reference source achieves 50 dB better
spurious performance, while maintaining essentially the same phase noise performance.
0
0
2000.1 MHz Carrier frequency
(A)
-40
PHASE NOISE (dBc/Hz)
-20
-60
Worst spur at 100 kHz offset
at ~-52 dBc with 50 MHz
crystal
-80
-100
-120
Worst spur at 5.1 MHz offset
at -100 dBc with tunable
crystal
-60
-80
-100
(B)
-120
-140
-140
-160
-160
-180
-180
0.1
2000.1 MHz Carrier frequency
-40
PHASE NOISE (dBc/Hz)
-20
1
10
100
1000
10000
100000
OFFSET (kHz)
Figure 13. PLLVCO Operating Guide Worst spur at
any offset, fixed 50 MHz reference, output frequency
= 2000.1 MHz
0.1
1
10
100
1000
10000
100000
OFFSET (kHz)
Figure 14. PLLVCO Operating Guide worst
spur at any offset, tunable reference (another
PLLVCO Operating Guide), output frequency =
Many spurious measurements, such as the ones in Figure 13 and Figure 14 can be summarized into a
single plot of worst case spurious at any offset vs. carrier frequency as shown in Figure 15. A log frequency
display relative to the 2000 MHz fixed reference Integer Boundary was used to emphasize the importance
of the loop bandwidth on spurious performance of the fixed reference case. This technique clearly shows
the logarithmic roll-off of the worst case spurious when operating near the Integer Boundary. In this case
the loop filter bandwidth of the HMC830LP6GE was 100 kHz.
A - 17
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(A)
WORST SPUR (dBc)
-60
(B)
-70
-80
Fixed 50 MHz Reference
Tunable Reference
-90
-100
-110
-120
2GHz +1kHz
2GHz +10kHz
2GHz +100kHz
2GHz +1000kHz
2GHz +10000kHz
OUTPUT FREQUENCY
Figure 15. Largest observed spurious, at any offset, using a fixed 50
MHz reference source and a tunable reference source.
For example worst case spurious operating at 2000.1 MHz (point (A)) in Figure 13 with a fixed 50 MHz
reference) is represented by a single point in Figure 15 (point (A)) on the blue curve. Similarly, worst case
spurious from Figure 14 with variable reference, operating at 2000.1 MHz is represented by a single point
in Figure 15 (point (B)) on the green curve.
The plot in Figure 15 is generated by tuning the carrier frequency away from Integer Boundary and
recording the worst case spurious, at any offset, at each operating frequency. Figure 15 shows that the
worst case spurious for the 50 MHz fixed reference case, is nearly constant between -51 dBc and -55
dBc when operating with a carrier frequency less than 100 kHz from the Integer Boundary (blue curve).
It also shows that the worst case spurious rolls off at about 25 dB/decade relative to 1 loop bandwidth.
For example, at an operating frequency of 2001 MHz (equivalent to 10 loop bandwidths offset) worst case
spurious is -80 dBc. Similarly, at an operating frequency of 2010 MHz (equivalent to 100 loop bandwidths)
worst case spurious is -100 dBc.
In contrast, the green curve of Figure 15 shows that the worst case spurious over the same operating
frequency range, when using an HMC830LP6GE tunable reference, is below -100 dBc at all operating
frequencies!
A
Product & Operating Guide
-50
In general all fractional PLLs have spurious when operating near Integer Boundaries. High performance
tunable reference makes it possible to operate a Hittite fractional PLL, virtually spur-free at all frequencies,
with little or no degradation in phase noise.
4.5
Integrated Phase Noise & Jitter
The standard deviation of VCO signal jitter may be estimated with a simple approximation if we assume
that the locked VCO has a constant phase noise, o| 2(fo), at offsets less than the loop 3 dB bandwidth and a
20 dB per decade roll-off at greater offsets. The simple locked VCO phase noise approximation is shown
on the left of Figure 16.
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Product & Operating Guide
A
Figure 16. PLL with Integrated VCO Phase Noise & Jitter
With this simplification the total integrated VCO phase noise, o| 2, in rads2 in the linear form is given by
o| 2 = o| 2 (f
) Bπ
(EQ 10)
o
where o| 2 (fo) is the single sideband phase noise in rads2 /Hz inside the loop bandwidth, and B is the 3 dB corner frequency of the closed loop PLL
The integrated phase noise at the phase frequency detector, o| 2pd
o| 2
pd
is just scaled by N2
= o| 2 /N2
(EQ 11)
The rms phase jitter of the VCO in rads, o| , is just the square root of the phase noise integral.
Since the simple integral of (EQ 10) is just a product of constants, we can easily do the integral in the log
domain. For example if the VCO phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop
bandwidth is 100 kHz, and the division ratio is 100, then the integrated phase noise at the phase frequency
detector, in dB, is given by:
2
o| pddB
= 10log ( o| 2 (fo)Bπ/N2) = -100 + 50 + 5 - 40 = -85 dBc
or equivalently, o| = 10 -85/20 = 53.6e-6 rads = 3.2e-3 degrees.
While the phase noise reduces by a factor of 20logN after division to the reference, due to the increased
period of the PD reference signal, the jitter is constant.
The rms jitter from the phase noise is then given by
Tjpn = Tpdo| pd/2π
(EQ 12)
In this example if the PD reference was 50 MHz, Tpd = 20ns, and hence Tjpn = 179 femto-sec.
It should be noted that this last expression is based upon a closed form integral of the entire spectrum of
the oscillator phase noise. This integral starts at DC. It is common for real system to evaluate jitter over
shorter intervals of time, hence the integral often starts at some finite frequency offset and will produce a
jitter that is less than that given by the full expression. Finally real oscillators have noise floors that also
contribute to jitter. The phase noise of a white noise floor is a simple integral of noise floor density times
bandwidth of interest to the system. This additional noise power should be added to the expression of
(EQ 16) to give a more accurate jitter number. Depending upon the bandwidth of the system in question
this noise floor contribution may be an important factor.
A - 19
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Reference Input Stage
A
Figure 17. Reference Path Input Stage
The reference buffer provides the path from an external reference source (generally crystal based) to
the R divider, and eventually to the phase detector. The buffer has two modes of operation controlled by
Reg 08h[21]. High Gain (Reg 08h[21] = 0), recommended below 200 MHz, and High frequency (Reg 08h[21]
= 1), for 200 to 350 MHz operation. The buffer is internally DC biased, with 100 Ω internal termination. For
50 Ω match, an external 100 Ω resistor to ground should be added, followed by an AC coupling capacitor
(impedance < 1 Ω), then to the XREFP pin of the part.
At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher
frequencies, a square or sinusoid can be used. The following table shows the recommended operating
regions for different reference frequencies. If operating outside these regions the part will normally still
operate, but with degraded reference path phase noise performance.
Minimum pulse width at the reference buffer input is 2.5 ns. For best spur performance when R = 1, the
pulse width should be (2.5ns + 8TPS), where TPS is the period of the VCO at the prescaler input. When R >
1 minimum pulse width is 2.5 ns.
Product & Operating Guide
4.6
Table 3. Reference Sensitivity Table
Square Input
Reference Input
Frequency
(MHz)
Slew > 0.5V/ns
Recommended
Sinusoidal Input
Recommended Swing (Vpp)
Min
Max
Recommended Power Range (dBm)
Recommended
Min
Max
< 10
YES
0.6
2.5
x
x
x
10
YES
0.6
2.5
x
x
x
25
YES
0.6
2.5
ok
8
15
15
50
YES
0.6
2.5
YES
6
100
YES
0.6
2.5
YES
5
15
150
ok
0.9
2.5
YES
4
12
200
ok
1.2
2.5
YES
3
8
Note: Reference frequency < 10 MHz is not supported by all products. See individual datasheets for more information.
Input referred phase noise of the PLL when operating at 50 MHz is between -150 and -156 dBc/Hz at
10 kHz offset depending upon the mode of operation. The input reference signal should be 10 dB better
than this floor to avoid deg­radation of the PLL noise contribution. It should be noted that such low levels
are only necessary if the PLL is the dominant noise contributor and these levels are required for the system
goals.
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4.7
Product & Operating Guide
A
Reference Path ’R’ Divider
The reference path “R” divider is based on a 14-bit counter and can divide input signals by values from 1
to 16,383 and is controlled by rdiv (Reg 02h).
Minimum pulse width at the reference buffer input is 2.5 ns. For best spur performance when R = 1, the
pulse width should be (2.5ns + 8Tps), where Tps is the period of the VCO at the prescaler input. When R
> 1 minimum pulse width is 2.5ns.
4.8
RF Path ’N’ Divider
The main RF path divider is capable of average divide ratios between 219-5 (524,283) and 20 in fractional
mode, and 219-1 (524,287) to 16 in integer mode. The VCO frequency range divided by the minimum N
divider value will place practical restrictions on the maximum usable PD frequency. For example a VCO
operating at 1.5 GHz in fractional mode with a minimum N divider value of 20 will have a maximum PD
frequency of 75 MHz. Please refer to the data sheet of the PLL with Integrated VCO for the applicable
limits.
4.9
Charge Pump & Phase Detector
The Phase detector (PD) has two inputs, one from the reference path divider and one from the RF path
divider. When in lock these two inputs are at the same average frequency and are fixed at a constant
average phase offset with respect to each other. We refer to the frequency of operation of the PD as
fpd. Most formula related to step size, delta-sigma modulation, timers etc., are functions of the operating
frequency of the PD, fpd. fpd is also referred to as the comparison frequency of the PD.
The PD compares the phase of the RF path signal with that of the reference path signal and controls the
charge pump output current as a linear function of the phase difference between the two signals. The
output current varies linearly over a full ±2π radians (±360°) of input phase difference.
4.10
Phase Detector Functions
Phase detector register Reg 0Bh allows manual access to control special phase detector features.
PD_up_en (Reg 0Bh[5]), if 0, masks the PD up output, which prevents the charge pump from pumping up.`
PD_dn_en (Reg 0Bh[6]), if 0, masks the PD down output, which prevents the charge pump from pumping
down.
Clearing both PD_up_en and PD_dn_en effectively tri-states the charge pump while leaving all other
functions operating internally.
PD Force UP Reg 0Bh[9] and PD Force DN Reg 0Bh[10] allows the charge pump to be forced up or down
respectively. This will force the VCO to the ends to the tuning range which can be useful in test of the VCO.
4.11
Phase Detector Window Based Lock Detect
Lock Detect Enable Reg 07h[3]=1 is a global enable for all lock detect functions.
The window based Lock Detect circuit effectively measures the difference between the arrival of the
reference and the divided VCO signals at the PD. The arrival time difference must consistently be less
than the Lock Detect window length, to declare lock. Either signal may arrive first, only the difference in
arrival times is counted.
4.11.1 Analog Window Lock Detect
The lock detect window may be generated by either an analog one shot circuit or a digital one shot based
upon an internal timer. Clearing Reg 07h[6]=0 will result in a fixed, analog, nominal 10 ns window, as
shown in Figure 18. The analog window cannot be used if the PD rate is above 50 MHz, or if the offset is
too large.
A - 21
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Figure 18. Normal Lock Detect Window - Integer Mode, Zero Offset
For example a 25 MHz PD rate with a 1 mA charge pump setting (Reg 09h[6:0]=Reg 09h[13:7]= 32h) and
a - 400 µA leakage (Reg 09h[20:14]=50h Reg 09h[22]= 1), would have an offset of about 400/1000 = 40%
of the PD period or about 16 ns. In such an extreme case the divided VCO would arrive 16 ns after the PD
reference, and would always arrive outside of the 10 ns lock detect window. In such a case the lock detect
circuit would always read unlocked, even though the VCO might be locked. When using the 10 ns analog
lock detect window, with a 40 ns PD period, the offset must always be less than 25% of the charge pump
setting, 20% to allow for tolerances. Hence a 1 mA charge pump setting can not use more than 200 µA
offset with a 25 MHz PD and an analog Lock detect window. Hence charge pump current, charge pump
offset, phase detector rate and lock detect window are related.
4.11.2 Digital Window Lock Detect
Setting Reg 07h[6]=1 will result in a variable length lock detect window based upon an internal digital timer.
The timer period is set by the number of cycles of the internal LD clock as programmed by Reg 07h[9:7].
The LD clock frequency is adjustable by Reg 07h[11:10]. The LD clock signal can be viewed via the GPO
test pins. Refer 4.16 for details.
Product & Operating Guide
A
4.11.3 Declaration of Lock
wincnt_max in Reg 07h[2:0] defines the number of consecutive counts of the divided VCO that must land
inside the lock detect window to declare lock. If for example we set wincnt_max = 2048, then the VCO
arrival would have to occur inside the window 2048 times in a row to be declared locked, which would
result in a Lock Detect Flag high. A single occurrence outside of the window will result in an out of lock, i.e.
Lock Detect Flag low. Once low, the Lock Detect Flag will stay low until the wincnt_max = 2048 condition
is met again.
The Lock Detect Flag status is always readable in Reg 12h[1], if locked = 1. Lock Detect status is also
output to the LD_SDO pin according to Reg 0Fh[4:0]=1. Again, if locked, LD_SDO will be high. Clearing
Reg 0Fh[6]=0 will display the Lock Detect Flag on LD_SDO except when a serial port read is requested, in
which case the pin reverts temporarily to the Serial Data Out pin, and returns to the Lock Detect Flag after
the read is completed. Refer to 4.11.5 for Timing of the Lock Detect information.
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4.11.4 Phase Offset & Fractional Linearity
Product & Operating Guide
A
When operating in fractional mode the linearity of the charge pump and phase detector are much more
critical than in integer mode. The phase detector linearity is degraded when operated with zero phase
offset. Hence in fractional mode it is necessary to offset the phase of the PD reference and the VCO at the
phase detector. In such a case, for example with an offset delay, as shown in Figure 19, the VCO arrival
will always occur after the reference. The lock detect circuit window may need to be adjusted to allow for
the delay being used.
Figure 19. Lock Detect Window - Fractional Mode with Offset
4.11.5 Digital Lock Detect with Digital Window Example
Typical Digital Lock detect window widths are shown in Table 3. Lock Detect windows typically vary ±10%
vs voltage and ±15% over temperature (-40°C to +85°C).
Table 4. Typical Digital Lock Detect Window
LD Timer Speed
Reg07[11:10]
Digital Lock Detect Window
Nominal Value ±25% (ns)
Fastest 00
6.5
8
11
17
29
53
100
195
01
7
8.9
12.8
21
36
68
130
255
10
7.1
9.2
13.3
22
38
72
138
272
Slowest 11
7.6
10.2
15.4
26
47
88
172
338
LD Timer Divide Setting
Reg07[9:7]
0
1
2
3
4
5
6
7
LD Timer
Divide Value
0.5
1
2
4
8
16
32
64
As an example, if we operate in fractional mode at 2GHz with a 50MHz PD, charge pump gain of 2mA and
a down leakage of 400uA. Then our average offset at the PD will be 0.4mA/2mA = 0.2 of the PD period
or about 4ns (0.2 x 1/50MHz). However, the fractional modulation of the VCO divider will result in time
excursions of the VCO divider output of +/-4Tvco from this average value (2ns in this example). Hence
when in lock, the divided VCO will arrive at the PD about 4 +/-2ns after the divided reference. The Lock
Detect window always starts on the arrival of the first signal at the PD, in this case the reference. The Lock
Detect window must be longer than 4ns+2ns (6ns) and shorter than the period of the PD, in this example,
20ns. A perfect Lock Detect window would be midway between these two values, or 13ns.
Tolerance on the window is +25% at +85 °C, -25% at -40 °C. Here 13ns nominal window may extend
by +25% at +85°C to 16 ns, which is fine for a PD period of 20 ns. Also the minimum window may be 9.75ns
at -40°C, which again works well for the worst case offset of 6 ns.
A - 23
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Figure 20. Lock Detect Window Example with 50 MHz PD and 4ns VCO Offset
There is always a good solution for the lock detect window for a given operating point. The user should
understand however that one solution does not fit all operating points. If charge pump offset or PD frequency
are changed significantly then the lock detect window may need to be adjusted.
4.11.6 Cycle Slip Prevention (CSP)
When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneous
frequencies of the two PD inputs are different, and the phase difference of the two inputs at the PD varies
rapidly over a range much greater than ±2π radians. Since the gain of the PD varies linearly with phase
up to ±2π, the gain of a conventional PD will cycle from high gain, when the phase difference approaches
a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. The
output current from the charge pump, shown in the middle curve in Figure 21, will cycle from maximum to
minimum even though the VCO has not yet reached its final frequency.
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the
cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena is
known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically,
as shown in the top plot in Figure 21. Cycle Slipping increases the time to lock to a value much greater than
that predicted by normal small signal Laplace analysis.
Product & Operating Guide
A
The synthesizer PD features an ability to reduce cycle slipping during acquisition. The Cycle Slip Preven­
tion (CSP) feature increases the PD gain during large phase errors. The specific phase error that triggers
the momentary increase in PD gain is set via Reg 0Bh[8:7].
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Product & Operating Guide
A
Figure 21. Cycle Slip Prevention (CSP)
4.11.7 Charge Pump Gain
A simplified diagram of the charge pump is shown in Figure 22. Charge pump Up and Down gains are set
by CP DN Gain and CP UP Gain respectively (Reg 09h[6:0] and [13:7]). The current gain of the pump in
Amps/radian is equal to the gain setting of this register divided by 2π.
For example if both CP DN Gain and CP UP Gain are set to ‘50d’ the output current of each pump will be 1
mA and the phase frequency detector gain kp = 1 mA/2π radians, or 159 µA/rad. See section 4.4 for more
information.
4.11.8 Charge Pump Phase Offset - Fractional Mode
In integer mode, the phase detector operates with zero offset, that is the divided reference signal and the
divided VCO signal arrive at the phase detector inputs at the same time. In fractional mode of operation,
charge pump linearity and ultimately, phase noise, is much better if the VCO and reference inputs are
operated with a phase offset. A phase offset is implemented by adding a constant DC offset current at the
output of the charge pump.
DC offset may be added to the UP or DN switching pumps using Leak Magnitude and one of LK Direction
DN or LK Direction UP (Reg 09h[21] or Reg 09h[22]). Offset Magnitude, Reg 09h[20:14] is a 7-bit register
with 5 µA LSB. Maximum offset is 635 µA. Down offset is highly recommended in fractional mode of
operation. Integer mode of operation works best with zero offset.
As an example, a PD comparison of fPD = 50 MHz (20 ns period) with the main pump gain set at 2 mA, and
a down (DN) offset of -385 µA would represent a phase offset of about (-385/2000)*360 = -69 degrees.
This is equivalent to the divided VCO arriving 3.8 ns after the reference at the PD input. It is critical that
phase offset be used in fractional mode. Normally, down offsets larger than 3 ns are typical.
Should charge pump gain be changed, for example to compensate for changes in VCO sensitivity, then
it is recommended to change the charge pump offset proportionally to maintain a constant phase offset.
A - 25
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Figure 22. Charge Pump Gain & Offset Control
4.12
Frequency Tuning
Frequency tuning will depend upon the actual VCO subsystem in use. The VCO will naturally restrict the
available range of operating frequencies.
Different VCO subsystems have different output modes offering one (or more for multi-mode devices) of
the following:
Fundamental (fo) output at the VCO frequency;
Doubler (2fo) output at twice the VCO frequency;
Divider (fo/2) output at half the VCO frequency;
Wideband VCO with outputs at fo or divided by any even number from 2 to 64;
In all cases, the PLL operates at the VCO’s fundamental frequency. Refer to the individual PLL with
Integrated VCO product data sheet for product specifics.
Product & Operating Guide
A
In general the VCO control of the internal fundamental frequency is done automatically when frequency
registers are programmed (please AutoCal).
Depending on the VCO subsystem type, the output frequencies can be divided or multiplied versions of
the internal fundamental VCO frequency. In general frequency tuning is always done at the fundamental
frequency. The divider output control is programmed separately by the user. Doubler outputs, for tri-band
and wide-band parts, are configured via PCB board connections.
4.12.1 Integer Mode
The PLL with Integrated VCO is capable of operating in integer mode. For Integer mode set the following
registers
a. disable the Fractional Modulator, Reg 06h[11]=0
b. bypass the Modulator circuit, Reg 06h[7]=1
In integer mode the VCO step size is fixed to that of the PD frequency, fpd. Integer mode typically has lower
phase noise than fractional mode for a given PD operating frequency. The advantage is usually of the order
of 2 to 3 dB. Integer mode, however, often requires a lower PD frequency to meet step size requirements.
The fractional mode advantage is that higher PD frequencies can be used, hence lower phase noise can
often be realized in fractional mode. Charge Pump offset should be disabled in integer mode.
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4.12.1.1Integer Frequency Tuning
Product & Operating Guide
A
In integer mode the digital Δ∑ modulator is shut off and the N (Reg 03h) divider may be programmed to any
integer value in the range 16 to 219-1. To run in integer mode configure Reg 06h as described, then program
the integer portion of the frequency as explained by (EQ 13), ignoring the fractional part.
a. Disable the Fractional Modulator, Reg 06h[11] = 0
b. Bypass the Modulator circuit Reg 06h[7] = 1
4.12.2 Fractional Mode
The PLL with Integrated VCO is placed in fractional mode by setting the following registers:
a. Enable the Fractional Modulator, Reg 06h[11]=1
b. Connect the Modulator in circuit, Reg 06h[7]=0
4.12.2.1Fractional Frequency Tuning
This is a generic example, with the goal of explaining how to program the output frequency. Actual variables
are dependant upon the VCO subsystem and reference in use.
The PLL with Integrated VCO in fractional mode can achieve frequencies at fractional multiples of the
reference. The frequency of the PLL with Integrated VCO, fvco, is given by
fvco =
fxtal
R
(Nint + Nfrac) = fint + ffrac
fout = fvco / k
(EQ 13)
(EQ 14)
Where:
fout
is the output frequency after any potential dividers or doublers.
k
is 0.5 for doubler, 1 for fundamental, or k = 1,2,4,6,…58,60,62 according to the
VCO Subsystem type
Nint
is the integer division ratio, Reg 03h, an integer number between 20 and
524,284
Nfrac
is the fractional part, from 0.0 to 0.99999...,Nfrac=Reg 04h/224
R
is the reference path division ratio, Reg 02h
fxtal
is the frequency of the reference oscillator input
fpd
is the PD operating frequency, fxtal /R
As an example, suppose the VCO subsystem in use supports a divide-by-2 mode:
fout
A - 27
1002.5 MHz (dependant on the VCO range and VCO subsystem
type in use)
k2
fvco
2,005 MHz
fxtal
= 50 MHz
R
=1
fpd
= 50 MHz
Nint
= 40
Nfrac
= 0.1
Reg 04h
= round(0.1 x 224) = round(1677721.6) = 1677722
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f VCO =
50e6
1
fout =
(40 +
f VCO
2
1677722
224
) = 2005 MHz + 1.2 Hz error
= 1002.5 MHz + 0.6 Hz error
(EQ 15)
(EQ 16)
In this example the output frequency of 1002.5 MHz is achieved by programming the 19-bit binary
value of 40d = 28h = 000 0000 0000 0010 1000 into intg_reg in Reg 03h, and the 24-bit binary value of
1677722d = 19999Ah = 0001 1001 1001 1001 1001 1010 into frac_reg in Reg 04h. The 0.6 Hz quantization
error can be eliminated using the exact frequency mode if required. In this example the output fundamental
is divided by 2. Specific control of the output divider is required. See section 6.0 and description for more
details.
4.12.2.2Exact Frequency Tuning
Due to quantization effects, the absolute frequency precision of a fractional PLL is normally limited by
the number of bits in the fractional modulator. For example, a 24 bit fractional modulator has frequency
resolution set by the phase detector (PD ) comparison rate divided by 224. The value 224 in the denominator
is sometimes referred to as the modulus. Hittite PLLs use a fixed modulus which is a binary number. In
some types of fractional PLLs the modulus is variable, which allows exact frequency steps to be achieved
with decimal step sizes. Unfortunately small steps using small modulus values results in large spurious
outputs at multiples of the modulus period (channel step size). For this reason Hittite PLLs use a large
fixed modulus. Normally the step size is set by the size of the fixed modulus. In the case of a 50 MHz PD
rate, a modulus of 224 would result in a 2.98 Hz step resolution, or 0.0596 ppm. In some applications it is
necessary to have exact frequency steps, and even an error of 3 Hz cannot be tol­erated.
Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be
exactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common
frequencies cannot be exactly represented. For example, Nfrac = 0.1 = 1/10 must be approximated as
round((0.1 x 224)/ 224 ) ≈ 0.100000024. At fPD = 50 MHz this translates to 1.2 Hz error. Hittite’s exact frequency
mode addresses this issue, and can eliminate quantization error by programming the channel step size to
FPD/10 in Reg 0Ch to 10 (in this example). More generally, this feature can be used whenever the desired
frequency, f VCO, can be exactly represented on a step plan where there are an integer number of steps
(<214)
across
integer-N
boundaries.
Mathematically,
this
situation
is
satisfied
if:
=
mod  fgcd 
VCOk


f

fPD 
14 
2


0=
where fgcd gcd(fVCO1, fPD ) and fgcd ≥ 
A
Product & Operating Guide
(EQ 17)
Where:
gcd stands for Greatest Common Divisor
fN = maximum integer boundary frequency < f VCO1
fPD = frequency of the Phase Detector
and f VCOk are the channel step frequencies where 0 < k < 224-1, As shown in Figure 23.
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Product & Operating Guide
A
Figure 23. Exact Frequency Tuning
Some fractional PLLs are able to achieve this by adjusting (shortening) the length of the Phase Accumulator
(the denominator or the modulus of the Delta-Sigma modulator) so that the Delta-Sigma modulator phase
accumulator repeats at an exact period related to the interval frequency (f VCOk - f VCO(k-1)) in Figure 23.
Consequently the shortened accumulator results in more frequent repeating patterns and as a result often
leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of
f VCOk - f VCO(k-1). For example, in some applications, these intervals might represent the spacing between
radio channels, and the spurious would occur at multiples of the channel spacing.
The Hittite method on the other hand is able to generate exact frequencies between adjacent integer-N
boundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency
steps with a high phase detector comparison rate, which allows Hittite PLLs to maintain excellent phase
noise and spurious performance in the Exact Frequency Mode.
4.12.2.3.3
Using Hittite Exact Frequency Mode
If the constraint in (EQ 17) is satisfied, Hittite PLL is able to generate signals with zero frequency error at
the desired VCO frequency. Exact Frequency Mode may be re-configured for each target frequency, or be
set-up for a fixed fgcd which applies to all channels.
4.12.2.4.4
Configuring Exact Frequency Mode For a Particular Frequency
1. Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO/fPD), where the
floor function is the rounding down to the nearest integer. Then the integer boundary frequency
fN = NINT ∙ fPD
2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd, where
fgcd = gcd(f VCO,fPD)
 24


3. Calculate and program the fractional register setting Reg =
04h N=
FRAC ceil 


is the ceiling function meaning “round up to the nearest integer.”
2
( fVCO − fN ) 
fPD
,


where ceil
Example: To configure HMC PLL for exact frequency mode at f VCO = 2000.2 MHz where Phase Detector
(PD) rate fPD = 61.44 MHz Proceed as follows:
Check (EQ 17) to confirm that the exact frequency mode for this f VCO is possible.
A - 29
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



)
(
fgcd =gcd 2000.2 × 106 ,61.44 × 106 =40 × 103 >
61.44 × 106
=3750
214
Since (EQ 17) is satisfied, Hittite PLL can be configured for exact frequency mode at
f VCO = 2000.2 MHz as follows:
f
4. NINT = Reg 03h = floor 
 2000.2 × 106 
 32
=
=
d 20h
 61.44 × 106 



VCO

=
floor 
 fPD 


5. Reg 0Ch =
fPD
61.44 × 106
61.44 × 106
=
=
= 1536
=
d 600h
40000
gcd ( fVCO , fPD ) gcd 2000.2 × 106 ,61.44 × 106
)
(
6. To program Reg 04h, the closest integer-N boundary frequency fN that is less than the
desired VCO frequency f VCO must be calculated. fN = fPD ∙ NINT. Using the current example:
fN =fPD × NINT =32 × 61.44 × 106 =1966.08 MHz.
(
)
 24
 224 f

2000.2 × 106 − 1966.08 × 106 
2
VCO − fN 
=
ceil 
=
=
d 8E2 AABh
 9317035

fPD
61.44 × 106








(
Then=
Reg04h ceil 
4.12.2.5.5
)
Hittite Exact Frequency Channel Mode
If it is desirable to have multiple, equally spaced, exact frequency channels that fall within
the same interval (ie. fN ≤ f VCOk < fN+1) where f VCOk is shown in Figure 23 and 1 ≤ k ≤ 214,
it is possible to maintain the same integer-N (Reg 03h) and exact frequency register (Reg 0Ch) settings
and only update the fractional register (Reg 04h) setting. The Exact Frequency Channel Mode is possible
if (EQ 17) is satisfied for at least two equally spaced adjacent frequency channels, i.e. the channel step
size.
To configure Hittite PLL for Exact Frequency Channel Mode, initially and only at the beginning, integer
(Reg 03h) and exact frequency (Reg 0Ch) registers need to be programmed for the smallest fVCO frequency
(f VCO1 in Figure 23), as follows:
A
Product & Operating Guide
 fPD
 214

=
fgcd gcd(fVCO , fPD ) and fgcd ≥ 
1. Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO1/fPD), where f VCO1 is
shown in Figure 23 and corresponds to minimum channel VCO frequency. Then the lower integer
boundary frequency is given by fN = NINT ∙ fPD.
2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd,
where fgcd = gcd((f VCOk+1 - f VCOk),fPD) = greatest common divisor of the desired equidistant channel
spacing and the PD frequency ((fVCOk+1 - f VCOk) and fPD).
Then, to switch between various equally spaced intervals (channels) only the fractional register (Reg 04h)
needs to be programmed to the desired VCO channel frequency f VCOk in the following manner:
(
)
 224 f

VCOk − fN 

f


PD



Reg 04h = NFRAC = ceil 
where fN = floor(f VCO1/fPD), and f VCO1, as shown in Figure 23, represents
the smallest channel VCO frequency that is greater than fN.
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Product & Operating Guide
A
Example: To configure Hittite PLL for Exact Frequency Mode for equally spaced intervals of 100 kHz
where first channel (Channel 1) = f VCO1 = 2000.200 MHz and Phase Detector (PD) rate fPD = 61.44 MHz
proceed as follows:
First check
that the exact frequency mode for this f VCO1 = 2000.2 MHz (Channel 1)
and f VCO2 = 2000.2 MHz + 100 kHz = 2000.3 MHz (Channel 2) is possible.
 fPD
 214


f
 and=
fgcd 2 gcd(fVCO2 , fPD ) and fgcd 2 ≥  PD

 214


=
fgcd1 gcd(fVCO1, fPD ) and fgcd1 ≥ 
)
(
=gcd ( 2000.3 × 10 ,61.44 × 10 ) =20 × 10




61.44 × 106
=3750
214
6
61.44 × 10
>
=3750
214
fgcd1 =gcd 2000.2 × 106 ,61.44 × 106 =40 × 103 >
fgcd 2
6
6
3
If (EQ 17) is satisfied for at least two of the equally spaced interval (channel) frequencies f VCO1,f VCO2 ,f VCO3 ,...
f VCON, as it is above, Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies,
and can be configured as follows:
f


6 
1  floor  2000.2 × 10=
 32
=
=
d 20h
1. Reg 03h = floor  VCO

 61.44 × 106 
 fPD 


2. Reg 0Ch =
61.44 × 106
61.44 × 106
d C00h
=
=
= 3072
=
20000
gcd 100 × 103 ,61.44 × 106
gcd ( fVCOk +1 − fVCOk ) , fPD
fPD
(
)
)
(
where (f VCOk+1 - f VCOk) is the desired channel spacing (100 kHz in this example).
3. To program Reg 04h the closest integer-N boundary frequency fN that is less than the smallest
channel VCO frequency f VCO1 must be calculated. fN = floor(f VCO1/fPD). Using the current example:
 2000.2 × 106 
 =32 × 61.44 × 106 =1966.08 MHz
 61.44 × 106 


fN =fPD × floor 
Then
 224 f
( VCO1 − fN )  for channel 1 where f

=
=
Reg 04h ceil
VCO1 2000.2 MHz


f


PD


 24
2000.2 × 106 − 1966.08 × 106 
2
d 8E2 AABh
= ceil 
=
=
 9317035
61.44 × 106




(
)
4. To change from channel 1 (f VCO1 = 2000.2 MHz) to channel 2 (f VCO2 = 2000.3 MHz), only
Reg 04h needs to be programmed, as long as all of the desired exact frequencies f VCOk (Figure 23)
fall between the same integer-N boundaries (fN < f VCOk < fN+1). In that case
(
)
 24
2000.3 × 106 − 1966.08 × 106 
2
=
=
d 8E9556h
 9344342
61.44 × 106




Reg 04h = ceil 
, and so on.
4.12.2.6Seed Register & AutoSeed Mode
The start phase of the fractional modulator digital phase accumulator (DPA) may be set to one of four
possible default values via the seed register Reg 06h[1:0]. If AutoSeed Reg 06h[8] is set, then the PLL
with Integrated VCO will automatically reload the start phase into the DPA every time a new fractional
frequency is selected. If AutoSeed is not set, then the PLL will start new fractional frequencies with the last
value left in the DPA from the last frequency. Hence the start phase will effectively be random. Certain zero
or binary seed values may cause spurious energy correlation at specific frequencies. Correlated spurs
are advantageous only in very special cases where the spurious are known to be far out of band and are
A - 31
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removed in the loop filter. For most cases a random, or non zero, non-binary start seed is recommended.
Further, since the AutoSeed always starts the accumulators at the same place, performance is repeatable
if AutoSeed is used. Reg 06h[1:0]=2 is recommended.
Soft Reset & Power-On Reset
The PLL with Integrated VCO features a hardware Power on Reset (POR). All chip registers will be reset to
default states approximately 250 µs after power up.
Writing Reg 00h[5]=1 (rst_swrst) performs a soft reset which initializes all PLL subsystem registers to their
default values. It is not necessary to clear the rst_swrst bit after a soft reset. A soft reset does not clear
the SPI mode of operation referred to in section 4.17.2. It should be noted that the VCO subsystem is not
affected by the PLL soft reset, the VCO subsystem registers can only be reset by removing the power
supply.
NOTE: if external power supplies or regulators have rise times slower than 250us, then it is advised to
write to the SPI reset register (Reg 00h[5]=1) immediately after power up, before any other SPI activity.
This will ensure starting from a known state.
4.14
Power Down Mode
Note that the VCO subsystem is not affected by the CEN or soft reset. Hence device power down is a two
step process. First power down the VCO by writing 0 to VCO register 1 via Reg 05h and then power down
the PLL by pulling CEN pin 17 low (assuming no SPI overrides (Reg 01h[0]=1)). This will result in all analog
functions and internal clocks disabled. Current consumption will typically drop below 10 µA in Power Down
state. The serial port will still respond to normal communication in Power Down mode.
It is possible to ignore the CEN pin, by clearing chipen_pin_select (Reg 01h[0]=0). Control of Power Down
Mode then comes from the serial port register chipen_from_spi, Reg 01h[1] .
It is also possible to leave various blocks on when in Power Down (see Reg 01h), including:
a. Internal Bias Reference Sources Reg 01h[2]
b. PD Block
Reg 01h[3]
c. CP Block Reg 01h[4]
d. Reference Path Buffer Reg 01h[5]
e. VCO Path buffer Reg 01h[6]
f. Digital I/O Test pads Reg 01h[7]
Product & Operating Guide
4.13
A
To mute the RF output but leave the VCO running and the PLL locked write the following:
For Narrowband and Triband devices Reg 05h=C80D. To re-enable the RF output write Reg 05h=E80D.
Wideband devices can operate in either manualRFO (VCO_Reg 03h[2]=1) or autoRFO (VCO_Reg
03h[2])=0 modes. The autoRFO (auto RF Output) mode switches between “VCO divide-by-1” and “output
divider” sub-blocks depending on the divider setting. With output divider set to “1” (VCO_Reg 02h[5:0]=1)
autoRFO mode automatically enables the “VCO divide-by-1” sub-block and disables the “output divider”
sub-block. To mute the output in autoRFO mode set VCO_Reg 02h[5:0]=0. Divider values other then “0”
or “1” cause autoRFO to enable the VCO output divider and disable the divide-by-1 bypass. In manualRFO
mode the VCO sub-blocks are manually enabled/disabled with VCO_Reg 01h[4:1]. Mute the RF output in
manualRFO mode by turning off the RF buffer, RF divider and divide-by-1 sub-blocks (VCO_Reg 01h=3).
Note the PLL buffer and master enable bits are left on to prevent a loss of lock during mute. To un-mute
the output turn on the RF buffer and, depending on the divide value stored in VCO_Reg 02h[5:0], either
the RF divider or divide-by-1 sub-blocks. It is not a valid condition to turn on both the divide-by-1 and RF
divider sub-blocks at the same time.
4.15
Chip Identification
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PLLs WITH INTEGRATED VCO - RF APPLICATIONS
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4.16
General Purpose Output (GPO) Pin
The PLL shares the LD_SDO (Lock-Detect/Serial Data Out) pin to perform various functions. While the pin
is most commonly used to read back registers from chip via the SPI, it is also capable of exporting a variety
of interesting signals and real time test waveforms (including Lock Detect). It is driven by a tri-state CMOS
driver with ~200 Ω Rout. It has logic associated with it to dynamically select whether the driver is enabled,
and to decide which data to export from the chip.
Product & Operating Guide
A
PLL subsystem version information may be read by reading the content of read only register, chip_ID in
Reg 00h. It is not possible to read the VCO subsystem version.
In its default configuration, after power-on-reset, the output driver is disabled, and only drives during
appropriately addressed SPI reads. This allows it to share the output with other devices on the same bus.
Depending on the SPI mode, the read section of SPI cycle is recognized differently
HMC SPI Mode: The driver is enabled during the last 24 bits of SPI READ cycle (not during write
cycles).
Open SPI Mode: The driver is enabled if the chip is addressed - ie. The last 3 bits of SPI cycle =
‘000’b before the rising edge of SEN (Note A).
To monitor any of the GPO signals, including Lock Detect, set Reg 0Fh[7] = 1 to keep the SDO driver
always on. This stops the LDO driver from tristating and means that the SDO line cannot be shared with
other devices.
The chip will naturally switch away from the GPO data and export the SDO during an SPI read (Note B). To
prevent this automatic data selection, and always select the GPO signal, set “Prevent AutoMux of SDO”
(Reg 0Fh[6] = 1). The phase noise performance at this output is poor and uncharacterized. Also, the GPO
output should not be toggling during normal operation. Otherwise the spectral performance may degrade.
Note that there are additional controls available, which may be helpful if sharing the bus with other devices:
•
To allow the driver to be active (subject to the conditions above) even when the chip is disabled - set
Reg 01h[7] = 0.
•
To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else).
•
To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 0 or Reg 0Fh[9] = 0
respectively.
Note A: If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the part will start to
drive the bus.
Note B: In Open Mode, the active portion of the read is defined between the 1st SCK rising edge after
SEN, to the next rising edge of SEN.
Example Scenarios:
•
Drive SDO during reads, tri-state otherwise (to allow bus-sharing)
• No action required.
•
Drive SDO during reads, Lock Detect otherwise
• Set GPO Select Reg 0Fh[4:0] = ‘00001’ (which is default)
• Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1)
•
Always drive Lock Detect
• Set “ Prevent AutoMux of SDO” Reg 0Fh[6] = 1
• Set GPO Select Reg 0Fh[4:0]= 00001 (which is default)
• Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1))
The signals available on the GPO are selected by changing “GPO Select”, Reg 0Fh[4:0].
4.17
A - 33
SERIAL PORT
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4.17.1 Serial Port Modes of Operation
a. HMCSPI HMC Mode (HMC Legacy Mode) - Single slave per HMCSPI Bus
b. HMCSPI Open Mode - Up to 8 slaves per HMCSPI Bus. This mode is useful to imitate protocols found
on other manufacturer’s PLLs.
Both Modes support 5-bits of register address space. HMC Mode can support up to 6 bits of register
address.
Register 0 has a dedicated function in each mode. Open Mode allows wider compatibility with other
manufacturers SPI protocols.
Table 5. Register 0 Comparison - Single vs Multi-User Modes
Single User
HMC Mode
Multi-User
Open Mode
READ
Chip ID
24-bits
Chip ID 24-bits
WRITE
Soft Reset,
General Strobes
Read Address [4:0]
Soft reset [5]
General Strobes [23:6]
4.17.2 HMCSPI Protocol Decision after Power-On Reset
On power up both types of modes are active and listening.
A decision to select the desired SPI protocol is made on the first occurrence of SEN or SCLK following a
hard reset, after which the protocol is fixed and only changeable by cycling the power OFF and ON.
a. If a rising edge on SEN is detected first HMC Mode is selected.
b. If a rising edge on SCLK is detected first Open mode is selected.
4.17.3 Serial Port HMC Mode - Single PLL
HMC Mode (Legacy Mode) serial port operation can only address and talk to a single PLL, and is compatible
with most HMC PLLs and PLLs with Integrated VCOs.
A
Product & Operating Guide
The HMC PLL with Integrated VCO serial port interface can operate in two different modes of operation.
The HMC Mode protocol, shown in figures Figure 24 and Figure 25, is designed for a 4 wire interface with
a fixed protocol featuring
a. 1 Read/Write bit
b. 6 Address bits
c. 24 data bits
d. 3 wire for Write only, 4 wire for Read/Write capability
4.17.3.1HMC Mode - Serial Port WRITE Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 6. SPI HMC Mode - Write Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
t1
SEN to SCLK setup time
8
ns
t2
SDI to SCLK setup time
3
ns
t3
SCLK to SDI hold time
3
ns
t4
SEN low duration
20
ns
t5
SCK to SEN fall
10
Max Serial port Clock Speed
ns
50
MHz
A typical HMC Mode WRITE cycle is shown in Figure 24.
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Product & Operating Guide
A
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle,
followed by a rising edge of SCK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low indi­cates a Write
cycle (/WR).
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave shifts the address bits in the next six rising edges of SCK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first.
f. Slave shifts the data bits on the next 24 rising edges of SCK (8-31).
g. The data is registered into the chip on the 32nd rising edge of SCK.
h. SEN is cleared after a minimum delay of t5. This completes the write cycle.
Figure 24. HMC Mode - Serial Port Timing Diagram - WRITE
4.17.3.2HMC Mode - Serial Port READ Operation
A typical HMC Mode READ cycle is shown in Figure 25.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed
by a rising edge SCLK. Note: The Lock Detect (LD) function is usually multiplexed onto the LD_SDO
pin. It is suggested that LD only be considered valid when SEN is low. In fact LD will not toggle until
the first active data bit toggles on LD_SDO, and will be restored immediately after the trailing edge of
the LSB of serial data out as shown in Figure 25.
b. The slave (PLL with Integrated VCO) reads SDI on the 1st rising edge of SCLK after SEN. SDI high
initiates the READ cycle (RD)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits on the next six rising edges of SCLK (2-7).
e. Slave switches from Lock Detect and places the requested 24 data bits on SD_LDO on the next 24
rising edges of SCK (8-31), MSB first .
f. Host registers the data bits on the next 24 falling edges of SCK (8-31).
g. Slave restores Lock Detect on the 32nd rising edge of SCK.
h. Deassertion of SEN completes the cycle
Table 7. SPI HMC Mode - Read Timing Characteristics
Parameter
A - 35
Conditions
Min.
Typ.
Max
Units
t1
SEN to SCLK setup time
8
ns
t2
SDI to SCLK setup time
3
ns
t3
SCLK to SDI hold time
3
ns
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SEN low duration
t5
SCLK to SDO delay
t6
Recovery Time
20
ns
8.2ns+0.2
ns/pF
10
ns
ns
Figure 25. HMC Mode - Serial Port Timing Diagram - READ
4.17.4 Serial Port Open Mode
The Serial Port Open Mode, shown in Figure 26 and Figure 27, features:
a. Compatibility with general serial port protocols that use shift and strobe approach to communication
b. Compatible with HMC PLL with Integrated VCO solutions, useful to address multiple chips of various
types from a single serial port bus.
A
Product & Operating Guide
t4
The Open Mode protocol has the following general features:
a. 3-bit chip address , can address up to 8 devices connected to the serial bus
b. Wide compatibility with multiple protocols from multiple vendors
c. Simultaneous Write/Read during the SPI cycle
d. 5-bit address space
e. 3 wire for Write Only capability, 4 wire for Read/Write capability
HMC RF PLLs with integrated VCOs support Open Mode. Some legacy PLL and microwave PLLs with
integrated VCOs only support HMC Mode. Consult the relevant data sheets for details.
Typical serial port operation can be run with SCLK at speeds up to 50 MHz.
4.17.4.1Open Mode - Serial Port WRITE Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 8. SPI Open Mode - WRITE Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
t1
SDI setup time to SCLK Rising Edge
3
ns
t2
SCLK Rising Edge to SDI hold time
3
ns
t3
SEN low duration
10
ns
t4
SEN high duration
10
ns
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Product & Operating Guide
A
t5
SCLK 32 Rising Edge to SEN Rising Edge
10
ns
t6
Recovery Time
20
ns
Max Serial port Clock Speed
50
MHz
A typical WRITE cycle is shown in Figure 26.
a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.
b. the slave (PLL with Integrated VCO) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK
(25-29)
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite
reserves chip address a2:a0 = 000 for all RF PLL with Integrated VCOs.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
Figure 26. Open Mode - Serial Port Timing Diagram - WRITE
4.17.4.2Open Mode - Serial Port READ Operation
A typical READ cycle is shown in Figure 27.
In general, in Open Mode the LD_SDO line is always active during the WRITE cycle. During any Open Mode
SPI cycle LD_SDO will contain the data from the current address written in Reg 00h[4:0]. If Reg00h[4:0]
is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in
progress. If it is desired to READ from a specific address, it is necessary in the first SPI cycle to write the
desired address to Reg00h[4:0], then in the next SPI cycle the desired data will be available on LD_SDO.
An example of the Open Mode two cycle procedure to read from any random address is as follows:
a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI
as shown in Figure 27. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on
the next cycle.
b. the slave (PLL with Integrated VCO) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5
falling edges of SCLK (25-29). r4:r0=00000.
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32)..Chip
address is always 000 for RF PLL with Integrated VCOs.
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Table 9. SPI Open Mode - Read Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
t1
SDI setup time to SCLK Rising Edge
3
ns
t2
SCLK Rising Edge to SDI hold time
3
ns
t3
SEN low duration
10
ns
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Product & Operating Guide
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the the address transfer of the two part READ cycle.
j. If one does not wish to write data to the chip at the same time as we do the second cycle , then it is
recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of
the cycle.
k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCLK.
l. Slave (PLL with Integrated VCO) shifts the SDI data on the next 32 rising edges of SCLK.
m. Slave places the desired read data (ie. data from the address specified in Reg 00h[7:3] of the first
cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling the LD
output.
m. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock
Detect on LD_SDO.
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Product & Operating Guide
A
A - 39
t4
SEN high duration
t5
SCLK Rising Edge to SDO time
10
ns
t6
Recovery TIme
10
ns
t7
SCK 32 Rising Edge to SEN Rising Edge
10
ns
8.2ns+0.211ns/pF
4.17.4.3HMCSPI Open Mode READ Operation - 2 Cycles
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Product & Operating Guide
A
Figure 27. Serial Port Timing Diagram - READ
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For more information on using the GPO pin while in SPI Open Mode please see section 4.16.
4.18
Configuration at Start-Up
To configure the PLL after power up, follow the instructions below:
1. Configure the reference divider (write to Reg 02h), if required.
Product & Operating Guide
A
2. Configure the delta-sigma modulator (write to Reg 06h).
• Configuration involves selecting the mode of the delta-sigma modulator (Mode A or Mode B),
selection of the delta-sigma modulator seed value, and configuration of the delta-sigma modulator
clock scheme. It is recommended to use the values found in the Hittite PLL evaluation board
control software register files.
3. Configure the charge pump current and charge pump offset current (write to Reg 09h)
4. Configure the VCO Subsystem (write to Reg 05h, for more information see section 4.19)
5. Program the frequency of operation
• Program the integer part (write to Reg 03h)
• Program the fractional part (write to Reg 04h)
Once the PLL is configured after startup, in most cases the user only needs to change frequencies by
writing to (Reg 03h integer register and Reg 04h fractional register), and possibly adjust the charge pump
settings by writing to Reg 09h.
Example: To configure HMC820LP6CE in fundamental mode, after power up, for output frequency of
2361 MHz, assuming 50 MHz reference frequency, the following sequence needs to be executed:
1. Reg 02h = 1h. (Optional since default = 1.)
2. Reg 06h = 202F4Ah. (Set the delta-sigma modulator to operate in Fractional Mode B, set the seed
value, and configure the delta-sigma modulator clock scheme).
3. Reg 09h = 0BCF3Ch. (Program 1.2 mA charge pump current with 300 µA Down Offset current to the
charge pump).
4.
Configure the VCO subsystem. For more information on the VCO subsystem and communication with
the VCO subsystem see section 4.19, and “6.0 VCO Subsystem Register Map”.
• Reg 05h = E80Dh. (Indirect write to VCO_Reg 01h, Enables).
• Reg 05h = 8B95h. (Indirect write to VCO_Reg 02h, Configuration).
• Reg 05h = D11Dh. (Indirect write to VCO_Reg 03h, Configuration).
• Reg 05h = 5h. (Indirect write to VCO_Reg00h, Reset the address in Reg 05h to VCO_Reg 00h).
NOTE: It is highly recommended to conclude any configuration of the VCO subsystem by
writing Reg 05h = 5h. Doing so ensures that any subsequent frequency changes using AutoCal
procedure work correctly. Please see section 4.2.1 and 4.19 for more details. This example is
for Triband or Narrowband parts. Wideband parts require Reg 05h=0 as the final Reg05h write.
5. Program the frequency of operation (set the integer-N and fractional divider values).
• Reg 03h = 2F. This programs the integer-N divider value to 47.
• Reg 04h = 3851ECh. This programs the fractional divider to 0.22
Then the output frequency fVCO = FPD(NINT + NFRAC) = 50 MHz x 47.22 = 2361 MHz.
For detailed and most up-to-date start-up configuration of an individual part please refer to the appropriate
Register Setting Files found in the HIttite PLL Evaluation Software received with a product evaluation kit
or downloaded from www.hittite.com.
4.19
VCO Serial Port Interface (SPI)
The PLL communicates with the internal VCO subsystem via an internal 16 bit VCO Serial Port, (see Figure
7). The internal serial port is used to control the step tuned VCO and other VCO subsystem functions if
available, such as RF output divider control and RF buffer enable.
A - 41
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Writes to the VCO’s control registers are handled indirectly, via writes to Reg 05h of the PLL. A write to PLL
Reg 05h causes the PLL subsystem to forward the packet, MSB first, across its internal serial link to the
VCO subsystem, where it is interpreted.
The VCO serial port has the capability to communicate with multiple subsystems inside the IC. For this
reason each subsystem has a subsystem ID, Reg 05h[2:0].
Each subsystem has multiple registers to control the functions internal to the subsystem, which may be
different from one subsystem to the next. Hence each subsystem has internal register addresses bits
(Reg 05h[6:3])
Finally the data required to configure each register within the VCO subsystem is contained in Reg 05h[15:7].
4.19.1 VSPI Use of Reg05h
The packet data written into Reg 05h is sub-parsed by logic at the VCO subsystem into the following 3
fields:
1. [2:0] - 3 bits - VCO_ID, target subsystem ID = 101b or 000b depending on the product.
2. [6:3] - 4 bits - VCO_REGADDR, the internal register address inside the VCO subsystem.
3. [15:7] - 9- bits- VCO_DATA, data field to write into the VCO register.
For example, to write 11101_0000 into register 1 of the narrow-band VCO subsystem (VCO_ID = ‘101’b),
and turn off the divider, the following needs to be written to Reg 05h =’11101_0000, 0001, 101’ (clear bit 5,
of register 1, at SPI target ID ‘101‘b).
The AutoCal controller only updates the data field of Reg 05h. The VCO_REGADDR and VCO_ID bits
must also be set correctly or AutoCal will send its data to the wrong location. Set VCO_REGADDR=0
by initializing Reg 05h[6:3]=0. This causes all AutoCal data to be sent to the VCO switch capacitor
register VCO_Reg 00h. The subsystem ID depends on the type of device. For Wideband devices set the
subsystem ID to “0” (Reg 05h[2:0])=0) or “5” for Triband and Narrowband devices (Reg 05h[2:0]=5).
A
Product & Operating Guide
Note that the internal VCO subsystem SPI (VSPI) runs at the rate of the AutoCal FSM clock, TFSM, (section
4.2.1) where the FSM clock frequency cannot be greater than 50 MHz. The VSPI clock rate is set by
Reg 0Ah[14:13].
Writing Reg 05h=0 for Wideband devices (or Reg 05h=5 for Narrowband and Triband devices) initializes
VCO_ID and VCO_REGADDR for AutoCal but it also clears VCO_DATA. Since every write to Reg 05h
causes a data transfer to the VCO subsystem, this clears the VCO switch capacitor selection stored at
VCO_Reg 00h and causes the VCO to oscillate at its highest frequency. Most likely the PLLVCO loses lock
until AutoCal selects the correct switch capacitors for the desired frequency. AutoCal runs after writing
frequency control register Reg 03h in integer mode or Reg 04h in Fractional-N mode. This is the reason
the final Reg 05h write must be followed by an update to the frequency control register. To prevent the
lose of lock initialize VCO_DATA with the correct switch capacitor selection found in Reg 10h[7:0]. The
procedure is as follows:
First read Reg 10h, then write to Reg 05h as follows:
Reg 05h = vv x yyyyy 0 0000 iii
Reg 05h[2:0] = iii, VCO_ID, 3 bits (000 or 101 depending upon the subsystem)
Reg 05h[6:3] = 0000, VCO_REG_ADDR
Reg 05h[7] = 0 , calibration tune voltage off
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Product & Operating Guide
A
5.0
Reg 05h[12:8] = 0 or VCO caps as stored in Reg 10h[4:0]
Reg 05h[13] = don’t care
Reg 05h[15:14] = yy, Wideband VCO Selection as stored in Reg 10h[7:6], don’t care Narrowband
PLL Register Map
5.1
Bit
[23:0]
5.2
Reg 00h ID Register (Read Only)
Type
RO
chip_ID
Width
24
Default
Description
95198
A7975
PLL ID for HMCXXXLP6CE where XXX ≠ 837 or 840
PLL ID for HMC837LP6CE, HMC840LP6CE & Wideband
PLL+VCO’s
Reg 00h Open Mode Read Address/RST Strobe Register (Write Only)
Bit
Type
[4:0]
WO
[5]
[23:6]
5.3
Name
Name
Width
Default
Description
Read Address
5
-
WRITE ONLY) Read Address for next cycle - Open Mode
Only
WO
Soft Reset
1
-
Soft Reset - both SPI modes reset (set to 0 for proper
operation)
WO
Not Defined
18
-
Not Defined (set to 0 for proper operation)
Width
Default
Description
1 = take PLL enable via CEN pin, see Power Down Mode
description
Reg 01h Enables Register
(Default 000002h)
Bit
Type
Name
[0]
R/W
chipen_pin_select
1
0
[1]
R/W
chipen_from_spi
1
1
SPI’s PLL enable bit
[2]
R/W
Keep_bias_on
1
0
when PLL is disabled, keeps internal bias generators on,
ignores chip enable control.
[3]
R/W
Keep_PD_on
1
0
when PLL is disabled, keeps PD circuit on, ignores Chip
enable control
[4]
R/W
Keep_CP_on
1
0
when PLL is disabled, keeps Charge Pump on, ignores
Chip enable control
[5]
R/W
Keep_Ref_buf_on
1
0
when PLL is disabled, keeps Reference buffer block on,
ignores Chip enable control
[6]
R/W
Keep_VCO_on
1
0
when PLL is disabled, keeps VCO divider buffer on,
ignores Chip enable control
[7]
R/W
Keep_GPO_driver_on
1
0
when PLL is disabled, keeps GPO output Driver On,
ignores Chip enable control
[8]
R/W
Reserved
1
0
Reserved
[9]
R/W
Reserved
1
0
Reserved
0 = take PLL enable via SPI (chipen_from_spi) Reg01[1]
5.4
Reg 02h REFDIV Register
(Default 000001h)
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[13:0]
5.5
Type
R/W
Name
rdiv
Width
Default
Description
1
Reference Divider ’R’ Value “(EQ 13)”)
Divider use also requires refBufEn Reg08[3]=1and Divider
min 1d
max 16383d
14
Reg 03h Frequency Register - Integer Part
(Default 000019h)
Bit
Type
Name
Width
Default
Description
VCO Divider Integer part, used in all modes, see (EQ 13)
[18:0]
R/W
intg
19
25d
Fractional Mode
min 20d
max 219 -4 = 7FFFCh = 524,284d
Integer Mode
min 16d
max 219 -1 = 7FFFFh = 524,287d
5.6
Reg 04h Frequency Register - Fractional Part
(Default 000000h)
Bit
Type
Name
Width
Default
Description
VCO Divider Fractional part (24-bit unsigned) see
Fractional Frequency Tuning
[23:0]
5.7
R/W
frac
24
0
Width
Default
Used in Fractional Mode only (Nfrac = Reg 04h/224
min 0d
max 224-1
Reg 05h VCO SPI Register
(Default 000000h)
Bit
Type
Name
A
Product & Operating Guide
Bit
Description
[2:0]
R/W
[2:0] - VCO Subsystem_ID,
3
0
101b - narrowband and tri-band products
000b - wideband products
[6:3]
R/W
VCO Subsystem register address
4
0
For interfacing with the VCO please see section 4.19.
[15:7]
R/W
VCO Subsystem data
9
0
Note: Reg05h is a special register used for indirect addressing of the VCO subsystem. Writes to Reg05h are
automatically forwarded to the VCO subsystem by the VCO SPI state machine controller.
Reg05h is a Read-Write register. However, Reg05h only holds the contents of the last transfer to the VCO subsystem.
Hence it is not possible to read the full contents of the VCO subsystem. Only the content of the last transfer to the
VCO subsystem can be read. Please take note of special considerations for AutoCal related to Reg05h.
Once VCO register programming has been completed, Reg05h needs to be programmed to 0 for Wideband devices
or 5 for Narrowband and Tri-band devices. More accurately, only the lower 7 bits need to be set. The other bits can
be set as needed:
xxxx xxxx xxxx xxxx x000 0000 for Wideband devices;
xxxx xxxx xxxx xxxx x000 0101 for Narrowband and Tri-band devices;
Refer to section 4.19.
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Product & Operating Guide
A
5.8
(Default 200B4Ah)
Bit
[1:0]
Type
R/W
Name
seed
Width
2
Default
Description
2
Selects the Seed in Fractional Mode
00: 0 seed Not recommended
01: lsb seed Not recommended
02: B29D08h seed Recommended
03: 50F1CDh seed
Note; Writes to this register are stored in the PLL with
Integrated VCO and are only loaded into the modulator
when a frequency change is executed and if AutoSeed
Reg06h[8] =1
[3:2]
R/W
order
2
2
Select the Modulator Type
0: 1st order Not recommended
1: 2nd order Not recommended
2: Mode B Recommended
3: Mode A
[6:4]
R/W
Reserved
3
4
Program 100
0: Use Modulator, Required for Fractional Mode,
1: Bypass Modulator, Required for Integer Mode
[7]
R/W
frac_bypass
1
0
[8]
R/W
AutoSeed
1
1
1: loads the seed whenever the frac register is written
0: when frac register write changes frequency, modulator
starts with previous contents
Note: In bypass fractional modulator output is ignored,
but fractional modulator continues to be clocked if frac_
rstb =1, Can be used to test the isolation of the digital
fractional modulator from the VCO output in integer mode
[9]
R/W
clkrq_refdiv_sel
1
1
selects the modulator clock source- for Test Only
1: VCO divider clock (Recommended for normal
operation)
0: Ref divider clock
Ignored if bits [10]=0 or [21]=1 are set
[10]
R/W
SD Modulator Clk Select
1
0
Program 1
0: disable frac core, use for Integer Mode or Integer Mode
with CSP
1: Enable Frac Core, required for Fractional Mode, or
Integer isolation testing
This register controls whether AutoCal starts on an
Integer or a Fractional write
[11]
R/W
SD Enable
1
1
[12]
R/W
Reserved
1
0
Program 0
[13]
R/W
Reserved
1
0
Program 0
[15:14]
R/W
Reserved
2
0
Program 0
[17:16]
R/W
Reserved
2
0
Program 11
[18]
R/W
BIST Enable
1
0
Program 0
R/W
RDiv BIST Cycles
2
0
Program 00
RDiv BIST Cycles
00: 1032
01: 2047
10: 3071
11: 4095
[21]
R/W
auto_clock_config
1
1
Program 0
[22]
R/W
Reserved
1
0
Program 0
[20:19]
A - 45
Reg 06h SD CFG Register
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Reg 07h Lock Detect Register
(Default 00014Dh)
Bit
[2:0]
Type
R/W
Name
lkd_wincnt_max
Width
3
Default
5d
Description
lock detect window
sets the number of consecutive counts of divided VCO
that must land inside the Lock Detect Window to declare
LOCK
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
[3]
R/W
Enable Internal Lock Detect
1
1
see section 4.16
[5:4]
R/W
Reserved
2
0
Reserved
[6]
R/W
Lock Detect Window type
1
1
Lock Detection Window Timer Selection
1: Digital programmable timer
0: Analog one shot, nominal 10 ns window
[9:7]
R/W
LD Digital Window duration
3
2
0 Lock Detection - Digital Window Duration
0: 1/2 cycle
1: 1 cycle
2: 2 cycles
3: 4 cycles
4: 8 cycles
5: 16 cycles
6: 32 cycles
7: 64 cycles
[11:10]
R/W
LD Digital Timer Freq Control
2
0
Lock Detect Digital Timer Frequency Control
“00” fastest “11” slowest
[12]
R/W
LD Timer Test Mode
1
0
1: force Timer Clock ON Continuously - For Test Only
0: Normal Timer operation - one shot
[13]
R/W
Auto Relock - One Try
1
0
1: Attempts to re-lock with VCO auto-calibration if Lock
Detect fails for any reason. Only tries once.
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5.9
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A
A - 47
5.10
Reg 08h Analog EN Register
(Default C1BEFFh)
Bit
Type
Width
Default
[0]
R/W
bias_en
Name
1
1
Program 1
Description
[1]
R/W
cp_en
1
1
Program 1
[2]
R/W
PD_en
1
1
Program 1
[3]
R/W
refbuf_en
1
1
Program 1
[4]
R/W
vcobuf_en
1
1
Program 1
0 - Pin LD_SDO disabled
[5]
R/W
gpo_pad_en
1
1
1 - and RegFh[7]=1 , Pin LD_SDO is always on required
for use of GPO port.
1 - and RegFh[7]=0 Pin LD_SDO is off if unmatched chip
address is seen on the SPI, allowing a shared SPI with
other compatible parts
[6]
R/W
reserved
1
1
Program 1
[7]
R/W
VCO_Div_Clk_to_dig_en
1
1
Program 1
[8]
R/W
reserved
1
0
Program 0
[9]
R/W
Prescaler Clock enable
1
1
Program 1
[10]
R/W
VCO Buffer and Prescaler
Bias Enable
1
1
Program 1
[11]
R/W
Charge Pump Internal
Opamp enable
1
1
Program 1
[14:12]
R/W
reserved
3
011
Program 011
[17:15]
R/W
reserved
3
011
Program 011
[18]
R/W
spare
1
0
Don’t Care
[19]
R/W
reserved
1
0
Program 0
[20]
R/W
reserved
1
0
Program 0
[21]
R/W
High Frequency Reference
1
0
Program 1 for Ref In > =200 MHz, 0 <200MHz
[22]
R/W
spare
1
1
Don’t Care
[23]
R/W
spare
1
1
Don’t Care
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Reg 09h Charge Pump Register
(Default 403264h)
Bit
[6:0]
[13:7]
Type
R/W
R/W
Name
CP DN Gain
Width
7
CP UP Gain
7
Default
Description
100d
64h
Charge Pump DN Gain Control 20 µA√step
Affects fractional phase noise and lock detect settings
0d = 0 µA
1d = 20 µA
2d = 40 µA
...
127d = 2.54mA
100d
64h
Charge Pump UP Gain Control 20 µA per step
Affects fractional phase noise and lock detect settings
0d = 0 µA
1d = 20 µA
2d = 40 µA
...
127d = 2.54mA
[20:14]
R/W
Offset Magnitude
7
0
Charge Pump Offset Control 5 µA/step
Affects fractional phase noise and lock detect settings
0d = 0 µA
1d = 5 µA
2d = 10 µA
...
127d = 635 µA
[21]
R/W
Offset UP enable
1
0
Recommended setting = 0
[22]
R/W
Offset DN enable
1
1
Recommended setting = 1 in Fractional Mode, 0
otherwise
[23]
R/W
HiKcp
1
0
Program 0
5.12
Reg 0Ah VCO AutoCal Configuration Register
(Default 002205h)
Bit
[2:0]
Type
R/W
Name
Vtune Resolution
Width
3
Default
5
Description
A
Product & Operating Guide
5.11
R Divider Cycles
0-1
1-2
2-4
3-8
4 - 32
5 - 64
6 - 128
7 - 256
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Product & Operating Guide
A
5.12
Reg 0Ah VCO AutoCal Configuration Register
(Default 002205h)
Bit
[5:3]
Type
R/W
Name
VCO Curve Adjustment
Width
3
Default
0
Description
Program 000
VCO Curve Adjustment vs Temp for AutoCal
0 - Disabled
1 : + 1 Curve
2: +2 Curves
3: +3 Curves
4: -4 Curves
5: -3 Curves
6: -2 Curves
7: -1 Curve
Wait State Setup 100 TFSM see section 4.2.4
[7:6]
R/W
Wait State Set Up
2
0
Tmmt = 1 measurement cycle of AutoCal
0: Wait Only at Startup Use for Narrowband & Tri-band
devices
1: Wait on startup and after first Tmmt cycle Use for
Wideband devices
2: Wait on startup and after first two Tmmt cycles
3: Wait on startup and after first three Tmmt cycles
[9:8]
R/W
Num of SAR BIts in VCO
2
2
Number of SAR bits in VCO
0: 8 - Use for Wideband devices
1: 7 - Do not use
2: 6 - Use for Narrowband & Tri-band devices
3: 5 - Do not use
[10]
R/W
Force Curve
1
0
Program 0
[11]
R/W
Bypass VCO Tuning
1
0
Program 0 for normal operation using VCO auto
calibration
[12]
R/W
No VSPI Trigger
1
0
Program 0 for normal operation. If 1, serial transfers to
VCO sub-system (via Reg 05) are disabled
[14:13]
R/W
FSM/VSPI Clock Select
2
1
Set the AutoCal FSM and VSPI Clock (50 MHz maximum)
0: Input Crystal Reference
1: Input Crystal Reference/4
2: Input Crystal Reference/16
3: Input Crystal Reference/32
[15]
R/W
Xtal Falling Edge for FSM
1
0
Program 0 for normal operation. Program 1 only for BIST
use
[16]
R/W
Force RDivider Bypass
1
0
Program 0
5.13
Reg 0Bh PD Register
(Default 0F8061h)
Bit
Type
Width
Default
[2:0]
R/W
PD_del_sel
Name
3
1
Program 001 Sets PD reset path delay
Description
[3]
R/W
Short PD Inputs
1
0
Program 0 for normal operation. 1 shorts the inputs of the
Phase frequency detector - Test Only
Program 0 for typical operation. Inverts the PD polarity
[4]
R/W
pd_phase_sel
1
0
0- Use with a positive tuning slope VCO and Passive
Loop Filter (default)
1- Use with a Negative Slope VCO or with an inverting
Active Loop Filter with a Positive Slope VCO
[5]
A - 49
R/W
PD_up_en
1
1
Program 1 Enables the PD UP output
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PLLs WITH INTEGRATED VCO - RF APPLICATIONS
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Reg 0Bh PD Register
(Default 0F8061h)
Bit
Type
[6]
R/W
Name
PD_dn_en
Width
Default
Description
1
1
Program 1 Enables the PD DN output
[8:7]
R/W
CSP Mode
2
0
Cycle Slip Prevention Mode
Extra current is driven into the loop filter when the phase
error is larger than:
0: Disabled
1: 5.4ns
2: 14.4ns
3: 24.1ns
This delay varies by +- 10% with temperature, and +- 12%
with process.
[9]
R/W
Force CP UP
1
0
Forces CP UP output on - Use for Test only
[10]
R/W
Force CP DN
1
0
Forces CP DN output on - Use for Test only
[11]
R/W
Force CP MId Rail
1
0
Force CP MId Rail - Use for Test only
[14:12]
R/W
Reserved
3
0
Program as follows:
HMC820 000
HMC821 000
HMC822 000
HMC824 000
HMC826 000
HMC828 000
HMC829 100
HMC830 100
HMC831 000
HMC836 000
HMC837 000
HMC838 000
HMC839 000
HMC840 000
HMC1032 100
HMC1034 100
[16:15]
R/W
CP Internal OpAmp Bias
2
3
Program 11
R/W
MCounter Clock Gating
2
3
Program 11 MCounter Clock Gating
0: MCounter Off
1: N<128
2: N< 1023
3: All Clocks ON (Recommended)
[19]
R/W
spare
1
1
Don’t Care
[21:20]
R/W
reserved
2
0
Program 00
[18:17]
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5.13
A - 50
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Product & Operating Guide
A
A - 51
5.13
Reg 0Bh PD Register
(Default 0F8061h)
Bit
Type
[23:22]
R/W
5.14
Name
reserved
Width
Default
2
0
Description
Program 00
Reg 0Ch Fine Frequency Correction Register
(Default 000000h)
Bit
[13:0]
Type
R/W
Name
Number of Channels per Fpd
Width
14
Default
Description
0
Comparison Frequency divided by the Correction Rate,
Must be an integer. Frequencies at exactly the correction
rate will have zero frequency error.
0: Disabled
1: Disabled
2:16383d (3FFFh)
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5.15
Reg 0Fh GPO_SPI_RDIV Register
(Default 000001h)
Bit
Type
Name
Width
Default
Description
A
0: Data from Reg0F[5]
1: Lock Detect Output
2. Lock Detect Trigger
3: Lock Detect Window Output
4: Ring Osc Test
5. Pullup Hard from CSP
6. PullDN hard from CSP
7. Reserved
8: Reference Buffer Output
9: Ref Divider Output
10: VCO divider Output
11. Modulator Clock from VCO divider
12. Auxiliary Clock
13. Aux SPI Clock
14. Aux SPI Enable
15. Aux SPI Data Out
16. PD DN
17. PD UP
18. SD3 Clock Delay
19. SD3 Core Clock
20. AutoStrobe Integer Write
21. Autostrobe Frac Write
22. Autostrobe Aux SPI
23. SPI Latch Enable
24. VCO Divider Sync Reset
25. Seed Load Strobe
26.-29 Not Used
30. SPI Output Buffer En
31. Soft RSTB
[4:0]
R/W
gpo_select
5
1
[5]
R/W
GPO Test Data
1
0
1 - GPO Test Data. This level appears on LD_SDO pin if
Bits [4:0]=00000
[6]
R/W
Prevent Automux SDO
1
0
1- Outputs GPO data only (LD if Bits [4:0]=00001)
0 - Automuxes between SDO and GPO data
[7]
R/W
LDO Driver Always On
1
0
1- LD_SDO Pin Driver always on
0 - LD_SDO Pin driver only on during SPI read cycle
[8]
R/W
Disable PFET
1
0
Program 0
[9]
R/W
Disable NFET
1
0
Program 0
Width
Default
5.16
Product & Operating Guide
Signal selected here is output to SDO pin when enabled
Reg 10h VCO Tune Register
(Default 000020h)
Bit
[7:0]
Type
RO
Name
VCO Switch Setting
8
32d
Description
Read Only Register. Indicates the VCO switch setting
selected by the AutoCal state machine to yield the
nearest free running VCO frequency to the desired
operating frequency. Not valid when Reg10h[8] = 1,
AutoCal Busy. Note if a manual change is done to the
VCO switch settings this register will not indicate the
current VCO switch position.
0 = highest frequency
1 = 2nd highest
...
256 = lowest frequency
Note: VCO subsystems may not use all the MSBs, in
which case the unused bits are don’t care
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Product & Operating Guide
A
A - 53
[8]
5.17
RO
AutoCal Busy
1
0
Busy when AutoCal state machine is searching for the
nearest switch setting to the requested frequency.
Reg 11h SAR Register
(Default 7FFFFh)
Bit
Type
Width
Default
[18:0]
RO
SAR Error Mag Counts
19
219-1
SAR Error Magnitude Counts
[19]
RO
SAR Error Sign
1
0
SAR Error Sign 0=+ve 1=-ve
5.18
Name
Description
Reg 12h GPO2 Register
(Default 000000h)
Bit
Type
Width
Default
[0]
RO
GPO
1
0
GPO State
[1]
RO
Lock Detect
1
0
Lock Detect Status
1 = Locked
0 = Unlocked
5.19
Name
Description
Reg 13h BIST Register
(Default 1259h)
Bit
Type
Width
Default
[15:0]
RO
BIST Signature
Name
16
4697d
[16]
RO
BIST Busy
1
0
Description
BIST Signature
BIST Busy
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PLLs WITH INTEGRATED VCO - RF APPLICATIONS
PRODUCT & OPERATING GUIDE
VCO Subsystem Register Map
Please note that the VCO subsystem uses indirect addressing via Reg 05h. For more detailed information
on how to write to the VCO subsystem please see section “4.19 VCO Serial Port Interface (SPI)”.
6.1
Bit
VCO_Reg 00h Tuning
Type
Name
Width
Default
[0]
WO
Cal
1
0
[8:1]
WO
CAPS
8
16d
Width
Default
6.2
Bit
Description
VCO tune voltage is redirected to a temperature
compensated calibration voltage
VCO sub-band selection.
0 - max frequency
1111 1111 - min frequency.
Not all sub-bands are used on the various products.
VCO_Reg 01h Enables
Type
Name
Description
Narrowband Parts
[3:0]
WO
spare
4
0
Don’t care
[4]
WO
PLL_buf_en
1
1
VCO to PLL Buffer Enable
[5]
WO
div_en
1
1
VCO output divider enable (if applicable)
[6]
WO
RF_buf_en
1
1
Enables RF Buffer to Output
[7]
WO
VCO_core_en
1
1
Enables VCO Core
[8]
WO
Master Enable
1
1
Master enable
1 - Master enable of VCO Subsystem
0 - Powers down entire VCO Subsystem
1
0 - All VCO subsystem blocks Off
Manual mode (VCO_Reg 03h[2] = 1)
1- ANDed with local enables only
Auto Mode (VCO_Reg 03h[2] = 0)
1- Master enable ignores local enables
Wideband Parts [*]
[0]
A
WO
Master Enable VCO Subsystem
1
[1]
WO
Manual Mode PLL buffer enable
1
1
Enables PLL Buffer in manual mode only
[2]
WO
Manual Mode RF buffer enable
1
1
Enables RF Buffer to Output in manual mode only
[3]
WO
Manual Mode Divide by 1 enable
1
1
Enables RF divide by 1 in manual mode only
[4]
WO
Manual Mode RF Divider enable
1
1
Enables RF divider in manual mode only
[8:5]
WO
Spare
4
0
Don’t care
Product & Operating Guide
6.0
[*] Graphical representation of the wideband VCO Subsystem is available in section 4.1.5
For example, to turn off the HMC821LP6CE narrowband VCO subsystem output divider, bit 5 in VCO Reg01h needs
to be cleared. If the other bits are left unchanged, then ‘11101 0000’ needs to be written into VCO Reg01h. The VCO
subsystem register is accessed via a write to PLL subsystem Reg 05h = ‘11101 0000 0001 101’ = E80Dh
Reg 05h[2:0] = 101; VCO subsystem ID 5
Reg 05h[6:3] = 0001; VCO subsystem register address
Reg 05h[10:7] = 0000; don’t care
Reg 05h[11] = 1; PLL buffer enable
Reg 05h[12] = 0; VCO divider disabled
Reg 05h[13] = 1; RF buffer enabled
Reg 05h[14] = 1; VCO core enabled
Reg 05h[15] = 1; master enabled
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Product & Operating Guide
A
6.3
Bit
VCO_Reg 02h Biases
Type
Name
Width
Default
Description
Narrowband Parts
[1:0]
WO
VCO PLL Buffer Bias
2
1
[3:2]
WO
VCO Output Divider Bias
2
1
[5:4]
WO
RF Output Buffer Bias
2
1
[8:6]
WO
VCO Bias for tri-band parts
3
001
010
101
VCO Bias for Tri-band parts.
Don’t care for Single Band parts
Tri-Band devices HMC837, HMC840 (recommended value 001)
Tri-band devices HMC838, HMC839 (program value 100, do not
use default value)
Tri-band devices HMC820, HMC821, HMC822 (program value
100, do not use default value)
Wideband Parts [*]
[5:0]
WO
RF Divide ratio
6
1
0 - Mute, VCO and PLL buffer On, RF output stages Off
1 - Fo
2 - Fo/2
3 - invalid, defaults to 2
4 - Fo/4
5 - invalid, defaults to 4
6 - Fo/6
...
60 - Fo/60
61 - invalid, defaults to 60
62 - Fo/62
> 62 - invalid, defaults to 62
Note: This register automatically controls the enables to the,
RF output buffer, RF divider, RF divide by 1 path, and requires
Master Enable (VCO_Reg 01h[0] = 1) and AutoRFO mode
(VCO_Reg 03h [2] = 0)
Note: bit[0] is a don’t care in ManualRFO mode.
[7:6]
WO
RF output buffer gain control
2
3
11 - Max Gain
10 - Max Gain - 3 dB
01 - Max Gain - 6 dB
00 - Max Gain - 9 dB
[8]
WO
Divider output stage gain
control
1
0
For VCO output Divide-by-1 or 2, set to 1 (0 reduces output
power, degrading noise floor performance)
For VCO output Divide-by-4 or higher, set to 0. Use this bit to
maintain flat output power across divider settings
[*] Graphical representation of the wideband VCO Subsystem is available in section 4.1.5
For example, to configure the HMC821LP6CE narrowband VCO subsystem to the required bias settings for Fo mode,
Transfer 117h (‘1 0001 0111’ ) to VCO Reg02h. VCO subsystem register is accessed via a write to PLL subsystem
Reg 05h = ‘1 0001 0111 0010 101’ = 8B95h
Reg 05h[2:0] = 101; subsystem ID 5
Reg 05h[6:3] = 0010; VCO register address 2
Reg 05h[15:7] = 1 0001 0111; required bias setting
For example to configure the Wideband HMC830 in divide-by-1 mode with various gains set the following:
Reg 05h=E090h for max gain
Reg 05h=C090h for max gain -3dB
Reg 05h=A090h for max gain -6dB
Reg 05h=8090h for max gain -9dB
A - 55
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PRODUCT & OPERATING GUIDE
PLL Reg05h Values for VCO_Reg 02h Required Config Narrowband ONLY
Program Reg 05h according to the following table. Writing values below to Reg 05h ensures the correct
recommended settings are written to the VCO subsystem VCO_Reg 02h.
Specified performance is only guaranteed with the required settings in this table. Other settings are not
supported.
Part #
Fo/2
Fo
2Fo
HMC820LP6CE
8B95
8B95
8395
HMC821LP6CE
8B95
8B95
8395
HMC822LP6CE
8B95
8B95
8395
HMC824LP6CE
0195h
N/A
N/A
HMC826LP6CE
0195h
N/A
N/A
HMC828LP6CE
N/A
0195h
N/A
HMC831LP6CE
N/A
0195h
N/A
HMC836LP6CE
N/A
N/A
0195h
2295h
HMC837LP6CE
2A95h
2A95h
HMC838LP6CE
8B95
8B95
8395
HMC839LP6CE
8B95
8B95
8395
HMC840LP6CE
2A95h
2A95h
2295h
6.4
Bit
VCO_Reg 03h Config
Type
Name
Width
Default
Description
Narrowband Tri-Band Parts
[0]
WO
Spare
1
0
[4:1]
WO
MSB Correction
4
3
[6:5]
WO
Temp Compensation
2
1
[8:7]
WO
PLL Buffer Gain
2
1
Don’t care
A
Product & Operating Guide
6.3.1
Narrowband Single Band Parts
[4:0]
WO
Spare
5
0
[6:5]
WO
Temp compensation
2
1
[8:7]
WO
PLL Buffer Gain
2
1
Don’t care
Wideband Parts [*]
[0]
WO
RF buffer SE enable
1
1
1- single-ended mode of RF buffer (pin RF_N On, RF_P
Off)
0- differential mode both RF_P and RF_N On
[1]
WO
reserved
1
0
Program 0
[2]
WO
Manual RFO Mode
1
0
0 - AutoRFO mode (recommended)
1 - ManualRFO mode
AutoRFO mode controls output buffers and RF divider
enables according to RF divider setting in VCO_Reg
02h[5:0]
ManualRFO mode requires manual enables of individual
blocks via VCO_Reg01h
[4:3]
WO
RF buffer bias
2
2
Program 10
[8:5]
WO
Spare
4
2
Don’t care
[*] Graphical representation of the wideband VCO Subsystem is available in section 4.1.5
For example, to configure the HMC840LP6CE narrowband VCO subsystem to the required Trim settings for 2Fo
mode, 1C6h needs to be transferred to VCO Register 03h. ‘1 1100 0110’ needs to be written into VCO register 03h.
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A
Reg 05h[2:0] = 101; subsystem ID 5
Reg 05h[6:3] = 0011; VCO register address 03
Reg 05h[15:7] = 1 1100 0110; required trim settings
Product & Operating Guide
VCO subsystem register is accessed via a write to PLL subsystem Reg 05h = ‘1 1100 0110 0011 101’ = E31Dh
6.4.1
PLL Reg05h Values for VCO_Reg 03h Required Config Narrowband ONLY
Program PLL Reg 05h according to the following table. Writing values below to Reg 05h ensures the
correct recommended settings are written to the VCO subsystem VCO_Reg 03h.
Specified performance is only guaranteed with the required settings in this table. Other settings are not
supported.
Part #
Fo/2
Fo
2Fo
HMC820LP6CE
D11Dh
D11Dh
D11Dh
HMC821LP6CE
D11Dh
D11Dh
D11Dh
HMC822LP6CE
D11Dh
D11Dh
D11Dh
HMC824LP6CE
501Dh
N/A
N/A
HMC826LP6CE
501Dh
N/A
N/A
HMC828LP6CE
N/A
401Dh
N/A
HMC831LP6CE
N/A
501Dh
N/A
HMC836LP6CE
N/A
N/A
501Dh
HMC837LP6CE
211Dh
211Dh
E11Dh
HMC838LP6CE
D11Dh
D11Dh
D11Dh
HMC839LP6CE
D11Dh
D11Dh
D11Dh
HMC840LP6CE
231Dh
231Dh
E31Dh
6.5
VCO_Reg 04h, VCO_Reg 05h, VCO_Reg 06h Wideband Devices Only
Program PLL Reg 05h according to the following table. Writing values below to Reg 05h ensures the
correct recommended settings are written to these VCO subsystem registers.
Specified performance is only guaranteed with the required settings in this table. Other settings are not
supported.
Part #
VCO Reg04h
VCO Reg05h
VCO Reg06h
Wideband Parts Only
HMC829LP6GE
B6A0h
7E28h
Default (7FB0h)
HMC830LP6GE
60A0h
1628h
Default (7FB0h)
HMC1032LP6GE
60A0h
1628h
Default (7FB0h)
HMC1034LP6GE
60A0h
1628h
Default (7FB0h)
NOTES:
A - 57
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Product & Operating Guide
A
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