REVISIONS LTR DESCRIPTION DATE APPROVED A Delete figure 5 and all Daisy chain mode references under footnote 13/ as specified under table I. Add typical limits to INE, DNE, FSE, ZSE, AE, ZIN, IDD, ISS, ICC, and IOICC as specified under table I. - ro 13-10-02 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A PAGE 18 19 20 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 13-04-11 TITLE MICROCIRCUIT, DIGITAL-LINEAR, 20 BIT, VOLTAGE OUTPUT DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE A REV AMSC N/A DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ CODE IDENT. NO. DWG NO. V62/12664 16236 A PAGE 1 OF 20 5962-V087-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 20 bit, voltage output digital to analog converter (DAC) microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12664 - Drawing number 01 X B Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD5791 20 bit, voltage output digital to analog converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 20 JEDEC PUB 95 Package style MO-153-AC Thin shrink small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 2 1.3 Absolute maximum ratings. 1/ Positive analog supply voltage (VDD) to analog ground reference (AGND) -0.3 V to +34 V Negative analog supply (VSS) to AGND ...................................................... -34 V to +0.3 V VDD to VSS ................................................................................................. -0.3 V to +34 V Digital supply voltage (VCC) to digital ground reference (DGND) ................ -0.3 V to +7 V Digital interface supply (IOVCC) to DGND .................................................. -0.3 V to VCC + 3 V or +7 V (whichever is less) Digital inputs to DGND ................................................................................ -0.3 V to IOVCC + 0.3 V or +7 V (whichever is less) Analog output voltage (VOUT) to AGND ...................................................... -0.3 V to VDD + 0.3 V Positive reference force voltage (VREFPF) to AGND .................................. -0.3 V to VDD + 0.3 V Positive reference sense voltage (VREFPS) to AGND ................................. -0.3 V to VDD + 0.3 V Negative reference force voltage (VREFNF) to AGND ................................. VSS – 0.3 V to + 0.3 V Negative reference sense voltage (VREFNS) to AGND ............................... VSS – 0.3 V to +0.3 V DGND to AGND .......................................................................................... -0.3 V to +0.3 V Storage temperature range (TSTG) ............................................................. -65°C to +150°C Maximum junction temperature range (TJ) .................................................. +150°C Power dissipation (PD) ................................................................................ 174.8 mW 2/ Electrostatic discharge (ESD): Human body model (HBM) ...................................................................... 1.5 kV 1.4 Recommended operating conditions. 3/ Operating free-air temperature range (TA) .................................................. -55°C to +125°C 1.5 Thermal characteristics. Thermal resistance, junction to case (θJC) .................................................. 45°C/W Thermal resistance, junction to ambient (θJA) ............................................. 143°C/W 1/ 2/ 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Power dissipation (PD) = ( TJ max – TA ) / θJA = (150 – 125) / 143 = 0.1748 W. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Timing waveforms. The timing waveforms shall be as shown in figures 3 and 4. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Min Unit Max Static performance 4/ Resolution Integral nonlinearity error (relative accuracy) INE VREFP = +10 V, VREFN = -10 V -55°C to +125°C 01 20 0°C to +105°C 01 -1 -1.5 -55°C to +125°C -1.5 -55°C to +125°C -3 -55°C to +125°C DNE 01 -55°C to +125°C VREFP = +10 V, VREFN = -10 V -2.5 -55°C to +125°C 01 +125°C After 1,000 hours FSE +1.5 +2.5 0.16 typical LSB 0.19 typical After 1,000 hours Full scale error LSB ±1 typical +25°C After 500 hours +1 ±0.75 typical +25°C Linearity error long 6/ term stability -1 -1.5 -55°C to +125°C VREFP = +5 V, VREFN = 0 V +3 ±0.5 typical +25°C VREFP = +10 V, VREFN = 0 V +1.5 ±0.25 typical +25°C Differential nonlinearity error +1.5 ±1 typical +25°C VREFP = +5 V, VREFN = 0 V 5/ LSB ±0.5 typical +25°C VREFP = +10 V, VREFN = 0 V 5/ +1 ±0.25 typical +25°C VREFP = +10 V, VREFN = -10 V 5/ Bits 0.11 typical +100°C VREFP = +10 V, VREFN = -10 V 5/ 01 -55°C to +125°C -11 -55°C to +125°C LSB +11 ±0.25 typical +25°C -21 -55°C to +125°C VREFP = +5 V, VREFN = 0 V 5/ +7 ±0.1 typical +25°C VREFP = +10 V, VREFN = 0 V 5/ -7 +21 ±0.8 typical +25°C See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Unit Min Max -4 +4 Static performance – continued. 4/ Full scale error FSE VREFP = +10 V, VREFN = -10 V 5/ 01 0°C to +105°C ±0.1 typical +25°C -4 0°C to +105°C VREFP = +10 V, VREFN = 0 V 5/ -6 0°C to +105°C Zero scale error ZSE VREFP = +10 V, VREFN = -10 V 5/ +25°C 01 ±0.02 typical ppm FSR/ °C -55°C to +125°C 01 -7 LSB -10 -55°C to +125°C -21 -55°C to +125°C -4 0°C to +105°C -4 0°C to +105°C -6 0°C to +105°C +6 ±0.75 typical +25°C Zero scale error 5/ temperature coefficient +4 ±0.15 typical +25°C VREFP = +5 V, VREFN = 0 V 5/ +4 ±0.1 typical +25°C VREFP = +10 V, VREFN = 0 V 5/ +21 ±0.75 typical +25°C VREFP = +10 V, VREFN = -10 V 5/ +10 ±0.15 typical +25°C VREFP = +5 V, VREFN = 0 V 5/ +7 ±0.1 typical +25°C VREFP = +10 V, VREFN = 0 V 5/ +6 ±0.8 typical +25°C Full scale error temperature coefficient +4 ±0.25 typical +25°C VREFP = +5 V, VREFN = 0 V 5/ LSB 01 +25°C ±0.04 typical ppm FSR/ °C See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions Temperature, TA Device type Limits Unit Min Max -6 +6 Static performance – continued. 4/ Gain error AE VREFP = +10 V, VREFN = -10 V 5/ 01 -55°C to +125°C ±0.3 typical +25°C -10 -55°C to +125°C VREFP = +10 V, VREFN = 0 V 5/ -20 -55°C to +125°C -6 0°C to +105°C -6 0°C to +105°C -7 0°C to +105°C 5/ R1, RFB matching +7 ±0.4 typical +25°C Gain error temperature coefficient +6 ±0.4 typical +25°C VREFP = +5 V, VREFN = 0 V 5/ +6 ±0.3 typical +25°C VREFP = +10 V, VREFN = 0 V 5/ +20 ±0.4 typical +25°C VREFP = +10 V, VREFN = -10 V 5/ +10 ±0.4 typical +25°C VREFP = +5 V, VREFN = 0 V 5/ ppm FSR +25°C 01 ±0.04 typical ppm FSR/ °C +25°C 01 0.01 typical % See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Output characteristics. Conditions 2/ 3/ Temperature, TA Device type Limits Unit Min Max VREFN VREFP 5/ Output voltage range +25°C 01 Output slew rate +25°C 01 50 typical V/µs +25°C 01 1 typical µs Output voltage settling time 10 V step to 0.02%, using AD845 buffer in unity gain mode 500 code step to ±1 LSB 7/ Output noise spectral density V 1 typical At 1 kHz, DAC code = midscale 01 +25°C 7.5 typical At 10 kHz, DAC code = midscale 7.5 typical At 100 kHz, DAC code = midscale 7.5 typical nV / Hz Output voltage noise DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 8/ +25°C 01 1.1 typical µVPP Midscale glitch impulse VREFP = +10 V, VREFN = -10 V +25°C 01 3.1 typical nVsec 9/ MSB segment glitch impulse 9/ Output enabled glitch impulse VREFP = +10 V, VREFN = 0 V 1.7 typical VREFP = +5 V, VREFN = 0 V 1.4 typical 01 +25°C VREFP = +10 V, VREFN = -10 V 9.1 typical VREFP = +10 V, VREFN = 0 V 3.6 typical VREFP = +5 V, VREFN = 0 V 1.9 typical On removal of output ground clamp nVsec +25°C 01 45 typical nVsec Digital feedthrough +25°C 01 0.4 typical nVsec DC output impedance (normal mode) +25°C 01 3.4 typical kΩ DC output impedance (output clamped to ground) +25°C 01 6 typical kΩ See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Min Unit Max Output characteristics – continued. 5/ Spurious free dynamic range 1 kHz tone, 10 kHz sample rate +25°C 01 100 typical dB Total harmonic distortion 1 kHz tone, 10 kHz sample rate +25°C 01 97 typical dB VREFP input range -55°C to +125°C 01 5 VDD – 2.5 V VREFN input range -55°C to +125°C 01 VSS + 2.5 V 0 V -55°C to +125°C 01 5 Reference inputs. 5/ DC input impedance ZIN VREFP, VREFN, code dependent, typical mid-scale code 6.6 typical +25°C Input capacitance CIN VREFP, VREFN kΩ +25°C 01 -55°C to +125°C 01 15 typical pF Logic inputs. 5/ Input current 10/ IIN Input low voltage VIL IOVCC = 1.71 V to 5.5 V -55°C to +125°C 01 Input high voltage VIH IOVCC = 1.71 V to 5.5 V -55°C to +125°C 01 +25°C 01 Pin capacitance -1 +1 µA 0.3 x IOVCC V 0.7 x IOVCC V 5 typical pF See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 9 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Min Unit Max Logic output (SDO) 5/ Output low voltage VOL IOVCC = 1.71 V to 5.5 V, sinking 1 mA -55°C to +125°C 01 Output high voltage VOH IOVCC = 1.71 V to 5.5 V, sourcing 1 mA -55°C to +125°C 01 -55°C to +125°C 01 +25°C 01 High impedance leakage current High impedance output capacitance Power requirements. 0.4 V V IOVCC – 0.5 V ±1 3 typical µA pF All digital inputs at DGND or IOVCC Positive analog supply voltage VDD -55°C to +125°C 01 7.5 VSS + 33 V Negative analog supply voltage VSS -55°C to +125°C 01 VDD - 33 -2.5 V Digital supply voltage VCC -55°C to +125°C 01 2.7 5.5 V Digital interface supply voltage IOVCC -55°C to +125°C 01 1.71 5.5 V Positive analog supply current IDD -55°C to +125°C 01 5.2 mA IOVCC ≤ VCC 4.2 typical +25°C Negative analog supply current 01 -55°C to +125°C ISS 01 -55°C to +125°C ICC IOICC SDO disabled 01 -55°C to +125°C VDD ± 10%, VSS = 15 V µA 140 µA 52 typical +25°C DC power 5/ 11/ supply rejection ratio 900 600 typical +25°C Digital interface supply current mA 4 typical +25°C Digital supply current 4.9 01 +25°C ±0.6 typical µV/V ±0.6 typical VSS ± 10%, VDD = 15 V See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 10 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Min Power requirements - continued. All digital inputs at DGND or IOVCC AC power 5/ supply rejection ratio VDD ± 200 mV, 50 Hz/60 Hz, 01 +25°C Unit Max 95 typical dB VSS = -15 V 95 typical ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V Timing requirements. 12/ SCLK cycle time 13/ t1 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t2 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t3 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t4 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t5 SYNC rising edge hold time Minimum SYNC high time 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t7 Data setup time t8 ns 5 ns 2 ns 48 ns 40 IOVCC = 3.3 V to 5.5 V SYNC rising edge to next SCLK falling edge ignore 9 2 IOVCC = 3.3 V to 5.5 V t6 ns 5 IOVCC = 3.3 V to 5.5 V SCLK falling edge to 15 5 IOVCC = 3.3 V to 5.5 V SYNC to SCLK falling edge setup time ns 10 IOVCC = 3.3 V to 5.5 V SCLK low time 92 60 IOVCC = 3.3 V to 5.5 V SCLK high time ns 28 IOVCC = 3.3 V to 5.5 V SCLK cycle time (readback) modes 40 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 8 ns 6 IOVCC = 3.3 V to 5.5 V 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 9 ns 7 IOVCC = 3.3 V to 5.5 V See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 11 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Min Unit Max Timing requirements – continued. 12/ Data hold time t9 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t10 to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V SYNC rising edge to output response time t13 t15 01 +25°C IOVCC = 1.71 V to 3.3 V t16 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t17 ns 130 typical ns 130 typical ns 50 ns 50 01 +25°C IOVCC = 1.71 V to 3.3 V 140 typical ns 140 typical IOVCC = 3.3 V to 5.5 V SYNC falling edge to first SCLK rising edge 14 130 typical IOVCC = 3.3 V to 5.5 V CLR pulse activation time ns 130 typical IOVCC = 3.3 V to 5.5 V ( LDAC tied low) CLR pulse width low 01 +25°C IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V t14 20 11 IOVCC = 3.3 V to 5.5 V LDAC falling edge to output response time ns 16 IOVCC = 3.3 V to 5.5 V t12 13 10 IOVCC = 3.3 V to 5.5 V t11 ns 7 IOVCC = 3.3 V to 5.5 V LDAC falling edge 12 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V 0 ns 0 IOVCC = 3.3 V to 5.5 V See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 12 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ 3/ Temperature, TA Device type Limits Min Unit Max Timing requirements – continued. 12/ SYNC rising edge to SDO tristate t18 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V, 65 ns CL = 50 pF 60 IOVCC = 3.3 V to 5.5 V, CL = 50 pF SCLK rising edge to SDO valid t19 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V, 62 ns CL = 50 pF 45 IOVCC = 3.3 V to 5.5 V, CL = 50 pF SYNC rising edge to SCLK rising edge ignore t20 RESET pulse width low t21 01 -55°C to +125°C IOVCC = 1.71 V to 3.3 V t22 01 +25°C IOVCC = 1.71 V to 3.3 V 2/ 35 typical ns 35 typical 01 +25°C IOVCC = 1.71 V to 3.3 V 150 typical ns 150 typical IOVCC = 3.3 V to 5.5 V 1/ ns 0 IOVCC = 3.3 V to 5.5 V IOVCC = 3.3 V to 5.5 V RESET pulse activation time 0 Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Unless otherwise specified, VDD = +12.5 V to +16.5 V, VSS = -16.5 V to -12.5 V, VREFP = +10 V, VREFN = -10 V, VCC = +2.7 V to +5.5 V, IOVCC = +1.71 V to +5.5 V, RL = unloaded, and CL = unloaded. 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ Unless otherwise specified, for typical conditions, TA = +25°C, VDD = +15 V, VSS = -15 V, VREFP = +10 V, and VREFN = -10 V. Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer. Guaranteed by design and characterization; not production tested. Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. The device configured in x2 gain mode, 25 pF compensation capacitor on AD797. Includes noise contribution from AD8676BRZ voltage reference buffers. The device is configured in the bias compensation mode with a low pass resistor-capacitor (RC) filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance). Current flowing in an individual logic pin. Includes PSRR of AD8676BRZ voltage reference buffers. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH) / 2. Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 13 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 14 Case X Dimensions Inches Symbol Millimeters Min Med Max Min Med Max A --- --- .047 --- --- 1.20 A1 .001 --- .005 0.05 --- 0.15 b .007 --- .011 0.19 --- 0.30 c .003 --- .007 0.09 --- 0.20 D .251 0.255 .259 6.40 6.50 6.60 E .169 0.173 .177 4.30 4.40 4.50 E1 .251 BSC 6.40 BSC e .025 BSC 0.65 BSC L .017 .023 .029 0.45 0.60 0.75 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Falls within reference to JEDEC MO-153-AC. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 15 Device type 01 Case outline X Terminal number Terminal symbol 1 INV 2 VOUT 3 VREFPS Description Connection to inverting input of external amplifier. Analog output voltage. Positive reference sense voltage input. A voltage range of 5 V to VDD – 2.5 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFPF pin. 4 VREFPF Positive reference force voltage input. A voltage range of 5 V to VDD – 2.5 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFPS pin. 5 VDD Positive analog supply connection. A voltage range of 7.5 V to 16.5 V can be connected. VDD should be decoupled to AGND. 6 RESET Active low reset logic input pin. Asserting this pin returns the device to its power on status. 7 CLR Active low clear logic input pin. Asserting this pin sets the DAC register to a user defined value and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 8 LDAC Active low load DAC input pin. This is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC . If LDAC is held high during the write cycle, the input register is updated, but the output is held off until the falling edge of LDAC . The LDAC pin should not be left unconnected. 9 VCC 10 IOVCC Digital supply connection. A voltage in the range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND. Digital interface supply pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of 1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC. FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 16 Device type 01 Case outline X Terminal number Terminal symbol Description 11 SDO Serial data output pin. Data is clocked out on the rising edge of the serial clock input. 12 SDIN Serial data input pin. This device has a 24 bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial clock input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock rates of up to 35 MHz. 14 SYNC Active low digital interface synchronization input pin. This is the frame synchronization signal for the input data. When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The input shift register is updated on the rising edge of SYNC . 15 DGND Ground reference pin for digital circuitry. 16 VREFNF Negative reference force voltage input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFNS pin. 17 VREFNS Negative reference sense voltage input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFNF pin. 18 VSS Negative analog supply connection. A voltage range of -16.5 V to -2.5 V can be connected. VSS should be decoupled to AGND. 19 AGND 20 RFB Ground reference pin for analog circuitry. Feedback connection for external amplifier. FIGURE 2. Terminal connections - continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 17 FIGURE 3. Write mode timing diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 18 FIGURE 4. Readback mode timing diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 19 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12664-01XB 24355 AD5791SRU-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices Route 1 Industrial Park P.O. Box 9106 Norwood, MA 02062 Point of contact: Raheen Business Park Limerick, Ireland SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12664 PAGE 20